JP6626802B2 - Electro-optical devices and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and an electronic apparatus that are effective when, for example, a pixel circuit is miniaturized.

In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (Organic Light Emitting Diode, hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a pixel circuit including the light emitting element and the transistor is generally provided corresponding to a pixel of an image to be displayed, corresponding to the intersection of the scanning line and the data line. In such a structure, when a data signal having a potential corresponding to the gray level of a pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light-emitting element. Thereby, the light emitting element emits light with luminance according to the gradation level. At this time, if the characteristics such as the threshold voltage of the transistor vary from pixel circuit to pixel circuit, display unevenness that impairs the uniformity of the display screen occurs. For this reason, a technique for compensating the characteristics of the transistor has been proposed (for example, see Patent Document 1).
In addition, the electro-optical device is often required to have a smaller display size and a higher display definition. In order to achieve both a reduction in display size and a high definition display, it is necessary to miniaturize a pixel circuit. Therefore, a technology in which an electro-optical device is provided in, for example, a silicon integrated circuit has been proposed (for example, Patent Document 1). 2).

JP 2007-316462 A JP 2009-288435 A

By the way, when the pixel circuit is miniaturized, it is necessary to control the current supplied to the light emitting element in a minute area. The current supplied to the light-emitting element is controlled by the voltage between the gate and the source of the transistor, but in a small area, the current supplied to the light-emitting element increases for a small change in the voltage between the gate and the source. Will change.
On the other hand, a circuit for outputting a data signal has a higher driving capability in order to charge a data line in a short time. It is difficult for a circuit having such a high driving capability to output a data signal with extremely fine precision.
The present invention has been made in view of the above-described circumstances, and one of the objects of the present invention is to eliminate the need for a data signal with high precision and to reduce the current supplied to a light emitting element while compensating for the characteristics of a transistor. It is an object of the present invention to provide an electro-optical device and an electronic device that can supply well.

In order to achieve the above object, in an electro-optical device according to the present invention, a plurality of scanning lines, a plurality of data lines, a first storage capacitor having one end connected to the data line, and a plurality of data lines. A second storage capacitor for holding the potential of each of the lines, a pixel circuit provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, and a driving circuit for driving the pixel circuit. The pixel circuit includes a first transistor that supplies a current corresponding to a voltage between a gate and a source, a light emitting element that emits light at a luminance corresponding to a current supplied by the first transistor, the data line, and the data line. A second transistor that is turned on or off between a gate of the first transistor and a third transistor that is turned on or off between a gate and a drain of the first transistor; The first transistor and the light emitting element are connected in series between a power supply on a high side and a power supply on a low side, and the driving circuit supplies a first potential for supplying the data line and an initial potential during a first period. A power supply line; electrically connecting the other end of the first storage capacitor to a second power supply line for supplying a predetermined potential; and connecting the data line to the data line during a second period following the first period. And the first power supply line are electrically disconnected from each other, and the second transistor and the third transistor are turned on while maintaining the connection between the other end of the first storage capacitor and the second power supply line, In a third period following the second period, the other end of the first storage capacitor is electrically disconnected from the second power supply line, and a signal of a potential corresponding to the luminance is applied to the other end of the first storage capacitor. And turning off the second transistor at the end of the third period. The features.
According to the present invention, in the first period, the data line, the first storage capacitor, and the second storage capacitor are initialized. When the second transistor and the third transistor are turned on in the second period, the data line and the gate of the first transistor have a potential corresponding to the threshold voltage of the first transistor. In the third period, when a signal having a potential corresponding to the luminance is supplied to the other end of the first storage capacitor in a state where the second transistor is turned on, the data line and the gate of the first transistor are driven in accordance with the threshold voltage. From the applied potential, the potential variation at the other end of the first storage capacitor is shifted by the voltage divided by the capacitance ratio. Therefore, the potential range at the gate of the first transistor is narrower than the potential range at the other end of the first storage capacitor. Therefore, according to the present invention, a current to be supplied to the light emitting element can be supplied with high accuracy while compensating for the characteristics of the transistor, while not requiring a data signal with high precision.

In the present invention, the driving circuit has a third storage capacitor corresponding to the data line, and the drive circuit temporarily holds a data signal of a potential according to a gradation level, which is supplied before the third period. Preferably, during the third period, the potential held in the third storage capacitor is supplied to the other end of the first storage capacitor as a signal of a potential corresponding to the luminance.
In this configuration, a first switch and a second switch are provided corresponding to the third storage capacitor, and an output terminal of the first switch is connected to the other end of the first storage capacitor. An input terminal is connected to one end of the third storage capacitor and an output terminal of the second switch, the input terminal of the second switch is supplied with the data signal before the third period, and the driving circuit Prior to the third period, the second switch is turned on with the first switch turned off, and the first switch is turned on with the second switch turned off in the third period. It is preferable to turn it on.
In this aspect, when the data signal is supplied to the input terminal of the second switch at least in the first period or the second period, the supply of the data signal and the potential according to the threshold voltage of the first transistor are performed. The operation of setting to the gate can be executed in parallel with time.
Further, in such an embodiment, the data lines are grouped into a plurality of data lines, input terminals of the second switches corresponding to the plurality of data lines belonging to one group are commonly connected, and the driving circuit includes: The plurality of second switches belonging to the one group may be turned on in a predetermined order according to the supply of the data signal.

In the present invention, the pixel circuit includes a fourth transistor that turns on or off between a terminal on the first transistor side and a third power supply line that supplies a predetermined reset potential among two terminals of the light emitting element. It is good also as composition which has. According to this configuration, it is possible to suppress the influence of the holding voltage of the parasitic capacitance of the light emitting element.
In this configuration, the plurality of third power supply lines may be provided along the data lines for each of the plurality of data lines.
In this aspect, when one end of the second storage capacitor is connected to the data line and the other end of the second storage capacitor is connected to the third power supply line, for example, the data line and the third power supply line are connected to each other. When the second storage capacitor is configured by sandwiching the insulating layer with the above, a relatively large capacitor can be formed in a small space as the second storage capacitor.
The driving circuit may be configured to turn off the third transistor during the third period.
Further, the pixel circuit has a fifth transistor that is turned on or off in a current path supplied to the light emitting element by the first transistor, and the driving circuit turns off the fourth transistor so that the fifth transistor is turned off. The transistor may be turned on. Thus, the period during which the parasitic capacitance of the light emitting element is reset and the period during which current is supplied to the light emitting element to emit light can be made exclusive.
The pixel circuit may include a fourth storage capacitor that holds a voltage between a gate and a source of the first transistor. The fourth storage capacitor may be a parasitic capacitance of the first transistor or a separately provided capacitor.
Note that the present invention can be conceptualized as an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus including the electro-optical device. A display device such as a head-mounted display (HMD) or an electronic viewfinder is typically used as the electronic device.

FIG. 1 is a perspective view illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. 2 is a diagram illustrating a configuration of the electro-optical device. FIG. 2 is a diagram illustrating a pixel circuit in the electro-optical device. 4 is a timing chart illustrating an operation of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 4 is an explanatory diagram of the operation of the electro-optical device. FIG. 3 is a diagram illustrating amplitude compression of a data signal in the electro-optical device. FIG. 3 is a diagram illustrating characteristics of a transistor in the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment. 4 is a timing chart illustrating an operation of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 3 is an operation explanatory diagram of the electro-optical device. FIG. 2 is a perspective view illustrating an HMD using the electro-optical device according to the embodiment and the like. FIG. 2 is a diagram illustrating an optical configuration of an HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<First embodiment>
FIG. 1 is a perspective view illustrating a configuration of an electro-optical device 10 according to an embodiment of the present invention.
The electro-optical device 10 is, for example, a micro display that displays an image on a head-mounted display. Although details of the electro-optical device 10 will be described later, the electro-optical device 10 is an organic EL device in which a plurality of pixel circuits and a driving circuit for driving the pixel circuits are formed on a silicon substrate, for example. Certain OLEDs are used.
The electro-optical device 10 is housed in a frame-shaped case 72 opened in the display unit, and is connected to one end of an FPC (Flexible Printed Circuits) substrate 74. The control circuit 5 of the semiconductor chip is mounted on the FPC board 74 by COF (Chip On Film) technology, and a plurality of terminals 76 are provided to be connected to an upper circuit (not shown). Image data is supplied from the upper circuit via a plurality of terminals 76 in synchronization with a synchronization signal. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. In the image data, the gradation level of the pixel of the image to be displayed is specified by, for example, 8 bits.
The control circuit 5 has a function of both a power supply circuit of the electro-optical device 10 and a data signal output circuit. That is, the control circuit 5 supplies various control signals and various potentials generated according to the synchronization signal to the electro-optical device 10, converts digital image data into analog data signals, and supplies the analog image signals to the electro-optical device 10. I do.

FIG. 2 is a diagram illustrating a configuration of the electro-optical device 10 according to the first embodiment. As shown in this figure, the electro-optical device 10 is roughly divided into a scanning line driving circuit 20, a demultiplexer 30, a level shift circuit 40, and a display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. More specifically, in the display unit 100, m scanning lines 12 are provided extending in the horizontal direction in the figure, and (3n) columns of data lines 14 grouped every three columns are vertically arranged in the figure. The scanning lines 12 are provided in such a manner that they are electrically insulated from each other. A pixel circuit 110 is provided at an intersection of the m-th scanning line 12 and the (3n) -th column data line 14. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix of m rows × 3n columns.

Here, m and n are both natural numbers. In the matrix of the scanning lines 12 and the pixel circuits 110, in order to distinguish rows, the rows may be referred to as 1, 2, 3,... Similarly, in order to distinguish the columns (columns) of the matrix of the data lines 14 and the pixel circuits 110, the columns may be referred to as 1, 2, 3,..., (3n-1), and (3n) columns from the left in the drawing. . When an integer j of 1 or more and n or less is used to generalize and describe the group of the data lines 14, the j-th group counted from the left includes the (3j-2) th column and the (3j-1) ) Means that the data lines 14 of the (th) and (3j) th columns belong.
Note that the three pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the data lines 14 in three columns belonging to the same group are used for R (red), G (green), and B (blue) pixels, respectively. Correspondingly, these three pixels represent one dot of a color image to be displayed. That is, in the present embodiment, the configuration is such that the color of one dot is expressed by additive color mixture by the light emission of the OLED corresponding to RGB.

In the present embodiment, a power supply line 16 (third power supply line) is provided along the data line 14 for each column. A potential Vorst as a reset potential is commonly supplied to each power supply line 16. Further, a storage capacitor 50 is provided for each column. Specifically, one end of the storage capacitor is connected to the data line 14, and the other end is connected to the power supply line 16. Therefore, the storage capacitor 50 functions as a second storage capacitor that holds the potential of the data line 14.
Note that the storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the wiring forming the data line 14 and the wiring forming the power supply line 16.
Although the storage capacitor 50 is provided outside the display unit 100 in FIG. 2, this is merely an equivalent circuit, and may be provided inside the display unit 100 or from inside to outside. Of course. Although not shown in FIG. 2, the capacitance of the storage capacitor 50 is Cdt.

The following control signal is supplied to the electro-optical device 10 by the control circuit 5. Specifically, the electro-optical device 10 includes a control signal Ctr for controlling the scanning line driving circuit 20 and control signals Sel (1), Sel (2), and Sel for controlling selection in the demultiplexer 30. (3), control signals / Sel (1), / Sel (2), and / Sel (3) which are logically inverted with respect to these signals, and negative logic for controlling the level shift circuit 40. A control signal / Gini and a positive logic control signal Gref are supplied. Note that the control signal Ctr actually includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
Further, the electro-optical device 10 includes the data signals Vd (1), Vd (2),..., Vd (n) in the 1, 2,. Correspondingly supplied by the control circuit 5. Note that the maximum potential of the data signals Vd (1) to Vd (n) is Vmax, and the minimum potential is Vmin.

The scanning line drive circuit 20 generates a scanning signal for sequentially scanning the scanning lines 12 line by line over a period of a frame in accordance with a control signal Ctr. Here, the scanning signals supplied to the scanning lines 12 of the 1, 2, 3,..., (M−1), and m-th rows are Gwr (1), Gwr (2), Gwr (3),. Gwr (m-1) and Gwr (m).
Note that the scanning line driving circuit 20 generates various control signals synchronized with the scanning signals in addition to the scanning signals Gwr (1) to Gwr (m) for each row and supplies the generated signals to the display unit 100. In FIG. 2, illustration is omitted. The frame period refers to a period required for the electro-optical device 10 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the period is one. This is a period of 8.3 milliseconds for a cycle.

The demultiplexer 30 is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group.
Here, the input terminals of the transmission gates 34 corresponding to the (3j-2), (3j-1), and (3j) columns belonging to the j-th group are commonly connected to each other, and the data signal Vd ( j) is supplied.
The transmission gate 34 provided in the leftmost column (3j-2) column in the j-th group performs control when the control signal Sel (1) is at the H level (when the control signal / Sel (1) is at the L level). ). Similarly, the transmission gates 34 provided in the (3j-1) -th column, which is the center column in the j-th group, output the control signal Sel (2) at the H level (when the control signal / Sel (2) is at the L level). ), The transmission gate 34 provided in the rightmost column (3j) in the j-th group transmits the control signal Sel (3) at the H level (control signal / Sel (3)). (When is at L level).

  The level shift circuit 40 has a set of a storage capacitor 44, a P-channel MOS transistor 45, and an N-channel MOS transistor 43 for each column, and a data signal output from the output terminal of the transmission gate 34 in each column. Is shifted. Here, one end of the storage capacitor 44 is connected to the data line 14 of the corresponding column and the drain node of the transistor 45, while the other end of the storage capacitor 44 is connected to the output terminal of the transmission gate 34 and the drain node of the transistor 43. And connected to. Therefore, the storage capacitor 44 functions as a first storage capacitor having one end connected to the data line 14. Although not shown in FIG. 2, the capacitance of the storage capacitor 44 is assumed to be Crf1.

The source node of the transistor 45 in each column is commonly connected to a power supply line 61 that supplies a potential Vini as an initial potential over each column, and the control signal / Gini is commonly supplied to the gate node across each column. Therefore, the transistor 45 electrically connects the data line 14 and the power supply line 61 when the control signal / Gini is at the L level, and electrically disconnects when the control signal / Gini is at the H level. It has a configuration.
Further, the source node of the transistor 43 in each column is commonly connected to the power supply line 62 that supplies the potential Vref as a predetermined potential across the columns, and the control signal Gref is commonly supplied to the gate node across the columns. For this reason, the transistor 43 electrically connects the node h, which is the other end of the storage capacitor 44, to the power supply line 62 when the control signal Gref is at the H level, and electrically connects when the control signal Gref is at the L level. Is not connected to the server.

  In the present embodiment, the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40 are divided for convenience, but these can be collectively conceptualized as a driving circuit for driving the pixel circuit 110. .

The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration from an electrical standpoint, here, the i-th row (3j−3) located at the (3j−2) th column of the leftmost column in the i-th row and the j-th group is used here. 2) The pixel circuits 110 in a column will be described as an example.
Note that i is a symbol generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

  As shown in FIG. 3, the pixel circuit 110 includes P-channel MOS transistors 121 to 125, an OLED 130, and a storage capacitor 132. This pixel circuit 110 is supplied with a scanning signal Gwr (i), control signals Gel (i), Gcmp (i), and Gorst (i). Here, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are supplied by the scanning line driving circuit 20 corresponding to the i-th row. For this reason, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are columns other than the focused (3j-2) column in the i-th row. Are commonly supplied to the pixel circuits.

In the transistor 122 in the pixel circuit 110 in the i-th row (3j-2) column, the gate node is connected to the i-th scanning line 12, and one of the drain and source nodes is the data in the (3j-2) -th column. The other end is connected to the gate node g of the transistor 121, one end of the storage capacitor 132, and the drain node of the transistor 123. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
In the transistor 121, a source node is connected to the power supply line 116, and a drain node is connected to a source node of the transistor 123 and a source node of the transistor 124, respectively. Here, the power supply line 116 is supplied with a potential Vel which is a higher side of the power supply in the pixel circuit 110.
In the transistor 123, a control signal Gcmp (i) is supplied to a gate node.
In the transistor 124, a control signal Gel (i) is supplied to a gate node, and a drain node is connected to a source node of the transistor 125 and an anode of the OLED 130, respectively.
In the transistor 125, the gate node is supplied with the control signal Gorst (i) corresponding to the i-th row, and the drain node is connected to the power supply line 16 corresponding to the (3j-2) -th column and maintained at the potential Vorst. I'm dripping.

  Here, the transistor 121 corresponds to a first transistor, the transistor 122 corresponds to a second transistor, and the transistor 123 corresponds to a third transistor. Further, the transistor 125 corresponds to a fourth transistor, and the transistor 124 corresponds to a fifth transistor.

The other end of the storage capacitor 132 is connected to the power supply line 116. Therefore, the holding capacitor 132 holds the voltage between the source and the drain of the transistor 121. Here, when the capacity of the storage capacitor 132 is expressed as Cpix, the capacity Cdt of the storage capacity 50, the capacity Crf1 of the storage capacity 44, and the capacity Cpix of the storage capacity 132 are as follows.
Cdt> Crf1 >> Cpix
Is set to be
That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1.
Note that as the storage capacitor 132, a capacitor parasitic on the gate node g of the transistor 121 or a capacitor formed by sandwiching an insulating layer between conductive layers different from each other in a silicon substrate may be used.

  In this embodiment, since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to the potential Vel.

The anode of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 common to all of the pixel circuits 110, and is maintained at the potential Vct which is the lower side of the power supply in the pixel circuit 110.
The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode and a light-transmissive cathode on the silicon substrate. Then, on the emission side (cathode side) of the OLED 130, a color filter corresponding to any of RGB is superimposed.
In such an OLED 130, when a current flows from the anode to the cathode, the holes injected from the anode and the electrons injected from the cathode are recombined in the organic EL layer to generate excitons and generate white light. . The white light generated at this time is transmitted through the cathode opposite to the silicon substrate (anode), is colored by a color filter, and is visually recognized by an observer.

<Operation of First Embodiment>
The operation of the electro-optical device 10 will be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of each unit in the electro-optical device 10.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 of the 1st to mth rows are in one horizontal scanning period (H) in one frame period. Each time it is scanned sequentially.
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described in the scanning period in which the i-th row is horizontally scanned, particularly focusing on the pixel circuit 110 in the i-th row (3j-2) column.

In the present embodiment, the scanning period of the i-th row is roughly divided into an initialization period shown in FIG. 4B, a compensation period shown in FIG. 4C, and a writing period shown in FIG. Can be Then, after the writing period of (d), the light emitting period shown in (a) is provided after a short interval, and the scanning period of the i-th row is resumed after the lapse of one frame period. Therefore, in the order of time, the cycle of (emission period) → initialization period → compensation period → writing period → (emission period) is repeated.
In FIG. 4, the scanning signal Gwr (i-1), control signal Gel (i-1), Gcmp (i-1), For each of Gorst (i-1), one horizontal scan is performed more temporally than the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) corresponding to the i-th row. The waveform is temporally preceding by the period (H).

<Emission period>
For convenience of explanation, the description will be made from the light emission period which is a premise of the initialization period. As shown in FIG. 4, during the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level, and the control signal Gel (i) is at the L level. Further, among the control signals Gel (i), Gcmp (i) and Gorst (i) which are logic signals, the control signal Gel (i) is at the L level and the control signals Gcmp (i) and Gorst (i) are at the H level. Level.
Therefore, as shown in FIG. 5, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130. As described later, in the present embodiment, the voltage Vgs during the light emission period is a value obtained by level-shifting the threshold voltage of the transistor 121 according to the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.

Note that the light emission period of the i-th row is a period during which horizontal scanning is performed on a portion other than the i-th row, so that the potential of the data line 14 varies as appropriate. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here.
In FIG. 5, paths important in the description of the operation are indicated by thick lines (the same applies to FIGS. 6 to 8 and FIGS. 13 to 16 below).

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period (b) starts as the first period. In the initialization period, the control signal Gel (i) changes to the H level and the control signal Gorst (i) changes to the L level, as compared with the light emission period.
Therefore, as illustrated in FIG. 6, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode of the OLED 130 is reset to the potential Vorst.
As described above, since the OLED 130 has a configuration in which the organic EL layer is sandwiched between the anode and the cathode, a capacitance Coled is parasitic between the anode and the cathode as shown by a broken line in the figure. When a current is flowing through the OLED 130 during the light emitting period, the voltage between the anode and the cathode of the OLED 130 is held by the capacitor Coled. The held voltage is reset by turning on the transistor 125. For this reason, in the present embodiment, when a current flows through the OLED 130 again in a later light emission period, the OLED 130 is less affected by the voltage held by the capacitor Coled.

In detail, for example, when the display state is changed from a high-luminance display state to a low-luminance display state, if the configuration is not reset, a high voltage when the luminance is high (a large current flows) is held. In addition, even if an attempt is made to apply a small current, an excessive current will flow, and it will not be possible to make a display state of low luminance. On the other hand, in the present embodiment, since the potential of the anode of the OLED 130 is reset by turning on the transistor 125, reproducibility on the low luminance side is improved.
In the present embodiment, the potential Vorst is set so that the difference between the potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, the OLED 130 is off (non-light emitting) in the initialization period (compensation period and writing period described below).

  On the other hand, in the initialization period, the control signal / Gini goes low and the control signal Gref goes high, so that in the level shift circuit 40, the transistors 45 and 43 are turned on as shown in FIG. Therefore, the data line 14 as one end of the storage capacitor 44 is initialized to the potential Vini, and the node h as the other end of the storage capacitor 44 is initialized to the potential Vref.

In the present embodiment, the potential Vini is set so that (Vel−Vini) is higher than the threshold voltage | Vth | of the transistor 121. Note that since the transistor 121 is a P-channel transistor, the threshold voltage Vth based on the potential of the source node is negative. Therefore, in order to prevent confusion in the description of the height relationship, the threshold voltage is represented by the absolute value | Vth | and is defined by the magnitude relationship.
In the present embodiment, the potential Vref is set to a value such that the potential of the node h increases in a later writing period with respect to the potentials of the data signals Vd (1) to Vd (n). It is set to be lower than the minimum value Vmin.

<Compensation period>
In the scanning period of the i-th row, the second period is the compensation period (c). In the compensation period, the scanning signal Gwr (i) and the control signal Gcmp (i) are at the L level as compared with the initialization period. On the other hand, during the compensation period, the control signal / Gini goes high while the control signal Gref is kept high.
For this reason, as shown in FIG. 7, in the level shift circuit 40, when the transistor 45 is turned off while the transistor 43 is turned on, the node h is fixed to the potential Vref. On the other hand, in the pixel circuit 110 on the i-th row (3j-2) column, the gate node g is electrically connected to the data line 14 by turning on the transistor 122, so that the gate node g has the potential at the beginning of the compensation period. Vini.

Since the transistor 123 is turned on during the compensation period, the transistor 121 is diode-connected. Therefore, a drain current flows through the transistor 121 to charge the gate node g and the data line 14. More specifically, the current flows through a route of the power supply line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j-2) th column. Therefore, the data line 14 and the gate node g connected to each other by turning on the transistor 121 rise from the potential Vini.
However, the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), so that the data line 14 and the gate node g have the potential (Vel−−V) until the end of the compensation period. | Vth |). Therefore, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

<Write period>
After the initialization period, a writing period (d) is reached as a third period. In the writing period, the control signal Gcmp (i) becomes H level, so that the diode connection of the transistor 121 is released, while the control signal Gref becomes L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) th column to the gate node g in the pixel circuit 110 in the i-th row (3j-2) is in a floating state, the potential in the path is held. It is maintained at (Vel− | Vth |) by the capacitors 50 and 132.

  In the writing period of the i-th row, the control circuit 5, in the j-th group, sequentially transmits the data signal Vd (j) to the i-th row (3j-2) column, the i-th row (3j-1) column, i Switching to a potential corresponding to the gradation level of the pixel in the row (3j) column. On the other hand, the control circuit 5 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. Although not shown in FIG. 4, the control circuit 5 has control signals / Sel (1) and / Sel (2) that are logically inverted with respect to the control signals Sel (1), Sel (2) and Sel (3). ) And / Sel (3) are also output. Thus, in the demultiplexer 30, the transmission gates 34 in each group are turned on in the order of the leftmost column, the center column, and the rightmost column.

Here, when the transmission gate 34 in the leftmost column is turned on by the control signals Sel (1) and / Sel (1), as shown in FIG. In addition, the potential changes from the potential Vref fixed during the compensation period to the potential of the data signal Vd (j), that is, the potential corresponding to the gradation level of the pixel in the i-th row (3j-2) column. At this time, the potential change of the node h is represented by ΔV, and the potential after the change is represented by (Vref + ΔV).
On the other hand, since the gate node g is connected to one end of the storage capacitor 44 via the data line 14, the capacitance ratio k1 is changed from the potential (Vel− | Vth |) during the compensation period to the potential change ΔV of the node h. A value shifted in the ascending direction by the multiplied value (Vel− | Vth | + k1 · ΔV). At this time, if the voltage Vgs of the transistor 121 is expressed as an absolute value, the voltage becomes a value (| Vth | -k1.multidot..DELTA.V) obtained by subtracting from the threshold voltage | Vth |
The capacitance ratio k1 is Crf1 / (Cdt + Crf1). Strictly speaking, the capacitance Cpix of the storage capacitor 132 must also be considered, but the capacitance Cpix is set to be sufficiently smaller than the capacitances Crf1 and Cdt, and is ignored.

FIG. 9 is a diagram showing the relationship between the potential of the data signal and the potential of the gate node g during the writing period. The data signal supplied from the control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gray level of the pixel as described above. In the present embodiment, the data signal is not directly written to the gate node g, but is level-shifted as shown in FIG.
At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k1. For example, when the capacitances of the storage capacitors 44 and 50 are set such that Crf1: Cdt = 1: 9, the potential range ΔVgate of the gate node g can be compressed to 1/10 of the potential range ΔVdata of the data signal.
The direction and how much to shift the potential range ΔVgate of the gate node g with respect to the potential range ΔVdata of the data signal can be determined by the potentials Vp (= Vel− | Vth |) and Vref. This is because the potential range ΔVdata of the data signal is compressed with the capacitance ratio k1 with reference to the potential Vref, and the compression range shifted with reference to the potential Vp becomes the potential range ΔVgate of the gate node g. That's why.

As described above, in the writing period of the i-th row, the gate node g of the pixel circuit 110 of the i-th row changes the potential change ΔV of the node h from the potential (Vel− | Vth |) in the compensation period to the capacitance ratio k1. (Vel- | Vth | + k1.multidot..DELTA.V) which is shifted by a corresponding amount.
Eventually, the scanning signal Gwr (i) becomes H level, and the transistor 122 is turned off. As a result, the writing period ends, and the potential of gate node g is fixed at the shifted value.

<Emission period>
After the end of the writing period of the i-th row, the light-emitting period starts after one horizontal scanning period. In this light emission period, the control signal Gel (i) is at the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i-th row (3j-2) column. Since the voltage Vgs between the gate and the source is (| Vth | -k1.multidot..DELTA.V), the current corresponding to the gradation level causes the OLED 130 to set the threshold voltage of the transistor 121 as shown in FIG. It will be supplied in a compensated state.
Such an operation is also performed in time parallel in the other pixel circuits 110 in the i-th row other than the pixel circuit 110 in the (3j-2) -th column in the scanning period of the i-th row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), and the m-th row during the period of one frame, and is repeated for each frame. It is.

  According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal. Can be applied between the gate and the source. Therefore, even in the case where the minute current flowing through the OLED 130 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the minute pixel circuit 110, the current supplied to the OLED 130 is accurately controlled. It becomes possible to do.

In addition, as shown by a broken line in FIG. 3, a capacitance Cprs is actually parasitic between the data line 14 and the gate node g in the pixel circuit 110. For this reason, if the potential change width of the data line 14 is large, it propagates to the gate node g via the capacitor Cprs, so that so-called crosstalk or unevenness occurs, thereby deteriorating the display quality. The effect of the capacitance Cprs appears remarkably when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, since the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, the influence via the capacitance Cprs can be suppressed.

  According to the present embodiment, a period longer than the scanning period, for example, two horizontal scanning periods can be ensured as a period during which the transistor 125 is turned on, that is, as a reset period of the OLED 130. The initialized voltage can be sufficiently initialized.

  Further, according to the present embodiment, the current Ids supplied to the OLED 130 by the transistor 121 cancels out the influence of the threshold voltage. For this reason, according to the present embodiment, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the variation is compensated, and a current corresponding to the gradation level is supplied to the OLED 130. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display can be achieved.

This cancellation will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weak inversion region (sub-threshold region) in order to control a small current supplied to the OLED 130.
In the figure, A indicates a transistor having a large threshold voltage | Vth |, and B indicates a transistor having a small threshold voltage | Vth |. In FIG. 10, the voltage Vgs between the gate and the source is a difference between the characteristic indicated by the solid line and the potential Vel. In FIG. 10, the current of the vertical scale is represented by a logarithm in which the direction from the source to the drain is positive (upward).
During the compensation period, the potential of the gate node g changes from the potential Vini to the potential (Vel− | Vth |). For this reason, the transistor A having a large threshold voltage | Vth | moves the operating point from S to Aa, while the transistor B having a small threshold voltage | Vth | moves the operating point from S to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is designated, in the writing period, the potential shift amount from the operating points Aa and Ba is , Both have the same k11ΔV. Therefore, the operating point of the transistor A shifts from Aa to Ab, and the operating point of the transistor B shifts from Ba to Bb. However, the current at the operating point after the potential shift is substantially the same for both the transistors A and B. Ids will be aligned.

<Second embodiment>
In the first embodiment, the data signal is directly supplied by the demultiplexer 30 to the other end of the storage capacitor 44 in each column, that is, the node h. Therefore, in the scanning period of each row, a period during which the data signal is supplied from the control circuit 5 is an equal writing period, and thus there is a large time constraint.
Therefore, a second embodiment capable of relaxing such a time constraint will be described next. Note that, in the following, in order to avoid repetition of the description, the description will be made focusing on the differences from the first embodiment.

FIG. 11 is a diagram illustrating a configuration of the electro-optical device 10 according to the second embodiment.
The second embodiment shown in this figure differs from the first embodiment shown in FIG. 2 mainly in that a storage capacitor 41 and a transmission gate 42 are provided in each column of the level shift circuit 40.

Specifically, in each column, the transmission gate 42 is electrically inserted between the output terminal of the transmission gate 34 and the other end of the storage capacitor 44. That is, the input terminal of the transmission gate 42 is connected to the output terminal of the transmission gate 34, and the output terminal of the transmission gate 42 is connected to the other end of the storage capacitor 44 .
Note that the transmission gates 42 in each column are turned on all at once when the control signal Gcpl supplied from the control circuit 5 is at the H level (when the control signal / Gcpl is at the L level) .

  In each column, one end of the storage capacitor 41 is connected to the output terminal of the transmission gate 34 (the input terminal of the transmission gate 42), and the other end of the storage capacitor 41 is grounded to a fixed potential, for example, the potential Vss. I have. Although not shown in FIG. 11, the capacitance of the storage capacitor 41 is assumed to be Crf2. Note that the potential Vss corresponds to an L level of a scan signal or a control signal which is a logic signal.

<Operation of Second Embodiment>
The operation of the electro-optical device 10 according to the second embodiment will be described with reference to FIG. FIG. 12 is a timing chart for explaining the operation in the second embodiment.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 of the 1st to mth rows are in one horizontal scanning period (H) in one frame period. It is the same as the first embodiment in that the scanning is performed in order every time. In the second embodiment, the scanning period of the i-th row is in the order of the initialization period shown in (b), the compensation period shown in (c), and the writing period shown in (d). This is the same as in the first embodiment. In the writing period (d) in the second embodiment, the scanning signal changes from L to H level from when the control signal Gcpl changes from L to H level (when the control signal / Gcpl changes to L level). It is a period until time.
In the second embodiment, as in the first embodiment, the cycle of (emission period) → initialization period → compensation period → write period → (emission period) is repeated in the order of time. However, the second embodiment is different from the first embodiment in that the data signal supply period precedes the write period, not the data signal supply period equal write period. Specifically, the second embodiment is different from the first embodiment in that a data signal can be supplied over an initialization period (a) and a compensation period (b).

<Emission period>
In the second embodiment, as shown in FIG. 12, during the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level, the control signal Gel (i) is at the L level, and the control signal Gcmp (i), Gorst (i) is at H level.
Therefore, as illustrated in FIG. 13, in the pixel circuit 110 in the i-th row (3j−2) column, the transistor 124 is turned on while the transistors 122, 123, and 125 are turned off. Basically, it is the same as the first embodiment. That is, the transistor 121 supplies a current Ids according to the gate-source voltage Vgs to the OLED 130.

<Initialization period>
When the scanning period of the i-th row is reached, first, the initialization period (b) starts.
In the initialization period in the second embodiment, the control signal Gel (i) changes to the H level and the control signal Gorst (i) changes to the L level as compared with the light emission period.
Therefore, as shown in FIG. 14, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode of the OLED 130 is reset to the potential Vorst by turning on the transistor 124. Therefore, the operation of the pixel circuit 110 is basically the same as that of the first embodiment. Become.

On the other hand, in the initialization period in the second embodiment, the control signal / Gini goes low, the control signal Gref goes high, and the control signal Gcpl goes low. Therefore, in the level shift circuit 40, as shown in FIG. 14, the transistors 45 and 43 are turned on, and the transmission gate 42 is turned off. Therefore, the data line 14 which is one end of the storage capacitor 44 is initialized to the potential Vini, and the node h which is the other end of the storage capacitor 44 is initialized to the potential Vref.
In the second embodiment, as to the potential Vref, the potential of the node h rises and changes in a later writing period with respect to the potential of the data signals Vd (1) to Vd (n), as in the first embodiment. Is set to a value that

As described above, in the second embodiment, the control circuit 5 supplies the data signal over the initialization period and the compensation period. That is, in the j-th group, the control circuit 5 sequentially transmits the data signal Vd (j) to the i-th row (3j-2) column, the i-th row (3j-1) column, and the i-th row (3j) column. The control signal Sel (1), Sel (2), and Sel (3) are exclusively set to the H level in order in accordance with the switching of the potential of the data signal, while switching to the potential corresponding to the gradation level of the pixel. Thus, in the demultiplexer 30, the transmission gates 34 in each group are turned on in the order of the leftmost column, the center column, and the rightmost column.
Here, during the initialization period, when the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel (1), as shown in FIG. The data signal is stored in the storage capacitor 41.

<Compensation period>
In the scanning period of the i-th row, the compensation period shown in FIG. In the compensation period in the second embodiment, the scanning signal Gwr (i) changes to the L level and the control signal Gcmp (i) changes to the L level as compared with the initialization period.
Therefore, as shown in FIG. 15, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 122 is turned on, and the gate node g is electrically connected to the data line 14 while the transistor 123 is turned on. When turned on, the transistor 121 is diode-connected.
Therefore, the current flows through the path of the power supply line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j-2) th column, so that the gate node g rises from the potential Vini and then (Vel− | Vth |). Therefore, also in the second embodiment, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

In the second embodiment, during the compensation period, the control signal / Gini becomes H level while the control signal Gref is maintained at H level, so that the node h in the level shift circuit 40 is fixed at the potential Vref.
When the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel (1) during the compensation period, the data signal Vd (j) is held by the holding capacitor 41 as shown in FIG. Is done.

If the transmission gate 34 in the leftmost column belonging to the j-th group has already been turned on by the control signal Sel (1) during the initialization period, the transmission gate 34 will not be turned on during the compensation period. There is no change in that the data signal Vd (j) is stored in the storage capacitor 41.
When the compensation period ends, the control signal Gcmp (i) becomes H level, so that the diode connection of the transistor 121 is released.

  In the second embodiment, since the control signal Gref is at the L level between the end of the compensation period and the start of the next writing period, the transistor 43 is turned off. Therefore, the path from the data line 14 in the (3j-2) th column to the gate node g in the pixel circuit 110 in the i-th row (3j-2) column is in a floating state, but the potential of the path is It is maintained at (Vel− | Vth |) by the storage capacitors 50 and 132.

<Write period>
In the writing period in the second embodiment, the control signal Gcpl is at the H level (the control signal / Gcpl is at the L level). As a result, as shown in FIG. 16, the transmission gate 42 is turned on in the level shift circuit 40, so that the data signal stored in the storage capacitor 41 is supplied to the node h which is the other end of the storage capacitor 44. Therefore, the node h shifts from the potential Vref in the compensation period. That is, the node h changes to the potential (Vref + ΔV).

On the other hand, since the gate node g is connected to one end of the storage capacitor 44 via the data line 14, the capacitance ratio k2 is changed from the potential (Vel− | Vth |) during the compensation period to the potential change ΔV of the node h. The value is shifted in a direction to increase by the multiplied value. In other words, the potential of the gate node g is shifted upward from the potential (Vel− | Vth |) during the compensation period by a value obtained by multiplying the potential change ΔV of the node h by the capacitance ratio k2 (Vel− | Vth). | + K2 ・ ΔV).
In the second embodiment, the capacitance ratio k2 is a capacitance ratio of Cdt, Crf1, and Crf2. As described above, the capacity Cpix of the storage capacity 132 is ignored.
At this time, if the voltage Vgs of the transistor 121 is expressed as an absolute value, the threshold voltage | Vth | becomes a value (| Vth | -k2.multidot..DELTA.V) obtained by subtracting the shift of the potential rise of the gate node g from the threshold voltage | Vth |.

<Emission period>
In the second embodiment, after the end of the writing period of the i-th row, the light-emitting period starts one horizontal scanning period. In this light emission period, the control signal Gel (i) is at the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i-th row (3j-2) column.
The gate-source voltage Vgs is (| Vth | -k2.multidot..DELTA.V), which is a value obtained by level-shifting the threshold voltage of the transistor 121 by the potential of the data signal. Therefore, as shown in FIG. 13, a current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.
Such an operation is also performed in time parallel in the other pixel circuits 110 in the i-th row other than the pixel circuit 110 in the (3j-2) -th column in the scanning period of the i-th row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), and the m-th row during the period of one frame, and is repeated for each frame. It is.

According to the second embodiment, similar to the first embodiment, in the fine pixel circuit 110, the minute current flowing through the OLED 130 changes relatively largely with respect to the gate-source voltage Vgs of the transistor 121. Also, the current supplied to the OLED 130 can be accurately controlled.
According to the second embodiment, similarly to the first embodiment, it is possible to sufficiently initialize the voltage held in the parasitic capacitance of the OLED 130 during the light emission period, and to set the threshold voltage of the transistor 121 for each pixel circuit 110. Even if there is variation, the occurrence of display unevenness that impairs the uniformity of the display screen can be suppressed, so that high-quality display can be achieved.

According to the second embodiment, the operation of holding the data signal supplied from the control circuit 5 via the demultiplexer 30 in the holding capacitor 41 is executed from the initialization period to the compensation period. For this reason, it is possible to ease the time constraint on the operation to be performed during one horizontal scanning period.
For example, as the gate-source voltage Vgs approaches the threshold voltage in the compensation period, the current flowing through the transistor 121 decreases. Therefore, it takes time until the gate node g converges to the potential (Vel− | Vth |). In the second embodiment, as shown in FIG. 12, a longer compensation period can be secured than in the first embodiment. For this reason, according to the second embodiment, the variation in the threshold voltage of the transistor 121 can be compensated more accurately than in the first embodiment.
Further, the speed of the data signal supply operation can be reduced.

<Applications / Modifications>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible, for example. In addition, one or a plurality of arbitrarily selected modifications may be appropriately combined with each other.

<Control circuit>
In the embodiment, the control circuit 5 for supplying the data signal is provided separately from the electro-optical device 10. However, the control circuit 5 is also provided on the silicon substrate together with the scanning line drive circuit 20, the demultiplexer 30, and the level shift circuit 40. Alternatively, they may be integrated.

<Substrate>
In the embodiment, the electro-optical device 10 is configured to be integrated on a silicon substrate, but may be configured to be integrated on another semiconductor substrate. Further, a polysilicon process may be applied to form a glass substrate or the like. In any case, the pixel circuit 110 is miniaturized, and this is effective for a configuration in which the drain current of the transistor 121 greatly changes exponentially with respect to the change of the gate voltage Vgs.

<Control signal Gcmp (i)>
In the embodiments and the like, in the i-th row, the control signal Gcmp (i) is set to the H level during the writing period, but may be set to the L level. That is, the threshold compensation by turning on the transistor 123 and the writing to the node gate g may be performed in parallel.

<Demultiplexer>
In the embodiment and the like, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group and the data signals are supplied. It may be “2” or “4” or more.
Also, a configuration may be adopted in which data signals are supplied to the data lines 14 in each column at the same time line-sequentially without grouping, that is, without using the demultiplexer 30.

<Transistor channel type>
In the above-described embodiments and the like, the transistors 121 to 125 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, the P-channel type and the N-channel type may be appropriately combined.

<Others>
In the embodiments and the like, an OLED which is a light emitting element is exemplified as the electro-optical element. However, an electroluminescent element such as an inorganic light emitting diode or an LED (Light Emitting Diode) may be used as long as it emits light at a luminance corresponding to a current.

<Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the application example is applied will be described. The electro-optical device 10 is suitable for applications in which pixels have a small size and high-definition display. Therefore, a description will be given taking a head-mounted display as an example of the electronic apparatus.

FIG. 17 is a diagram showing an appearance of a head mounted display, and FIG. 18 is a diagram showing an optical configuration thereof.
First, as shown in FIG. 17, the head-mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in appearance, similar to general glasses. Also, as shown in FIG. 18, the head mounted display 300 includes the electro-optical device 10L for the left eye and the right eye on the back side (the lower side in the figure) of the lenses 301L and 301R near the bridge 320. And an electro-optical device 10R.
The image display surface of the electro-optical device 10L is disposed so as to be on the left side in FIG. Thereby, the display image by the electro-optical device 10L is emitted in the direction of 9 o'clock in the figure via the optical lens 302L. The half mirror 303L reflects an image displayed by the electro-optical device 10L in the direction of 6 o'clock, while transmitting light incident from the direction of 12:00.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the direction of 3 o'clock in the figure via the optical lens 302R. The half mirror 303R reflects an image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12:00 o'clock direction.

In this configuration, the wearer of the head-mounted display 300 can observe a display image by the electro-optical devices 10L and 10R in a see-through state superimposed on an outside state.
Further, in the head-mounted display 300, of the binocular images with parallax, the left-eye image is displayed on the electro-optical device 10L and the right-eye image is displayed on the electro-optical device 10R. The displayed image can be perceived as if it has a depth and a three-dimensional effect (3D display).

  The electro-optical device 10 can be applied to an electronic viewfinder in a video camera, a digital camera with interchangeable lenses, and the like, in addition to the head-mounted display 300.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical device, 12 ... Scan line, 14 ... Data line, 20 ... Scan line drive circuit, 30 ... Demultiplexer, 40 ... Level shift circuit, 41,44,50 ... Storage capacity, 100 ... Display part, 110 ... Pixel circuit, 116 power supply line, 118 common electrode, 121 to 125 transistor, 130 OLED, 132 storage capacitor, 300 head mounted display.

Claims (9)

A data signal output circuit for outputting a data signal;
A first switch having a first input terminal to which the data signal is supplied, and a first output terminal;
A second switch having a second input terminal connected to the first output terminal and a second output terminal;
A first capacitor that holds the potentials of the first output terminal and the second input terminal of the second switch;
A second capacitive element having one end connected to the second output terminal of the second switch;
A first wiring connected to the other end of the second capacitance element;
A pixel circuit connected to the first wiring and including a light emitting element ;
A first power supply line to which a first potential is supplied,
A third switch for controlling conduction or non-conduction between the second output terminal and one end of the second capacitance element, and the first power supply line;
With
The electro-optical device, wherein the first switch and the second switch are exclusively turned on. A second power supply line to which the reset potential has been supplied;
A fourth switch for controlling conduction or non-conduction between the other end of the second capacitance element and the first wiring, and the second power supply line;
The electro-optical device according to claim 1, further comprising: The pixel circuit includes:
A first transistor;
And the light emitting element having two terminals,
A second transistor that is turned on or off between the first wiring and the gate of the first transistor;
A third transistor that is turned on or off between a gate and a drain of the first transistor;
Including
3. The electro-optical device according to claim 1, wherein the first transistor and the light emitting element are connected in series between a power supply on a higher side and a power supply on a lower side. 4. The pixel circuit includes:
The light emitting device according to claim 3, further comprising: a fourth transistor that turns on or off between a terminal on the first transistor side and a third power supply line that supplies a predetermined reset potential, among the two terminals of the light emitting element. An electro-optical device according to claim 1. The electro-optical device according to any one of claims 1 to 3, further comprising a third feeding lines provided along said first wire. The electro-optical device according to claim 5, further comprising a third capacitance element having one end connected to the first wiring and the other end connected to the third power supply line. The electro-optical device according to claim 6, wherein the capacitance of the second capacitance element is smaller than the capacitance of the third capacitance element. A data signal output circuit for outputting a data signal;
A first switch having a common terminal to which the data signal is supplied, and a first output terminal ;
A second switch having a common terminal to which the data signal is supplied, and a second output terminal;
A third switch having a first input terminal connected to the first output terminal and a third output terminal;
A fourth switch having a second input terminal connected to the second output terminal and a fourth output terminal;
A first capacitance element that holds a potential of the first output terminal and the first input terminal;
A second capacitor that holds the potentials of the second output terminal and the second input terminal;
A third capacitive element having one end connected to the third output end;
A fourth capacitive element having one end connected to the fourth output end;
A first wiring connected to the other end of the third capacitive element,
A second wiring connected to the other end of the fourth capacitance element,
A first pixel circuit connected to the first wiring and including a first light emitting element ;
A second pixel circuit connected to the second wiring and including a second light emitting element ;
A first power supply line to which a first potential is supplied,
A fifth switch for controlling conduction or non-conduction between the third output terminal and one end of the third capacitance element, and the first power supply line;
A sixth switch for controlling conduction or non-conduction between the fourth output terminal and one end of the fourth capacitance element, and the first power supply line;
With
The first switch and the third switch are exclusively turned on,
An electro-optical device, wherein the second switch and the fourth switch are exclusively turned on . An electronic apparatus comprising the electro-optical device according to claim 1.

Images