JP6677464B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a fin field effect transistor and a method of manufacturing the same.

  In manufacturing a highly integrated semiconductor device, it is essential to make a pattern finer. In order to integrate a large number of elements in a small area, the size of individual elements must be made as small as possible. For this reason, the total width of each pattern to be formed and the distance between the patterns are required. A certain pitch must be reduced. 2. Description of the Related Art Recently, a design rule of a semiconductor device is rapidly reduced, so that a pattern having a fine pitch is formed due to a limit of resolution in a photolithography process for forming a pattern required to realize the semiconductor device. There is a limit.

US Patent No. 8,329,592 US Patent No. 8,455,945 US Patent No. 8,623,712 US Patent No. 8,822,320 US Patent Publication No. 2014/0001562

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can minimize the chip area overhead while ensuring the driving characteristics of transistors in different regions.
Problems to be solved by the present invention are not limited to the above problems, and other problems will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a substrate including a first region, a second region, and a third region between the first region and the second region. Forming first and second preliminary active patterns protruding from the substrate on the substrate in the first and second regions, respectively, wherein the first and second preliminary active patterns are Forming a mask pattern exposing the third region on the substrate, including a portion overlapping the third region, and when viewed from a plane, the mask pattern is not overlapped with the third region; Performing a first etching process using the mask pattern as an etching mask to form first and second active patterns from the first and second preliminary active patterns, respectively; and forming a gate structure on the substrate. Shaping and The gate structure includes a first gate structure that crosses the first active pattern and a second gate structure that crosses the second active pattern, wherein the first active pattern includes the first to third gates. The second active patterns extend in a first direction, which is a direction crossing the region, and are separated from each other in a second direction intersecting the first direction. The second active patterns are extended in the first direction and are separated from each other in the second direction. is, the distance between the first active pattern adjacent to each other in the second direction, unlike the spacing between the second active pattern adjacent to each other in the second direction, the third region by the first etching process A second trench is formed, and a lower surface of the second trench is lower than a lower surface of the first trench defining the first and second preliminary active patterns, and a maximum width of the second trench along the first direction. Is Characterized by defining a width along the first direction of the third region.

  According to one embodiment, each of the first preliminary active patterns includes a pair of first line patterns extending parallel to the first direction and the pair of first line patterns at one end of each of the pair of first line patterns. A first connection pattern for connecting one line pattern to each other, wherein the first connection pattern is overlapped with the third region, and each of the second preliminary active patterns is extended in parallel with the first direction. And a second connection pattern that connects the pair of second line patterns to each other at one end of each of the second line pattern and the pair of second line patterns, and the second connection pattern is overlapped with the third region. Can be

According to an embodiment, the first and second connection patterns may be removed by the first etching process.
According to one embodiment, an interval between the pair of first line patterns may be different from an interval between the pair of second line patterns.
According to one embodiment, an interval between the first preliminary active patterns adjacent to each other is substantially the same as the interval between the pair of first line patterns, and an interval between the second preliminary active patterns adjacent to each other. May be substantially the same as the interval between the pair of second line patterns.

  According to one embodiment, forming the first and second pre-active patterns includes forming a hard mask film on the substrate, forming a sacrificial pattern on the hard mask film, The sacrificial pattern includes a first sacrificial pattern provided in the first region and a second sacrificial pattern provided in the second region, and includes first and second sacrificial patterns on sidewalls of the first and second sacrificial patterns, respectively. Forming a spacer, removing the first and second sacrificial patterns, etching the hard mask film exposed by the first and second spacers, and providing a first region provided in the first region. Forming a hard mask pattern and a second hard mask pattern provided in the second region; and etching the upper portion of the substrate using the first and second hard mask patterns as an etching mask. , Forming a first trench defining the first and second preliminary active pattern Te can contain.

  According to one embodiment, forming the first and second sacrificial patterns includes forming a sacrificial film on the hard mask film and photolithography using a first wavelength exposure source on the sacrificial film. Performing a lithography process to form a first photoresist pattern provided in the first region and a second photoresist pattern provided in the second region, and forming the first and second photoresist patterns Etching the sacrificial film as an etching mask.

According to one embodiment, the first photoresist pattern has a structure in which a line and space pattern having a first pitch is repeatedly arranged, and the second photoresist pattern is formed from the first photoresist pattern. A line and space pattern having a second pitch different from the first pitch and spaced apart by a first distance in the first direction, wherein the first distance is smaller than the first wavelength; May be.
According to one embodiment, the first and second photoresist patterns include one end extending to the third region, and the first distance is equal to one end of the first photoresist pattern and the one adjacent to the one end. The second photoresist pattern may be defined by a maximum distance among the distances between one ends of the second photoresist pattern.

According to one embodiment, at least one of the first photoresist patterns may be connected to and integrated with at least one of the second photoresist patterns.
According to one embodiment, the hard mask film includes a lower mask film and an upper mask film sequentially stacked on the substrate, and etching the hard mask film includes forming the upper mask film and the lower mask film. Ru can involve sequentially to etch the mask layer.
According to one embodiment, the gate structure may not be formed in the third region.
According to one embodiment, the first gate structure forms a memory cell transistor,
The second gate structure may constitute a peripheral circuit transistor.

  According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: patterning a substrate to form a first trench defining a preliminary active pattern; A first pre-active pattern extending in a second direction intersecting the first direction and being separated from the first pre-active pattern in the first direction, and extending in the first direction; A second pre-active pattern that is separated from the second pre-active pattern in the second direction, and a space between the first pre-active patterns that are adjacent to each other in the second direction is a second pre-active pattern that is adjacent to the second direction. Forming a mask pattern that exposes one end of the first and second pre-active patterns on the substrate that are different from each other and that are opposed to each other in the first direction; Removing one end in an etching process using the mask pattern as an etching mask to form first and second active patterns from the first and second preliminary active patterns; and forming the first and second active patterns on the substrate. Forming a first gate structure crossing an active pattern and a second gate structure crossing the second active pattern, the second trench having a lower surface lower than the lower surface of the first trench by the etching process. The distance between the first and second active patterns in the first direction may be defined by the width of the second trench in the first direction.

According to one embodiment, each of the preliminary active patterns includes a pair of first line patterns extending parallel to the first direction and the pair of first line patterns at one end of each of the pair of first line patterns. A first connection pattern for connecting the patterns to each other, wherein each of the second preliminary active patterns includes a pair of second line patterns extending in parallel with the first direction and one end of each of the pair of second line patterns. And a second connection pattern for connecting the pair of second line patterns to each other, wherein the first and second connection patterns correspond to the one ends of the first and second preliminary active patterns, respectively.
According to one embodiment, the interval between the first preliminary active patterns adjacent to each other in the second direction is substantially the same as the interval between the pair of first line patterns, and the interval between the first preliminary active patterns in the second direction. The interval between adjacent second preliminary active patterns may be substantially the same as the interval between the pair of second line patterns.

According to one embodiment, forming the first trench includes sequentially forming a lower mask film and an upper mask film on the substrate, and forming a sacrificial pattern on the upper mask film. The sacrificial pattern includes a first sacrificial pattern provided in a first region and a second sacrificial pattern provided in a second region , and includes first and second sacrificial patterns on sidewalls of the first and second sacrificial patterns, respectively. Forming a spacer, etching the upper mask film using the first and second spacers as an etching mask to form first and second upper mask patterns in the first and second regions, respectively; Etching the lower mask film using the first and second upper mask patterns as an etching mask to form first and second lower mask patterns in the first and second regions, respectively; The method comprising etching an upper portion of the substrate a mask pattern as an etching mask may include.

According to an embodiment, the first photoresist pattern extends in the first direction, is spaced apart from the second direction by a first distance, and the second photoresist pattern extends in the first direction. The second photoresist pattern is spaced apart from the first photoresist pattern by a second distance in the second direction that is smaller than the first wavelength in the first direction. Can only be separated.
According to one embodiment, the first and second photoresist patterns include one ends facing each other in the first direction, and the third distance is equal to one end of the first photoresist pattern and the one adjacent thereto. The second photoresist pattern may be defined by a maximum distance among the distances between one ends of the second photoresist pattern.

According to one embodiment, at least one of the first photoresist patterns may be connected to and integrated with at least one of the second photoresist patterns.
According to one embodiment, a dummy pattern may not be formed between the first active pattern and the second active pattern.
According to one embodiment, the first gate structure forms a memory cell transistor,
The second gate structure may constitute a peripheral circuit transistor.

According to one embodiment of the present invention, there is provided a semiconductor device including a substrate including a first region, a second region, and a third region between the first and second regions;
The first active pattern protruding from the substrate in the first region, the second active pattern protruding from the substrate in the second region, and the first active pattern may be a first active pattern crossing the first to third regions. The second active patterns extend in one direction and are separated from each other in a second direction intersecting the first direction, and the second active patterns are extended in the first direction and separated from each other in the second direction, and are separated from each other in the second direction. An interval between the first active patterns adjacent to each other is different from an interval between the second active patterns adjacent to each other in the second direction;
A first gate structure traversing the first active pattern, and a second gate structure traversing the second active pattern;
The third region is defined by a trench provided in the substrate between the first and second regions, and the first active pattern is formed at a boundary between the first region and the third region in the second direction. And the second active pattern has sidewalls aligned along the second direction at a boundary between the second region and the third region.

According to one embodiment, a maximum width of the trench along the first direction is substantially equal to a separation distance between the sidewalls of the first and second active patterns in the first direction. Good.
According to one embodiment, the boundary between the first region and the third region is defined by a point where an upper surface of the substrate in the first region contacts one sidewall of the trench when viewed from one end. The boundary between the second region and the third region is defined by a point where the upper surface of the substrate in the second region contacts another side wall of the trench facing the one side wall when viewed from one end. Can be
According to one embodiment, the first gate structure forms a memory cell transistor,
The second gate structure can constitute a peripheral circuit transistor.

  According to the concept of the present invention, when performing a photolithography process for an active pattern formed in a different region, a photoresist pattern having a different pitch is formed so as to be located closest to each other. can do. As a result, the separation between the active patterns formed in different regions can be minimized. This can minimize the chip area overhead.

FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1 is a sectional view taken along lines AI-I'II-II 'and III-III'. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view taken along lines AI-I ′ II-II ′ and III-III ′. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a sectional view taken along lines AI-I 'II-II' and III-III '. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a sectional view taken along lines AI-I ′ II-II ′ and III-III ′. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a sectional view taken along lines AI-I 'II-II' and III-III '. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a sectional view taken along lines AI-I ', II-II' and III-III '. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a sectional view taken along lines AI-I ', II-II' and III-III '. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8 is a sectional view taken along lines AI-I'II-II 'and III-III'. FIG. 6 is a plan view for explaining a modified form of the first and second photoresist patterns. FIG. 9B is a sectional view taken along lines IV-IV ′, V-V ′, and VI-VI ′ of FIG. 9A. 1 is a block diagram of an electronic system including a semiconductor device formed according to an embodiment of the inventive concept. The figure showing the example where an electronic system is applied to a mobile phone.

  Advantages and features of the present invention, and a method of achieving the same will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms. This embodiment is provided merely for the purpose of complete disclosure of the present invention and for completely informing the person skilled in the art to which the present invention belongs to the category of the present invention. It is only defined by the category of the term. Like reference numerals refer to like elements throughout the specification.

  In this specification, when a certain material film such as a conductive film, a semiconductor film, or an insulating film is referred to as being “on” another material film or a substrate, the certain material film is referred to as another material film or This means that it may be formed directly on the substrate or another material film may be interposed between them. Also, in various embodiments herein, the terms first, second, third, etc. are used to describe a material film or process step, but this is merely used to describe any particular material film or process step. Is only used to distinguish it from other material films or other process steps, and should not be limited by such terms.

  The terms used in the specification are for describing the embodiments, and are not intended to limit the present invention. As used herein, the singular includes the plural unless specifically stated otherwise. As used herein, "comprises" and / or "comprising" refer to one or more other components, steps, and / or operations. And / or does not exclude the presence or addition of elements.

  Further, the embodiments described in this specification are described with reference to a cross-sectional view and / or a plan view, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective description of technical contents, and the form of the example diagram may be modified depending on manufacturing techniques and / or tolerances. Therefore, the embodiments of the present invention are not limited to the specific forms illustrated in the drawings, but may include changes in the forms generated by the manufacturing process. For example, the etching region illustrated at right angles may be rounded or have a predetermined curvature. Therefore, the regions illustrated in the drawings have schematic attributes, and the pattern of the regions illustrated in the drawings is for illustrating a specific form of the device region, and is not for limiting the scope of the invention. Absent.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.
1A to 8A are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1B to 8B are cross-sectional views taken along lines II ′, II-II ′, and III-III ′ of FIGS. 1A to 8A, respectively. FIG. 9A is a plan view for explaining a modification of the first and second photoresist patterns. FIG. 9B is a sectional view taken along lines IV-IV ′, VV ′, and VI-VI ′ in FIG. 9A.

  Referring to FIGS. 1A and 1B, a substrate 100 including first to third regions R1 to R3 is provided. The first region R1 and the second region R2 are separated from each other, and the third region R3 is interposed between the first region R1 and the second region R2. The substrate 100 includes a semiconductor material. In this case, the substrate 100 is a semiconductor substrate or an epitaxial layer. As an example, the substrate 100 includes at least one of crystalline silicon, amorphous silicon, doped silicon, and silicon germanium.

  According to one embodiment, the first region R1 is a cell array region in which a plurality of memory cells for storing data are formed. For example, in the first region R1, a plurality of 6T SRAM cells including six transistors or 8T SRAM cells including eight transistors are formed. However, the concept of the present invention is not limited to this. The second region R2 is a part of a peripheral circuit region where a peripheral circuit is formed. For example, the second region R2 is a region where a column decoder or a sense amplifier is formed. That is, a peripheral circuit transistor electrically connected to the memory cell transistor in the first region R1 is formed in the second region R2. The third region R3 is a separation distance required to prevent the transistors in the first and second regions R1 and R2 from interfering with each other when the transistors in the first and second regions R1 and R2 are driven. Corresponds to a buffer area for securing

  A hard mask film 125 and a sacrificial film 130 are sequentially formed on the substrate 100. According to one embodiment, the hard mask layer 125 includes a lower mask layer 110 on the substrate 100 and an upper mask layer 120 on the lower mask layer 110. The lower mask layer 110 is formed of a material having etch selectivity with respect to the substrate 100. For example, the lower mask layer 110 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. The upper mask layer 120 is formed of a material having etch selectivity with respect to the lower mask layer 110. For example, the upper mask layer 120 includes polysilicon. The sacrificial layer 130 is formed of a material having etch selectivity with respect to the upper mask layer 120. For example, the sacrificial layer 130 may include a spin on hard mask (SOH) or an amorphous carbon layer (ACL).

  In the present embodiment, the hard mask film 125 is illustrated as a two-layer laminated structure, but the concept of the present invention is not limited thereto. According to another embodiment, the hard mask layer 125 may include a three-layer structure. Although not shown, an etch stop layer (not shown) may be formed between the upper mask layer 120 and the sacrificial layer 130. The etch stop film includes, for example, SiON.

  A photolithography process is performed on the sacrificial layer 130 to form a photoresist pattern. In detail, the photoresist pattern includes a first photoresist pattern 142 formed in the first region R1 and a second photoresist pattern 144 formed in the second region R2. The first and second photoresist patterns 142 and 144 may be formed by applying a resist material on the sacrificial layer 130 to form a photoresist layer, and performing an exposure and development process on the photoresist layer. Performed and formed. Although not shown, an anti-reflection film (not shown) may be formed on the sacrificial film 130 before forming the photoresist layer. As an example, the anti-reflection film is formed using an organic ARC (active-reflective coating) film. The first and second photoresist patterns 142 and 144 are formed simultaneously.

  According to an exemplary embodiment, the first and second photoresist patterns 142 and 144 have a structure in which line and space patterns are repeatedly arranged. Specifically, the first photoresist pattern 142 has a line shape extending in the first direction D1, and has a first width W1 along the second direction D2. Here, the second direction D2 intersects the first direction D1. In addition, the first photoresist patterns 142 are separated from each other by a first distance greater than the first width W1 in the second direction D2. Here, the separation distance between the first photoresist patterns 142 is defined as a second width W2. Similarly, the second photoresist pattern 144 has a line shape extending in the first direction D1, and has a third width W3 along the second direction D2.

  The second photoresist patterns 144 are separated from each other by a distance greater than the third width W3 in the second direction D2. Here, the separation distance between the second photoresist patterns 144 is defined as a fourth width W4. At this time, the first width W1 is different from the third width W3 (for example, W1 <W3), and the second width W2 is different from the fourth width W4 (for example, W2 <W4). That is, the pitch of the first photoresist pattern 142 is different from that of the second photoresist pattern 144. Although the first and second photoresist patterns 142 and 144 are illustrated as having a constant pitch, the concept of the present invention is not limited thereto.

  According to one embodiment, the first photoresist pattern 142 and the second photoresist pattern 144 are separated from each other along the first direction D1. More specifically, one end of each of the first and second photoresist patterns 142 and 144 is extended into the third region R3, and one end of each of the first and second photoresist patterns 142 and 144 facing each other is They are separated from each other by a fixed distance dp along the first direction D1. According to the concept of the present invention, a separation distance dp between the first and second photoresist patterns 142 and 144 is determined by a light source used in an exposure process for forming the first and second photoresist patterns 142 and 144. Smaller than the wavelength (λ) (ie, dp <λ). In this case, unlike the illustrated example, one ends of the first and second photoresist patterns 142 and 144 may not be properly patterned due to mutual interference of the exposed light.

  For example, the width of one end of the first photoresist pattern 142 is larger or smaller than the first width W1, and the width of one end of the second photoresist pattern 144 is larger or smaller than the third width W3. On the other hand, unlike the illustrated example, the distance between the first and second photoresist patterns 142 and 144 may not be constant. In this case, the separation distance dp between the first and second photoresist patterns 142 and 144 is the first direction D1 between one end of the first photoresist pattern 142 and one end of the second photoresist pattern 144 adjacent thereto. Is defined as the largest separation distance among the separation distances along.

  According to another embodiment, as shown in FIGS. 9A and 9B, opposing ends of the first and second photoresist patterns 142 and 144 may be connected to each other to form one body. That is, the connection photoresist pattern 146 is interposed between one ends of the first and second photoresist patterns 142 and 144. The connection photoresist pattern 146 is formed as one type of pattern defect generated by forming the first and second photoresist patterns 142 and 144 having different pitches close to each other. is there. That is, one ends of the first and second photoresist patterns 142 and 144 are connected to each other due to a bridge failure generated by mutual interference of the exposed light.

  In this embodiment, the connection photoresist pattern 146 is illustrated as having a flat plate shape in which one end of each of the plurality of first and second photoresist patterns 142 and 144 is connected to each other and integrated. The inventive concept is not so limited. Unlike the illustrated example, the connection photoresist pattern 146 may have a shape in which one end of one first photoresist pattern 142 and one end of one second photoresist pattern 144 are connected to each other to form one body. .

  The shape of the sacrificial pattern, the spacer, the hard mask pattern, and the preliminary active pattern, which will be formed later according to the shape of the photoresist pattern described above, is partially different, but the shape of the finally formed active pattern is a photoresist pattern. Are substantially the same irrespective of the difference in shape. Also, a series of steps for forming such an active pattern is substantially the same regardless of the difference in the shape of the photoresist pattern. Hereinafter, for simplicity, the description will be made based on the shapes of the first and second photoresist patterns formed in FIGS. 1A and 1B.

  Referring to FIGS. 2A and 2B, the sacrificial layer 130 exposed by the first and second photoresist patterns 142 and 144 (see FIGS. 1A and 1B) is patterned, and the first and second sacrificial patterns 132 are formed. 134 is formed. The patterning of the sacrificial layer 130 is performed using, for example, an anisotropic dry etching process using the first and second photoresist patterns 142 and 144 as an etching mask. Accordingly, the first sacrificial pattern 132 is formed by transferring the shape of the first photoresist pattern 142, and the second sacrificial pattern 134 is formed by transferring the shape of the second photoresist pattern 144. That is, like the first and second photoresist patterns 142 and 144, the first and second sacrificial patterns 132 and 134 have a structure in which line and space patterns are repeatedly arranged.

  The width and the separation distance of the first sacrificial pattern 132 are substantially the same as those of the first photoresist pattern 142. Similarly, the width and the separation distance of the second sacrificial pattern 134 are substantially the same as those of the second photoresist pattern 144. The first sacrificial patterns 132 have a first width W1, and adjacent first sacrificial patterns 132 are separated from each other by a second width W2. The second sacrificial patterns 134 have a third width W3, and the adjacent second sacrificial patterns 134 are separated from each other by a fourth width W4.

  Subsequently, a first spacer 152 covering the side wall of the first sacrificial pattern 132 and a second spacer 154 covering the side wall of the second sacrificial pattern 134 are formed. According to an exemplary embodiment, the first and second spacers 152 and 154 may be formed on the substrate 100 by forming a spacer layer that conformally covers the first and second sacrificial patterns 132 and 134, and then the upper mask layer 120 may be exposed. Until the spacer film is formed by performing an anisotropic etching process on the entire surface of the spacer film. The first and second spacers 152 and 154 formed as described above surround the entire sidewalls of the first and second sacrificial patterns 132 and 134, respectively. The spacer film includes, for example, silicon oxide. Such a spacer film is formed by an ALD (Atomic Layer Deposition) process.

  On the other hand, the interval between the first spacers 152 adjacent in the second direction D2 has a fifth width W5, and the interval between the second spacers 154 adjacent in the second direction D2 has a sixth width W6. Here, the fifth width W5 is defined as the minimum distance between the side walls of the first spacer 152 facing each other in the second direction D2, and the sixth width W6 is defined as the distance between the side walls of the second spacer 154 facing each other in the second direction D2. Is defined as the minimum distance of According to one embodiment, the fifth width W5 is substantially equal to the first width W1, and the sixth width W6 is substantially equal to the third width W3. The fifth width W5 is realized by adjusting the first width W1, the second width W2, and the thickness of the spacer layer. Similarly, the sixth width W6 is realized by adjusting the third width W3, the fourth width W4, and the thickness of the spacer film.

  Referring to FIGS. 3A and 3B, the first and second sacrificial patterns 132 and 134 (see FIGS. 2A and 2B) are removed. According to one embodiment, the removal of the first and second sacrificial patterns 132 and 134 is performed using, for example, an ashing and / or stripping process.

  Subsequently, the upper mask layer 120 is etched by an etching process using the first and second spacers 152 and 154 as an etching mask, thereby forming first and second upper mask patterns 122 and 124. The first and second upper mask patterns 122 and 124 have a shape obtained by transferring the shapes of the first and second spacers 152 and 154, respectively. Although only one end of each of the first and second upper mask patterns 122 and 124 is shown, the other end has the same shape as the one end. In conclusion, each of the first upper mask patterns 122 has a closed curve shape in which a pair of line patterns extending parallel to the first direction D1 are connected to each other at both ends. According to one embodiment, the distance between the inner walls of the first upper mask pattern 122 is substantially equal to the first width W1 of the first sacrificial pattern 132. In addition, the interval between the first upper mask patterns 122 adjacent to each other in the second direction D2 is substantially equal to the fifth width W5.

  Similarly, each of the second upper mask patterns 124 has a closed curve shape in which a pair of line patterns extending parallel to the first direction D1 are connected to each other at both ends. According to one embodiment, the distance between the inner walls of the second upper mask pattern 124 is substantially equal to the third width W3 of the second sacrificial pattern 134. In addition, the distance between the second upper mask patterns 124 adjacent to each other in the second direction D2 is substantially equal to the sixth width W6. Meanwhile, even after the etching process for forming the upper mask pattern is completed, the first and second spacers 152 and 154 remain on the first and second upper mask patterns 122 and 124.

  4A and 4B, the first and second lower mask patterns 112 and 114 are formed by etching the lower mask layer 110 in an etching process using the first and second upper mask patterns 122 and 124 as an etching mask. It is formed. The first and second lower mask patterns 112 and 114 have substantially the same shape as the first and second upper mask patterns 122 and 124, respectively. Here, the first upper mask pattern 122 and the first lower mask pattern 112 constitute a first hard mask pattern 127, and the second upper mask pattern 124 and the second lower mask pattern 114 constitute a second hard mask pattern 129. . According to one embodiment, the first and second spacers 152 and 154 are removed during an etching process for forming the first and second lower mask patterns 112 and 114, or the first and second spacers 152 and 154 are removed. It is removed before forming the second lower mask patterns 112 and 114.

  5A and 5B, the substrate 100 is etched using the first hard mask pattern 127 (see FIGS. 4A and 4B) and the second hard mask pattern 129 (see FIGS. 4A and 4B) as an etching mask. By etching the upper portion, a first trench T1 defining first and second preliminary active patterns AP1a and AP2a is formed. The first preliminary active pattern AP1a is formed in the first region R1, and the second preliminary active pattern AP2a is formed in the second region R2. The first preliminary active pattern AP1a has substantially the same shape as the first upper mask pattern 122 and the first lower mask pattern 112 when viewed from a plane.

  Specifically, each of the first preliminary active patterns AP1a is connected to each other at one end of each of the pair of first line patterns L1 and the pair of first line patterns L1 extending in parallel with the first direction D1. The first connection pattern C1 is included. Such a part of the first line pattern L1 and the first connection pattern C1 are located in the third region R3. The interval between the pair of first line patterns L1 is substantially equal to the first width W1 of the first sacrificial pattern 132. In addition, the interval between the first preliminary active patterns AP1a adjacent to each other in the second direction D2 is substantially equal to the fifth width W5. According to one embodiment, the first width W1 is substantially the same as the fifth width W5.

  Similarly, the second preliminary active pattern AP2a has substantially the same shape as the second upper mask pattern 124 and the second lower mask pattern 114 when viewed from above. Specifically, each of the second preliminary active patterns AP2a is connected to each other at one end of each of the pair of second line patterns L2 and the pair of second line patterns L2 extending parallel to the first direction D1. The second connection pattern C2 is included. Such a part of the second line pattern L2 and the second connection pattern C2 are located in the third region R3. The interval between the pair of second line patterns L2 is substantially equal to the third width W3 of the second sacrificial pattern 132. In addition, the interval between the second preliminary active patterns AP2a adjacent to each other in the second direction D2 is substantially equal to the sixth width W6. According to one embodiment, the third width W3 is substantially the same as the sixth width W6. The first and second preliminary active patterns AP1a and AP2a have a shape protruding from the substrate 100 in a direction perpendicular to the upper surface of the substrate 100 when viewed from one end. After forming the first and second preliminary active patterns AP1a and AP2a, the remaining first and second upper mask patterns 122 and 124 and / or the first and second lower mask patterns 112 and 114 are removed.

  Referring to FIGS. 6A and 6B, a first mask pattern 160 is formed on the substrate 100. The first mask pattern 160 exposes the entire third region R3. That is, when viewed from a plane, the first mask pattern 160 does not overlap with the third region R3. Accordingly, a part of the first preliminary active pattern AP1a (that is, a part of the first line pattern L1 and the first connection pattern C1) and a part of the second preliminary active pattern AP2a (that is, one part of the second line pattern L2). The portion and the second connection pattern C2) are exposed by the first mask pattern 160. The first mask pattern 160 includes, for example, an SOH material. Although not shown, the first mask pattern 160 also exposes the other ends of the first and second preliminary active patterns AP1a and AP2a.

  7A and 7B, an etching process using the first mask pattern 160 as an etching mask is performed to form a second trench T2. The second trench T2 extends further below the substrate 100 than the first trench T1. That is, the lower surface of the second trench T2 is lower than the lower surface of the first trench T1. While the etching process is performed, a part of the first preliminary active pattern AP1a exposed by the first mask pattern 160 (that is, a part of the first line pattern L1 and the first connection pattern C1) and the first preliminary active pattern AP1a are exposed. A part of the second preliminary active pattern AP2a (that is, a part of the second line pattern L2 and the second connection pattern C2) is removed. As a result, first and second active patterns AP1b and AP2b are formed from the first and second preliminary active patterns AP1a and AP2a, respectively. Hereinafter, a series of steps for removing a part of the first preliminary active pattern AP1a and a part of the second preliminary active pattern AP2a is referred to as a fin cut step.

  The first active patterns AP1b thus formed have a line shape extending in the first direction D1, and are separated from each other in the second direction D2. Similarly, the second active patterns AP2b extend in the first direction D1 and are separated from each other in the second direction D2. The distance between the first active patterns AP1b along the second direction D2 corresponds to the first width W1 and the fifth width W5 of the first preliminary active pattern AP1a. When the first width W1 and the fifth width W5 are substantially the same, the distance between the first active patterns AP1b along the second direction D2 has a constant distance of the first distance d1. The distance between the second active patterns AP2b along the second direction D2 corresponds to the third width W3 and the sixth width W6 of the second preliminary active pattern AP2a. When the third width W3 and the sixth width W6 are substantially the same, the distance between the second active patterns AP2b along the second direction D2 has a constant distance of the second distance d2. In the present embodiment, the first distance d1 is different from the second distance d2. As an example, the second distance d2 is larger than the first distance d1.

  After forming the second trench T2, the first mask pattern 160 is removed. Removing the first mask pattern 160 is performed using, for example, an ashing and / or stripping process. Thereafter, an element isolation pattern ST filling the first and second trenches T1 and T2 is formed. For example, forming the element isolation pattern ST includes forming an element isolation film filling the first and second trenches T1 and T2 on the substrate 100 and flattening the element isolation film until the substrate 100 is exposed. To include The upper portions of the device isolation patterns ST are etched to expose the upper portions of the first and second active patterns AP1b and AP2b. The upper portions of the first and second active patterns AP1b and AP2b exposed by the device isolation pattern ST are defined as first and second active fins AF1 and AF2, respectively. According to one embodiment, before forming the isolation patterns ST, unnecessary first active patterns AP1b 'are removed. In order to remove the unnecessary first active pattern AP1b ', for example, a mask pattern (not shown) exposing the unnecessary first active pattern AP1b' is formed, and this is used as an etching mask. Including performing.

  The first active pattern AP1b formed as described above has sidewalls aligned along the second direction D2 at a boundary between the first region R1 and the third region R3. Here, the boundary between the first region R1 and the third region R3 is a point where, when viewed from one end, the upper surface of the substrate 100 in the first region R1 is in contact with the side wall of the second trench T2 adjacent to the first region R1. Is defined by Similarly, the second active pattern AP2b has sidewalls aligned along the second direction D2 at a boundary between the second region R2 and the third region R3. Here, the boundary between the second region R2 and the third region R3 is a point where, when viewed from one end, the upper surface of the substrate 100 in the second region R2 is in contact with the side wall of the second trench T2 adjacent to the second region R2. Is defined by As a result, the distance dap between the side walls of the first and second active patterns AP1b and AP2b facing each other defines the width of the third region R3 along the first direction D1.

  In addition, the distance dap between the side walls of the first and second active patterns AP1b and AP2b facing each other is substantially the same as the width of the second trench T2 along the first direction D1. That is, the width of the second trench T2 along the first direction D1 defines the width of the third region R3 along the first direction D1. On the other hand, unlike the illustrated one, the second trench T2 has a sidewall profile whose width decreases toward the lower surface. In this case, the width of the second trench T2 is defined by the width having the maximum value of the width. The width of the third region R3 is designed as a minimum distance that allows the transistors of the first and second regions R1 and R2 (ie, fin field effect transistors) to be driven without interference between each other. You.

  In general, the first and second active patterns AP1b and AP2b having different pitches are formed apart from each other more than necessary due to the limitation of resolution of a photolithography process for forming the first and second active patterns. This causes an increase in chip area overhead. However, according to the concept of the present invention, when performing the photolithography process for the first and second active patterns AP1b and AP2b, the first and second photoresist patterns 142 and 144 are located close to each other at a maximum. Can be formed. As a result, the distance between the first and second active patterns AP1b and AP2b to be formed later can be minimized. Even if a pattern failure occurs in a part of the first and second preliminary active patterns AP1a and AP2a which are formed later due to the pattern failure of the first and second photoresist patterns, such a pattern failure part is not shown in FIG. 7A. And can be removed by the fin cut process described with reference to FIG. As a result, the transistors formed in the first and second regions R1 and R2 can secure a minimum separation distance that does not interfere with each other, and can minimize the area of the third region R3. Accordingly, it is possible to minimize the chip area overhead while securing the driving characteristics of the transistors in the first and second regions R1 and R2.

  Referring to FIGS. 8A and 8B, first and second gate structures GS1 and GS2 crossing the first and second active patterns AP1b and AP2b are formed on the substrate 100, respectively. Each of the first gate structures GS1 includes a first gate dielectric pattern GD1 and a first gate electrode GE1 sequentially stacked on the substrate 100. Each of the second gate structures GS2 includes a second gate dielectric pattern GD2 and a second gate electrode GE2 sequentially stacked on the substrate 100. According to one embodiment, forming the first and second gate structures GS1 and GS2 includes forming a first interlayer insulating film 170 having an opening, and forming a gate dielectric film and a gate electrode film in the opening. In order. According to another embodiment, forming the first and second gate structures GS1 and GS2 includes patterning a gate dielectric film and a gate electrode film sequentially stacked on the substrate 100.

  In this case, the first interlayer insulating film 170 is formed after forming the first and second gate structures GS1 and GS2. The first and second gate dielectric patterns GD1 and GD2 include a silicon oxide film, a silicon oxynitride film, or a high dielectric film having a higher dielectric constant than the silicon oxide film. The first and second gate electrodes GE1 and GE2 include at least one of a doped semiconductor, a metal, and a conductive metal nitride. The first interlayer insulating film 170 includes, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride. Although not shown, gate spacers are formed on both side walls of each of the first and second gate structures GS1 and GS2.

  First source / drain regions are formed on the first active patterns AP1b on both sides of each of the first gate structures GS1, and second source / drain regions are formed on the second active patterns AP2b on both sides of each of the second gate structures GS2. A drain region is formed. Here, the first gate structure GS1 and the first source / drain regions form the memory cell transistors of the cell array described with reference to FIGS. 1A and 1B. In addition, the first active fins AF1 disposed below each of the first gate structures GS1 correspond to a channel region of the memory cell transistor. In addition, the second gate structure GS2 and the second source / drain regions constitute a peripheral circuit transistor of the peripheral circuit described with reference to FIGS. 1A and 1B. The second active fins AF2 disposed below each of the second gate structures GS2 correspond to a channel region of a peripheral circuit transistor.

  Thereafter, a first contact CT1 for applying a voltage to the first source / drain region and a second contact CT2 for applying a voltage to the second source / drain region are formed. The first and second contacts CT1 and CT2 are formed in the second interlayer insulating film 180 covering the upper surfaces of the first and second gate structures GS1 and GS2. For example, the second interlayer insulating film 180 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride.

  According to the concept of the present invention, by forming the third region R3 so as to have a minimum width, the third region R3 is formed in the third region R3 in the process of forming the first and second gate structures GS1 and GS2. Forming a dummy pattern (ie, a dummy gate structure) can be omitted. That is, the dummy pattern may not be interposed between the substrate 100 and the first interlayer insulating film 170 in the third region R3.

8A and 8B, a semiconductor device according to example embodiments will be described.
Referring to FIGS. 8A and 8B, the substrate 100 includes first to third regions R1 to R3. The first region R1 and the second region R2 are separated from each other, and the third region R3 is interposed between the first region R1 and the second region R2. The substrate 100 includes a semiconductor material. In this case, the substrate 100 is a semiconductor substrate or an epitaxial layer. As an example, the substrate 100 includes at least one of crystalline silicon, amorphous silicon, doped silicon, and silicon germanium.

  According to one embodiment, the first region R1 is a cell array region where a plurality of memory cells for storing data are arranged. As an example, a plurality of 6T SRAM SRAM cells including six transistors or 8T SRAM cells including eight transistors are arranged in the first region R1. However, the concept of the present invention is not limited to this. The second region R2 is a part of the peripheral circuit region where the peripheral circuits are arranged. For example, the second region R2 is a region where a column decoder or a sense amplifier is arranged. That is, a peripheral circuit transistor electrically connected to the memory cell transistor in the first region R1 is disposed in the second region R2. The third region R3 is a separation distance required to prevent the transistors in the first and second regions R1 and R2 from interfering with each other when the transistors in the first and second regions R1 and R2 are driven. Corresponds to a buffer area for securing

  A first active pattern AP1b protruding from the substrate 100 is disposed on the substrate 100 in the first region R1. The first active patterns AP1b have a line shape extending in the first direction D1, and are separated from each other in the second direction D2. A second active pattern AP2b protruding from the substrate 100 is disposed on the substrate 100 in the second region R2. The second active patterns AP2b have a line shape extending in the first direction D1, and are separated from each other in the second direction D2. According to one embodiment, the distance between the first active patterns AP1b along the second direction D2 is different from the distance between the second active patterns AP2b along the second direction D2. For example, the distance between the first active patterns AP1b adjacent to each other in the second direction D2 has a first distance d1, and the distance between the second active patterns AP2b adjacent to each other in the second direction D2 is greater than the first distance d1. It has a large second distance d2. The first and second active patterns AP1b and AP2b are separated from each other in the first direction D1 via the third region R3.

  Meanwhile, the third region R3 is defined by a second trench T2 provided in the substrate 100 between the first and second regions R1 and R2. That is, the upper surface of the substrate 100 in the third region R3 is located at a lower level than the upper surface of the substrate 100 in the first and second regions R1 and R2. According to one embodiment, the first active pattern AP1b has a sidewall aligned along the second direction D2 at a boundary between the first region R1 and the third region R3. Here, the boundary between the first region R1 and the third region R3 is a point where, when viewed from one end, the upper surface of the substrate 100 in the first region R1 is in contact with the side wall of the second trench T2 adjacent to the first region R1. Is defined by In addition, the second active pattern AP2b has a side wall that is aligned along the second direction D2 at a boundary between the second region R2 and the third region R3. Here, the boundary between the second region R2 and the third region R3 is a point where, when viewed from one end, the upper surface of the substrate 100 in the second region R2 is in contact with the side wall of the second trench T2 adjacent to the second region R2. Is defined by

  The distance dap between the side walls of the first and second active patterns AP1b and AP2b facing each other defines the width of the third region R3 along the first direction D1. In addition, the distance dap between the side walls of the first and second active patterns AP1b and AP2b facing each other is substantially the same as the width of the second trench T2 along the first direction D1. That is, the width of the second trench T2 along the first direction D1 defines the width of the third region R3 along the first direction D1. On the other hand, unlike the illustrated one, the second trench T2 has a sidewall profile whose width decreases toward the lower surface. In this case, the width of the second trench T2 is defined by the width having the maximum value of the width. The width of the third region R3 is designed as a minimum distance that allows the transistors in the first and second regions R1 and R2 to be driven without interference between each other.

  An element isolation pattern ST is arranged on a substrate 100. The device isolation pattern ST of the first region R1 exposes an upper portion of the first active pattern AP1b. The device isolation pattern ST in the second region R2 exposes the upper portion of the second active pattern AP2b. Here, upper portions of the first and second active patterns AP1b and AP2b exposed by the device isolation pattern ST are defined by a first active fin AF1 and a second active fin AF2, respectively. The element isolation pattern ST in the third region R3 fills the second trench T2.

  A first gate structure GS1 crossing the first active pattern AP1b is disposed on the substrate 100 in the first region R1, and a second gate structure GS2 crossing the second active pattern AP2b on the substrate 100 in the second region R2. Are located. Each of the first gate structures GS1 includes a first gate dielectric pattern GD1 covering an upper surface and side walls of the first active pattern AP1b, and a first gate electrode GE1 on the first gate dielectric pattern GD1. The first gate dielectric pattern GD1 and the first gate electrode GE1 extend in the second direction D2. Each of the second gate structures GS2 includes a second gate dielectric pattern GD2 covering an upper surface and a side wall of the second active pattern AP2b, and a second gate electrode GE2 on the second gate dielectric pattern GD2. The second gate dielectric pattern GD2 and the second gate electrode GE2 extend in the second direction D2. The first and second gate dielectric patterns GD1 and GD2 include a silicon oxide film, a silicon oxynitride film, or a high dielectric film having a higher dielectric constant than the silicon oxide film. The first and second gate electrodes GE1 and GE2 include at least one of a doped semiconductor, a metal, and a conductive metal nitride. Although not shown, gate spacers may be disposed on both side walls of each of the first and second gate structures GS1 and GS2.

  First source / drain regions are disposed on the first active patterns AP1b on both sides of each of the first gate structures GS1, and second source / drain regions are disposed on the second active patterns AP2b on both sides of each of the second gate structures GS2. A drain region is provided. Here, the first gate structure GS1 and the first source / drain regions form a memory cell transistor of the cell array. In addition, the first active fins AF1 disposed below each of the first gate structures GS1 correspond to a channel region of the memory cell transistor. Further, the second gate structure GS2 and the second source / drain region constitute a peripheral circuit transistor of the peripheral circuit. The second active fins AF2 disposed below each of the second gate structures GS2 correspond to a channel region of a peripheral circuit transistor.

  The first interlayer insulating film 170 is disposed on the substrate 100. The first interlayer insulating film 170 covers sidewalls of the first and second gate structures GS1 and GS2. Second interlayer insulating film 180 is disposed on first interlayer insulating film 170. The second interlayer insulating film 180 covers the upper surfaces of the first and second gate structures GS1 and GS2. Each of the first and second interlayer insulating films 170 and 180 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride. In the second interlayer insulating film 180, a first contact CT1 for applying a voltage to the first source / drain region and a second contact CT2 for applying a voltage to the second source / drain region are arranged.

FIG. 10 is a block diagram of an electronic system including a semiconductor device formed according to an exemplary embodiment.
Referring to FIG. 10, an electronic system 1100 according to an exemplary embodiment includes a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 are connected to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

  The controller 1110 includes at least one of a microprocessor, a digital signal process, a microcontroller, and a logic device capable of performing similar functions. The input / output device 1120 includes a keypad, a keyboard, a display device, and the like. The storage device 1130 stores data and / or command words. The interface 1140 performs a function of transmitting data to the communication network or receiving data from the communication network. Interface 1140 is in a wired or wireless form. For example, the interface 1140 includes an antenna or a wired / wireless transceiver. Although not shown, the electronic system 1100 further includes a high-speed DRAM and / or SRAM as an operation memory for improving the operation of the controller 1110. The semiconductor device according to the embodiment of the present invention may be provided in the storage device 1130 or may be provided as a part of the controller 1110, the input / output device 1120, the I / O, and the like.

  The electronic system 1100 includes a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player. The present invention can be applied to a music player, a memory card, or any electronic product that can transmit and / or receive information in a wireless environment.

  The electronic system (1100 in FIG. 10) can be applied to electronic control devices of various electronic devices. FIG. 11 illustrates an example in which the electronic system (1100 in FIG. 10) is applied to a mobile phone 1200. In addition, the electronic system (1100 in FIG. 10) may be applied to a portable notebook computer, an MP3 player, a navigation, a solid state disk (SSD), an automobile or a household appliance (Household appliances). be able to.

  As described above, the embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art to which the present invention pertains do not modify the technical idea and essential features of the present invention. It can be understood that the present invention can be implemented in other specific modes. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects, and not limiting.

DESCRIPTION OF SYMBOLS 100 Substrate 110 Lower mask film 120 Upper mask film 125 Hard mask film 130 Sacrificial film 132 First sacrificial pattern 134 Second sacrificial pattern 142 First photoresist pattern 144 Second photoresist pattern 152 First spacer 154 Second spacer AF1 First Active fin AF2 Second active fin AP1a First preliminary active pattern AP2a Second preliminary active pattern ST Element isolation pattern T1 First trench T2 Second trench

Claims (24)

Providing a substrate including a first region, a second region, and a third region between the first region and the second region;
Forming first and second preliminary active patterns protruding from the substrate on the substrate in the first and second regions, respectively, wherein the first and second preliminary active patterns are Including overlapping parts,
Forming a mask pattern on the substrate that exposes the third region, wherein the mask pattern does not overlap with the third region when viewed from a plane;
Performing a first etching process using the mask pattern as an etching mask to form first and second active patterns from the first and second preliminary active patterns, respectively;
Forming a gate structure on the substrate, the gate structure including: a first gate structure traversing the first active pattern; and a second gate structure traversing the second active pattern.
The first active patterns extend in a first direction, which is a direction crossing the first to third regions, and are separated from each other in a second direction that intersects the first direction. The distance between the first active patterns extending in one direction and separated from each other in the second direction, and the distance between the first active patterns adjacent to each other in the second direction is equal to the distance between the second active patterns adjacent to each other in the second direction. different Ri,
A second trench is formed in the third region by the first etching process;
A lower surface of the second trench is lower than a lower surface of the first trench defining the first and second preliminary active patterns;
The method of manufacturing a semiconductor device according to claim 1, wherein a maximum width of the second trench along the first direction defines a width of the third region along the first direction . Each of the first preliminary active patterns connects the pair of first line patterns to each other at one end of each of the pair of first line patterns extending in parallel with the first direction and each of the pair of first line patterns. A first connection pattern, wherein the first connection pattern is overlapped with the third region;
Each of the second preliminary active patterns connects the pair of second line patterns to each other at one end of each of the pair of second line patterns and the pair of second line patterns extending parallel to the first direction. The method of claim 1, further comprising a second connection pattern, wherein the second connection pattern overlaps the third region.   3. The method of claim 2, wherein the first and second connection patterns are removed by the first etching process.   3. The method according to claim 2, wherein an interval between the pair of first line patterns is different from an interval between the pair of second line patterns. An interval between the first preliminary active patterns adjacent to each other is substantially the same as the interval between the pair of first line patterns;
5. The method of claim 4, wherein an interval between the second pre-active patterns adjacent to each other is substantially the same as the interval between the pair of second line patterns. Forming the first and second preliminary active patterns includes:
Forming a hard mask film on the substrate;
Forming a sacrificial pattern on the hard mask film, wherein the sacrificial pattern includes a first sacrificial pattern provided in the first region and a second sacrificial pattern provided in the second region;
Forming first and second spacers on sidewalls of the first and second sacrificial patterns, respectively;
Removing the first and second sacrificial patterns;
Etching the hard mask layer exposed by the first and second spacers to form a first hard mask pattern provided in the first region and a second hard mask pattern provided in the second region; When,
2. The method of claim 1, further comprising: etching the upper portion of the substrate using the first and second hard mask patterns as an etching mask to form first trenches defining the first and second preliminary active patterns. A method for manufacturing a semiconductor device. Forming the first and second sacrificial patterns comprises:
Forming a sacrificial film on the hard mask film;
A photolithography process using a first wavelength exposure source is performed on the sacrificial layer to form a first photoresist pattern provided in the first region and a second photoresist pattern provided in the second region. Forming and
7. The method of claim 6, further comprising: etching the sacrificial layer using the first and second photoresist patterns as an etching mask. The first photoresist pattern has a structure in which a first pitch line and space pattern is repeatedly arranged,
The second photoresist pattern is spaced apart from the first photoresist pattern by a first distance in the first direction, and a line and space pattern having a second pitch different from the first pitch is repeatedly arranged. Have
The method according to claim 7, wherein the first distance is smaller than the first wavelength. The first and second photoresist patterns include one end extending to the third region,
9. The semiconductor device of claim 8, wherein the first distance is defined by a maximum separation distance between one end of the first photoresist pattern and one end of the second photoresist pattern adjacent thereto. Manufacturing method.   8. The method of claim 7, wherein at least one of the first photoresist patterns is connected to and integrated with at least one of the second photoresist patterns. The hard mask film includes a lower mask film and an upper mask film sequentially stacked on the substrate,
7. The method of claim 6, wherein etching the hard mask layer includes sequentially etching the upper mask layer and the lower mask layer.   2. The method according to claim 1, wherein the gate structure is not formed in the third region. The first gate structure constitutes a memory cell transistor;
2. The method according to claim 1, wherein the second gate structure forms a peripheral circuit transistor. Patterning a substrate to form a first trench defining a preliminary active pattern, wherein the preliminary active pattern extends in a first direction and is spaced apart from each other in a second direction intersecting the first direction; A preliminary activation pattern, and a second preliminary activation pattern that is spaced apart from the first preliminary activation pattern in the first direction, extends in the first direction, and is spaced apart from each other in the second direction. An interval between the first preliminary active patterns adjacent to each other is different from an interval between the second preliminary active patterns adjacent to each other in the second direction;
Forming a mask pattern on the substrate exposing one ends of the first and second preliminary active patterns facing each other in the first direction;
Removing the one end in an etching process using the mask pattern as an etching mask to form first and second active patterns from the first and second preliminary active patterns;
Forming a first gate structure across the first active pattern and a second gate structure across the second active pattern on the substrate;
A second trench having a lower surface lower than the lower surface of the first trench is formed by the etching process, and a separation distance in the first direction between the first and second active patterns is equal to the first distance of the second trench. A method for manufacturing a semiconductor device defined by a width along a direction. Each of the preliminary active patterns includes a pair of first line patterns extending in parallel with the first direction and a first connecting the pair of first line patterns at one end of each of the pair of first line patterns. Including the connection pattern,
Each of the second preliminary active patterns connects the pair of second line patterns to each other at one end of each of the pair of second line patterns extending in parallel with the first direction and the pair of second line patterns. The method of claim 14 , further comprising a second connection pattern, wherein the first and second connection patterns correspond to the one ends of the first and second preliminary active patterns, respectively. The interval between the first preliminary active patterns adjacent to each other in the second direction is substantially the same as the interval between the pair of first line patterns,
The method of claim 15 , wherein the distance between the second preliminary active patterns adjacent to each other in the second direction is substantially equal to the distance between the pair of second line patterns. Forming the first trench comprises:
Sequentially forming a lower mask film and an upper mask film on the substrate;
Forming a sacrificial pattern on the upper mask film, wherein the sacrificial pattern includes a first sacrificial pattern provided in a first region and a second sacrificial pattern provided in a second region ;
Forming first and second spacers on sidewalls of the first and second sacrificial patterns, respectively;
Etching the upper mask layer using the first and second spacers as an etching mask to form first and second upper mask patterns in the first and second regions, respectively;
Etching the lower mask film using the first and second upper mask patterns as an etching mask to form first and second lower mask patterns in the first and second regions, respectively;
The method of claim 14 , further comprising etching an upper portion of the substrate using the first and second lower mask patterns as an etching mask. Forming the first and second sacrificial patterns comprises:
Forming a sacrificial film on the upper mask film;
A photolithography process using a first wavelength exposure source is performed on the sacrificial layer to form a first photoresist pattern provided in the first region and a second photoresist pattern provided in the second region. Forming and
The method of claim 17 , further comprising etching the sacrificial layer using the first and second photoresist patterns as an etching mask. The first photoresist pattern extends in the first direction and is spaced apart from the second direction by a first distance.
The second photoresist pattern extends in the first direction and is spaced apart from the first photoresist pattern by a second distance different from the first distance in the second direction. 20. The method of claim 18 , wherein the first direction is separated by a third distance smaller than the first wavelength. The first gate structure constitutes a memory cell transistor;
The method of claim 14 , wherein the second gate structure forms a peripheral circuit transistor. A substrate including a first region, a second region, and a third region between the first and second regions;
The first active pattern protruding from the substrate in the first region, the second active pattern protruding from the substrate in the second region, and the first active pattern may be a first active pattern crossing the first to third regions. The second active patterns extend in one direction and are separated from each other in a second direction intersecting the first direction, and the second active patterns are extended in the first direction and separated from each other in the second direction, and are separated from each other in the second direction. An interval between the first active patterns adjacent to each other is different from an interval between the second active patterns adjacent to each other in the second direction;
A first gate structure traversing the first active pattern, and a second gate structure traversing the second active pattern;
The third region is defined by a trench provided in the substrate between the first and second regions, and the first active pattern is formed at a boundary between the first region and the third region in the second direction. A semiconductor device having sidewalls aligned along the second direction, and wherein the second active pattern has sidewalls aligned along the second direction at a boundary between the second region and the third region. 22. The semiconductor device of claim 21 , wherein a maximum width of the trench in the first direction is substantially equal to a distance between the sidewalls of the first and second active patterns in the first direction. The boundary between the first region and the third region is defined by a point where the upper surface of the substrate in the first region contacts one sidewall of the trench when viewed from one end,
The boundary between the second region and the third region is defined by a point where, when viewed from one end, the upper surface of the substrate in the second region contacts another side wall of the trench facing the one side wall. A semiconductor device according to claim 21 . The first gate structure constitutes a memory cell transistor;
22. The semiconductor device according to claim 21 , wherein the second gate structure forms a peripheral circuit transistor.

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