JP6665889B2 - 電気光学装置および電子機器 - Google Patents
電気光学装置および電子機器 Download PDFInfo
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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Description
1−1.第1実施形態
1−1a.基本構成
図1は、第1実施形態に係る電気光学装置1の平面図である。図2は、第1実施形態に係る電気光学装置1の断面図である。図1および図2に示す電気光学装置1は、TFT(Thin Film Transistor)をスイッチング素子として用いるアクティブマトリックス方式の透過型液晶装置である。以下、図1および図2に基づいて、電気光学装置1の基本構成を説明する。なお、以下では、説明の便宜上、図1および図2のそれぞれに示す互いに直交するx軸、y軸、およびz軸を適宜用いて説明する。また、図2は、図1中のA−A線断面図である。
図3は、第1実施形態における素子基板2の電気的な構成を示す等価回路図である。図3に示すように、素子基板2には、n本の走査線244とm本の信号線246とn本の容量線245とが形成される。ただし、nおよびmは2以上の整数である。n本の走査線244とm本の信号線246との各交差に対応してスイッチング素子であるトランジスター23が配置される。
図4は、第1実施形態における素子基板2の一部を示す平面図である。図4に示すように、素子基板2において、トランジスター23は、平面視で信号線246と走査線244とが交差する交差部に重なって配置される。なお、図4では図示を省略するが、平面視で当該交差部には、蓄積容量20も重なって配置される。
次に、本発明の第2実施形態について説明する。本実施形態は、第1部分および第2部分を有する配線の電位が異なる以外は、第1実施形態と同様である。なお、以下の説明では、第2実施形態に関し、第1実施形態との相違点を中心に説明し、同様の事項に関してはその説明を省略する。また、図9において、第1実施形態と同様の構成については、同一符号を付す。
電気光学装置1は、各種電子機器に用いることができる。
Claims (8)
- 基材と、
画素電極と、
ゲート電極と半導体層とを含むトランジスターと、
前記画素電極と前記トランジスターとの間に配置される絶縁性の第1層と、
前記画素電極と前記第1層との間に配置される配線部と、前記第1層を貫通して前記ゲート電極と電気的に接続されるとともに、平面視で前記半導体層の両側にそれぞれ配置される壁部と、を含む走査線と、
前記画素電極と前記走査線との間に配置される絶縁性の第2層と、
前記画素電極と前記第2層との間に配置される絶縁性の第3層と、
前記第2層と前記第3層との間に配置され、平面視で前記ゲート電極に重なる第1部分と、平面視で前記半導体層の両側にそれぞれ配置された前記壁部の間において、前記第2層を貫通して設けられた開口内に配置される第2部分と、を含み、遮光性を有するとともに固定電位が印加される配線と、を有する、電気光学装置。 - 基材と、
画素電極と、
ゲート電極と半導体層とを含むトランジスターと、
前記画素電極と前記トランジスターとの間に配置される絶縁性の第1層と、
前記画素電極と前記第1層との間に配置される配線部と、前記第1層を貫通して前記ゲート電極と電気的に接続されるとともに、平面視で前記半導体層の両側にそれぞれ配置される壁部と、を含む走査線と、
前記画素電極と前記走査線との間に配置される絶縁性の第2層と、
前記画素電極と前記第2層との間に配置される絶縁性の第3層と、
前記第2層と前記第3層との間に配置され、平面視で前記ゲート電極に重なる第1部分と、平面視で前記半導体層の両側にそれぞれ配置された前記壁部の間において、前記第2層を貫通して設けられた開口内に配置される第2部分と、を含み、遮光性を有するとともに前記トランジスターのドレイン領域に電気的に接続される配線と、を有する、電気光学装置。 - 前記基材と前記トランジスターとの間に、前記走査線の壁部と電気的に接続される遮光体を備える、請求項1または2に記載の電気光学装置。
- 前記第2部分は、平面視で前記走査線と離間して配置される、請求項1ないし3のいずれか1項に記載の電気光学装置。
- 前記半導体層は、ソース領域、ドレイン領域、前記ソース領域と前記ドレイン領域との間に配置されるチャネル領域、および前記ドレイン領域と前記チャネル領域との間に配置されるLDD領域を有し、
前記第2部分は、平面視で前記LDD領域に重なる、請求項1に記載の電気光学装置。 - 前記配線は、金属で構成される、請求項1ないし5のいずれか1項に記載の電気光学装置。
- 前記走査線は、金属で構成される、請求項1ないし6のいずれか1項に記載の電気光学装置。
- 請求項1ないし7のいずれか1項に電気光学装置を有する、電子機器。
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JP2018118762A JP6665889B2 (ja) | 2018-06-22 | 2018-06-22 | 電気光学装置および電子機器 |
US16/448,407 US10754215B2 (en) | 2018-06-22 | 2019-06-21 | Electro-optical device and electronic apparatus |
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