JP6661057B1 - Limiting amplifier circuit - Google Patents

Abstract

The limiting amplifier circuit (3) has a function of adjusting a voltage offset that is a difference in DC voltage component between the positive-phase signal and the negative-phase signal of the input first differential signal, and has the first A first differential amplifier circuit (31) that amplifies the differential signal and outputs a second differential signal that is the amplified signal, and amplifies the second differential signal to a predetermined amplitude. A second differential amplifier circuit (32), a signal detection circuit (34) that determines whether or not the second differential signal includes a received signal, and a voltage offset of the voltage offset based on the determination result of the signal detection circuit. And an offset control circuit (35) for controlling the adjustment amount.

Description

  The present invention relates to a limiting amplifier circuit that amplifies an input signal to a predetermined amplitude.

  In recent years, a one-to-many access optical communication system called a PON (Passive Optical Network) system in which one optical fiber can be shared by a plurality of users has been widely used. The PON system includes one OLT (Optical Line Terminal) as a station side device, a plurality of ONUs (Optical Network Units) as subscriber side devices, and an optical star as a passive element connecting the OLT and the ONU. It is composed of a coupler and an optical fiber connecting the OLT, the ONU and the optical star coupler.

  In order to increase the number of ONUs accommodated in the PON system, it is required to increase the maximum connection distance between the OLT and the ONU and increase the number of ONU branches. For this reason, the difference in distance from the OLT for each ONU increases, and the OLT receives a packet signal having a large signal strength difference. Generally, in a process of receiving an optical signal transmitted via an optical fiber, the optical signal is converted into a current signal, and is then identified by a clock data recovery circuit. At this time, in order to keep the signal level of the input signal to the clock data recovery circuit constant, the converted current signal is linearly amplified by a transimpedance amplifier, and then has a predetermined amplitude using a limiting amplifier circuit. Is input to the clock data recovery circuit.

  Since the power supply voltage required for the transimpedance amplifier and the limiting amplifier circuit is different from the power supply voltage required for the digital circuit after the clock data recovery circuit, there is a difference between the limiting amplifier circuit and the clock data recovery circuit. It is often AC (Alternative Current) coupled. If the difference in the magnitude of the DC voltage component between the positive-phase signal and the negative-phase signal of the differential signal changes at the beginning of the received signal, signal distortion occurs and a code error occurs.

  Non-Patent Document 1 discloses a technique for canceling a voltage offset which is a difference between DC voltage components between a positive-phase signal and a negative-phase signal of a differential signal by using feedback from an output to an input of a limiting amplifier circuit. Have been.

M.Moller, H.-M.Rein, and H.Wernz, “13 Gb / s Si-Bipolar AGC Amplifier IC with High Gain and Wide Dynamic Range for Optical-Fiber Receivers,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol .29, No. 7, pp. 815-822, July 1994.

  However, according to the technique disclosed in Non-Patent Document 1, there is a problem that the code error rate may increase in a signal reception section. Specifically, the photoelectric conversion element generally used in the PON system has a characteristic that the noise increases as the power of the input optical signal increases. That is, the noise on the mark side of the OOK (On Off Keying) signal is greater than the noise on the space side. Therefore, if the midpoint of each of the amplitudes of the normal phase signal and the negative phase signal is simply taken, the code error rate may increase.

  The present invention has been made in view of the above, and an object of the present invention is to provide a limiting amplifier circuit capable of reducing a bit error rate.

In order to solve the above-described problem and achieve the object, a limiting amplifier circuit according to the present invention provides a limiting amplifier circuit that includes a first differential signal having a difference in DC voltage component between a positive phase signal and a negative phase signal. A first differential amplifier circuit that has a function of adjusting a voltage offset, amplifies the first differential signal, and outputs a second differential signal that is an amplified signal; A second differential amplifier circuit for amplifying the differential signal to a predetermined amplitude, and determining whether or not the second differential signal includes a received signal, wherein the second differential signal includes the received signal If not, a first value indicating that a received signal has not been detected is output as a determination result, and if the second differential signal includes a received signal, a second value indicating that a received signal has been detected is determined as a determination result. a signal detecting circuit for outputting a value, when the result is a first value, the second differential amplifier circuit Controlling an adjustment amount of voltage offset on the basis of the force, when the result is a second value, and a offset control circuit for controlling the adjustment amount of voltage offset on the basis of the offset control signal inputted from the outside It is characterized by the following.

  The limiting amplifier circuit according to the present invention has an effect that the code error rate can be reduced.

FIG. 1 is a diagram illustrating a configuration of a limiting amplifier circuit according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the limiting amplifier circuit shown in FIG. FIG. 2 shows a partial configuration of the first differential amplifier circuit shown in FIG. FIG. 4 is a diagram illustrating a configuration of a limiting amplifier circuit according to a second embodiment of the present invention. FIG. 4 is a diagram illustrating a configuration of a limiting amplifier circuit according to a third embodiment of the present invention. FIG. 9 is a diagram illustrating a configuration of a limiting amplifier circuit according to a fourth embodiment of the present invention.

  Hereinafter, a limiting amplifier circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited by the embodiment.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration of the limiting amplifier circuit 3 according to the first embodiment of the present invention. The limiting amplifier circuit 3 is provided in the burst optical receiver. The limiting amplifier circuit 3 includes an APD (Avalanche Photo Diode) 1 which is a photoelectric conversion element for converting an input optical signal into a current signal, and a transimpedance amplifier 2 which converts a current signal output from the APD 1 into a voltage signal. And a signal is input through the. The limiting amplifier circuit 3 amplifies the output signal of the transimpedance amplifier 2 to a predetermined amplitude, and inputs the amplified signal to the CDR 5 via the AC coupling capacitors 41 and 42. FIG. 1 shows only a part of the configuration of the burst optical receiver relating to the invention according to the present embodiment, and the burst optical receiver has components other than those shown in FIG. You may.

  The APD 1 converts an input optical signal into a current signal and outputs the current signal. The APD 1 has a characteristic that the noise increases as the power of the input signal increases. For example, the noise on the mark side of the OOK signal is larger than the noise on the space side. The current signal output from the APD 1 is input to the transimpedance amplifier 2.

  The transimpedance amplifier 2 is a preamplifier having a high gain, and converts an input current signal into a voltage signal. The transimpedance amplifier 2 amplifies an input signal and outputs a first differential signal that is an amplified signal. The amplitude of the voltage signal output from the transimpedance amplifier 2 depends on the power of the input signal. The transimpedance amplifier 2 is, for example, a linear amplifier. The first differential signal output from the transimpedance amplifier 2 is input to the limiting amplifier circuit 3. The first differential signal includes a pair of a normal phase signal and a negative phase signal.

  The limiting amplifier circuit 3 includes a first differential amplifier circuit 31, a second differential amplifier circuit 32, an output buffer 33, a signal detection circuit 34, an offset control circuit 35, and a switch 36.

  The first differential amplifier circuit 31 amplifies the first differential signal and outputs a second differential signal that is an amplified signal. The first differential amplifier circuit 31 has a higher output signal power as the input signal power is higher. The first differential amplifier circuit 31 is, for example, a linear amplifier that linearly amplifies an input signal. The first differential amplifier circuit 31 has a function of adjusting a voltage offset, which is a difference between DC voltage components between a positive-phase signal and a negative-phase signal of the input first differential signal.

  The second differential amplifier circuit 32 is a limiting amplifier that amplifies the second differential signal output from the first differential amplifier circuit 31 to a predetermined amplitude. It can be said that the second differential amplifier circuit 32 limits the amplitude of the output signal of the limiting amplifier circuit 3 to a predetermined value.

  The output buffer 33 converts the amplified second differential signal into a signal transfer level to the CDR 5. The output buffer 33 outputs the converted second differential signal to an output terminal connected to the CDR 5.

  The signal detection circuit 34 determines whether or not the second differential signal output from the first differential amplifier circuit 31 includes a signal received from the opposite device. The signal detection circuit 34 determines whether or not the second differential signal includes a received signal based on, for example, the amplitude of the input differential signal. More specifically, when the amplitude of the input differential signal is larger than a predetermined threshold, the signal detection circuit 34 can determine that the second differential signal includes the received signal. In this case, when the amplitude of the input differential signal is equal to or smaller than the threshold, the signal detection circuit 34 determines that the second differential signal does not include the received signal. The threshold value used by the signal detection circuit 34 may have a hysteresis to reduce the possibility of malfunction. Further, the threshold value may be a value stored in advance internally or a value appropriately given from the outside.

  The determination method used by the signal detection circuit 34 is not limited to the above. For example, the signal detection circuit 34 compares a predetermined signal pattern with a signal pattern of the second differential signal, and determines whether the second differential signal includes a received signal based on the comparison result. Is determined. The signal detection circuit 34 detects the signal pattern by calculating the number of clocks of the input signal using the counter circuit, and can determine whether or not the second differential signal includes the received signal. Further, the signal detection circuit 34 may detect a break in the signal instead of detecting the reception signal. When the second differential signal does not include the reception signal, the signal detection circuit 34 outputs a first value indicating that the reception signal has not been detected as a determination result. When the second differential signal includes the reception signal, the signal detection circuit 34 outputs a second value indicating that the reception signal has been detected as a determination result.

  The offset control circuit 35 controls the adjustment amount of the voltage offset based on an offset control signal input from outside the limiting amplification circuit 3. The offset control circuit 35 can output an offset setting signal for controlling the voltage offset of the first differential amplifier circuit 31. The offset control circuit 35 can output two types of offset setting signals. The first offset setting signal of the two types of offset setting signals is the first adjustment amount used when the second differential signal does not include the reception signal, that is, the first adjustment amount used in the no-signal section where the reception signal is not detected. Show. The second offset setting signal of the two types of offset setting signals indicates a second adjustment amount used when the second differential signal includes a reception signal, that is, a signal section in which the reception signal is detected. . The first adjustment amount is a value for minimizing the voltage offset, that is, for approaching zero. The second adjustment amount is a value different from the first adjustment amount.

  The offset control circuit 35 determines the first offset setting signal and the second offset setting signal based on an externally input offset control signal. For example, the offset control signal may be input using a digital signal interface such as an I2C (Inter-Integrated Circuit) and held in a register in the limiting amplifier circuit 3 or may be input as an analog voltage signal. . Although the offset control signal is directly input in FIG. 1, for example, an external command may be input, and the offset control circuit 35 may perform an arithmetic process based on the input command. Further, if a similar effect can be obtained, the offset control signal does not need to maintain a constant value during operation, and may be a value that changes with time by performing arithmetic processing.

  The switch 36 switches an offset setting signal input to the first differential amplifier circuit 31 from two types of offset setting signals output from the offset control circuit 35. The switch 36 can switch the offset setting signal input to the first differential amplifier circuit 31 based on the value output from the signal detection circuit 34.

  The output of the limiting amplifier circuit 3 is AC-coupled to the CDR 5 by the AC coupling capacitors 41 and 42. The CDR 5 re-times the signal output from the limiting amplifier circuit 3 and identifies the input differential signal. The transimpedance amplifier 2 and the limiting amplifier circuit 3 require a power supply voltage of about 3.3 V in order to secure analog characteristics. Since the CDR 5 can be realized by a digital circuit, the CDR 5 can be driven by a power supply voltage lower than the power supply voltages of the transimpedance amplifier 2 and the limiting amplifier circuit 3. The drive voltage of the CDR 5 is, for example, 1.8 V.

  FIG. 2 is a diagram for explaining the operation of the limiting amplifier circuit 3 shown in FIG. FIG. 2 shows the positive-phase voltage, which is the voltage of the positive-phase signal input to the limiting amplifier circuit 3 from above, the output voltage from the signal detection circuit 34, and the positive-phase voltage input to the CDR5.

  First, in the no-signal period, the output voltage from the signal detection circuit 34 becomes the first value “Low”. In this case, the switch 36 enters a state in which the first offset setting signal for the no-signal section is input to the first differential amplifier circuit 31. When the first offset setting signal is input to the first differential amplifier circuit 31, control is performed so that the voltage offset of the differential signal output from the first differential amplifier circuit 31 approaches zero. At this time, the center voltage of the positive-phase signal input to the limiting amplifier circuit 3 is the voltage VCM3, and the center voltage of the positive-phase signal input to the CDR5 is the voltage VCM5.

  In the signal reception period, first, the signal detection circuit 34 detects the amplitude of the output signal of the first differential amplifier circuit 31 and changes the output voltage from the first value “Low” to the second value. Transition to a certain “High”. When the output of the signal detection circuit 34 transitions to “High”, the switch 36 switches the offset setting signal input to the first differential amplifier circuit 31 so that the second offset setting signal changes to the first differential amplifier circuit. 31 is input. When the first differential amplifier circuit 31 operates according to the second offset setting signal, the center voltage of the positive-phase signal input to the limiting amplifier circuit 3 is shifted to a higher voltage side than the voltage VCM3. The center voltage of the positive-phase signal input to the CDR 5 is constant regardless of the input light power, and does not shift from the voltage VCM5.

  By the above operation, after the operation delay time of the signal detection circuit 34, the switching time of the switch 36, and the operation delay time of the offset control circuit 35 have elapsed, the voltage offset can be shifted to a desired optimum point.

  The time constant of the DC voltage drift due to AC coupling between the limiting amplifier circuit 3 and the CDR 5 is usually several tens μs, whereas the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the offset control are performed. The operation delay of the circuit 35 is usually several ns to several tens ns. For this reason, the DC drift of the differential signal at the CDR5 input terminal becomes almost negligible due to the AC coupling. In addition, during the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the operation delay of the offset control circuit 35, the accuracy of signal determination is reduced and effective communication cannot be established. T (International Telecommunication Union Telecommunication standardization sector) Since the preamble length allocated to the 10 Gbps uplink signal specified in 9807.1 is from 128.6 ns to 610.9 ns, it is possible to satisfy these values.

  FIG. 3 is a diagram showing a partial configuration of the first differential amplifier circuit 31 shown in FIG. The first differential amplifier circuit 31 has terminating resistors 311 and 312 at the input portion so that reflection does not occur when a high-frequency signal is input. Further, the first differential amplifier circuit 31 includes a differential pair 313 and variable current sources 314 and 315. The differential pair 313 amplifies the differential signal. Each of the variable current sources 314 and 315 is connected between the signal input terminal and the ground GND. The value of the current flowing through each of the variable current sources 314 and 315 is determined by the offset control circuit 35. By relatively changing the current value flowing through each of the variable current sources 314 and 315, the voltage offset of the differential signal can be changed.

  Although the variable current sources 314 and 315 are connected between the signal input terminal and the ground GND in FIG. 3, the variable current sources 314 and 315 are connected between each of the terminating resistors 311 and 312 and the signal input terminal. They may be connected or a combination thereof. Further, in FIG. 3, the variable current sources 314 and 315 are respectively connected to the two differential lines, but the current source connected to one of the positive-phase signal and the negative-phase signal is a fixed current source. The other may be a variable current source. Furthermore, the portion of the first differential amplifier circuit 31 to which the current source for adjusting the voltage offset is connected is not limited to the input portion. For example, a current source may be connected to the inside of the first differential amplifier circuit 31 such as an output section of the differential pair 313, or a current source may be connected to the input section of the first differential amplifier circuit 31 and a plurality of locations inside the first differential amplifier circuit 31. A source may be connected.

  As described above, by changing the adjustment amount of the voltage offset based on whether or not the differential signal to be processed includes the received signal, the input to the CDR 5 is performed in both the non-signal section and the signal receiving section. The center voltage of the signal can be kept constant. Therefore, even when the limiting amplifier circuit 3 and the CDR 5 are AC-coupled, the bit error rate can be reduced. Also, highly efficient communication with a reduced preamble length is possible. In addition, the limiting amplifier circuit 3 performs a process of determining whether or not the received signal is included, using the signal after the amplification. For this reason, it is not necessary to integrate the signal components, or the integration of the minimum time is sufficient, so that the presence or absence of the received signal can be determined at high speed. Therefore, the voltage offset can be adjusted at high speed, and the code error rate can be reduced while maintaining the uplink transmission efficiency.

Embodiment 2 FIG.
FIG. 4 is a diagram illustrating a configuration of the limiting amplifier circuit 3-1 according to the second embodiment of the present invention. In the first embodiment, the limiting amplifier circuit 3 using two externally input offset control signals has been described. However, in the second embodiment, the number of externally input offset control signals is one. A limiting amplifier circuit 3-1 that can obtain the same effect as in the first embodiment will be described. Hereinafter, the same components as those in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted. A different portion from the first embodiment will mainly be described.

  The limiting amplifier 3-1 has two offset control circuits 351 and 352. The offset control circuit 351 outputs a first offset setting signal used when the input signal does not include the received signal, and the offset control circuit 352 is used when the input signal includes the received signal. And outputs a second offset setting signal. The differential signal output from the second differential amplifier circuit 32 is input to the offset control circuit 351, and the offset control circuit 351 controls the adjustment amount of the voltage offset based on the output of the second differential amplifier circuit 32. One offset control signal is input to the offset control circuit 352 from outside the limiting amplification circuit 3-1. The offset control circuit 352 controls the adjustment amount of the voltage offset based on the input offset control signal.

  The offset control circuit 351 is, for example, an integration circuit using an operational amplifier. Further, the offset control circuit 351 may include an ADC (Analog-to-Digital Converter) that samples a differential signal, and a digital filter that integrates the differential signal.

  As described above, according to the second embodiment of the present invention, the same effect as in the first embodiment can be obtained, and the number of offset control signals input to the limiting amplifier circuit 3-1 can be reduced. Can be one. In this case, the number of offset control signals is reduced as compared with the limiting amplifier circuit 3, so that the number of memories required outside the limiting amplifier circuit 3-1 can be reduced, and the offset control signal can be reduced. There is an advantage that pre-adjustment of the control signal is not required.

Embodiment 3 FIG.
FIG. 5 is a diagram illustrating a configuration of the limiting amplifier circuit 3-2 according to the third embodiment of the present invention. In the first and second embodiments, the signal detection circuit 34 determines the value of the output voltage based on the amplitude of the output signal of the first differential amplifier circuit 31 during both the reception of the optical signal and the non-signal transition. The timing for switching was determined. On the other hand, in the third embodiment, the signal detection circuit 34-1 changes the output voltage value from “High” to “Low” by using a reset signal input from outside the limiting amplification circuit 3-2 as a trigger. Transition to. That is, upon receiving the reset signal, the signal detection circuit 34-1 outputs a determination result indicating that the second differential signal output from the first differential amplifier circuit 31 does not include the received signal.

  The signal detection circuit 34-1 can be configured using a single latch circuit. Therefore, there is an advantage that the configuration of the signal detection circuit 34-1 can be simplified.

  FIG. 5 shows a limiting amplifier circuit 3-2 in which the signal detecting circuit 34 of the limiting amplifier circuit 3 according to the first embodiment is replaced with a signal detecting circuit 34-1 corresponding to a reset signal. The present embodiment is not limited to such an example. For example, in the configuration including the two offset control circuits 351 and 352 shown by the limiting amplifier circuit 3-1, the signal detection circuit 34-1 corresponding to the reset signal may be used. In this case, as in the second embodiment, only one offset control signal is input from the outside, so that the number of memories required outside the limiting amplifier circuit 3-2 can be reduced and the offset control signal can be reduced. There is an advantage that the pre-adjustment of the control signal becomes unnecessary.

Embodiment 4 FIG.
FIG. 6 is a diagram illustrating a configuration of the limiting amplifier circuit 3-3 according to the fourth embodiment of the present invention. In the first, second and third embodiments, the output of the first differential amplifier circuit 31 is input to the signal detection circuits 34 and 34-1. In the fourth embodiment, the limiting amplifier circuit 3- 3 is branched before being input to the first differential amplifier circuit 31, amplified by the third differential amplifier circuit 37, and input to the signal detection circuit 34-2. I do.

  The third differential amplifying circuit 37 is arranged before the signal detection circuit 34-2. The third differential amplifier circuit 37 amplifies the first differential signal and inputs it to the signal detection circuit 34-2. The signal detection circuit 34-2 determines whether or not the second differential signal includes a received signal based on the amplified first differential signal output from the third differential amplifier circuit 37.

  By adopting the configuration shown in FIG. 6, the signal line finally connected to the CDR 5 and the signal line connected to the signal detection circuit 34-2 are separated in the limiting amplifier circuit 3-3. Becomes possible. For this reason, there is an advantage that it is possible to optimize each signal line and set each amplifier.

  The third differential amplifier circuit 37 is a linear amplifier in which the amplitude of the output signal depends on the amplitude of the input signal, similarly to the first differential amplifier circuit 31. If the signal line finally connected to the CDR 5 is not adversely affected, the signal line may be directly connected to the signal detection circuit 34-2 without passing through the third differential amplifier circuit 37.

  Further, the limiting amplifier circuit 3-3 according to the fourth embodiment is not limited to the configuration illustrated in FIG. For example, the limiting amplification circuit 3-3 may include two offset control circuits 351 and 352, or the signal detection circuit 34-2 may receive a reset signal. Alternatively, the limiting amplifier circuit 3-3 may include two offset control circuits 351 and 352, and the signal detection circuit 34-2 may receive a reset signal.

  The configurations described in the above embodiments are merely examples of the contents of the present invention, and can be combined with other known technologies, and can be combined with other known technologies without departing from the gist of the present invention. Parts can be omitted or changed.

  1 APD, 2 transimpedance amplifier, 3,3-1,3-2,3-3 limiting amplifier circuit, 5 CDR, 31 first differential amplifier circuit, 32 second differential amplifier circuit, 33 output buffer , 34, 34-1, 34-2 signal detection circuit, 35, 351, 352 offset control circuit, 36 switch, 37 third differential amplifier circuit, 41, 42 AC coupling capacitance, 311, 312 termination resistance, 313 difference Dynamic pair, 314, 315 Variable current source.

Claims (6)

A function of adjusting a voltage offset, which is a difference between DC voltage components between a positive-phase signal and a negative-phase signal of the input first differential signal, and amplifying the first differential signal; A first differential amplifier circuit that outputs a second differential signal that is an amplified signal;
A second differential amplifier circuit for amplifying the second differential signal to a predetermined amplitude;
It is determined whether or not the second differential signal includes a received signal. If the second differential signal does not include a received signal, a first result indicating that the received signal is not detected is determined as a result of the determination. A signal detection circuit that outputs a value, and outputs a second value indicating that the received signal has been detected as a determination result when the second differential signal includes a received signal;
When the determination result is the first value, the adjustment amount of the voltage offset is controlled based on the output of the second differential amplifier circuit, and when the determination result is the second value, An offset control circuit that controls an adjustment amount of the voltage offset based on an offset control signal input from the
A limiting amplifier circuit comprising:   The offset control circuit, when the determination result is the first value, inputs a first offset setting signal indicating an adjustment amount for minimizing the voltage offset to the first differential amplifier circuit, 2. The method according to claim 1, wherein when the determination result is the second value, a second offset setting signal indicating an adjustment amount different from the first offset setting signal is input to the first differential amplifier circuit. 2. The limiting amplifier circuit according to 1.   When the amplitude of the second differential signal is larger than a predetermined threshold, the signal detection circuit determines that the second differential signal includes the received signal, and determines whether the second differential signal includes the received signal. The limiting amplifier circuit according to claim 1, wherein when the amplitude is equal to or smaller than the threshold, it is determined that the second differential signal does not include the received signal.   The signal detection circuit determines whether or not the second differential signal includes a received signal based on a comparison result between the signal pattern of the second differential signal and a predetermined signal pattern. The limiting amplifier circuit according to claim 1 or 2, wherein: The signal detection circuit receives the reset signal, the determination result as a limiting amplifier circuit according to claim 1, any one of 4 and outputs the first value. A third differential amplifier circuit that is arranged at a stage preceding the signal detection circuit and amplifies the first differential signal;
3. The signal detection circuit according to claim 1, wherein the signal detection circuit determines whether the second differential signal includes a reception signal based on an output of the third differential amplifier circuit. 4. Limiting amplifier circuit.

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