JP6649731B2 - Identify signals to read back from FPGA - Google Patents

Description

  The present invention relates to a method for automatically specifying a model signal of an FPGA program that can be read out from an FPGA by readback after the FPGA is built. The invention further relates to a data processing device configured to perform the method described above. The invention further relates to a computer program product comprising computer-implemented instructions for performing the steps of the method described above after being loaded and executed on a suitable data processing device. The invention further relates to a digital memory medium comprising electronically readable control signals, wherein the control signals are associated with a programmable data processing device such that the method described above is implemented in the data processing device. Operative digital memory media.

  Real-time simulation of complex dynamic models imposes stringent requirements on modern compute nodes themselves due to severe time constraints. In automotive hardware-in-the-loop simulation (HiL), such models are used especially where high-speed control circuits need to be connected. This applies, for example, to the simulation of cylinder pressure sensors, which play an increasingly important role in improving fuel economy or reducing emissions. However, short latencies and cycle times are indispensable even in control systems with high dynamics, such as electric motors. These are virtually infeasible with CPU-based simulations.

  Field programmable gate arrays (FPGAs) can support real-time simulation of compute nodes by being responsible for computing the dynamic portion of the model. Because FPGAs have high flexibility and can process signals in parallel, the use of FPGAs makes it easy to meet the demanding requirements of hard real-time. FPGAs can be used as hardware accelerators for compute node CPUs. Such an extension for the HiL simulator is, for example, the dSPACE DS5203-FPGA Board. Thus, for example, the very dynamic part of the environment model is transferred to the FPGA, which ensures that the controller has a sufficiently accurate and fast response time. An FPGA hardware configuration based on the creation of a general program called an FPGA code is usually created in a build process based on an FPGA model described in a hardware description language.

  Control system models are becoming increasingly complex with increasing demands on accuracy, which makes them more difficult to process. In the automotive HiL environment, such models are basically created using Mathwork's Matlab / Simulink toolset. Simulink illustrates such a model in the form of a block-based block diagram. In the block diagram, a plurality of model parts can be grouped into subsystems and interconnected by signals. The data flow between these blocks is represented via signal lines.

  In a CPU-based real-time simulation, the model block diagram is first translated into C / C ++ source files using Simulink Coder. These source files are then translated by a compiler into an application executable on a compute node by a real-time operating system. In addition, a trace file is created in the CPU build. The trace file is, for example, a graphically modeled topology file in Simulink.

  Translating the model into a CPU application results in the simulation calculations being performed sequentially with a fixed step size. Thus, a consistent mapping of all model states or model variables, such as data on signal lines and / or data on block input / output values, is always present in the main memory of the computing node. By directly accessing the main memory, model variables can be analyzed and / or manipulated in an experimental tool such as, for example, ContolDesk. Random read / write access to HiL simulation variables is possible. Based on the trace file, a signal value such as, for example, engine speed can be selected and output or manipulated by a display. This procedure is summarized in the HiL environment under the terms “measurement” and “fit”.

  FPGA-based simulations can be modeled in a Simulink block diagram, for example, using the Xilinx System Generator (XSG) and dSPACE's FPGA-Programming Blockset, similar to CPU-based simulations .

  However, unlike CPU simulation, this model is not translated into an iterative programming language, but into a hardware description language that describes customized digital circuits. The customized circuit description is translated into an FPGA configuration data stream by a synthesis process when creating the FPGA code. Therefore, each model variable that the user wants to measure or fit must be guided through explicit signal modeling to the interface of the FPGA. Following this fit, the model must be translated anew, which can take several hours. Under such circumstances, the development cycle of real-time simulation based on FPGA may be extremely long.

  In the case of some FPGAs, it is possible to stop and read the entire state of the FPGA for debugging purposes. However, due to the closed input / output characteristics of the FPGA, it is impossible to arbitrarily access the model state like the main memory of the computation node. That is, it is not possible to read a signal from the FPGA during operation or to change this signal in some cases. Reading of signals from the FPGA can be performed, for example, via a readback (Readback). In the readback, data is copied from the operation level of the FPGA to the configuration level, and data is read from the configuration level. Therefore, it is basically possible to read arbitrary registry data from the FPGA. Conversely, according to the partial reconfiguration, data can be copied from the configuration level of the FPGA to the operation level of the FPGA in order to change the register data. However, not all signals can be accessed via registers.

  The problem that exists with readback is that it is only after the build process is finished that it is possible to determine which signals can be read back. This is however a problem. This is because the modeling and build processes of the FPGA take time. In order to be able to read back the relevant non-recoverable signal and to have access to all relevant data during FPGA operation, for example, explicit modeling of registers to read this signal is required It is.

  Thus, against the background of the prior art described above, the problem underlying the present invention is that in a method of the type described above, it is easy to identify a model signal for FPGA programming that can be read out from the FPGA by readback after the FPGA build, It is an object of the present invention to provide a method for reducing development time for an FPGA program and increasing flexibility in reading and / or changing a signal value.

  This object is achieved according to the invention by the features described in the independent claims. Advantageous embodiments of the invention are set out in the dependent claims.

  Therefore, according to the present invention, there is provided a method for automatically specifying a model signal of an FPGA program that can be read out from the FPGA by readback after the FPGA build. The method includes creating an FPGA model, and creating FPGA code from the FPGA model, wherein the method creates the FPGA code from the FPGA model before the step of creating the FPGA code ends. The method includes the additional step of performing an automatic analysis to identify signals readable by readback from the FPGA, and the method includes outputting a signal readable by readback from the FPGA.

  According to the present invention, there is further provided a data processing device configured to perform the method described above.

  According to the present invention, there is further provided a computer program product comprising computer-implemented instructions for performing the steps of the method described above after being loaded and executed on a suitable data processing device.

  According to the invention, furthermore, a digital memory medium comprising electronically readable control signals, the control signals comprising a programmable data processing device such that the method described above is implemented in the data processing device. A digital memory medium is presented that cooperates with.

  That is, a core idea of the present invention is to identify a signal that can be read out from the FPGA by readback before the creation of the FPGA code from the FPGA model is completed. By automatically identifying the signals that can be read back from the FPGA by readback, such signals can be displayed, for example, in a modeler that creates an FPGA model, whereby the modeler Before the end of the creation of the data, it is possible to take appropriate measures, such as adapting the FPGA model, for implementing the required signal so that the signal can be read out by readback.

  After the FPGA build, the created FPGA code is transmitted to the FPGA, where it can be executed. Here, the readback signal can be read from the FPGA by readback. The readable signal corresponds to a model signal readable by readback.

  Creating an FPGA model is the first step in creating FPGA code. Models describing the functions of the FPGA to be implemented are created in a conventional manner. The creation of the FPGA model itself is well known to those skilled in the art and can be implemented as part of an overall model that includes a CPU model for components implemented on the CPU of the compute node.

  Following creation of the FPGA model, FPGA code is created from the FPGA model. In this case, an FPGA hardware configuration based on an FPGA model described in a hardware description language is created as the FPGA code. Creating FPGA code generally involves a build process that includes a plurality of individual steps, which are typically performed separately in a predetermined order. Since a plurality of individual steps are provided in creating the FPGA code from the FPGA model, it is possible to perform an automatic analysis at different times during the creation of the FPGA code. However, this is only possible if each of these steps is independent and produces an intermediate result that can be automatically analyzed. The creation of the FPGA code itself from the FPGA model is known to those skilled in the art.

  Automatic analysis to identify signals that can be read back from the FPGA by readback can be performed in different ways and at different stages during the creation of the FPGA code from the FPGA model. Details regarding this will be described later.

  The output of a signal readable by the readback from the FPGA is preferably performed immediately after the analysis, so that at an early point in the generation of the FPGA code from the FPGA model, which signals can be read back from the FPGA by the readback. It becomes possible to clarify. The output of a signal that can be read out from the FPGA by readback can be basically performed in any manner, for example, in the form of a list of signals that can be read out from the FPGA. The output can be implemented, for example, in a development environment for creating FPGA code. Usually, an FPGA model is created in a development environment.

  In an advantageous embodiment of the present invention, the step of performing the automatic analysis for identifying a signal readable by the FPGA by readback includes the step of storing a signal for storing the signal in the FPGA. Detecting that it is implemented in Since the signal value stored in the register can be read out by readback, detection of the register in the signal path of a certain signal indicates that the signal can be read out in the FPGA. Temporary storage is also considered as signal preservation if the register is used during signal processing only to temporarily store signal values, for example.

  In an advantageous embodiment of the invention, the step of detecting that the register for storing the signal is implemented in the FPGA comprises the step of implementing a delay element for the signal. Detecting that the user is running. The delay elements of the model perform signal processing, which requires temporary storage of signal values. Therefore, in order to implement the delay element of the model, it is necessary to implement a register readable by readback in the signal path.

  In an advantageous embodiment of the invention, the step of performing the automatic analysis for identifying a signal readable by readback from the FPGA comprises identifying the signal readable by readback from the FPGA. Analyzing the FPGA model for the purpose. FPGA models are used as the basis for creating FPGA code. Automatic analysis can already be performed based on the FPGA model. This is because it is difficult to track individual signals, especially in the case of extensive and complex models. FPGA models can also contain individual and independent blocks, which make it difficult for the modeler to track the signal path. During automatic analysis, the signal path can be automatically tracked, so that any implementation that exists at any position in the signal path and that can read the relevant signal by readback is identified. Can be collected. This makes it possible, for example, to automatically detect the implementation of a register for storing or temporarily storing a signal value, which is present at an arbitrary position in the signal path of the signal, from which the corresponding signal is obtained. It turns out that reading is possible by readback. This automatic analysis is very efficient because the analysis of the FPGA model can already be performed before performing other steps to create the FPGA code.

  In an advantageous embodiment of the invention, the step of creating the FPGA model comprises the step of creating a hierarchical FPGA model comprising an upper subsystem and at least one lower subsystem, from the FPGA Performing the automatic analysis to identify a signal readable by readback includes performing an automatic and recursive analysis of the FPGA model initiated in the higher-level subsystem . As a result, in the FPGA model, a function block that facilitates creation of the FPGA model can be created as a subsystem. In this way, the subsystem can be easily reused. The use of the subsystem further improves the visibility of the FPGA model. This is because only a few blocks need to be shown above the top level of the hierarchical FPGA model. Automatic and recursive analysis of FPGA models supports the creation of such forms of FPGA models by recursively analyzing all subsystems, eg, function blocks, during analysis.

  In an advantageous embodiment of the invention, said step of performing an automatic and recursive analysis of said FPGA model initiated in said higher-level subsystem comprises the same step in said higher-level subsystem and lower-level subsystem. Identifying a signal. For example, an output signal of a subsystem having an implementation that cannot be read by readback is read out by a readback signal in a method that cannot be determined first in a lower subsystem, that is, in a method that cannot be determined by a higher system. You may have an implementation that enables it. Particularly preferably, the signals are tracked between the upper and lower subsystems, so that a given signal can be easily analyzed without having to later associate each signal between the hierarchical subsystems. Becomes possible.

  In an advantageous embodiment of the present invention, the step of creating the FPGA code from the FPGA model includes performing a synthesis to create a network list, wherein a signal readable by readback from the FPGA is provided. Performing the automatic analysis to identify includes analyzing the network list to identify signals that can be read back from the FPGA by readback. Performing the synthesis to create the network list is usually a step that starts directly with the FPGA model, and is an early step in the creation of the FPGA code, usually the first step. Therefore, the analysis can be performed at an early point in the creation of the FPGA code, and which signals can be read out from the FPGA by readback can be identified at an earlier point in the creation of the FPGA code. During synthesis to create the network list, a high-level description of the system based on the FPGA model is converted into a network list, preferably in a synthesis tool. After the synthesis, basically, which signal is mapped to the register is already determined. However, the specific properties become apparent only after mapping to the target technology. The step of performing synthesis for creating a network list is basically known when creating FPGA code from an FPGA model, and need not be further described.

  In an advantageous embodiment of the invention, said step of generating said FPGA code from said FPGA model comprises the steps of a "Map" step, a "Place" step and a "Route" step. Performing the automatic analysis to identify signals readable by the FPGA from the FPGA, including at least one step, wherein the "map" step and the "place" step and the "route" Analyzing the results of at least one of the steps accordingly. When creating FPGA code from an FPGA model, the "map", "place" and "route" steps are independent steps that are performed individually, and the results of these steps are read back by readback. Each can be analyzed separately to identify possible signals. This means that the analysis of which signals in the FPGA code are readable by readback can be performed substantially at any time when the FPGA code is created. Generally, the "map", "place" and "route" steps are performed in this order as described. That is, a “map” step is performed first, a “place” step is performed, and finally a “route” step is performed. Preferably, the analysis is performed as early as possible during the development of the FPGA code, so that which signals in the FPGA code can be read back by readback can be identified as early as possible. Becomes This allows the possibly required adaptation of the FPGA model to be performed at an earlier point in time, which is advantageous in generating FPGA code from an FPGA model that is often very time consuming. The "map" step, "place" step and "route" step are basically known when creating FPGA code from an FPGA model and need not be further described.

  In an advantageous embodiment of the invention, the step of performing the automatic analysis to identify a signal readable by readback from the FPGA comprises identifying the signal readable by readback from the FPGA. Analyzing the network model to identify signals readable by the FPGA from the FPGA, the "map" step and the "place" step, and Analyzing the result of one of the "root" steps, the automatic analysis for identifying a signal readable by readback from the FPGA. The step of implementing the at least two Tsu based on flop, comprising comparing the identification result of the read enable signal by the read-back from the FPGA. By comparing the identification result of the signal readable by the readback from the FPGA based on the at least two steps, the quality of the identification of the signal readable by the readback from the FPGA can be improved. For example, the effects of automatic optimization during FPGA code creation can be reduced. In this way, the multi-stage method described herein reduces the development cycle time. In this case, the "map" step and / or the "place" step and / or the "route" step are independent steps, each performed individually, and the result of these steps identifies the signal that can be read by readback. Each of which can be analyzed separately. Therefore, the comparison of the identification results of the signals readable by the readback from the FPGA based on the at least two steps is performed in each of the individual “map” and / or “place” and / or “route” steps. Comparing the identification result of a signal that can be read out from the FPGA by readback based on the identification result. Preferably, an alert is generated if the comparison shows that a signal is readable in one of the analysis steps but not in the other.

  Preferably, said step of analyzing said FPGA model to identify signals readable by said FPGA by readback and said analyzing said network list to identify signals readable by said FPGA by readback. And the step of comparing the identification result of the signal readable by the readback from the FPGA, wherein the step of comparing the signal readable by the readback from the FPGA model based on the automatic analysis of the FPGA model. The identification result is compared with the identification result of a signal that can be read out from the FPGA by readback based on the automatic analysis of the network list. Since both the step of creating an FPGA model and the step of creating a network list have a significant effect on the implementation of registers for storing or temporarily storing signals, an FPGA based on these two steps is used. The identification of signals that are readable by readback allows reliable predictions to be made regarding the implementation of signals that are readable by readback. In general, synthesis tools convert a high-level description of a system as an FPGA model into a network list. After this step, it is basically determined which signals are mapped to the registers. However, the specific properties become apparent only after mapping to the target technology. Comparing the result of the preceding prediction with the synthesis result in the form of a network list, the quality of the identification of the signal readable by the readback is significantly improved, and thus the two-stage method described herein In addition, the time in the development cycle is significantly reduced. It is not necessary to perform the "map" and "place" and "route" implementation steps to determine whether a model signal is mapped to a component of the read-back FPGA.

  In an advantageous embodiment of the invention, the step of creating the FPGA model comprises the step of marking a model signal for reading in the FPGA model, and outputting a signal readable by the readback from the FPGA. The step of checking whether a signal readable by readback from the FPGA includes the marked model signal, and the step of reading a signal readable by readback from the FPGA to the model marked. Outputting a warning if the signal is not included. Therefore, the modeler and / or the user of the FPGA model can already specify the model signal that should be readable before creating the FPGA code. In general, the large number of signals in the FPGA model eliminates the need for the user to check every signal individually, but instead renders the desired model signal unavailable for readback. Can be identified directly based on the output of the alert. This alert can be created in various ways, for example in a development environment where the model signal is marked. Preferably, the warning is created based on the marking of the model signal.

  In an advantageous embodiment of the invention, the step of creating the FPGA model comprises marking a model signal for reading in the FPGA model, wherein the step of creating the FPGA code from the FPGA model comprises: Automatically implementing the model signal to be read as a signal readable by readback. Thus, the modeler and / or the user of the FPGA model can already specify the model signals that should be readable before creating the FPGA code, thereby making this possible when creating the FPGA code from the FPGA model. Can be automatically considered. In this case, since there is no need to change the FPGA model, errors during implementation can be reduced or eliminated. Due to the large number of signals in a typical FPGA model, the user also needs to individually implement all signals that are desired to be readable signals so that they can be read by readback. Instead, it can be easily determined based on the marking that the desired model signal is available for reading by readback.

  In this case, preferably, in one of the steps of creating the FPGA code, an implementation enabling reading of the marked signal is automatically performed, for example by implementing a register for temporarily storing the signal. Can be implemented. Preferably, a further warning is output if the automatic implementation of the model signal for reading out by readback fails. For this purpose, as described above, it is possible to specify which model signal is readable by readback, and to perform a comparison between the signal readable by readback and the marked signal. . If the signal readable by the readback does not include the marked signal, a warning is output.

  Alternatively, first, the creation of the FPGA code from the FPGA model is started, and depending on the automatic analysis to identify the signals that can be read from the FPGA by readback, the marked signal is It can first be checked whether it is already included in the signal that can be read by readback. The FPGA code then implements an explicit and automatic implementation of the model signal for reading as a signal readable by readback, i.e., a different implementation than the normal case without a marked signal. This can be done automatically in one of the steps of creating, whereby the marked model signal is automatically implemented as a signal that can be read by readback. If the marked signal is already included in the signal that can be read by readback, no change in the implementation of the FPGA code based on the marking of the model signal is required. Again, preferably, a warning is output if the automatic implementation of the model signal for reading using readback fails.

  In a preferred embodiment of the present invention, the step of outputting a signal readable by readback from the FPGA automatically includes, within the FPGA model, a model signal corresponding to a signal readable by readback from the FPGA. Marking. This allows a modeler or FPGA model user to quickly and easily identify which signals can be read back from the FPGA by readback. Therefore, the FPGA model can be directly adapted to enable reading of a model signal that cannot be read from the FPGA with the FPGA code currently created from the FPGA model. Marking of signals readable by readback can be performed, for example, in a development environment for creating an FPGA model.

  Hereinafter, the present invention will be described in more detail based on preferred embodiments with reference to the accompanying drawings.

5 is a flowchart of a method for automatically identifying a model signal of an FPGA program that can be read out from the FPGA by readback after the FPGA build, according to the first preferred embodiment; FIG. 1 is a schematic diagram of a data processing device for creating an FPGA code, which includes an FPGA model, a computation node including an FPGA for executing the FPGA code, and a host system for controlling the computation node. FIG. 3 is a diagram illustrating an example of a hierarchical FPGA model. FIG. 4 illustrates an example of performing an automatic analysis for the hierarchical FPGA model of FIG. 3.

  FIG. 1 shows a flowchart of a method of the present invention for automatically identifying a model signal of an FPGA program, which can be read out from an FPGA by readback after the FPGA build, according to a first preferred embodiment.

  Referring first to FIG. 2, the interaction of the hardware components for performing the method and the hardware components for executing the FPGA code is illustrated. FIG. 2 illustrates an FPGA model 2 and a data processing device 1 for creating an FPGA code 3 from the FPGA model 2. In order to generate the FPGA code 3 from the FPGA model 2, a build 4 is performed in the data processing device 1. In the FPGA build 4, an FPGA hardware configuration is created as the FPGA code 3 from the FPGA model 2 via VHDL, which is a well-known hardware description language. The method of FIG. 1 described in detail below is performed in the data processing device 1. Basically, it is also possible to execute the creation of the FPGA model 2 and the build 4 in different data processing devices 1 respectively.

  Generally, in build 4, CPU code 5 is created in addition to FPGA code 3. The CPU code 5 and the FPGA code 3 are created from one common model including the FPGA model 2. This model is created by Simulink in this embodiment. Then, the CPU code 5 and the FPGA code 3 can be transmitted to the calculation node 6. Therefore, the computation node 6 includes a CPU 7 for executing the CPU code 5 and an FPGA 8 for executing the FPGA code 3. The FPGA 8 is an Xilinx FPGA in this embodiment.

  FIG. 2 further shows a host system 9 for controlling the computing node 6. The computing node 6 is connected to a host system 9 via a network connection (not shown). In build 4, an additional trace file 10 is created, which allows the host system 9 to access the signal values of the CPU 7 and the signal values of the programming 8 to the FPGA during the operation of the compute node 6. Becomes Read access to the FPGA 8 is performed via readback, and write access is performed via partial reconfiguration.

  Hereinafter, a method for automatically specifying a model signal of an FPGA program that can be read out from the FPGA by readback after the FPGA build will be described.

  The method starts with the creation of the FPGA model 2 in the data processing device 1 in step S100. The FPGA model 2 describes a function to be realized by the FPGA 8. Some examples of the FPGA model 2 are also illustrated in FIG. As can be seen from FIG. 3, the FPGA model 2 is a hierarchical FPGA model 2. FIG. 3 illustrates a higher-order subsystem 11 including a lower-order subsystem 12. These subsystems 11 and 12 constitute individual independent blocks.

  As shown in FIG. 3, in the upper subsystem 11, a read marking 14 is set in the signal path 13 in order to mark a model signal in the FPGA model 2 to be read out by read back. No changes are made to FPGA model 2.

  In step S110, a first step of performing an automatic analysis for identifying a signal that can be read from the FPGA 8 by readback is performed. In this regard, the FPGA model 2 is analyzed to identify signals that can be read from the FPGA 8 by readback.

  At this time, it is automatically detected that the register 15 (shown in FIG. 3) for storing or temporarily storing the signal is implemented at an arbitrary position of the signal path 13 in the FPGA 8. Furthermore, the implementation of the delay element at any position in the signal path 13 of the signal is automatically detected. Since the signal path 13 is automatically tracked, an implementation can be identified and collected at any location in the signal path 13 to make the corresponding signal readable by readback. In this case, the automatic analysis performs a recursive analysis of the FPGA model 2 started by the higher-order subsystem 11.

  In the recursive analysis, the same signal in the lower subsystem 11 and the upper subsystem 12 is specified. Therefore, in one of the subsystems 11 and 12, a signal implemented so as to be readable by readback is used as a signal readable at an arbitrary position by readback. Performing a recursive analysis is illustrated in FIG. As can be seen from FIG. 4, in the module 16 called Traceability Prediction (TraceabilityForecast), a prediction is made for each signal s as to whether or not it can be read out by readback. For this purpose, first, the source block of the signal s is read by the function srcblock. Next, whether or not the input block is a subsystem in the FPGA model 2 is checked by a check in step isSubsystem. If so, the function TraceabilityForecast is called again. If not, it is checked in step isAtomic whether the input block is not a subsystem, ie whether it cannot be further divided into atomic blocks. If so, in step isRegistered, it is checked whether the block is mapped to register 15 after synthesis, ie whether the signal is stored or temporarily stored in register 15. This is the case in the case described above, where the register 15 or the delay element is implemented, but also if the block has a delay Zx (where x> 0), or This is also the case if this block is part of a predefined list, that is, if it is a special block that is predefined to contain a readable implementation. In the next step, it is checked in the function equals whether the two signals beyond the hierarchy, ie the two signals in the upper subsystem 11 and the lower subsystem 12, represent the same signal. . If applicable, in step doMarkSignal, this signal is marked as a signal that can be read back from the FPGA by readback and added to a first list containing signals that can be read from the FPGA by readback. .

  In step S120, build 4 is started. Build 4 starts with FPGA model 2 and at the end of build 4, FPGA code is created. The FPGA code 2 is an FPGA hardware configuration based on an FPGA model described in a hardware description language.

  In step S130, as a first step of build 4, synthesis for creating a network list is performed. At this time, the synthesis tool converts the high-level description of the system based on the FPGA model 2 into a network list.

  In step S140, the network list is automatically analyzed to identify a signal that can be read from the FPGA 8 by readback. After the build 4, a second list including a signal that can be read out from the FPGA 8 by readback is created.

  In step S150, the list created in step S110 is compared with the list created in S140. That is, the first list and the second list each including a signal that can be read by the FPGA 8 by readback are compared. Then, one integrated list including signals that can be read out from the FPGA 8 by readback is created, and the signals included in the integrated list are read back from the FPGA 8 in both the first list and the second list. It is included as a readable signal. If there is a signal that is included in only one of the two lists, that is, a signal that was not carried over to the consolidated list, a warning is created and displayed, for example, in FPGA model 2.

  In step S160, a signal that can be read out from the FPGA 8 by readback is output. The output of a signal readable by the FPGA 8 by readback is performed in the form of a list in a development environment for creating an FPGA code. In addition, in the FPGA model 2, a model signal corresponding to a signal that can be read out from the FPGA 8 by readback in the FPGA model 2 is automatically marked.

  In step S170, it is checked whether all signals marked by the read marking 14 can be read from the FPGA 8 by readback, that is, whether they are part of an integrated list. If the signal marked by the lead marking 14 cannot be read by readback, a warning is output by creating and displaying a warning using the lead marking 14 of the model signal as a clue.

  If it is determined by the check in step S170 that the signal marked by the read marking 14 cannot be read from the FPGA 8 by readback, the model signal is read in the FPGA 8 by readback in step S180. Automatically implemented as possible signals. For this purpose, a register 15 for temporarily storing the signal value is automatically implemented in the signal path 13 of the signal. If the automatic implementation of the register 15 fails, a corresponding warning is output.

  In step S190, the creation of the FPGA code 3 ends. Accordingly, in Build 4, a “Map” step, a “Place” step, and a “Route” step are performed, and the FPGA code 3 is created.

  According to the present method for identifying the signals of the FPGA 8 that can be read out from the FPGA 8 by readback after the generation of the FPGA code 3, these signals of the FPGA 8 are converted into the corresponding partial resources of the FPGA 8 as long as the signals are supported by the FPGA 8. It has turned out that it is also possible to describe via a configuration. In the second embodiment of the present invention, the above-described method is performed to specify a signal that can be changed by the partial reconfiguration after the FPGA code 3 is created. For this purpose, the FPGA 8 simply needs to provide a corresponding manipulation means, such as the partial reconfiguration described above.

  The method is implemented as a computer program product comprising computer-implemented instructions, which, after being loaded and executed on the data processing device 1, perform the steps of the method described above.

  The digital memory medium supplies an electronically readable control signal, which cooperates with the data processing device 1 such that the method described above is implemented in the data processing device 1.

1 data processing device 2 FPGA model 3 FPGA code 3
4 Build 5 CPU code 6 Compute node 7 CPU
8 FPGA
9 Host system 10 Trace file 11 Upper subsystem 12 Lower subsystem 13 Signal path 14 Read marking 15 Register 16 Traceability prediction (TraceabilityForecast) module

Claims (15)

A method for automatically specifying a model signal of an FPGA program that can be read out from an FPGA (8) by readback after an FPGA build (4), wherein the method includes:
Creating an FPGA model (2);
A data processing device for creating an FPGA code (3) from the FPGA model (2) ;
Including
The method further comprises: before the step of generating the FPGA code (3) from the FPGA model (2) is completed, wherein the data processing device identifies a signal readable by the FPGA (8) by readback. Including the additional step of performing an automated analysis for
The method, wherein the data processing device, viewing contains a step of outputting a readable signal by the read-back from the FPGA (8),
The step of performing the automatic analysis to identify a signal readable by the FPGA (8) by readback includes the step of: storing the signal from the FPGA model (2) by the data processing device. register (15), characterized in including Mukoto the step of detecting that it is implementation in said FPGA (8),
Method. The step of performing the automatic analysis to identify a signal readable by the FPGA (8) by readback includes the steps of: storing a signal (15) in the FPGA (8); Detecting that it has been implemented.
The method of claim 1. The step of detecting that a register (15) for storing the signal is implemented in the FPGA (8) comprises determining that a delay element for the signal is implemented. Detecting,
The method of claim 2. The step of performing the automatic analysis to identify a signal readable by readback from the FPGA (8) comprises the step of: identifying the signal readable by readback from the FPGA (8). Analyzing the model (2).
The method according to claim 1. Creating said FPGA model (2) comprises creating a hierarchical FPGA model (2) comprising an upper subsystem (11) and at least one lower subsystem (12);
The step of performing the automatic analysis to identify a signal that can be read out from the FPGA (8) by readback is performed by the automatic operation of the FPGA model (2) started in the upper subsystem (11). Performing a statistical and recursive analysis.
The method of claim 4. The step of performing an automatic and recursive analysis of the FPGA model (2) starting in the upper subsystem (11) comprises the steps of: the upper subsystem (11) and the lower subsystem (12) And identifying the same signal at
The method of claim 5. Creating said FPGA code (3) from said FPGA model (2) comprises performing a synthesis to create a network list;
The step of performing the automatic analysis to identify a signal readable by readback from the FPGA (8) includes the step of: executing the network to identify a signal readable by readback from the FPGA (8). Analyzing the list.
The method according to any one of claims 1 to 6. The step of creating the FPGA code (3) from the FPGA model (2) includes at least one of a “Map” step, a “Place” step, and a “Route” step Including
The step of performing the automatic analysis to identify a signal readable by the FPGA (8) by readback includes the steps of the "Map" step, the "Place" step, and the " Analyzing the results of at least one of the "Route" steps accordingly.
The method according to claim 1. Creating said FPGA code (3) from said FPGA model (2) comprises performing a synthesis to create a network list;
The step of creating the FPGA code (3) from the FPGA model (2) includes at least one of a “Map” step, a “Place” step, and a “Route” step Including
Performing said automatic analysis to identify a signal readable by said FPGA (8) by readback;
Analyzing the FPGA model (2) to identify a signal readable by readback from the FPGA (8);
Analyzing the network list to identify signals readable by readback from the FPGA (8);
Analyzing the result of at least one of the "Map" step and / or the "Place" step and / or the "Route" step ;
Comprising at least two steps from a group comprising
Performing the automatic analysis to identify a signal that is readable by readback from the FPGA (8) is readable by readback from the FPGA (8) based on the at least two steps; Comparing the identification results of the various signals.
A method according to any one of claims 1 to 8. Generating said FPGA model (2) comprises marking a model signal for reading in said FPGA model (2);
Outputting the signal readable by readback from the FPGA (8) includes checking whether the signal readable by readback from the FPGA (8) includes the marked model signal. And, if the signal readable by the readback does not include the marked model signal, comprises the step of outputting a warning,
The method according to claim 1. Creating said FPGA model (2) comprises marking a model signal for reading in said FPGA model (2);
The step of generating the FPGA code (3) from the FPGA model (2) includes automatically implementing the model signal for reading as a signal readable by readback. Do
The method according to claim 1. The step of outputting a signal readable by readback from the FPGA (8) includes automatically outputting a model signal corresponding to a signal readable by readback from the FPGA (8) in the FPGA model (2). Marking the to,
A method according to any one of the preceding claims.   A data processing device (1) configured to carry out the method according to any one of the preceding claims. The computer program for executing the steps according to one of the method of claims 1 12. The computer, computer-readable recording medium storing a program for executing the steps according to one of the method of claims 1 12.