JP6647352B1 - SiC semiconductor device - Google Patents

Abstract

An SiC semiconductor device capable of reducing an influence on a SiC semiconductor layer due to a reforming line is provided. A SiC semiconductor device includes a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first main surface. SiC semiconductor layer 2 having a plurality of side surfaces 5A to 5D connecting second main surface 4, and one layer formed on each side surface 5A to 5D of SiC semiconductor layer 2 in a band shape, inclined with respect to first main surface 3 And a plurality of modified lines 22A to 22D modified to have properties different from those of the SiC single crystal. [Selection diagram] FIG.

Description

  The present invention relates to a SiC semiconductor device.

  In recent years, a method of processing a SiC semiconductor wafer called stealth dicing has attracted attention. In the stealth dicing method, after a SiC semiconductor wafer is selectively irradiated with laser light, the SiC semiconductor wafer is cut along a portion irradiated with the laser light. According to this method, a SiC semiconductor wafer having relatively high hardness can be cut without using a cutting member such as a dicing blade, so that the manufacturing time can be reduced.

  Patent Document 1 discloses a method of manufacturing a SiC semiconductor device using a stealth dicing method. In the manufacturing method of Patent Literature 1, a plurality of rows of reformed regions (reformed lines) are formed on the entire side surfaces of the SiC semiconductor layer cut from the SiC semiconductor wafer. The plurality of rows of modified regions extend along the tangent direction of the main surface of the SiC semiconductor layer and are formed at intervals in the normal direction of the main surface of the SiC semiconductor layer.

JP 2012-146878 A

  The reforming line is formed by modifying the SiC single crystal of the SiC semiconductor layer to another property. Therefore, considering the influence of the reforming line on the SiC semiconductor layer, it is not desirable to form a plurality of reforming lines on the entire side surface of the SiC semiconductor layer. Examples of the influence on the SiC semiconductor layer due to the reforming line include a change in the electrical characteristics of the SiC semiconductor layer due to the reforming line and the occurrence of cracks in the SiC semiconductor layer starting from the reforming line. You.

  One embodiment of the present invention provides a SiC semiconductor device capable of reducing an influence on a SiC semiconductor layer due to a reforming line.

  One embodiment of the present invention includes a first main surface as an element formation surface, a second main surface opposite to the first main surface, and the first main surface and the second main surface. An SiC semiconductor layer having a plurality of side surfaces connecting surfaces, and a portion formed in a band shape on each of the side surfaces of the SiC semiconductor layer, one layer at a time, and extending obliquely with respect to the first main surface; Provided is a SiC semiconductor device including: a plurality of reforming lines modified to have properties different from those of a crystal.

  According to this SiC semiconductor device, the cutting start point is formed in the region on the first main surface side of the SiC semiconductor layer and the region on the second main surface side of the SiC semiconductor layer by the single layer reforming line. Therefore, at the time of manufacturing the SiC semiconductor device, the SiC semiconductor wafer can be appropriately cut without forming a plurality of reforming lines along the thickness direction of the SiC semiconductor wafer. Thereby, it is possible to appropriately reduce the formation area of the reforming line on each side surface of the SiC semiconductor layer. Therefore, the influence on the SiC semiconductor layer due to the reforming line can be reduced.

FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present invention. FIG. 2 is a plan view showing a silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first embodiment of the reforming line. FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 as viewed from another angle. FIG. 5 is an enlarged view of a region V shown in FIG. FIG. 6 is an enlarged view of a region VI shown in FIG. FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG. FIG. 9 is a perspective view showing a SiC semiconductor wafer used for manufacturing the SiC semiconductor device shown in FIG. FIG. 10A is a cross-sectional view showing one example of the method for manufacturing the SiC semiconductor device shown in FIG. FIG. 10B is a view showing a step after FIG. 10A. FIG. 10C is a diagram showing a step after FIG. 10B. FIG. 10D is a diagram showing a step after FIG. 10C. FIG. 10E is a diagram showing a step after FIG. 10D. FIG. 10F is a diagram showing a step after FIG. 10E. FIG. 10G is a diagram showing a step after FIG. 10F. FIG. 10H is a diagram showing a step after FIG. 10G. FIG. 10I is a view showing a step after FIG. 10H. FIG. 10J is a view showing a step after FIG. 10I. FIG. 10K is a diagram showing a step after FIG. 10J. FIG. 10L is a diagram showing a step after FIG. 10K. FIG. 10M is a diagram showing a step after FIG. 10L. FIG. 11A is a partial cross-sectional view of the SiC semiconductor wafer structure, and is a partial cross-sectional view for describing a first embodiment of the shape of the reforming line formed in the step of FIG. 10K. FIG. 11B is a partial cross-sectional view of the SiC semiconductor wafer structure, and is a partial cross-sectional view for explaining a second embodiment of the shape of the reforming line formed in the step of FIG. 10K. FIG. 12 is a perspective view showing a semiconductor package in which a SiC semiconductor device is incorporated, through a sealing resin. FIG. 13A is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a second embodiment of the reforming line. FIG. 13B is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a third embodiment of the reforming line. FIG. 13C is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fourth embodiment of the reforming line. FIG. 13D is a perspective view showing the SiC semiconductor device shown in FIG. 3 and is a perspective view showing a fifth embodiment of the reforming line. FIG. 13E is a perspective view showing the SiC semiconductor device shown in FIG. 3 and is a perspective view showing a sixth embodiment of the reforming line. FIG. 13F is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a seventh embodiment of the reforming line. FIG. 14 is a perspective view showing the SiC semiconductor device according to the second embodiment of the present invention, and is a perspective view showing a structure to which the reforming line according to the first embodiment is applied. FIG. 15 is a perspective view of the SiC semiconductor device according to the third embodiment of the present invention viewed from one angle, and is a perspective view showing a structure to which the reforming line according to the first embodiment is applied. FIG. 16 is a perspective view of the SiC semiconductor device shown in FIG. 15 viewed from another angle. FIG. 17 is a plan view showing the SiC semiconductor device shown in FIG. FIG. 18 is a plan view in which the resin layer is removed from FIG. FIG. 19 is an enlarged view of a region XIX shown in FIG. 18 and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. FIG. 20 is a sectional view taken along the line XX-XX shown in FIG. FIG. 21 is a sectional view taken along the line XXI-XXI shown in FIG. FIG. 22 is an enlarged view of a region XXII shown in FIG. FIG. 23 is a sectional view taken along the line XXIII-XXIII shown in FIG. FIG. 24 is an enlarged view of a region XXIV shown in FIG. FIG. 25 is a graph for explaining sheet resistance. FIG. 26 is an enlarged view of a region corresponding to FIG. 19 and is an enlarged view showing the SiC semiconductor device according to the fourth embodiment of the present invention. FIG. 27 is a sectional view taken along the line XXVII-XXVII shown in FIG. FIG. 28 is an enlarged view of a region corresponding to FIG. 22, and is an enlarged view showing the SiC semiconductor device according to the fifth embodiment of the present invention. FIG. 29 is an enlarged view of a region corresponding to FIG. 19 and is an enlarged view showing the SiC semiconductor device according to the sixth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the embodiment of the present invention, a hexagonal SiC (silicon carbide) single crystal is applied. The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal) -SiC single crystal, a 4H-SiC single crystal, and a 6H-SiC single crystal according to the period of the atomic arrangement. In the embodiment of the present invention, an example in which a 4H—SiC single crystal is applied will be described, but other polytypes are not excluded from the present invention.

Hereinafter, the crystal structure of the 4H—SiC single crystal will be described. FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal (hereinafter, simply referred to as “unit cell”) applied to an embodiment of the present invention. FIG. 2 is a plan view showing a silicon surface of the unit cell shown in FIG.
Referring to FIGS. 1 and 2, the unit cell has a tetrahedral structure in which four C atoms are bonded to one Si atom in a tetrahedral arrangement (tetrahedral arrangement). The unit cell has an atomic arrangement in which tetrahedral structures are stacked in four periods. The unit cell has a regular hexagonal silicon surface, a regular hexagonal carbon surface, and a hexagonal prism structure having six side surfaces connecting the silicon surface and the carbon surface.

The silicon surface is a termination surface terminated by Si atoms. On the silicon surface, one Si atom is located at each of the six vertices of the regular hexagon, and one Si atom is located at the center of the regular hexagon.
The carbon surface is a terminal surface terminated by C atoms. On the carbon surface, one C atom is located at each of the six vertices of the regular hexagon, and one C atom is located at the center of the regular hexagon.

The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c) including the a1, a2, a3, and c axes. The value of a3 of the four coordinate axes takes a value of-(a1 + a2). Hereinafter, a crystal plane of a 4H—SiC single crystal will be described with reference to a silicon plane as an example of a hexagonal terminal plane.
The a1 axis, a2 axis, and a3 axis are the arrangement directions of the closest Si atoms (hereinafter simply referred to as “nearest atom directions”) with respect to the Si atom located at the center in a plan view of the silicon surface viewed from the c axis. )). The a1, a2, and a3 axes are set at an angle of 120 ° in accordance with the arrangement of Si atoms.

The c-axis is set in the direction normal to the silicon surface with reference to the Si atom located at the center. The silicon plane is a (0001) plane. The carbon plane is the (000-1) plane.
The side surface of the hexagonal prism includes six crystal planes along the direction of the nearest atom in a plan view of the silicon surface viewed from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes each including two closest Si atoms in plan view of the silicon plane viewed from the c-axis.

The side surfaces of the hexagonal prism are (1-100), (0-110), (-1010), and (-1100) clockwise from the tip of the a1 axis in a plan view of the silicon surface viewed from the c-axis. Plane, (01-10) plane and (10-10) plane.
The diagonal planes along the diagonal line of the hexagonal prism include six crystal planes along a crossing direction that intersects the nearest atom direction in a plan view of the silicon plane viewed from the c-axis. More specifically, the diagonal plane of the hexagonal prism includes six crystal planes each including two Si atoms that are not closest to each other in a plan view of the silicon plane viewed from the c-axis. When viewed from the Si atom located at the center, the crossing direction of the closest atom direction is an orthogonal direction orthogonal to the closest atom direction.

The diagonal planes of the hexagonal prism are (11-20) plane, (1-210) plane, (-2110) plane, (-1-120) plane, and (- 12-10) plane and (2-1-10) plane.
The crystal direction of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

  The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

The hexagonal crystal is six-fold symmetric, and has an equivalent crystal plane and an equivalent crystal direction every 60 °. For example, the (1-100) plane, the (0-110) plane, the (-1010) plane, the (-1100) plane, the (01-10) plane, and the (10-10) plane form equivalent crystal planes. ing.
The [1-100] direction, [0-110] direction, [-1010] direction, [-1100] direction, [01-10] direction, and [10-10] direction form equivalent crystal directions. ing. The [11-20] direction, [1-210] direction, [-2110] direction, [-1-120] direction, [-12-10] direction, and [2-1-10] direction are equivalent. A crystal direction is formed.

The c-axis is in the [0001] direction ([000-1] direction). The a1 axis is the [2-1-10] direction ([-2110] direction). The a2 axis is the [-12-10] direction ([1-210] direction). The a3 axis is in the [-1-120] direction ([11-20] direction).
The (0001) plane and the (000-1) plane are collectively referred to as a c-plane. The [0001] direction and the [000-1] direction are collectively referred to as the c-axis direction. The (11-20) plane and the (-1-120) plane are collectively referred to as an a-plane. The [11-20] direction and the [-1-120] direction are collectively referred to as the a-axis direction. The (1-100) plane and the (-1100) plane are collectively referred to as an m plane. The [1-100] direction and the [-1100] direction are collectively referred to as the m-axis direction.

FIG. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first embodiment of the reforming lines 22A to 22D. FIG. 4 is a perspective view of the SiC semiconductor device 1 shown in FIG. 3 as viewed from another angle.
FIG. 5 is an enlarged view of a region V shown in FIG. FIG. 6 is an enlarged view of a region VI shown in FIG. FIG. 7 is a plan view of the SiC semiconductor device 1 shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG.

Referring to FIGS. 3 to 8, SiC semiconductor device 1 includes SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 2 is formed in a rectangular chip shape.
The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. are doing. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter, simply referred to as “plan view”) viewed from the normal direction Z thereof. .

The first main surface 3 is an element formation surface on which a semiconductor element is formed. Second main surface 4 of SiC semiconductor layer 2 is formed of a ground surface having a grinding mark. Side surfaces 5A to 5D are each formed of a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 5A to 5D do not have grinding marks.
Thickness TL of SiC semiconductor layer 2 may be not less than 40 μm and not more than 200 μm. The thickness TL may be from 40 μm to 60 μm, from 60 μm to 80 μm, from 80 μm to 100 μm, from 100 μm to 120 μm, from 120 μm to 140 μm, from 140 μm to 160 μm, from 160 μm to 180 μm, or from 180 μm to 200 μm. The thickness TL is preferably not less than 60 μm and not more than 150 μm.

In this embodiment, first main surface 3 and second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon surface). Second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.
The first main surface 3 and the second main surface 4 have an off angle θ inclined at an angle of 10 ° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be not less than 0 ° and not more than 5.0 °. Off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5 ° or more and 3.0 ° or less, 3.0 ° or more and 3.5 ° or less, 3.5 ° or more and 4.0 ° or less, 4.0 ° or more and 4.5 ° or less, or 4.5 ° or more and 5.0 ° or less. The angle may be set in the following range. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off-angle θ may be set in a range from 3.0 ° to 4.5 °. In this case, it is preferable that the off-angle θ is set in a range from 3.0 ° to 3.5 ° or from 3.5 ° to 4.0 °.
The off angle θ may be set in the range of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off-angle θ is set in the range of 1.5 ° to 2.0 ° or 2.0 ° to 2.5 °.

The length of each of the side surfaces 5A to 5D may be 0.5 mm or more and 10 mm or less. The surface areas of the side surfaces 5A to 5D are equal to each other in this embodiment. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in plan view, the surface area of the side surfaces 5A, 5C may be smaller than the surface area of the side surfaces 5B, 5D, or the side surfaces 5B, 5D. May be exceeded.
In this embodiment, the side surface 5A and the side surface 5C extend along the first direction X and face each other in a second direction Y intersecting with the first direction X. In this embodiment, the side surfaces 5B and 5D extend along the second direction Y and face each other in the first direction X. The second direction Y is more specifically a direction orthogonal to the first direction X.

In this embodiment, the first direction X is set in the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set in the a-axis direction ([11-20] direction) of the SiC single crystal.
Side surface 5A and side surface 5C are formed by the a-plane of the SiC single crystal, and face each other in the a-axis direction. The side surface 5A is formed by the (-1-120) plane of the SiC single crystal. Side surface 5C is formed by the (11-20) plane of the SiC single crystal.

Side surface 5B and side surface 5D are formed by the m-plane of the SiC single crystal, and face each other in the m-axis direction. Side surface 5B is formed by the (-1100) plane of the SiC single crystal. Side surface 5D is formed by the (1-100) plane of the SiC single crystal.
The side surface 5A and the side surface 5C are inclined with respect to the normal to the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. A surface may be formed.

In this case, when the normal to the first main surface 3 of the SiC semiconductor layer 2 is 0 °, the side surfaces 5A and 5C have an off angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. It may be inclined at an appropriate angle. The angle corresponding to the off angle θ may be equal to the off angle θ, or may be an angle exceeding 0 ° and less than the off angle θ.
On the other hand, side surface 5B and side surface 5D extend planarly along the normal line of first main surface 3 of SiC semiconductor layer 2. More specifically, the side surfaces 5B and 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

In this embodiment, SiC semiconductor layer 2 has a stacked structure including n ⁺ -type SiC semiconductor substrate 6 and n-type SiC epitaxial layer 7. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6.
The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. Side surfaces 5A to 5D of SiC semiconductor layer 2 are formed by SiC semiconductor substrate 6 and SiC epitaxial layer 7.

The n-type impurity concentration of SiC epitaxial layer 7 is lower than the n-type impurity concentration of SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of SiC epitaxial layer 7 is lower than the n-type impurity concentration of SiC semiconductor substrate 6. The n-type impurity concentration of SiC semiconductor substrate 6 may be not less than 1.0 × 10 ¹⁸ cm ^{−3 and not} more than 1.0 × 10 ²¹ cm ⁻³ . The n-type impurity concentration of SiC epitaxial layer 7 may be not less than 1.0 × 10 ¹⁵ cm ^{−3 and not} more than 1.0 × 10 ¹⁸ cm ⁻³ .

  Thickness TS of SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS is 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, 90 μm to 100 μm, 100 μm to 110 μm, 110 μm to 120 μm, 120 μm to 130 μm, It may be 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By reducing the thickness of the SiC semiconductor substrate 6, the resistance value can be reduced by shortening the current path.

  The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

In the SiC semiconductor layer 2, an active region 8 and an outer region 9 are set. The active region 8 is a region where a Schottky barrier diode D as an example of a semiconductor element is formed. The outer region 9 is a region outside the active region 8.
The active region 8 is set at the center of the SiC semiconductor layer 2 with a space between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the inner region in plan view. The active region 8 is set in a square shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

The outer region 9 is set in a region between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the periphery of the active region 8. The outer region 9 is set in an endless shape (in this embodiment, a square ring) surrounding the active region 8 in plan view.
On the first main surface 3 of the SiC semiconductor layer 2, a main surface insulating layer 10 is formed. Main surface insulating layer 10 selectively covers active region 8 and outer region 9. Main surface insulating layer 10 may have a single-layer structure including a silicon oxide (SiO ₂ ) layer or a silicon nitride (SiN) layer.

Main surface insulating layer 10 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, main surface insulating layer 10 has a single-layer structure made of a silicon oxide layer.
The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed of cleavage planes.

The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
On the main surface insulating layer 10, a first main surface electrode layer 12 is formed. The first main surface electrode layer 12 is formed at the center of the SiC semiconductor layer 2 with an interval from the side surfaces 5A to 5D of the SiC semiconductor layer 2 to an inner region in plan view.

On the main surface insulating layer 10, a passivation layer 13 (insulating layer) is formed. Passivation layer 13 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.
Passivation layer 13 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure made of a silicon nitride layer.

The side surfaces 14A, 14B, 14C, 14D of the passivation layer 13 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 to an inner region in plan view. Passivation layer 13 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in plan view. The passivation layer 13 exposes the main surface insulating layer 10.
In the passivation layer 13, a subpad opening 15 that exposes a part of the first main surface electrode layer 12 as a pad region is formed. Subpad opening 15 is formed in a quadrangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
On the passivation layer 13, a resin layer 16 (insulating layer) is formed. The passivation layer 13 and the resin layer 16 form one insulating laminated structure (insulating layer). In FIG. 7, the resin layer 16 is indicated by hatching.

The resin layer 16 may include a negative type or positive type photosensitive resin. In this embodiment, the resin layer 16 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 16 may include polyimide as an example of a negative type photosensitive resin.
The resin side surfaces 17A, 17B, 17C, 17D of the resin layer 16 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 to the inner region in plan view. The resin layer 16 exposes the periphery of the first main surface 3 of the SiC semiconductor layer 2 in plan view. The resin layer 16 exposes the main surface insulating layer 10 together with the passivation layer 13. In this embodiment, the resin side surfaces 17A to 17D of the resin layer 16 are formed flush with the side surfaces 14A to 14D of the passivation layer 13.

The resin side surfaces 17A to 17D of the resin layer 16 are portions that divided the dicing street when cutting out the SiC semiconductor device 1 from one SiC semiconductor wafer. In this embodiment, the side surfaces 14A to 14D of the passivation layer 13 are also portions that have divided the dicing street.
By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is not necessary to physically cut the resin layer 16 and the passivation layer 13. Thereby, SiC semiconductor device 1 can be smoothly cut out from one SiC semiconductor wafer. Further, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

  The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 25 μm or less. Even if the distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) is 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 25 μm Good. Of course, side surfaces 14A to 14D of passivation layer 13 may be formed flush with side surfaces 5A to 5D of SiC semiconductor layer 2.

A pad opening 18 is formed in the resin layer 16 to expose a part of the first main surface electrode layer 12 as a pad region. Pad opening 18 that is formed in a square shape having parallel four sides on the sides 5A~5D of the SiC semiconductor layer 2 in a plan view.
The pad opening 18 communicates with the sub pad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the sub pad opening 15. The inner wall of the pad opening 18 may be located on the side surfaces 5A to 5D of the SiC semiconductor layer 2 with respect to the inner wall of the sub pad opening 15. The inner wall of the pad opening 18 may be located in a region inside the SiC semiconductor layer 2 with respect to the inner wall of the sub pad opening 15. The resin layer 16 may cover the inner wall of the subpad opening 15.

The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
A second main surface electrode layer 19 is formed on second main surface 4 of SiC semiconductor layer 2. The second main surface electrode layer 19 forms an ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

A plurality of reforming lines 22A to 22D (modified layers) are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D are formed one by one on the side surfaces 5A to 5D in a one-to-one correspondence.
The reforming lines 22A to 22D include a single-layer reforming line 22A formed on the side surface 5A, a single-layer reforming line 22B formed on the side surface 5B, a single-layer reforming line 22C formed on the side surface 5C, Also, it includes a one-layer reforming line 22D formed on the side surface 5D. The reforming lines 22A to 22D have a single layer in this embodiment.

An aspect in which a single-layer reforming line 22A is formed by a plurality of reforming lines 22A formed by overlapping a plurality of reforming lines 22A on the single-layer reforming line 22A. May be included.
In the one-layer reforming line 22B, a plurality of reforming lines 22B are formed so as to overlap with each other, so that a single-layer reforming line 22B can be regarded as being formed by a plurality of reforming lines 22B. May be included.

In the one-layer reforming line 22C, a plurality of reforming lines 22C are formed so as to overlap with each other, so that a single-layer reforming line 22C can be regarded as being formed by the plural-layer reforming line 22C. May be included.
An aspect in which a single-layer reforming line 22D is formed by overlapping a plurality of reforming lines 22D with each other in the one-layer reforming line 22D. May be included.

However, in these cases, since a plurality of reforming lines 22A to 22D must be formed for each of the side surfaces 5A to 5D, it cannot be said that the reforming lines 22A to 22D are preferable in view of an increase in man-hours and a delay in manufacturing time. . Therefore, this embodiment shows an example in which the reforming lines 22A to 22D each having a single layer are formed on each of the side surfaces 5A to 5D.
The reforming lines 22A to 22D include a layered region in which a part of the SiC single crystal forming the side surfaces 5A to 5D is modified to have a property different from that of the SiC single crystal. The modified lines 22A to 22D include regions in which the density, the refractive index, or the mechanical strength (crystal strength), or other physical properties are changed to properties different from those of the SiC single crystal.

  The reforming lines 22A to 22D may include at least one of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The melt-rehardened layer is a layer that is hardened again after a part of the SiC semiconductor layer 2 is melted. The defect layer is a layer including holes, cracks, and the like formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer in which a part of the SiC semiconductor layer 2 has been subjected to dielectric breakdown. The refractive index change layer is a layer in which a part of the SiC semiconductor layer 2 has changed to a refractive index different from that of the SiC single crystal.

Each of the reforming lines 22 </ b> A to 22 </ b> D extends in a strip shape along the tangential direction of the first main surface 3, and includes a portion that extends obliquely with respect to the first main surface 3. The reforming lines 22A to 22D intersect the normal line of the first main surface 3 of the SiC semiconductor layer 2. Further, the modified lines 22A to 22D intersect with the tangent to the first main surface 3 of the SiC semiconductor layer 2.
In this embodiment, the reforming lines 22 </ b> A to 22 </ b> D are linearly inclined downward from the first main surface 3 to the second main surface 4. That is, the reforming lines 22 </ b> A to 22 </ b> D include portions extending linearly from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2.

  More specifically, the reforming lines 22A to 22D include a first end 23 on the first main surface 3 side and a second end 24 on the second main surface 4 side in the normal direction Z. The reforming lines 22A to 22D are inclined such that the first end 23 and the second end 24 run parallel to each other. The inclination angles and inclination directions of the reforming lines 22A to 22D are arbitrary, and are not limited to specific angles and directions.

  The reforming line 22A extends obliquely at an arbitrary angle with respect to the m-axis of the SiC single crystal on the side surface 5A. The reforming line 22B extends obliquely at an arbitrary angle with respect to the a-axis of the SiC single crystal on the side surface 5B. The reforming line 22C extends obliquely at an arbitrary angle with respect to the m-axis of the SiC single crystal on the side surface 5C. The reforming line 22D extends at an arbitrary angle with respect to the a-axis of the SiC single crystal on the side surface 5D.

The reforming lines 22A to 22D are formed at an interval from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. The reforming lines 22A to 22D expose the surface portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D. That is, the modified lines 22A to 22D are not formed on the main surface insulating layer 10, the passivation layer 13, and the resin layer 16.
The reforming lines 22A to 22D are formed at an interval from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The reforming lines 22A to 22D expose the surface portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

Thereby, the reforming lines 22A to 22D connect the respective side surfaces 5A to 5D of the SiC semiconductor layer 2 to the first main surface 3 side when viewed from the side normal to the respective side surfaces 5A to 5D of the SiC semiconductor layer 2. It is divided into two regions, namely, a region and a region on the second main surface 4 side.
The reforming lines 22A to 22D are formed on the SiC semiconductor substrate 6. The reforming lines 22A to 22D are formed at intervals from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4.

Thereby, the reforming lines 22A to 22D expose the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. That is, the SiC epitaxial layer 7 is included in a region on the first main surface 3 side of the region divided into two by the reforming lines 22A to 22D on the side surfaces 5A to 5D of the SiC semiconductor layer 2.
The reforming lines 22A to 22D include a first region 25, a second region 26 in which the first end 23 and the second end 24 are located in different regions in the thickness direction (normal direction Z) of the SiC semiconductor layer 2. Each includes a connection region 27.

  The first region 25 is a region where the first end 23 and the second end 24 are formed on the first main surface 3 side of the SiC semiconductor layer 2 in the modified lines 22A to 22D. In this embodiment, the first region 25 is formed near a corner of the SiC semiconductor layer 2. It is preferable that part or all of the first region 25 be located on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the middle part in the thickness direction of the SiC semiconductor layer 2.

The second region 26 is a region where the first end 23 and the second end 24 are shifted from the first region 25 toward the second main surface 4 of the SiC semiconductor layer 2 in the reforming lines 22A to 22D. It is. In this embodiment, second region 26 is formed near a corner of SiC semiconductor layer 2.
The first end 23 of the second region 26 is located on the second main surface 4 side with respect to the first end 23 of the first region 25. The first end 23 of the second region 26 may be located on the second main surface 4 side with respect to the second end 24 of the first region 25. Part or all of the second region 26 is preferably located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the middle part in the thickness direction of the SiC semiconductor layer 2.

  The connection region 27 is inclined downward from the first region 25 toward the second region 26, and connects the first region 25 and the second region 26. The connection region 27 extends linearly in this embodiment. When the first region 25 and the second region 26 sandwich the middle part in the thickness direction of the SiC semiconductor layer 2, the connection region 27 crosses the middle part in the thickness direction of the SiC semiconductor layer 2 and the first region 25 and the second region 26. The two regions 26 are connected.

A first region 25 of the reforming line 22A and a first region 25 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second region 26 of the reforming line 22A and a second region 26 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.
The first region 25 of the reforming line 22A and the second region 26 of the reforming line 22B may be located at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second region 26 of the reforming line 22A and a first region 25 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

The reforming line 22A and the reforming line 22B may be continuous with each other at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, or may be formed with an interval therebetween.
The first region 25 of the reforming line 22B and the first region 25 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. The second region 26 of the reforming line 22B and the second region 26 of the reforming line 22C may be located at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

A first region 25 of the reforming line 22B and a second region 26 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. A second region 26 of the reforming line 22B and a first region 25 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.
The reforming line 22B and the reforming line 22C may be continuous with each other at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, or may be formed with an interval therebetween.

The first region 25 of the reforming line 22C and the first region 25 of the reforming line 22D may be located at the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second region 26 of the reforming line 22C and a second region 26 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.
A first region 25 of the reforming line 22C and a second region 26 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second region 26 of the reforming line 22C and a first region 25 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.

The reforming line 22C and the reforming line 22D may be continuous with each other at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, or may be formed with an interval therebetween.
The first region 25 of the reforming line 22D and the first region 25 of the reforming line 22A may be located at the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. The second region 26 of the reforming line 22D and the second region 26 of the reforming line 22A may be located at the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

A first region 25 of the reforming line 22D and a second region 26 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. A second region 26 of the reforming line 22D and a first region 25 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.
The reforming line 22D and the reforming line 22A may be continuous with each other at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, or may be formed with an interval therebetween.

The reforming line 22A and the reforming line 22C may extend in directions that intersect each other when the side surfaces 5A and 5C are viewed from the side of the a-axis . The reforming line 22A and the reforming line 22C may extend in parallel with each other when the side surfaces 5A and 5C are viewed from the side of the a-axis .
The reforming line 22B and the reforming line 22D may extend in directions intersecting each other when the side surfaces 5B and 5D are viewed from the side in the m-axis direction . The reforming line 22B and the reforming line 22D may extend in parallel with each other when the side surfaces 5B and 5D are viewed from the side in the m-axis direction .

All of the reforming lines 22 </ b> A to 22 </ b> D may be formed at intervals at corners of the SiC semiconductor layer 2. Further, at least two of the reforming lines 22 </ b> A to 22 </ b> D may be connected to each other at a corner of the SiC semiconductor layer 2.
Further, all of the reforming lines 22 </ b> A to 22 </ b> D may be connected to each other at the corners of the SiC semiconductor layer 2. That is, the reforming lines 22A to 22D may be integrally formed so as to surround the SiC semiconductor layer 2. In this case, the reforming lines 22A to 22D form one endless (annular) reforming line surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

The thickness TR of the modified lines 22A to 22D in the normal direction Z is preferably equal to or less than the thickness TL of the SiC semiconductor layer 2 (TR ≦ TL). More preferably, the thickness TR of the reforming lines 22A to 22D is less than the thickness TS of the SiC semiconductor substrate 6 (TR <TS).
The thickness TR of the reforming lines 22A to 22D may be equal to or larger than the thickness TE of the SiC epitaxial layer 7 (TR ≧ TE). The thickness TR of the reforming line 22A, the thickness TR of the reforming line 22B, the thickness TR of the reforming line 22C, and the thickness TR of the reforming line 22D may be equal to or different from each other. You may.

The ratio TR / TL of the thickness TR of the modified lines 22A to 22D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.1 or more and less than 1.0. The ratio TR / TL is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0. It may be.
The ratio TR / TL is 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6. , 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TL is preferably 0.2 or more and 0.5 or less.

The ratio TR / TS of the thickness TR of the modified lines 22A to 22D to the thickness TS of the SiC semiconductor substrate 6 is more preferably 0.1 or more and less than 1.0. The ratio TR / TS is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0. It may be.
The ratio TR / TS is 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6. , 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TS is preferably 0.2 or more and 0.5 or less.

  Referring to FIG. 5, reforming line 22A includes a plurality of a-plane reforming sections 28 (reforming sections). In other words, the reforming line 22A is formed by an aggregate of a plurality of a-plane reforming sections 28. The plurality of a-plane modified portions 28 are portions where the SiC single crystal exposed from the side surface 5A has been modified to have properties different from those of the SiC single crystal. The area around the a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

The plurality of a-plane modified portions 28 connect one end 28a located on the first main surface 3 side, the other end 28b located on the second main surface 4 side, and one end 28a and the other end 28b. Each includes a connection portion 28c.
The plurality of a-plane modified portions 28 are each formed in a linear shape extending in the normal direction Z. Thereby, the plurality of a-plane modified portions 28 are formed in a stripe shape as a whole. The plurality of a-plane modified portions 28 may include a plurality of a-plane modified portions 28 formed in a tapered shape in which the width in the m-axis direction decreases from the one end 28a to the other end 28b.

  The plurality of a-plane modified portions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The plurality of a-plane modified portions 28 may overlap each other in the m-axis direction. More specifically, the plurality of a-plane modified portions 28 are spaced apart from each other such that the distance between the first main surface 3 and the one end 28 a gradually increases from the first region 25 toward the second region 26. It is formed. Further, the plurality of a-plane modified portions 28 are formed at intervals from each other such that the distance between the second main surface 4 and the other end portion 28 b gradually decreases from the first region 25 toward the second region 26. ing.

A strip-shaped region extending in the m-axis direction forms a line (first end 23) connecting the one end portions 28a of the plurality of a-plane reforming portions 28 and a line connecting the other end portions 28b of the plurality of a-plane reforming portions 28 ( Second end 24). The reforming line 22A is formed by this band-shaped region.
The plurality of a-plane reforming portions 28 may form cutouts formed by cutting the side surface 5A. The plurality of a-plane modified portions 28 may respectively form recesses that are recessed from the side surface 5A in the a-axis direction. The plurality of a-plane modified portions 28 may be formed in a dot shape (dot shape) according to the length in the normal direction Z or the width in the m-axis direction.

In the m-axis direction, the pitch PR between the central portions of the plurality of a-plane modified portions 28 adjacent to each other may be more than 0 μm and 20 μm or less. The pitch PR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.
In the m-axis direction, the width WR of each a-plane reforming section 28 may be more than 0 μm and 20 μm or less. The width WR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

The reforming line 22C has the same structure as the reforming line 22A, except that the reforming line 22C is formed on the side surface 5C. The description of the reforming line 22A is applied mutatis mutandis to the description of the reforming line 22C by replacing “side surface 5A” with “side surface 5C”.
Referring to FIG. 6, reforming line 22D includes a plurality of m-plane reforming sections 29 (reforming sections). In other words, the reforming line 22D is formed by an aggregate of a plurality of m-plane reforming sections 29. The plurality of m-plane modified portions 29 are portions where the SiC single crystal exposed from the side surface 5D has been modified to have properties different from those of the SiC single crystal. The area around each m-plane modified portion 29 on the side surface 5D may be modified to have a property different from that of the SiC single crystal.

The plurality of m-plane modifying portions 29 connect one end 29a located on the first main surface 3 side, the other end 29b located on the second main surface 4 side, and one end 29a and the other end 29b. It includes a connection portion 29c.
The plurality of m-plane modified portions 29 are each formed in a linear shape extending in the normal direction Z. Thereby, the plurality of m-plane modified portions 29 are formed in a stripe shape as a whole. The plurality of m-plane reforming sections 29 may include a plurality of m-plane reforming sections 29 formed in a tapered shape in which the width in the a-axis direction decreases from the one end 29a side to the other end 29b side.

  The plurality of m-plane modified portions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The plurality of m-plane reforming sections 29 may overlap each other in the a-axis direction. In this embodiment, the plurality of m-plane modified portions 29 are formed at intervals from each other such that the distance between the first main surface 3 and the one end portion 29a gradually increases from the first region 25 to the second region 26. Have been. Further, the plurality of m-plane modified portions 29 are formed at intervals from each other such that the distance between the second main surface 4 and the other end portion 29b gradually decreases from the first region 25 toward the second region 26. ing.

A band-like region extending in the a-axis direction is a line connecting the one end portions 29a of the plurality of m-plane reforming portions 29 (first end portion 23) and a line connecting the other end portions 29b of the plurality of m-plane reforming portions 29 ( Second end 24). The reforming line 22D is formed by this band-shaped region.
The plurality of m-plane reforming portions 29 may form cutouts formed by cutting out the side surface 5D. The plurality of m-plane modified portions 29 may form recesses that are recessed from the side surface 5D toward the m-axis direction. The plurality of m-plane modified portions 29 may be formed in a dot shape (dot shape) according to the length in the normal direction Z or the width in the a-axis direction.

In the a-axis direction, the pitch PR between the central portions of the plurality of m-plane modified portions 29 adjacent to each other may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.
In the a-axis direction, the width WR of each m-plane reforming section 29 may be more than 0 μm and 20 μm or less. The width WR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

The reforming line 22B has the same structure as the reforming line 22D except that the reforming line 22B is formed on the side surface 5B. The description of the reforming line 22D is applied mutatis mutandis to the description of the reforming line 22B by replacing "side surface 5D" with "side surface 5B".
Referring to FIG. 8, an n-type diode region 35 is formed in a surface layer portion of first main surface 3 of SiC semiconductor layer 2 in active region 8. In this embodiment, diode region 35 is formed at the center of first main surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 35 is set in a quadrangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view.

  The n-type impurity concentration of diode region 35 may be equal to or higher than the n-type impurity concentration of SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed using a part of the SiC epitaxial layer 7. The n-type impurity concentration of diode region 35 is equal to the n-type impurity concentration of SiC epitaxial layer 7. Diode region 35 may be formed by introducing an n-type impurity into the surface portion of SiC epitaxial layer 7.

In the outer region 9, a p ⁺ -type guard region 36 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The guard region 36 is formed in a band shape extending along the diode region 35 in a plan view.
More specifically, the guard region 36 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners or a ring shape) surrounding the diode region 35 in plan view. Thus, the guard region 36 is formed as a guard ring region. The diode region 35 is defined by the guard region 36 in this embodiment. The active area 8 is defined by the guard area 36.

The p-type impurity in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurity of the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.
On the first main surface 3 of the SiC semiconductor layer 2, the above-described main surface insulating layer 10 is formed. The main surface insulating layer 10 has a diode opening 37 for exposing the diode region 35. The diode opening 37 exposes the inner periphery of the guard region 36 in addition to the diode region 35. The diode opening 37 is formed in a square shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

On the main surface insulating layer 10, the above-mentioned first main surface electrode layer 12 is formed. The first main surface electrode layer 12 enters the diode opening 37 from above the insulating layer. First main surface electrode layer 12 is electrically connected to diode region 35 in diode opening 37.
More specifically, the first main surface electrode layer 12 forms a Schottky junction with the diode region 35. As a result, a Schottky barrier diode D having the first main surface electrode layer 12 as an anode and the diode region 35 as a cathode is formed. The passivation layer 13 and the resin layer 16 described above are formed on the main surface insulating layer 10.

FIG. 9 is a perspective view showing a SiC semiconductor wafer 41 used for manufacturing the SiC semiconductor device 1 shown in FIG.
The SiC semiconductor wafer 41 is a member serving as a base of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. In this embodiment, SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of SiC semiconductor substrate 6.

The SiC semiconductor wafer 41 is formed in a plate shape or a plate shape. SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43. ing.
The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS <TW). The thickness TW of SiC semiconductor wafer 41 is adjusted to the thickness TS of SiC semiconductor substrate 6 by grinding.

  The thickness TW may be more than 150 μm and 750 μm or less. The thickness TW may be more than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less, or 600 μm or more and 750 μm or less. In consideration of the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably more than 150 μm and 500 μm or less. The thickness TW is typically not less than 300 μm and not more than 450 μm.

In this embodiment, first wafer main surface 42 and second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon surface). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.
The first wafer main surface 42 and the second wafer main surface 43 have an off angle θ inclined at an angle of 10 ° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be not less than 0 ° and not more than 5.0 °. Off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5 ° or more and 3.0 ° or less, 3.0 ° or more and 3.5 ° or less, 3.5 ° or more and 4.0 ° or less, 4.0 ° or more and 4.5 ° or less, or 4.5 ° or more and 5.0 ° or less. The angle may be set in the following range. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off-angle θ may be set in a range from 3.0 ° to 4.5 °. In this case, it is preferable that the off-angle θ is set in a range from 3.0 ° to 3.5 ° or from 3.5 ° to 4.0 °.
The off angle θ may be set in the range of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off-angle θ is set in the range of 1.5 ° to 2.0 ° or 2.0 ° to 2.5 °.

  SiC semiconductor wafer 41 includes a first wafer corner 45 connecting first wafer main surface 42 and wafer side surface 44, and a second wafer corner 46 connecting second wafer main surface 43 and wafer side 44. The first wafer corner 45 has a first chamfered portion 47 inclined downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner portion 46 has a second chamfered portion 48 inclined downward from the second wafer main surface 43 toward the wafer side surface 44.

The first chamfered portion 47 may be formed in a convexly curved shape. The second chamfered portion 48 may be formed in a convexly curved shape. First chamfered portion 47 and second chamfered portion 48 suppress cracking of SiC semiconductor wafer 41.
On the wafer side surface 44 of the SiC semiconductor wafer 41, one orientation flat 49 is formed as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed in the side surface 44 of the SiC semiconductor wafer 41. In this embodiment, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

A plurality (for example, two) of orientation flats 49 indicating the crystal orientation may be formed on the side surface 44 of the SiC semiconductor wafer 41. The plurality (for example, two) of the orientation flats 49 may include a first orientation flat and a second orientation flat.
The first orientation flat may be a notch extending linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch extending linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

On the first wafer main surface 42 of the SiC semiconductor wafer 41, a plurality of device forming regions 51 respectively corresponding to the SiC semiconductor devices 1 are set. The plurality of device formation regions 51 are set in a matrix array with an interval in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).
Each device forming region 51 has four sides 52A, 52B, 52C, 52D along the crystal orientation of the SiC single crystal. The four sides 52A to 52D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. That is, the four sides 52A to 52D are defined by two sides 52A and 52C along the m-axis direction ([1-100] direction) and two sides 52B and 52D along the a-axis direction ([11-20] direction). Including.

The plurality of device forming regions 51 are each partitioned by a grid-shaped planned cutting line 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The planned cutting line 53 includes a plurality of first planned cutting lines 54 and a plurality of second planned cutting lines 55.
The plurality of first cutting lines 54 extend along the m-axis direction ([1-100] direction). The plurality of second planned cutting lines 55 extend along the a-axis direction ([11-20] direction). After a predetermined structure is formed in the plurality of device formation regions 51, the plurality of SiC semiconductor devices 1 are cut out by cutting the SiC semiconductor wafer 41 along the planned cutting line 53.

10A to 10M are cross-sectional views illustrating an example of a method for manufacturing the SiC semiconductor device 1 illustrated in FIG. 10A to 10M show only a region where three SiC semiconductor devices 1 are formed for convenience of description, and omit illustration of other regions.
Referring to FIG. 10A, in manufacturing SiC semiconductor device 1, first, SiC semiconductor wafer 41 is prepared (see also FIG. 9). Next, n-type SiC epitaxial layer 7 is formed on first main surface 42 of SiC semiconductor wafer 41.

In the step of forming SiC epitaxial layer 7, SiC is epitaxially grown from first wafer main surface 42 of SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.
Thus, a SiC semiconductor wafer structure 61 including the SiC semiconductor wafer 41 and the SiC epitaxial layer 7 is formed. SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

First main surface 62 and second main surface 63 of SiC semiconductor wafer structure 61 correspond to first main surface 3 and second main surface 4 of SiC semiconductor layer 2, respectively. The thickness TWS of the SiC semiconductor wafer structure 61 may be more than 150 μm and 800 μm or less. The thickness TWS is preferably more than 150 μm and 550 μm or less.
Next, referring to FIG. 10B, p ⁺ -type guard region 36 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The step of forming the guard region 36 includes a step of selectively introducing a p-type impurity into the surface layer of the first main surface 62 of the SiC semiconductor wafer structure 61 via an ion implantation mask (not shown). More specifically, guard region 36 is formed in the surface portion of SiC epitaxial layer 7.

Guard region 36 partitions active region 8 and outer region 9 in SiC semiconductor wafer structure 61. An n-type diode region 35 is defined in a region (active region 8) surrounded by the guard region 36.
Diode region 35 may be formed by selectively introducing an n-type impurity into a surface layer of first main surface 62 of SiC semiconductor wafer structure 61 via an ion implantation mask (not shown).

Next, referring to FIG. 10C, main surface insulating layer 10 is formed on first main surface 62 of SiC semiconductor wafer structure 61. Main surface insulating layer 10 includes silicon oxide (SiO ₂ ). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).
Next, referring to FIG. 10D, mask 64 having a predetermined pattern is formed on main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 respectively expose regions where the diode openings 37 are to be formed in the main surface insulating layer 10.

Next, unnecessary portions of the main surface insulating layer 10 are removed by an etching method via the mask 64. As a result, a diode opening 37 is formed in the main surface insulating layer 10. After the formation of the diode opening 37, the mask 64 is removed.
Next, referring to FIG. 10E, base electrode layer 66 serving as a base of first main surface electrode layer 12 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire area of the first main surface 62 of the SiC semiconductor wafer structure 61, and covers the main surface insulating layer 10. The first main surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Next, referring to FIG. 10F, a mask 67 having a predetermined pattern is formed on base electrode layer 66. The mask 67 has an opening 68 for exposing a region other than the region where the first main surface electrode layer 12 is to be formed in the base electrode layer 66.
Next, an unnecessary portion of the base electrode layer 66 is removed by an etching method via the mask 67. Thereby, the base electrode layer 66 is divided into the plurality of first main surface electrode layers 12. After the formation of the first main surface electrode layer 12, the mask 67 is removed.

Next, referring to FIG. 10G, passivation layer 13 is formed on first main surface 62 of SiC semiconductor wafer structure 61. Passivation layer 13 includes silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.
Next, referring to FIG. 10H, resin layer 16 is applied on passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may include polybenzoxazole as an example of a positive type photosensitive resin.

Next, referring to FIG. 10I, after resin layer 16 is selectively exposed, it is developed. Thereby, pad openings 18 are formed in the resin layer 16. Further, dicing streets 69 along the cutting lines 53 (sides 52A to 52D of each device forming area 51) are partitioned into the resin layers 16.
Next, unnecessary portions of the passivation layer 13 are removed. Unnecessary portions of the passivation layer 13 may be removed by an etching method via the resin layer 16. Thereby, a subpad opening 15 is formed in the passivation layer 13. Further, a dicing street 69 along the cutting line 53 is partitioned into the passivation layer 13.

In this embodiment, the step of removing unnecessary portions of the passivation layer 13 using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the sub pad opening 15 is formed in the passivation layer 13.
In this case, prior to the step of forming the resin layer 16, unnecessary portions of the passivation layer 13 are removed by an etching method using a mask, and a subpad opening 15 is formed. According to this step, the passivation layer 13 can be formed in any shape.

Next, referring to FIG. 10J, second main surface 63 of SiC semiconductor wafer structure 61 (second wafer main surface 43 of SiC semiconductor wafer 41) is ground. Thereby, SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is thinned. Also, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61.
The SiC semiconductor wafer structure 61 is ground until the thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2 is reached. The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm or more and 200 μm or less.

That is, the SiC semiconductor wafer 41 is ground until the thickness TW corresponds to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground until the thickness TW becomes 40 μm or more and 150 μm or less.
Next, referring to FIG. 10K, a plurality of reforming lines 70 (reforming layers) serving as bases of reforming lines 22A to 22D are formed. In the step of forming the reforming line 70, pulsed laser light is irradiated from the laser light irradiation device 71 toward the SiC semiconductor wafer structure 61.

In this embodiment, the SiC semiconductor wafer structure 61 is irradiated with the laser light from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the main surface insulating layer 10. The laser beam may be directly applied to the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.
The condensing part (focal point) of the laser beam is set at a middle part of the SiC semiconductor wafer structure 61 in the thickness direction. The irradiation position of the laser beam on the SiC semiconductor wafer structure 61 is moved along the line 53 to be cut (four sides 52A to 52D of each device forming area 51).

The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54. The irradiation position of the laser beam on the SiC semiconductor wafer structure 61 is moved along the second scheduled cutting line 55. Hereinafter, a specific shape of the reforming line 70 formed in this step will be described with reference to FIGS. 11A and 11B.
FIG. 11A is a partial cross-sectional view of the SiC semiconductor wafer structure 61 and is a partial cross-sectional view for explaining a first embodiment of the reforming line 70 formed in the step of FIG. 10K.

  Referring to FIG. 11, the position of the laser light focusing portion (focal point) in the thickness direction of SiC semiconductor wafer structure 61 is adjusted according to the irradiation position of the laser light on first planned cutting line 54. In this embodiment, a bent, curved, or curved reforming line that bends (meanders) a plurality of times toward the first main surface 62 and the second main surface 63 and extends along the first planned cutting line 54. 70 is formed.

By adjusting the condensing portion (focal point) of the laser beam, a curved line extending along the first planned cutting line 54 and meandering a plurality of times toward the first main surface 62 and the second main surface 63 is provided. A quality line 70 may be formed.
The bending cycle (meandering cycle) of the reforming line 70 along the first cutting line 54 is arbitrary depending on the appearance of the SiC semiconductor device 1 cut out from the SiC semiconductor wafer structure 61 (the shape of the reforming lines 22A and 22C). Take a value.

  Although not specifically illustrated, the same steps as those performed on the first scheduled cutting line 54 are also performed on the second scheduled cutting line 55. That is, the position of the condensing portion (focal point) of the laser beam in the thickness direction of the SiC semiconductor wafer structure 61 is adjusted according to the irradiation position of the laser beam on the second scheduled cutting line 55. In this embodiment, a bent, curved, or curved reforming line that bends (meanders) a plurality of times toward the first main surface 62 and the second main surface 63 and extends along the second scheduled cutting line 55. 70 is formed.

By adjusting the condensing portion (focal point) of the laser light, the curved portion extends along the second planned cutting line 55 and meanders a plurality of times toward the first main surface 62 and the second main surface 63. A quality line 70 may be formed.
The bending cycle (meandering cycle) of the reforming line 70 along the second scheduled cutting line 55 is arbitrary depending on the appearance of the SiC semiconductor device 1 cut out from the SiC semiconductor wafer structure 61 (the shape of the reforming lines 22B and 22D). Take a value. In this way, a plurality of reforming lines 70 are formed one layer at a time in a one-to-one correspondence with the four sides 52A to 52D of each device formation region 51.

The two reforming lines 70 along the sides 52A and 52C of the device forming region 51 include the a-plane reforming portions 28, respectively. The two reforming lines 70 along the sides 52B and 52D of the device forming region 51 include the m-plane reforming portions 29, respectively.
The plurality of reforming lines 70 are also laser processing marks formed in the middle part of the SiC semiconductor wafer structure 61 in the thickness direction. More specifically, the a-plane reforming section 28 and the m-plane reforming section 29 of the reforming line 70 are laser processing marks.

FIG. 11B is a partial cross-sectional view of the SiC semiconductor wafer structure 61 and is a partial cross-sectional view for explaining a second embodiment of the reforming line 70 formed in the step of FIG. 10K.
In the first embodiment, the example in which the reforming line 70 is formed in a belt shape continuously extending along the first planned cutting line 54 (second planned cutting line 55) has been described. However, as shown in FIG. 11B, the reforming line 70 may be formed intermittently along the first planned cutting line 54 (second planned cutting line 55).

In this case, the reforming line 70 preferably has a plurality of divided portions 70a formed one layer at a time in a one-to-one correspondence with each side 52A to 52D of each device forming region 51. The plurality of divided portions 70a correspond to the reforming lines 22A to 22D, respectively.
In this manner, a plurality of reforming lines 70 each including a plurality of divided portions 70a formed one layer at a time in a one-to-one correspondence with the four sides 52A to 52D of each device forming region 51 are formed. You.

The focusing portion (focus) of the laser beam, laser energy, pulse duty ratio, irradiation speed, and the like are arbitrary depending on the position, size, shape, thickness, and the like of the reforming line 70 (the reforming lines 22A to 22D) to be formed. Is determined.
Next, referring to FIG. 10L, second main surface electrode layer 19 is formed on second main surface 63 of SiC semiconductor wafer structure 61. The second main surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Prior to the step of forming the second main surface electrode layer 19, annealing may be performed on the second main surface 63 (ground surface) of the SiC semiconductor wafer structure 61. The annealing may be performed by a laser annealing using a laser beam.
According to the laser annealing method, the SiC single crystal in the surface portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form a Si amorphous layer. In this case, the SiC semiconductor device 1 having the Si amorphous layer in the surface portion of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and a Si amorphous layer coexist. According to the laser annealing method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be improved.

Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from SiC semiconductor wafer structure 61. In this step, a tape-shaped support member 73 is attached to the second main surface 63 of the SiC semiconductor wafer structure 61.
Next, an external force is applied to the cut line 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force to the cutting line 53 may be applied by a pressing member such as a blade.

In another embodiment, a support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the cut line 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.
In still another embodiment, an elastic supporting member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the elastic support member 73 in the m-axis direction and the a-axis direction.

When the SiC semiconductor wafer structure 61 is cleaved using the support member 73, it is preferable that the support member 73 be attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 with few obstacles.
In this manner, the SiC semiconductor wafer structure 61 is cleaved along the cut line 53 starting from the reforming line 70 (the reforming lines 22A to 22D), and the plurality of SiC semiconductor devices 1 are formed into one SiC semiconductor wafer structure. 61 (SiC semiconductor wafer 41).

  The portion of the reforming line 70 along the side 52A of each device forming region 51 becomes the reforming line 22A. The portion of the reforming line 70 along the side 52B of each device forming region 51 becomes the reforming line 22B. The portion of the reforming line 70 along the side 52C of each device forming region 51 becomes the reforming line 22C. The portion of the reforming line 70 along the side 52D of each device forming region 51 becomes the reforming line 22D. Through the steps including the above, the SiC semiconductor device 1 is manufactured.

  In this embodiment, the step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) was performed prior to the step of forming the reforming line 70 (the reforming lines 22A to 22D) (FIG. 10K). However, the grinding step of SiC semiconductor wafer structure 61 (FIG. 10J) is performed at an arbitrary timing after the step of preparing SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming second main surface electrode layer 19 (FIG. 10L). Can be implemented.

For example, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the step of forming SiC epitaxial layer 7 (FIG. 10A). Further, the grinding step (FIG. 10J) of SiC semiconductor wafer structure 61 may be performed after the forming step (FIG. 10K) of reforming line 70 (reforming lines 22A to 22D).
The grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) includes a preparation step of the SiC semiconductor wafer 41 (FIG. 10A) and a forming step of the reforming line 70 (the reforming lines 22A to 22D) (FIG. 10K). It may be carried out a plurality of times at an arbitrary timing before. The grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 is performed at an arbitrary timing after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming the second main surface electrode layer 19 (FIG. 10L). May be implemented in plural times.

FIG. 12 is a perspective view showing a semiconductor package 74 in which the SiC semiconductor device 1 is incorporated, through a sealing resin 79.
Referring to FIG. 12, semiconductor package 74 is of a so-called TO-220 type in this embodiment. The semiconductor package 74 includes the SiC semiconductor device 1, a pad section 75, a heat sink 76, a plurality of (two in this embodiment) terminals 77, a plurality of (two in this embodiment) conductive wires 78, and a sealing resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

The pad section 75 includes a metal plate. The pad section 75 may include iron, gold, silver, copper, aluminum, and the like. The pad section 75 is formed in a square shape in plan view. Pad portion 75 has a plane area larger than the plane area of SiC semiconductor device 1. SiC semiconductor device 1 is arranged on pad portion 75.
The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via the conductive bonding material 80. The conductive bonding material 80 is interposed in a region between the second main surface electrode layer 19 and the pad portion 75.

  The conductive bonding material 80 may be a metal paste or solder. The metal paste may be a conductive paste containing Au (gold), Ag (silver), or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be a lead-free solder. The solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

The heat sink 76 is connected to one side of the pad section 75. In this embodiment, the pad section 75 and the heat sink 76 are formed of a single metal plate. The heat sink 76 has a through hole 76a. The through hole 76a is formed in a circular shape.
The plurality of terminals 77 are arranged along a side opposite to the heat sink 76 with respect to the pad portion 75. Each of the plurality of terminals 77 includes a metal plate. The terminal 77 may include iron, gold, silver, copper, aluminum, and the like.

The plurality of terminals 77 include a first terminal 77A and a second terminal 77B. The first terminal 77 </ b> A and the second terminal 77 </ b> B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76. The first terminal 77A and the second terminal 77B extend in a band along a direction orthogonal to the arrangement direction.
The plurality of conductors 78 may be bonding wires or the like. The plurality of conductors 78 include a conductor 78A and a conductor 78B. The conducting wire 78A is electrically connected to the first terminal 77A and the first main surface electrode layer 12 of the SiC semiconductor device 1. Thereby, the first terminal 77A is electrically connected to the first main surface electrode layer 12 of the SiC semiconductor device 1 via the conducting wire 78A.

The conducting wire 78B is electrically connected to the second terminal 77B and the pad section 75. Thus, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 via the conductive wire 78B. The second terminal 77B may be formed integrally with the pad section 75.
The sealing resin 79 seals the SiC semiconductor device 1, the pad portion 75, and the plurality of conductive wires 78 so as to expose a part of the heat sink 76 and the plurality of terminals 77. The sealing resin 79 is formed in a rectangular parallelepiped shape.

  The form of the semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar to these may be applied.

  As described above, in the SiC semiconductor device 1, the reforming lines 22A to 22D extending in a belt shape inclined with respect to the first main surface 3 are formed one by one on each of the side surfaces 5A to 5D of the SiC semiconductor layer 2. More specifically, the SiC semiconductor device 1 includes a first region 25 formed on the first main surface 3 side of the SiC semiconductor layer 2, and a first region 25 formed on the second main surface 4 side of the SiC semiconductor layer 2. And a connection region 27 that connects the first region 25 and the second region 26.

  Thereby, the starting point of cutting can be appropriately formed in the region on the first main surface 3 side of the SiC semiconductor layer 2 and the region on the second main surface 4 side of the SiC semiconductor layer 2 by the single-layer reforming lines 22A to 22D. Therefore, at the time of manufacturing the SiC semiconductor device 1, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be formed without forming a plurality of reforming lines 70 along the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). 41) can be appropriately cut.

Thereby, it is possible to appropriately reduce the formation area of the modified lines 22A to 22D on each of the side surfaces 5A to 5D of the SiC semiconductor layer 2. Therefore, the influence on the SiC semiconductor layer 2 due to the reforming lines 22A to 22D can be reduced.
In particular, according to the SiC semiconductor device 1, the thinning process of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is performed, so that the SiC semiconductor wafer structure 61 (the reforming lines 22A to 22D) is used for the SiC semiconductor device. The wafer structure 61 can be appropriately cleaved.

  In other words, according to the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), a plurality of reforming lines 70 (reforming lines 22A to 22D) are not formed at intervals in the normal direction Z. In addition, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be appropriately cleaved. This makes it possible to more appropriately reduce the formation area of the reforming lines 22A to 22D on the side surfaces 5A to 5D of the SiC semiconductor layer 2. Further, the time for forming the reforming line 70 can be reduced.

In this case, second main surface 4 of SiC semiconductor layer 2 is formed of a ground surface. Preferably, SiC semiconductor device 1 includes SiC semiconductor layer 2 having a thickness TL of not less than 40 μm and not more than 200 μm. SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).
In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be not less than 40 μm and not more than 150 μm. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

The influence on the SiC semiconductor layer 2 due to the reforming line includes a change in the electrical characteristics of the SiC semiconductor layer 2 due to the reforming line, generation of cracks in the SiC semiconductor layer 2 starting from the reforming line, and the like. Is exemplified.
Fluctuations in the leakage current characteristics are exemplified as fluctuations in the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming line. The SiC semiconductor device may be sealed by a sealing resin 79 as shown in FIG.

In this case, it is conceivable that movable ions in the sealing resin 79 enter the SiC semiconductor layer 2 via the reforming line. In a structure in which a plurality of reforming lines are formed at intervals along the normal direction Z over the entire area of each of the side surfaces 5A to 5D, the risk of current path formation due to such an external structure increases.
Further, in a structure in which a plurality of reforming lines are formed along the normal direction Z over the entire area of each of the side surfaces 5A to 5D of the SiC semiconductor layer 2, the risk of cracking of the SiC semiconductor layer 2 increases. Therefore, as in the case of the SiC semiconductor device 1, by restricting the formation region of the reforming lines 22A to 22D, it is possible to suppress the fluctuation of the electrical characteristics of the SiC semiconductor layer 2 and the occurrence of cracks.

According to the SiC semiconductor device 1, the reforming lines 22 </ b> A to 22 </ b> D are formed at an interval from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. Stress is likely to concentrate at corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2.
Therefore, cracks are generated at corners of SiC semiconductor layer 2 by forming modified lines 22A to 22D at intervals from the corners connecting first main surface 3 and side surfaces 5A to 5D of SiC semiconductor layer 2. Can be appropriately suppressed.

  In particular, according to the SiC semiconductor device 1, the reforming lines 22A to 22D are formed on the SiC semiconductor substrate 6 avoiding the SiC epitaxial layer 7. That is, the reforming lines 22A to 22D expose the SiC epitaxial layer 7 on which the main part of the semiconductor element (the Schottky barrier diode D in this embodiment) is formed. Thereby, the influence on the semiconductor element due to the reforming lines 22A to 22D can be appropriately reduced.

Further, according to SiC semiconductor device 1, modified lines 22 </ b> A to 22 </ b> D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Stress is likely to concentrate at corners connecting the second main surface 4 and the side surfaces 5A to 5D of the SiC semiconductor layer 2.
Therefore, cracks are generated at corners of SiC semiconductor layer 2 by forming modified lines 22A to 22D at intervals from corners connecting second main surface 4 and side surfaces 5A to 5D of SiC semiconductor layer 2. Can be appropriately suppressed.

Further, according to SiC semiconductor device 1, it includes main surface insulating layer 10 and first main surface electrode layer 12 formed on first main surface 3 of SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A to 11D connected to the side surfaces 5A to 5D of the SiC semiconductor layer 2.
The main surface insulating layer 10 enhances insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12 in the structure in which the modified lines 22A to 22D are formed. Thereby, in the structure in which the modified lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the stability of the electrical characteristics of the SiC semiconductor layer 2 can be improved.

FIG. 13A is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a second embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
In the reforming lines 22 </ b> A to 22 </ b> D according to the first embodiment, the connection region 27 is inclined linearly downward from the first region 25 to the second region 26. On the other hand, in the reforming lines 22A to 22D according to the second embodiment, the connection region 27 is inclined downward in a concave curve from the first region 25 to the second region 26. That is, the reforming lines 22 </ b> A to 22 </ b> D according to the second embodiment include portions that extend from the first main surface 3 toward the second main surface 4 in a concavely curved shape.

  The reforming lines 22A to 22D according to the second embodiment are formed by adjusting a condensing portion (focal point) of a laser beam in a process of forming the reforming line 70 (the reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the second embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 13B is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a third embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
In the reforming lines 22 </ b> A to 22 </ b> D according to the first embodiment, the connection region 27 is inclined linearly downward from the first region 25 to the second region 26. On the other hand, in the reforming lines 22A to 22D according to the third embodiment, the connection region 27 is inclined downward in a convex curve from the first region 25 to the second region 26. That is, the reforming lines 22 </ b> A to 22 </ b> D according to the third embodiment include portions extending from the second main surface 4 toward the first main surface 3 in a convexly curved shape.

  The reforming lines 22A to 22D according to the third embodiment are formed by adjusting the condensing portion (focal point) of the laser light in the forming process of the reforming line 70 (the reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the third embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 13C is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fourth embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
The reforming lines 22 </ b> A to 22 </ b> D according to the first embodiment are each formed in a strip shape extending straight from the first main surface 3 toward the second main surface 4. On the other hand, the reforming lines 22 </ b> A to 22 </ b> D according to the fourth embodiment are each formed in a belt shape extending from the first main surface 3 to the second main surface 4 in a concavely curved shape.

That is, the reforming lines 22 </ b> A to 22 </ b> D according to the fourth embodiment include portions that extend from the first main surface 3 toward the second main surface 4 in a concavely curved shape. The reforming lines 22A to 22D extend in a concavely curved shape such that the first end 23 and the second end 24 run parallel to each other.
More specifically, the reforming lines 22A to 22D according to the fourth embodiment each include two first regions 25, one second region 26, and two connection regions 27, respectively. The two first regions 25 are respectively formed at two corners of the corresponding side surfaces 5A to 5D.

One second region 26 is formed in a region between two first regions 25 on corresponding side surfaces 5A to 5D. The two connection regions 27 connect the corresponding first region 25 and the corresponding second region 26 on the corresponding side surfaces 5A to 5D, respectively.
In the reforming line 22A and the reforming line 22C, the plurality of a-plane reforming portions 28 are formed after the distance between the first main surface 3 and the one end 28a gradually increases from the first region 25 toward the second region 26. , Are gradually spaced from the second region 26 toward the first region 25 and are spaced apart from each other.

In the reforming line 22B and the reforming line 22D, the plurality of m-plane reforming portions 29 are formed after the distance between the first main surface 3 and the one end portion 29a gradually increases from the first region 25 to the second region 26. , Are gradually spaced from the second region 26 toward the first region 25 and are spaced apart from each other.
The reforming lines 22A to 22D according to the fourth embodiment are formed by adjusting the condensing portions (focal points) of the laser light in the forming process of the reforming line 70 (the reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the fourth embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 13D is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fifth embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
The reforming lines 22 </ b> A to 22 </ b> D according to the first embodiment are each formed in a strip shape extending straight from the first main surface 3 toward the second main surface 4. On the other hand, the reforming lines 22 </ b> A to 22 </ b> D according to the fifth embodiment are each formed in a belt shape extending in a convex curve from the second main surface 4 to the first main surface 3.

That is, the reforming lines 22 </ b> A to 22 </ b> D according to the fifth embodiment include portions that extend in a convex curve from the second main surface 4 to the first main surface 3. The reforming lines 22A to 22D extend in a convexly curved shape so that the first end 23 and the second end 24 run parallel to each other.
More specifically, the reforming lines 22A to 22D according to the fifth embodiment each include one first region 25, two second regions 26, and two connection regions 27, respectively. One first region 25 is formed at a longitudinally intermediate portion of the corresponding side surface 5A to 5D.

The two second regions 26 are respectively formed at two corners of the corresponding side surfaces 5A to 5D. That is, one first region 25 is formed in a region between the two second regions 26 on the corresponding side surfaces 5A to 5D. The two connection regions 27 connect the corresponding first region 25 and the corresponding second region 26 on the corresponding side surfaces 5A to 5D, respectively.
In the reforming line 22A and the reforming line 22C, the plurality of a-plane reforming portions 28 are formed after the distance between the first main surface 3 and the one end 28a gradually decreases from the second region 26 to the first region 25. , From the first region 25 to the second region 26 so as to be gradually increased.

In the reforming line 22B and the reforming line 22D, the plurality of m-plane reforming portions 29 are formed after the distance between the first main surface 3 and the one end portion 29a gradually decreases from the second region 26 to the first region 25. , From the first region 25 to the second region 26 so as to be gradually increased.
The reforming lines 22A to 22D according to the fifth embodiment are formed by adjusting the condensing portion (focal point) of the laser beam in the forming process of the reforming line 70 (the reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the fifth embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 13E is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a sixth embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
The reforming lines 22 </ b> A to 22 </ b> D according to the first embodiment are each formed in a strip shape extending straight from the first main surface 3 toward the second main surface 4. On the other hand, the reforming lines 22A to 22D according to the sixth embodiment are formed in a belt shape extending in a curved shape (curved shape) meandering toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. Is formed.

That is, the reforming lines 22 </ b> A to 22 </ b> D according to the sixth embodiment include a portion extending in a concavely curved shape from the first main surface 3 toward the second main surface 4, and a portion extending from the second main surface 4 to the first main surface 3. And a portion extending in a convexly curved shape. More specifically, the reforming lines 22A to 22D extend in a meandering curved shape (curved shape) such that the first end 23 and the second end 24 run parallel to each other.
More specifically, the reforming lines 22A to 22D according to the sixth embodiment each include a plurality of first regions 25, a plurality of second regions 26, and a plurality of connection regions 27, respectively. The plurality of first regions 25 are formed at intervals in the tangential direction of the first main surface 3 on the corresponding side surfaces 5A to 5D.

The plurality of second regions 26 are formed at intervals from each other along the tangential direction of the first main surface 3 on the corresponding side surfaces 5A to 5D. Each second area 26 is located in an area between two adjacent first areas 25. The plurality of connection regions 27 connect the corresponding first region 25 and the corresponding second region 26 on the corresponding side surfaces 5A to 5D, respectively.
In the reforming line 22A and the reforming line 22C, the plurality of a-plane reforming portions 28 are formed after the distance between the first main surface 3 and the one end 28a gradually decreases from the second region 26 to the first region 25. , From the first region 25 to the second region 26 so as to be gradually increased.

In the reforming line 22B and the reforming line 22D, the plurality of m-plane reforming portions 29 are formed after the distance between the first main surface 3 and the one end portion 29a gradually decreases from the second region 26 to the first region 25. , From the first region 25 to the second region 26 so as to be gradually increased.
The reforming lines 22A to 22D according to the sixth embodiment are formed by adjusting the condensing portion (focal point) of the laser light in the process of forming the reforming line 70 (the reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the sixth embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 13F is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a seventh embodiment of the reforming lines 22A to 22D. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
The reforming lines 22A to 22D according to the first embodiment are formed in the same shape as the side surfaces 5A to 5D of the SiC semiconductor layer 2. On the other hand, the modified lines 22A to 22D according to the seventh embodiment are formed with different exclusive ratios RA, RB, RC, and RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The occupancy ratios RA to RD are the ratios of the reforming lines 22A to 22D occupying the side surfaces 5A to 5D.

  The occupancy ratios RA to RD differ more specifically according to the crystal plane of the SiC single crystal. The occupancy ratio RB, RD of the modified lines 22B, 22D formed on the m-plane of the SiC single crystal is less than the occupation ratio RA, RC (RB, RC) of the modified lines 22A, 22C formed on the a-plane of the SiC single crystal. RD ≦ RA, RC). The occupation ratios RB and RD are more specifically less than the occupation ratios RA and RC (RB, RD <RA, RC).

The occupation ratios RA and RC of the reforming lines 22A and 22C may be equal to each other or may be different from each other. Further, the occupation ratios RB, RD of the reforming lines 22B, 22D may be equal to each other or may be different from each other.
In this embodiment, the surface area of the reforming lines 22B and 22D with respect to the side surfaces 5B and 5D is smaller than the surface area of the reforming lines 22A and 22C with respect to the side surfaces 5A and 5C, respectively. In this embodiment, the thicknesses TR of the reforming lines 22B and 22D are less than the thicknesses TR of the reforming lines 22A and 22C, respectively.

  The reforming lines 22A to 22D according to the seventh embodiment are formed by adjusting the condensing portion (focal point) of the laser light in the step of forming the reforming line 70 (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the seventh embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.

In particular, the modified lines 22A to 22D according to the seventh embodiment are formed at different occupation ratios RA to RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. More specifically, the reforming lines 22A to 22D have different exclusive ratios RA to RD depending on the crystal plane of the SiC single crystal.
The occupation ratio RB, RD of the modified lines 22B, 22D formed on the m-plane of the SiC single crystal is less than the occupation ratio RA, RC (RB, RC) of the modified lines 22A, 22C formed on the a-plane of the SiC single crystal. RD ≦ RA, RC).

The SiC single crystal is easily broken along the nearest atom direction (see also FIG. 1 and FIG. 2) in a plan view of the c-plane (silicon surface) viewed from the c-axis, and along the crossing direction of the nearest atom direction. It has physical properties that it is hard to crack. The closest atom direction is the a-axis direction and its equivalent direction. The cross direction of the closest atom direction is the m-axis direction and its equivalent direction.
Therefore, in the step of forming the reforming line 70, since the crystal face along the nearest atom direction of the SiC single crystal has a relatively easy cracking property, the reforming line having a relatively large occupation ratio is relatively large. The SiC single crystal can be appropriately cut (cleaved) without forming 70 (see also FIG. 10L). The crystal plane along the nearest atom direction is the m-plane and its equivalent plane.

That is, in the forming process of the reforming line 70, the occupation ratio of the reforming line 70 along the second scheduled cutting line 55 extending in the a-axis direction is changed to the reforming line 70 along the first scheduled cutting line 54 extending in the m-axis direction. Can be smaller than the occupancy ratio.
On the other hand, a reforming line 70 having a relatively large occupation ratio is formed on the crystal plane of the SiC single crystal along the direction intersecting the closest atomic direction. As a result, inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61 can be suppressed, so that generation of cracks due to the physical properties of the SiC single crystal can be appropriately suppressed. The crystal plane along the crossing direction of the nearest atom direction is the a-plane and its equivalent plane.

  As described above, according to the modified lines 22A to 22D according to the seventh embodiment, the occupation ratios RA to RD of the modified lines 22A to 22D with respect to the side surfaces 5A to 5D are adjusted using the physical properties of the SiC single crystal, Can be reduced. Thereby, the influence on the SiC semiconductor layer 2 due to the reforming lines 22A to 22D can be further reduced. Further, the time for forming the reforming line 70 can be reduced.

The occupation ratios RA to RD may be adjusted by the surface area of the reforming lines 22A to 22D with respect to the side surfaces 5A to 5D. The occupation ratios RA to RD may be adjusted by the thickness TR of the reforming lines 22A to 22D.
First embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment, sixth embodiment, and seventh embodiment (hereinafter, simply referred to as "first to seventh embodiment"). The SiC semiconductor device 1 including at least two of the reforming lines 22A to 22D according to the above may be formed.

The features of the reforming lines 22A to 22D according to the first to seventh embodiments can be combined in any mode and any mode between them. That is, the reforming lines 22A to 22D having a form in which at least two of the characteristics of the reforming lines 22A to 22D according to the first to seventh embodiments are combined may be adopted.
For example, the characteristics of the reforming lines 22A to 22D according to the seventh embodiment are the same as those of the reforming lines 22A to 22D according to the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the sixth embodiment. It may be combined with features.

FIG. 14 is a perspective view showing the SiC semiconductor device 91 according to the second embodiment of the present invention, and is a perspective view showing a structure to which the modified lines 22A to 22D according to the first embodiment are applied. In the following, the structures corresponding to the structures described for SiC semiconductor device 1 are denoted by the same reference numerals, and description thereof is omitted.
In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. However, instead of or in addition to the reforming lines 22A to 22D according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, or the seventh embodiment. The reforming lines 22A to 22D according to the example may be employed. Further, the reforming lines 22A to 22D having a form in which at least two of the characteristics of the reforming lines 22A to 22D according to the first to seventh embodiments are combined may be employed.

Referring to FIG. 14, in this embodiment, insulating side surfaces 11A to 11D of main surface insulating layer 10 are formed spaced apart from side surfaces 5A to 5D of SiC semiconductor layer 2 in an inner region in plan view. Main surface insulating layer 10 exposes a peripheral portion of first main surface 3 of SiC semiconductor layer 2 in plan view.
The main surface insulating layer 10 exposes the periphery of the first main surface 3 of the SiC semiconductor layer 2 together with the resin layer 16 and the passivation layer 13. In this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are formed flush with the resin side surfaces 17A to 17D of the resin layer 16 and the side surfaces 14A to 14D of the passivation layer 13. In this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are also portions that have partitioned the dicing streets.

The main surface insulating layer 10 is formed by performing a step of removing the main surface insulating layer 10 by an etching method after the step of removing the passivation layer 13 in the above-described step of FIG. 10I.
In this case, in the above-described step of FIG. 10K, laser light may be directly applied to the inside of SiC semiconductor wafer structure 61 from first main surface 62 side of SiC semiconductor wafer structure 61 without through main surface insulating layer 10. .

As described above, the same effect as that described for the SiC semiconductor device 1 can also be obtained by the SiC semiconductor device 91. However, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable for enhancing the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12.
FIG. 15 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present invention viewed from one angle, showing a structure to which the modified lines 22A to 22D according to the first embodiment are applied. FIG. FIG. 16 is a perspective view of the SiC semiconductor device 101 shown in FIG. 15 viewed from another angle. FIG. 17 is a plan view showing the SiC semiconductor device 101 shown in FIG. FIG. 18 is a plan view in which the resin layer 129 is removed from FIG.

In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. That is, in the manufacturing process of the SiC semiconductor device 101, the same processes as those of the above-described processes of FIGS. 10A to 10M are applied.
In the SiC semiconductor device 101, in place of or in addition to the reforming lines 22A to 22D according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the sixth embodiment. Alternatively, the reforming lines 22A to 22D according to the seventh embodiment may be employed. Further, the reforming lines 22A to 22D having a form in which at least two of the characteristics of the reforming lines 22A to 22D according to the first to seventh embodiments are combined may be employed.

Referring to FIGS. 15 to 18, SiC semiconductor device 101 includes SiC semiconductor layer 102. SiC semiconductor layer 102 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 102 is formed in a rectangular parallelepiped chip shape.
The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. are doing. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (in this embodiment, a rectangular shape) in plan view (hereinafter, simply referred to as “plan view”) when viewed from their normal direction Z. .

The first main surface 103 is an element formation surface on which a semiconductor element is formed. Second main surface 104 of SiC semiconductor layer 102 is formed of a ground surface having a grinding mark. The side surfaces 105A to 105D are each formed of a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 105A to 105D do not have grinding marks.
Thickness TL of SiC semiconductor layer 102 may be not less than 40 μm and not more than 200 μm. The thickness TL may be from 40 μm to 60 μm, from 60 μm to 80 μm, from 80 μm to 100 μm, from 100 μm to 120 μm, from 120 μm to 140 μm, from 140 μm to 160 μm, from 160 μm to 180 μm, or from 180 μm to 200 μm. The thickness TL is preferably not less than 60 μm and not more than 150 μm.

In this embodiment, first main surface 103 and second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon surface). Second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.
The first main surface 103 and the second main surface 104 have an off angle θ inclined at an angle of 10 ° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be not less than 0 ° and not more than 5.0 °. Off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5 ° or more and 3.0 ° or less, 3.0 ° or more and 3.5 ° or less, 3.5 ° or more and 4.0 ° or less, 4.0 ° or more and 4.5 ° or less, or 4.5 ° or more and 5.0 ° or less. The angle may be set in the following range. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off-angle θ may be set in a range from 3.0 ° to 4.5 °. In this case, it is preferable that the off-angle θ is set in a range from 3.0 ° to 3.5 ° or from 3.5 ° to 4.0 °.
The off angle θ may be set in the range of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off-angle θ is set in the range of 1.5 ° to 2.0 ° or 2.0 ° to 2.5 °.

  The length of each of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). In this embodiment, the surface area of the side surfaces 105B and 105D exceeds the surface area of the side surfaces 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in plan view. In this case, the surface areas of the side surfaces 105A and 105C are equal to the side surfaces 105B and 105D.

In this embodiment, the side surface 105A and the side surface 105C extend along the first direction X and face each other in a second direction Y intersecting with the first direction X. In this embodiment, the side surfaces 105B and 105D extend along the second direction Y and face each other in the first direction X. The second direction Y is more specifically a direction orthogonal to the first direction X.
In this embodiment, the first direction X is set in the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set in the a-axis direction ([11-20] direction) of the SiC single crystal.

  Side surface 105A and side surface 105C form short sides of SiC semiconductor layer 102 in plan view. Side surface 105A and side surface 105C are formed by the a-plane of the SiC single crystal, and face each other in the a-axis direction. Side surface 105A is formed by the (−1-120) plane of the SiC single crystal. Side surface 105C is formed by the (11-20) plane of the SiC single crystal.

  Side surface 105B and side surface 105D form long sides of SiC semiconductor layer 102 in plan view. Side surface 105B and side surface 105D are formed by the m-plane of the SiC single crystal, and face each other in the m-axis direction. Side surface 105B is formed by the (-1100) plane of the SiC single crystal. Side surface 105D is formed by the (1-100) plane of the SiC single crystal.

The side surface 105A and the side surface 105C are inclined with respect to the normal to the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal to the first main surface 103 of the SiC semiconductor layer 102. A surface may be formed.
In this case, when the normal to the first main surface 103 of the SiC semiconductor layer 102 is 0 °, the side surfaces 105A and 105C have an off angle θ with respect to the normal to the first main surface 103 of the SiC semiconductor layer 102. It may be inclined at an appropriate angle. The angle corresponding to the off angle θ may be equal to the off angle θ, or may be an angle exceeding 0 ° and less than the off angle θ.

In this embodiment, SiC semiconductor layer 102 has a stacked structure including n ⁺ -type SiC semiconductor substrate 106 and n-type SiC epitaxial layer 107. The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 according to the first embodiment, respectively. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

First main surface 103 of SiC semiconductor layer 102 is formed by SiC epitaxial layer 107. Side surfaces 105A to 105D of SiC semiconductor layer 102 are formed by SiC semiconductor substrate 106 and SiC epitaxial layer 107.
Thickness TS of SiC semiconductor substrate 106 may be not less than 40 μm and not more than 150 μm. The thickness TS is 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, 90 μm to 100 μm, 100 μm to 110 μm, 110 μm to 120 μm, 120 μm to 130 μm, It may be 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By reducing the thickness of the SiC semiconductor substrate 106, the resistance value can be reduced by shortening the current path.

  The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

The n-type impurity concentration of SiC epitaxial layer 107 is lower than the n-type impurity concentration of SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of SiC epitaxial layer 107 is lower than the n-type impurity concentration of SiC semiconductor substrate 106. The n-type impurity concentration of SiC semiconductor substrate 106 may be not less than 1.0 × 10 ¹⁸ cm ^{−3 and not} more than 1.0 × 10 ²¹ cm ⁻³ . The n-type impurity concentration of SiC epitaxial layer 107 may be not less than 1.0 × 10 ¹⁵ cm ^{−3 and not} more than 1.0 × 10 ¹⁸ cm ⁻³ .

In this embodiment, SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along normal direction Z. More specifically, SiC epitaxial layer 107 includes a high-concentration region 108 having a relatively high n-type impurity concentration, and a low-concentration region 109 having a lower n-type impurity concentration than high-concentration region 108.
The high concentration region 108 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102. The low concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high concentration region 108.

The n-type impurity concentration of the high concentration region 108 may be 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The n-type impurity concentration of the low concentration region 109 may be not less than 1 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁶ cm ⁻³ .
The thickness of the high concentration region 108 is equal to or less than the thickness of the low concentration region 109. More specifically, the thickness of the high concentration region 108 is less than the thickness of the low concentration region 109. The thickness of the high concentration region 108 is less than half the total thickness of the SiC epitaxial layer 107.

In the SiC semiconductor layer 102, an active region 111 and an outer region 112 are set. The active region 111 is a region where a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. The outer region 112 is a region outside the active region 111.
The active region 111 is set at the center of the SiC semiconductor layer 102 with an interval from the side surfaces 105A to 105D of the SiC semiconductor layer 102 to an inner region in plan view. The active region 111 is set in a square shape (a rectangular shape in this embodiment) having four sides parallel to the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

The outer region 112 is set in a region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 111. The outer region 112 is set in an endless shape (square ring in this embodiment) surrounding the active region 111 in plan view.
On the first main surface 103 of the SiC semiconductor layer 102, a main surface insulating layer 113 is formed. Main surface insulating layer 113 selectively covers active region 111 and outer region 112. Main surface insulating layer 113 may include silicon oxide (SiO ₂ ).

  The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, 114D exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are formed of cleavage planes.

The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 113 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
On the main surface insulating layer 113, a main surface gate electrode layer 115 as one of the first main surface electrode layers is formed. Main surface gate electrode layer 115 penetrates main surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102.

Main surface gate electrode layer 115 includes gate pad 116 and gate fingers 117 and 118. Gate pad 116 and gate fingers 117 and 118 are arranged in active region 111.
Gate pad 116 is formed along side surface 105A of SiC semiconductor layer 102 in plan view. Gate pad 116 is formed along the central region of side surface 105A of SiC semiconductor layer 102 in plan view.

The gate pad 116 may be formed along a corner connecting any two of the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view. Gate pad 116 may be formed in a square shape in plan view.
Gate fingers 117 and 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 extends from the gate pad 116 and extends in a band along the periphery of the active region 111.

In this embodiment, outer gate fingers 117 are formed along three side surfaces 105A, 105B, and 105D of SiC semiconductor layer 102 so as to partition an inner region of active region 111 from three directions.
The outer gate finger 117 has a pair of open ends 119,120. The pair of open ends 119 and 120 are formed in a region facing the gate pad 116 with the inner region of the active region 111 interposed therebetween. In this embodiment, the pair of open ends 119 and 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

The inner gate finger 118 extends from the gate pad 116 to a region inside the active region 111. The inner gate finger 118 extends in a band shape in an area inside the active area 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.
On the main surface insulating layer 113, a main surface source electrode layer 121 as one of the first main surface electrode layers is further formed. Main surface source electrode layer 121 penetrates main surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102. In this embodiment, the main surface source electrode layer 121 includes a source pad 122, a source routing wiring 123, and a source connection part 124.

  Source pad 122 is formed in active region 111 at a distance from gate pad 116 and gate fingers 117 and 118. Source pad 122 has a C-shape (FIG. 17) in plan view so as to cover a C-shape (inverted C-shape in FIGS. 17 and 18) region defined by gate pad 116 and gate fingers 117 and 118. 18 and FIG. 18).

  The source routing wiring 123 is formed in the outer region 112. The source lead-out line 123 extends in a strip shape along the active region 111. In this embodiment, the source lead-out wiring 123 is formed in an endless shape (in this embodiment, a square ring) surrounding the active region 111 in a plan view. The source routing wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

  The source connection part 124 connects the source pad 122 and the source lead-out line 123. The source connection part 124 is provided in a region between the pair of open ends 119 and 120 of the outer gate finger 117. The source connection portion 124 crosses the boundary region between the active region 111 and the outer region 112 from the source pad 122, and is connected to the source routing wiring 123.

The MISFET formed in the active region 111 includes an npn-type parasitic bipolar transistor due to its structure. When the avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor is turned on. In this case, control of the MISFET may become unstable due to, for example, latch-up.
Therefore, in the SiC semiconductor device 101, an avalanche current absorption structure for absorbing an avalanche current generated in the outer region 112 is formed by utilizing the structure of the main surface source electrode layer 121.

More specifically, the avalanche current generated in the outer region 112 is absorbed by the source routing wiring 123 and reaches the source pad 122 via the source connection part 124. When a conducting wire (for example, a bonding wire) for external connection is connected to the source pad 122, the avalanche current is taken out by the conducting wire.
Thus, it is possible to prevent the parasitic bipolar transistor from being turned on by an undesired current generated in the outer region 112. Therefore, since the latch-up can be suppressed, the control stability of the MISFET can be improved.

A gate voltage is applied to main surface gate electrode layer 115. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, a GND voltage).
On the main surface insulating layer 113, a passivation layer 125 (insulating layer) is formed. The passivation layer 125 may have a single-layer structure including a silicon oxide layer or a silicon nitride layer.

The passivation layer 125 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 125 has a single-layer structure made of a silicon nitride layer.
The side surfaces 126A, 126B, 126C, 126D of the passivation layer 125 are formed at an interval from the side surfaces 105A to 105D of the SiC semiconductor layer 102 to an inner region in plan view. Passivation layer 125 exposes the periphery of SiC semiconductor layer 102 in plan view. The passivation layer 125 exposes the main surface insulating layer 113.

  Passivation layer 125 selectively covers main surface gate electrode layer 115 and main surface source electrode layer 121. A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125. Gate subpad opening 127 exposes gate pad 116. Source subpad opening 128 exposes source pad 122.

The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
On the passivation layer 125, a resin layer 129 (insulating layer) is formed. The passivation layer 125 and the resin layer 129 form one insulating laminated structure (insulating layer). In FIG. 17, the resin layer 129 is indicated by hatching.

The resin layer 129 may include a negative type or positive type photosensitive resin. In this embodiment, the resin layer 129 includes polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 129 may include polyimide as an example of a negative type photosensitive resin.
The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The resin side surfaces 130A, 130B, 130C, and 130D of the resin layer 129 are formed at intervals from the side surfaces 105A to 105D of the SiC semiconductor layer 102 to an inner region. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this embodiment, the resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125.

The resin side surfaces 130A to 130D of the resin layer 129 are portions that divide the dicing street when the SiC semiconductor device 101 is cut out from one SiC semiconductor wafer. In this embodiment, the side surfaces 126A to 126D of the passivation layer 125 also define the dicing street.
By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it is not necessary to physically cut the resin layer 129 and the passivation layer 125. Thereby, SiC semiconductor device 101 can be smoothly cut out from one SiC semiconductor wafer. Further, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

  The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less or 20 μm or more and 25 μm or less. Good. Of course, side surfaces 126A to 126D of passivation layer 125 may be formed flush with side surfaces 105A to 105D of SiC semiconductor layer 102.

A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.
The gate pad opening 131 of the resin layer 129 communicates with the gate subpad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate subpad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate subpad opening 127. The resin layer 129 may cover the inner wall of the gate subpad opening 127.

  The source pad opening 132 of the resin layer 129 communicates with the source subpad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source subpad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source subpad opening 128. The resin layer 129 may cover the inner wall of the source subpad opening 128.

The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
The drain electrode layer 133 as a second main surface electrode layer is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between main surface source electrode layer 121 and drain electrode layer 133 during off-time may be 1000 V or more and 10,000 V or less.

The drain electrode layer 133 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode layer 133 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.
The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any mode. The drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 104 of the SiC semiconductor layer 102.

The SiC semiconductor substrate 106 is formed as a drain region 134 of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 of the MISFET.
On the side surfaces 105A to 105D of the SiC semiconductor layer 102, a plurality of modified lines 22A to 22D according to the first embodiment are formed. The structure of the modified lines 22A to 22D according to the first embodiment is the same as that of the modified lines 22A to 22D according to the first embodiment except that they are formed in the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2. Same as the structure.

The description of the reforming lines 22A to 22D according to the first embodiment shall be applied mutatis mutandis to the description of the reforming lines 22A to 22D according to the third embodiment, and the reforming lines 22A to 22D according to the third embodiment, respectively. A specific description of 22D is omitted.
FIG. 19 is an enlarged view of region XIX shown in FIG. 18 and is a diagram for explaining the structure of first main surface 103 of SiC semiconductor layer 102. FIG. 20 is a sectional view taken along the line XX-XX shown in FIG. FIG. 21 is a sectional view taken along the line XXI-XXI shown in FIG. FIG. 22 is an enlarged view of a region XXII shown in FIG. FIG. 23 is a sectional view taken along the line XXIII-XXIII shown in FIG. FIG. 24 is an enlarged view of a region XXIV shown in FIG.

Referring to FIGS. 19 to 23, in active region 111, p-type body region 141 is formed in a surface layer portion of first main surface 103 of SiC semiconductor layer 102. Body region 141 defines active region 111.
In this embodiment, body region 141 is formed over the entire region where active region 111 is formed on first main surface 103 of SiC semiconductor layer 102. The body region 141 may have a p-type impurity concentration of 1.0 × 10 ¹⁷ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ⁻³ .

In the active region 111, a plurality of gate trenches 142 are formed in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a band shape extending along the first direction X (m-axis direction of the SiC single crystal) in plan view, and are spaced along the second direction Y (a-axis direction of the SiC single crystal). Are formed.
In this embodiment, each gate trench 142 extends from the peripheral portion on one side (the side surface 105B side) to the peripheral portion on the other side (the side surface 105D side) in the active region 111. The plurality of gate trenches 142 are formed in a stripe shape as a whole in plan view.

Each gate trench 142 traverses an intermediate portion between the peripheral edge on one side and the peripheral edge on the other side in the active region 111. One end of each gate trench 142 is located at one peripheral edge in the active region 111. The other end of each gate trench 142 is located on the other side of the active region 111.
The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is a length from the end on the connection portion side of each gate trench 142 and the outer gate finger 117 to the end on the opposite side in the cross section shown in FIG.

In this embodiment, the length of each gate trench 142 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of the one or more gate trenches 142 per unit area may be not less than 0.5 μm / μm ^{2 and not} more than 0.75 μm / μm ² .
Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion along the channel of the MISFET in the active region 111.

  The contact trench portion 144 is a portion mainly intended for contact with the outer gate finger 117 in the gate trench 142. The contact trench 144 extends from the active trench 143 to the periphery of the active region 111. The contact trench portion 144 is formed in a region immediately below the outer gate finger 117. The lead-out amount of the contact trench portion 144 is arbitrary.

Each gate trench 142 penetrates body region 141 and reaches SiC epitaxial layer 107. Each gate trench 142 includes a side wall and a bottom wall. The sidewall forming the long side of each gate trench 142 is formed by the a-plane of the SiC single crystal. The side wall forming the short side of each gate trench 142 is formed by the m-plane of the SiC single crystal.
The side wall of each gate trench 142 may extend along the normal direction Z. The sidewall of each gate trench 142 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102.

The angle formed by the side wall of each gate trench 142 in SiC semiconductor layer 102 with respect to first main surface 103 of SiC semiconductor layer 102 may be 90 ° or more and 95 ° or less (eg, 91 ° or more and 93 ° or less). . Each gate trench 142 may be formed in a tapered shape such that the opening area on the bottom wall side is smaller than the opening area on the opening side in cross-sectional view.
The bottom wall of each gate trench 142 is located in SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in high concentration region 108 of SiC epitaxial layer 107.

The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
The bottom wall of each gate trench 142 may be formed parallel to first main surface 103 of SiC semiconductor layer 102. Needless to say, the bottom wall of each gate trench 142 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

With respect to the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 is 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, 1.5 μm to 2.0 μm, 2.0 μm to 2.5 μm or 2.5 μm to 3 μm. 0.0 μm or less.
The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be from 0.1 μm to 0.5 μm, from 0.5 μm to 1.0 μm, from 1.0 μm to 1.5 μm, or from 1.5 μm to 2 μm.

Referring to FIG. 22, opening edge portion 146 of each gate trench 142 includes an inclined portion 147 inclined downward from first main surface 103 of SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge 146 of each gate trench 142 is a corner connecting the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each gate trench 142.
In this embodiment, the inclined portion 147 is formed in a concavely curved shape inward of the SiC semiconductor layer 102. The inclined portion 147 may be formed in a convex curved shape inward of each gate trench 142. The inclined portion 147 reduces the electric field concentration on the opening edge portion 146 of each gate trench 142.

In each gate trench 142, a gate insulating layer 148 and a gate electrode layer 149 are formed. In FIG. 19, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.
The gate insulating layer 148 includes at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). Including.

Gate insulating layer 148 may have a stacked structure including a SiN layer and a SiO ₂ layer stacked in this order from first main surface 103 side of SiC semiconductor layer 102. Gate insulating layer 148 may have a stacked structure including a SiO ₂ layer and a SiN layer stacked in this order from first main surface 103 of SiC semiconductor layer 102. The gate insulating layer 148 may have a single-layer structure including a SiO ₂ layer or a SiN layer. In this embodiment, the gate insulating layer 148 has a single-layer structure composed of a SiO ₂ layer.

The gate insulating layer 148 is formed in a film shape along the inner wall surface of the gate trench 142 so that a concave space is defined in the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.
The first region 148a is formed along the side wall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. Third region 148c is formed along first main surface 103 of SiC semiconductor layer 102. The third region 148 c of the gate insulating layer 148 forms a part of the main surface insulating layer 113.

The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be 2 or more and 5 or less. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be 2 or more and 5 or less.
The thickness Ta of the first region 148a may be not less than 0.01 μm and not more than 0.2 μm. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

  By reducing the thickness of the first region 148a of the gate insulating layer 148, an increase in carriers induced in a region near the side wall of each gate trench 142 in the body region 141 can be suppressed. Thereby, an increase in channel resistance can be suppressed. By increasing the thickness of the second region 148b of the gate insulating layer 148, electric field concentration on the bottom wall of each gate trench 142 can be reduced.

By increasing the thickness of the third region 148 c of the gate insulating layer 148, the withstand voltage of the gate insulating layer 148 in the vicinity of the opening edge 146 of each gate trench 142 can be improved. Further, by increasing the thickness of the third region 148c, the loss of the third region 148c by the etching method can be suppressed.
Thus, the removal of the first region 148a by the etching method due to the disappearance of the third region 148c can be suppressed. As a result, gate electrode layer 149 can be appropriately opposed to SiC semiconductor layer 102 (body region 141) with gate insulating layer 148 interposed therebetween.

The gate insulating layer 148 further includes a bulging portion 148d bulging toward the inside of each gate trench 142 at the opening edge 146 of each gate trench 142. The bulge 148d is formed at a corner connecting the first region 148a and the third region 148c of the gate insulating layer 148.
The bulging portion 148d protrudes inwardly into each gate trench 142. The bulging portion 148 d narrows the opening of each gate trench 142 at the opening edge 146 of each gate trench 142.

The bulging portion 148 d improves the withstand voltage of the gate insulating layer 148 at the opening edge portion 146. Of course, the gate insulating layer 148 having no bulging portion 148d may be formed. Further, a gate insulating layer 148 having a uniform thickness may be formed.
The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 interposed therebetween. More specifically, the gate electrode layer 149 is embedded in a concave space defined by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by a gate voltage.

The gate electrode layer 149 has an upper end located on the opening side of each gate trench 142. The upper end of the gate electrode layer 149 is formed in a concave curve shape depressed toward the bottom wall of each gate trench 142. The upper end of the gate electrode layer 149 has a constricted portion constricted along the bulged portion 148d of the gate insulating layer 148.
The cross-sectional area of gate electrode layer 149 (cross-sectional area orthogonal to the direction in which each gate trench 142 extends) may be not less than 0.05 μm ^{2 and not} more than 0.5 μm ² . The cross-sectional area of the gate electrode layer 149 is defined by the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

  The depth of the gate electrode layer 149 is a distance from the upper end to the lower end of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at an intermediate position between the upper end and the lower end of the gate electrode layer 149. When the upper end is a curved surface (a concave curve in this embodiment), the position of the upper end of the gate electrode layer 149 is an intermediate position in the depth direction on the upper surface of the gate electrode layer 149.

Gate electrode layer 149 includes p-type polysilicon to which p-type impurities are added. The p-type impurity of the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).
The p-type impurity concentration of gate electrode layer 149 is equal to or higher than the p-type impurity concentration of body region 141. More specifically, the p-type impurity concentration of gate electrode layer 149 is higher than the p-type impurity concentration of body region 141.

The p-type impurity concentration of the gate electrode layer 149 may be from 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²² cm ⁻³ . The sheet resistance of the gate electrode layer 149 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).
Referring to FIGS. 19 and 21, in active region 111, gate wiring layer 150 is formed. Gate wiring layer 150 is electrically connected to gate pad 116 and gate fingers 117 and 118. In FIG. 21, the gate wiring layer 150 is indicated by hatching.

Gate wiring layer 150 is formed on first main surface 103 of SiC semiconductor layer 102. More specifically, gate wiring layer 150 is formed on third region 148c of gate insulating layer 148.
In this embodiment, the gate wiring layer 150 is formed along the outer gate finger 117. More specifically, gate wiring layer 150 is formed along three side surfaces 105A, 105B, and 105D of SiC semiconductor layer 102 so as to partition an inner region of active region 111 from three directions.

  Gate wiring layer 150 is connected to gate electrode layer 149 exposed from contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by a lead portion of the gate electrode layer 149 drawn from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 150 is connected to the upper end of the gate electrode layer 149.

Referring to FIGS. 19, 20 and 22, a plurality of source trenches 155 are formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Each source trench 155 is formed in a region between two adjacent gate trenches 142.
The plurality of source trenches 155 are each formed in a band shape extending along the first direction X (m-axis direction of the SiC single crystal). The plurality of source trenches 155 are formed in a stripe shape as a whole in plan view. In the second direction Y, the pitch between the central portions of the adjacent source trenches 155 may be not less than 1.5 μm and not more than 3 μm.

Each source trench 155 penetrates through body region 141 and reaches SiC epitaxial layer 107. Each source trench 155 includes a side wall and a bottom wall. The side wall forming the long side of each source trench 155 is formed by the a-plane of the SiC single crystal. The side wall forming the short side of each source trench 155 is formed by the m-plane of the SiC single crystal.
The side wall of each source trench 155 may extend along the normal direction Z. The side wall of each source trench 155 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102.

The angle formed by the side wall of each source trench 155 with respect to first main surface 103 of SiC semiconductor layer 102 in SiC semiconductor layer 102 may be 90 ° or more and 95 ° or less (for example, 91 ° or more and 93 ° or less). . Each source trench 155 may be formed in a tapered shape such that the opening area on the bottom wall side is smaller than the opening area on the opening side in cross-sectional view.
The bottom wall of each source trench 155 is located in SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in high concentration region 108 of SiC epitaxial layer 107. The bottom wall of each source trench 155 is more specifically located in a region between the bottom wall of each gate trench 142 and the low concentration region 109.

The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
The bottom wall of each source trench 155 may be formed parallel to first main surface 103 of SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102.

In this embodiment, the depth of each source trench 155 is equal to or greater than the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.
The bottom wall of each source trench 155 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

In the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.
The first direction width of each source trench 155 may be substantially equal to the first direction width of each gate trench 142. The first direction width of each source trench 155 may be greater than or equal to the first direction width of each gate trench 142. The first direction width of each source trench 155 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

In each source trench 155, a source insulating layer 156 and a source electrode layer 157 are formed. In FIG. 19, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.
The source insulating layer 156 includes at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). Including.

The source insulating layer 156 may have a stacked structure including a SiN layer and a SiO ₂ layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a stacked structure including the SiO ₂ layer and the SiN layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single-layer structure including a SiO ₂ layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single-layer structure composed of a SiO ₂ layer.

The source insulating layer 156 is formed in a film shape along the inner wall surface of each source trench 155 so that a concave space is defined in each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.
The first region 156a is formed along the side wall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

The ratio Tsb / Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be 2 or more and 5 or less. The thickness Tsa of the first region 156a may be not less than 0.01 μm and not more than 0.2 μm. The thickness Tsb of the second region 156b may be not less than 0.05 μm and not more than 0.5 μm.
The thickness Tsa of the first region 156a may be substantially equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be substantially equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, the source insulating layer 156 having a uniform thickness may be formed.

The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 interposed therebetween. More specifically, the source electrode layer 157 is embedded in a concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by a source voltage.
The source electrode layer 157 has an upper end located on the opening side of each source trench 155. The upper end of source electrode layer 157 is formed below first main surface 103 of SiC semiconductor layer 102. The upper end of source electrode layer 157 may be located above first main surface 103 of SiC semiconductor layer 102.

The upper end portion of the source electrode layer 157 is formed in a concave curved shape depressed toward the bottom wall of each source trench 155. The upper end of source electrode layer 157 may be formed parallel to first main surface 103 of SiC semiconductor layer 102.
The upper end of the source electrode layer 157 may protrude above the upper end of the source insulating layer 156. The upper end of the source electrode layer 157 may be located lower than the upper end of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

The source electrode layer 157 preferably includes polysilicon having a property close to SiC in material. Thereby, stress generated in SiC semiconductor layer 102 can be reduced. In this embodiment, the source electrode layer 157 includes p-type polysilicon to which p-type impurities are added. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.
The p-type impurity concentration of source electrode layer 157 is equal to or higher than the p-type impurity concentration of body region 141. More specifically, the p-type impurity concentration of source electrode layer 157 is higher than the p-type impurity concentration of body region 141. The p-type impurity of the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The p-type impurity concentration of the source electrode layer 157 may be from 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²² cm ⁻³ . The sheet resistance of the source electrode layer 157 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).
The p-type impurity concentration of the source electrode layer 157 may be substantially equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be substantially equal to the sheet resistance of the gate electrode layer 149.

Source electrode layer 157 may include n-type polysilicon instead of or in addition to p-type polysilicon. The source electrode layer 157 may include at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy instead of or in addition to the p-type polysilicon.
Thus, SiC semiconductor device 101 has a plurality of trench gate structures 161 and a plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

In the surface layer portion of the body region 141, an n ⁺ type source region 163 is formed in a region along the side wall of each gate trench 142. The n-type impurity concentration of the source region 163 may be not less than 1.0 × 10 ¹⁸ cm ^{−3 and not} more than 1.0 × 10 ²¹ cm ⁻³ . The n-type impurity of the source region 163 may be phosphorus (P).
A plurality of source regions 163 are formed along one side wall and the other side wall of each gate trench 142. The plurality of source regions 163 are each formed in a band shape extending in the first direction X.

The plurality of source regions 163 are formed in a stripe shape as a whole in plan view. Each source region 163 is exposed from the side wall of each gate trench 142 and the side wall of each source trench 155.
As described above, the region along the side wall of the gate trench 142 in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 includes the source region from the first main surface 103 of the SiC semiconductor layer 102 toward the second main surface 104. 163, the body region 141, and the drift region 135 are formed in this order.

In the body region 141, a channel of the MISFET is formed in a region along the side wall of the gate trench 142. The channel is formed in the gate trench 142 in a region along the side wall facing the a-plane of the SiC single crystal. ON / OFF of the channel is controlled by the gate electrode layer 149.
In the active region 111, a plurality of p ⁺ -type contact regions 164 are formed in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. Each contact region 164 is formed in a region between two adjacent gate trenches 142 in plan view. Each contact region 164 is formed in a region opposite to the gate trench 142 with respect to each source region 163.

Each contact region 164 is formed along the inner wall of each source trench 155. In this embodiment, a plurality of contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at an interval from each gate trench 142.
The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of body region 141. The p-type impurity concentration of each contact region 164 may be not less than 1.0 × 10 ¹⁸ cm ^{−3 and not} more than 1.0 × 10 ²¹ cm ⁻³ . The p-type impurity of each contact region 164 may be aluminum (Al).

Each contact region 164 covers a side wall and a bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface region 164a, a second surface region 164b, and an inner wall region 164c.
The first surface layer region 164a covers one side wall of the source trench 155 in the surface layer portion of the body region 141. First surface region 164a is electrically connected to body region 141 and source region 163.

First surface layer region 164 a is located in a region on the first main surface 103 side of SiC semiconductor layer 102 with respect to the bottom of source region 163. In this embodiment, first surface layer region 164a has a bottom portion extending parallel to first main surface 103 of SiC semiconductor layer 102.
In this embodiment, the bottom of first surface layer region 164a is located in a region between the bottom of body region 141 and the bottom of source region 163. The bottom of first surface layer region 164a may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.

  In this embodiment, the first surface layer region 164a is drawn from the source trench 155 toward the adjacent gate trench 142. The first surface region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface region 164a is formed at an interval from the gate trench 142 to the source trench 155 side.

The second surface layer region 164b covers the other side wall of the source trench 155 in the surface layer portion of the body region 141. Second surface layer region 164b is electrically connected to body region 141 and source region 163.
Second surface layer region 164b is located in a region on the first main surface 103 side of SiC semiconductor layer 102 with respect to the bottom of source region 163. In this embodiment, second surface layer region 164b has a bottom portion extending parallel to first main surface 103 of SiC semiconductor layer 102.

In this embodiment, the bottom of second surface region 164b is located in a region between the bottom of body region 141 and the bottom of source region 163. The bottom of second surface region 164b may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.
In this embodiment, the second surface region 164b is drawn from the other side wall of the source trench 155 toward the adjacent gate trench 142. The second surface region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface region 164b is formed at a distance from the gate trench 142 to the source trench 155.

  The inner wall region 164c is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the first surface region 164a and the second surface region 164b (the bottom of the source region 163). The inner wall region 164c is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 155. Inner wall region 164c covers the side wall of source trench 155.

Inner wall region 164c covers a corner connecting the side wall and the bottom wall of source trench 155. The inner wall region 164c covers the bottom wall of the source trench 155 from the side wall of the source trench 155 via a corner. The bottom of the contact region 164 is formed by the inner wall region 164c.
A plurality of deep well regions 165 are formed in a surface portion of first main surface 103 of SiC semiconductor layer 102. Each deep well region 165 is also referred to as a withstand voltage adjustment region (withstand voltage holding region) for adjusting the withstand voltage of SiC semiconductor layer 102 in active region 111.

Each deep well region 165 is formed in SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in the high concentration region 108 of the SiC epitaxial layer 107.
Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

Each deep well region 165 is formed in a band shape extending along each source trench 155 in plan view. Each deep well region 165 covers the side wall of each source trench 155.
Each deep well region 165 covers a corner connecting the side wall and the bottom wall of each source trench 155. Each deep well region 165 covers the bottom wall of each source trench 155 from the side wall of each source trench 155 via a corner. Each deep well region 165 is continuous with the body region 141 on the side wall of each source trench 155.

Each deep well region 165 has a bottom located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.
The p-type impurity concentration of each deep well region 165 may be substantially equal to the p-type impurity concentration of body region 141. The p-type impurity concentration of each deep well region 165 may exceed the p-type impurity concentration of body region 141. The p-type impurity concentration of each deep well region 165 may be lower than the p-type impurity concentration of body region 141.

The p-type impurity concentration of each deep well region 165 may be equal to or less than the p-type impurity concentration of contact region 164. The p-type impurity concentration of each deep well region 165 may be lower than the p-type impurity concentration of contact region 164. The p-type impurity concentration of each deep well region 165 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

  Each deep well region 165 forms a pn junction with SiC semiconductor layer 102 (high concentration region 108 of SiC epitaxial layer 107). From this pn junction, a depletion layer extends toward a region between a plurality of gate trenches 142 adjacent to each other. This depletion layer extends toward the region on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142.

The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. A depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.
Referring to FIGS. 19 and 21, a p-type peripheral deep well region 166 is formed at the peripheral portion of active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, the peripheral deep well region 166 is formed in the high concentration region 108 of the SiC epitaxial layer 107.

The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 has the same potential as each deep well region 165. In this embodiment, the peripheral deep well region 166 is formed integrally with each deep well region 165.
More specifically, the peripheral deep well region 166 is formed in the peripheral portion of the active region 111 in a region along the inner wall of the contact trench 144 of each gate trench 142.

The peripheral deep well region 166 covers the side wall of the contact trench 144 of each gate trench 142. The peripheral deep well region 166 covers a corner connecting the side wall and the bottom wall of each contact trench portion 144.
The peripheral deep well region 166 covers the bottom wall of each contact trench portion 144 from the side wall of each contact trench portion 144 via a corner. Each deep well region 165 is continuous with the body region 141 on the side wall of each contact trench portion 144. The bottom of peripheral deep well region 166 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each contact trench portion 144.

The peripheral deep well region 166 overlaps the gate wiring layer 150 in plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) interposed therebetween.
The peripheral deep well region 166 includes a lead portion 166a drawn from each contact trench portion 144 to each active trench portion 143. The lead portion 166a is formed in the high concentration region 108 of the SiC epitaxial layer 107. The lead portion 166a extends along the side wall of each active trench portion 143, and covers the bottom wall of the active trench portion 143 through a corner.

The lead portion 166a covers the side wall of the active trench portion 143 of each gate trench 142. The lead portion 166a covers a corner connecting the side wall and the bottom wall of each active trench portion 143.
The lead portion 166a covers the bottom wall of each active trench portion 143 from the side wall of each active trench portion 143 via a corner. The lead portion 166a is continuous with the body region 141 on the side wall of each active trench portion 143. The bottom of the lead portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each active trench portion 143.

The p-type impurity concentration of peripheral deep well region 166 may be substantially equal to the p-type impurity concentration of body region 141. The p-type impurity concentration of peripheral deep well region 166 may be greater than the p-type impurity concentration of body region 141. The p-type impurity concentration of peripheral deep well region 166 may be lower than the p-type impurity concentration of body region 141.
The p-type impurity concentration of the peripheral deep well region 166 may be substantially equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be lower than the p-type impurity concentration of each deep well region 165.

The p-type impurity concentration of the peripheral deep well region 166 may be lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be lower than the p-type impurity concentration of the contact region 164. The peripheral deep well region 166 may have a p-type impurity concentration of 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

In a SiC semiconductor device including only a pn junction diode, there is little problem of electric field concentration in the SiC semiconductor layer 102 because of the structure including no trench. Each deep well region 165 (peripheral deep well region 166) brings a trench gate type MISFET closer to a pn junction diode structure.
Thereby, in the trench gate type MISFET, the electric field in the SiC semiconductor layer 102 can be reduced. Therefore, narrowing the pitch between a plurality of deep well regions 165 adjacent to each other is effective in reducing electric field concentration.

Further, according to each deep well region 165 having a bottom on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142, the depletion layer appropriately concentrates the electric field on each gate trench 142. Can be relaxed.
The distance between the bottom of each deep well region 165 and the second main surface 104 of SiC semiconductor layer 102 is preferably substantially constant. Thereby, it is possible to suppress the occurrence of variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

Therefore, the withstand voltage (for example, breakdown strength) of the SiC semiconductor layer 102 can be suppressed from being limited by the form of each deep well region 165, so that the withstand voltage can be appropriately improved.
In this embodiment, the high-concentration region 108 of the SiC epitaxial layer 107 is interposed between the deep well regions 165 adjacent to each other. Thus, in a region between the deep well regions 165 adjacent to each other, the resistance of a JFET (Junction Field Effect Transistor) can be reduced.

  Further, in this embodiment, the bottom of each deep well region 165 is located in high concentration region 108 of SiC epitaxial layer 107. Thus, the current path can be extended in the lateral direction parallel to the first main surface 103 of SiC semiconductor layer 102 from the bottom of each deep well region 165. Thereby, the current spreading resistance can be reduced. The low-concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102 in such a structure.

  By forming the source trench 155, a p-type impurity can be introduced into the inner wall of the source trench 155. Accordingly, since each deep well region 165 can be formed conformally to the source trench 155, the occurrence of variation in the depth of each deep well region 165 can be appropriately suppressed. By using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of SiC semiconductor layer 102.

Referring to FIG. 22, a low-resistance electrode layer 167 is formed on gate electrode layer 149. The low-resistance electrode layer 167 covers the upper end of the gate electrode layer 149 in each gate trench 142.
The low-resistance electrode layer 167 includes a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer 149. The sheet resistance of the low-resistance electrode layer 167 may be from 0.01 Ω / □ to 10 Ω / □.

  The low-resistance electrode layer 167 is formed in a film shape. The low-resistance electrode layer 167 has a connection portion 167a in contact with the upper end of the gate electrode layer 149 and a non-connection portion 167b opposite thereto. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 may be formed in a concave curved shape following the upper end of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 can take various forms.

The entire connection portion 167a of the low resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 167a of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.
The connection portion 167a of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 167a of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

For example, the center of connection portion 167a of low resistance electrode layer 167 is located below first main surface 103 of SiC semiconductor layer 102, and the periphery of connection portion 167a of low resistance electrode layer 167 is It may be located above the first main surface 103.
The entire non-connection portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connection portion 167b of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

The non-connection portion 167b of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connection portion 167b of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.
For example, the central portion of non-connection portion 167b of low-resistance electrode layer 167 is located below first main surface 103 of SiC semiconductor layer 102, and the peripheral portion of non-connection portion 167b of low-resistance electrode layer 167 is The first main surface 103 may be located above the first main surface 103.

The low-resistance electrode layer 167 has an edge portion 167c that is in contact with the gate insulating layer 148. An edge portion 167c of the low-resistance electrode layer 167 is in contact with a corner connecting the first region 148a and the second region 148b in the gate insulating layer 148.
The edge 167c of the low-resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge 167c of the low-resistance electrode layer 167 is in contact with the bulge 148d of the gate insulating layer 148.

An edge 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. Edge 167c of low-resistance electrode layer 167 is formed in a region closer to first main surface 103 of SiC semiconductor layer 102 than a boundary region between body region 141 and source region 163.
Therefore, the edge 167 c of the low-resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 interposed therebetween. Edge portion 167c of low-resistance electrode layer 167 does not face body region 141 with gate insulating layer 148 interposed therebetween.

Accordingly, formation of a current path in the region between the low-resistance electrode layer 167 and the body region 141 in the gate insulating layer 148 can be suppressed. The current path may be formed by undesired diffusion of the electrode material of the low resistance electrode layer 167 to the gate insulating layer 148.
In particular, a design in which the edge 167c of the low-resistance electrode layer 167 is connected to the third region 148c (the corner of the gate insulating layer 148) of the relatively thick gate insulating layer 148 reduces the risk of forming a current path. Valid on

  In the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). The thickness Tr of the low-resistance electrode layer 167 is preferably smaller than the thickness TG of the gate electrode layer 149 (Tr <TG). More specifically, it is preferable that the thickness Tr of the low-resistance electrode layer 167 be equal to or less than half (Tr ≦ TG / 2) the thickness TG of the gate electrode layer 149.

The ratio Tr / TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.
The current supplied into each gate trench 142 flows through the low-resistance electrode layer 167 having a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 149. Accordingly, the entire gate electrode layer 149 (the entire area of the active region 111) can be promptly shifted from the off state to the on state, so that a delay in switching response can be suppressed.

In particular, in the case of the gate trench 142 having a length on the order of millimeters (length of 1 mm or more), it takes time to transmit the current, but the low-resistance electrode layer 167 can appropriately suppress the switching response delay. . That is, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses a current into each gate trench 142.
In addition, as the cell structure becomes finer, the width, depth, cross-sectional area, and the like of the gate electrode layer 149 become smaller, so that there is a concern about a delay in switching response due to an increase in electric resistance in each gate trench 142. .

However, according to the low-resistance electrode layer 167, the entire gate electrode layer 149 can be promptly shifted from the off state to the on state, so that a switching response delay due to miniaturization can be appropriately suppressed.
Referring to FIG. 21, low-resistance electrode layer 167 also covers the upper end of gate wiring layer 150 in this embodiment. The portion of the low resistance electrode layer 167 covering the upper end of the gate wiring layer 150 is formed integrally with the portion of the low resistance electrode layer 167 covering the upper end of the gate electrode layer 149. Thus, the low-resistance electrode layer 167 covers the entire area of the gate electrode layer 149 and the entire area of the gate wiring layer 150.

Therefore, the current supplied from the gate pad 116 and the gate fingers 117 and 118 to the gate wiring layer 150 is applied to the entire gate electrode layer 149 and the gate wiring layer 150 via the low-resistance electrode layer 167 having a relatively low sheet resistance. Is transmitted.
Thus, the entire gate electrode layer 149 (the entire area of the active region 111) can be promptly shifted from the off state to the on state via the gate wiring layer 150, so that a delay in switching response can be suppressed.

In particular, in the case of the gate trench 142 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low-resistance electrode layer 167 covering the upper end of the gate wiring layer 150.
Low resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by silicidizing a portion of the gate electrode layer 149 forming a surface layer portion with a metal material. More specifically, the polycide layer is formed of a p-type polycide layer containing a p-type impurity added to the gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a specific resistance of 10 μΩ · cm or more and 110 μΩ · cm or less.

The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low-resistance electrode layer 167 are embedded is equal to or less than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.
The sheet resistance in the gate trench 142 is approximated to the sheet resistance of the low resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 142 is preferably less than 10Ω / □.

The low-resistance electrode layer 167 may include at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi _{2 and} WSi ₂ . In particular, among these species, NiSi, CoSi ₂ and TiSi ₂ are suitable as a polycide layer for forming the low-resistance electrode layer 167 because of their relatively small specific resistance and low temperature dependency.
On the first main surface 103 of the SiC semiconductor layer 102, a source subtrench 168 communicating with each source trench 155 is formed in a region along the upper end of the source electrode layer 157. Source sub-trench 168 forms a part of the side wall of each source trench 155.

In this embodiment, source subtrench 168 is formed in an endless shape (in this embodiment, a square ring) surrounding the upper end of source electrode layer 157 in plan view. The source subtrench 168 borders the upper end of the source electrode layer 157.
The source subtrench 168 is formed by digging down a part of the source insulating layer 156. More specifically, source subtrench 168 is formed by digging the upper end of source insulating layer 156 and the upper end of source electrode layer 157 from first main surface 103 of SiC semiconductor layer 102.

The upper end of the source electrode layer 157 has a shape confined inside the lower end of the source electrode layer 157. The lower end of the source electrode layer 157 is a portion located on the bottom wall side of each source trench 155 in the source electrode layer 157. The first direction width of the upper end of the source electrode layer 157 may be smaller than the first direction width of the lower end of the source electrode layer 157.
The source subtrench 168 is formed in a tapered shape having a bottom area smaller than an opening area in a sectional view. The bottom wall of source sub-trench 168 may be formed in a convex curve toward second main surface 104 of SiC semiconductor layer 102.

The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source subtrench 168. The first surface region 164a and the second surface region 164b of the contact region 164 are exposed from the inner wall of the source subtrench 168.
At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source subtrench 168. In the source insulating layer 156, the upper end of the first region 156a is located below the first main surface 103 of the SiC semiconductor layer 102.

  Opening edge portion 169 of each source trench 155 includes an inclined portion 170 inclined downward from first main surface 103 of SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge 169 of each source trench 155 is a corner connecting the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by the source sub-trench 168.

In this embodiment, the inclined portion 170 is formed in a concavely curved shape inward of the SiC semiconductor layer 102. The inclined portion 170 may be formed in a convexly curved shape inward of the source sub-trench 168. The inclined portion 170 reduces the electric field concentration on the opening edge 169 of each source trench 155.
Referring to FIGS. 23 and 24, active region 111 has an active main surface 171 forming a part of first main surface 103 of SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms a part of the first main surface 103 of the SiC semiconductor layer 102. Outer main surface 172 is connected to side surfaces 105A to 105D of SiC semiconductor layer 102 in this embodiment.

Active main surface 171 and outer main surface 172 face the c-plane of the SiC single crystal, respectively. The active main surface 171 and the outer main surface 172 each have an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
Outer main surface 172 is located on second main surface 104 side of SiC semiconductor layer 102 with respect to active main surface 171. In this embodiment, the outer region 112 is formed by digging the first main surface 103 of the SiC semiconductor layer 102 toward the second main surface 104. Therefore, outer main surface 172 is formed in a region recessed toward second main surface 104 of SiC semiconductor layer 102 with respect to active main surface 171.

The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. Outer main surface 172 may be formed at a depth substantially equal to the bottom wall of each source trench 155. The outer main surface 172 may be located substantially on the same plane as the bottom wall of each source trench 155.
The distance between the outer main surface 172 and the second main surface 104 of the SiC semiconductor layer 102 may be substantially equal to the distance between the bottom wall of each source trench 155 and the second main surface 104 of the SiC semiconductor layer 102.

Outer main surface 172 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 within a range from 0 μm to 1 μm with respect to the bottom wall of each source trench 155.
SiC epitaxial layer 107 is exposed from outer main surface 172. More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from outer main surface 172 of outer region 112. The outer main surface 172 faces the low concentration region 109 of the SiC epitaxial layer 107 with the high concentration region 108 of the SiC epitaxial layer 107 interposed therebetween.

In this embodiment, the active area 111 is divided into a plateau by the outer area 112. The active region 111 is formed as a plateau-shaped active plateau 173 projecting upward from the outer region 112.
Active plateau 173 includes an active sidewall 174 that connects active major surface 171 and outer major surface 172. The active side wall 174 defines a boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by an active main surface 171, an outer main surface 172, and an active side wall 174.

In this embodiment, the active side wall 174 extends along the normal direction Z of the active main surface 171 (outer main surface 172). Active side wall 174 is formed by the m-plane and the a-plane of the SiC single crystal.
The active side wall 174 may have an inclined surface inclined downward from the active main surface 171 to the outer main surface 172. The inclination angle of the active side wall 174 is an angle formed between the active side wall 174 and the active main surface 171 in the SiC semiconductor layer 102.

  In this case, the inclination angle of the active side wall 174 may be more than 90 ° and 135 ° or less. The inclination angle of the active side wall 174 may be more than 90 ° and 95 ° or less, 95 ° or more and 100 ° or less, 100 ° or more and 110 ° or less, 110 ° or more and 120 ° or less, or 120 ° or more and 135 ° or less. The inclination angle of the active side wall 174 is preferably more than 90 ° and 95 ° or less.

The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from active side wall 174.
At least the body region 141 is exposed from a region on the active main surface 171 side of the active side wall 174. FIGS. 23 and 24 show an example in which the body region 141 and the source region 163 are exposed from the active side wall 174.

In the outer region 112, the p ⁺ -type diode region 181 (impurity region), the p-type outer deep well region 182, and the p-type Field limit structure 183 is formed.
The diode region 181 is formed in a region between the active side wall 174 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in the outer region 112. Diode region 181 is formed at a distance from active side wall 174 and side surfaces 105A to 105D.

The diode region 181 extends in a band along the active region 111 in a plan view. In this embodiment, diode region 181 is formed in an endless shape (square ring in this embodiment) surrounding active region 111 in a plan view.
The diode region 181 overlaps with the source lead-out line 123 in plan view. The diode region 181 is electrically connected to the source routing wiring 123. The diode region 181 forms a part of the avalanche current absorption structure.

Diode region 181 forms a pn junction with SiC semiconductor layer 102. More specifically, diode region 181 is located in SiC epitaxial layer 107. Therefore, diode region 181 forms a pn junction with SiC epitaxial layer 107.
More specifically, diode region 181 is located in high concentration region 108 of SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high-concentration region 108. Thus, a pn junction diode Dpn having the diode region 181 as an anode and the SiC semiconductor layer 102 as a cathode is formed.

The entire diode region 181 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of diode region 181 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.
The bottom of diode region 181 may be formed at a depth substantially equal to the bottom of contact region 164. The bottom of diode region 181 may be located substantially flush with the bottom of contact region 164.

The p-type impurity concentration of diode region 181 is substantially equal to the p-type impurity concentration of contact region 164. Diode region 181 has a higher p-type impurity concentration than body region 141. The p-type impurity concentration of diode region 181 may be not less than 1.0 × 10 ¹⁸ cm ^{−3 and not} more than 1.0 × 10 ²¹ cm ⁻³ .
The outer deep well region 182 is formed in a region between the active side wall 174 and the diode region 181 in plan view. In this embodiment, the outer deep well region 182 is formed with an interval from the active side wall 174 toward the diode region 181 side. The outer deep well region 182 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) for adjusting the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

The outer deep well region 182 extends in a band along the active region 111 in plan view. In this embodiment, the outer deep well region 182 is formed in an endless shape (a square ring in this embodiment) surrounding the active region 111 in a plan view.
The outer deep well region 182 is electrically connected to the source lead-out line 123 via the diode region 181. The outer deep well region 182 may form a part of the pn junction diode Dpn. The outer deep well region 182 may form part of an avalanche current absorbing structure.

The entire outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.
The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of diode region 181. The bottom of the outer deep well region 182 may be formed at a depth substantially equal to the bottom of each deep well region 165. The bottom of outer deep well region 182 may be substantially coplanar with the bottom of each deep well region 165.

The distance between the bottom of outer deep well region 182 and outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155.
The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 is substantially equal to the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102. Is also good.

Thereby, the distance between the bottom of outer deep well region 182 and second main surface 104 of SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102 are reduced. The occurrence of variation can be suppressed.
Therefore, the withstand voltage (for example, breakdown strength) of the SiC semiconductor layer 102 can be suppressed from being restricted by the form of the outer deep well region 182 and the form of each deep well region 165, so that the withstand voltage can be appropriately improved. .

The bottom of outer deep well region 182 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 within a range of 0 μm or more and 1 μm or less with respect to the bottom of each deep well region 165.
The inner peripheral edge of the outer deep well region 182 may extend to near the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross a boundary region between the active region 111 and the outer region 112.

An inner peripheral edge of the outer deep well region 182 may cover a corner connecting the active side wall 174 and the outer main surface 172. The inner peripheral edge of the outer deep well region 182 may further extend along the active side wall 174 and may be connected to the body region 141.
In this embodiment, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap with the source routing wiring 123 in plan view. The outer peripheral edge of the outer deep well region 182 may be formed at an interval from the diode region 181 to the active side wall 174 side.

The p-type impurity concentration of outer deep well region 182 may be lower than the p-type impurity concentration of diode region 181. The p-type impurity concentration of outer deep well region 182 may be lower than the p-type impurity concentration of diode region 181.
The p-type impurity concentration of the outer deep well region 182 may be substantially equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of outer deep well region 182 may be substantially equal to the p-type impurity concentration of body region 141.

The p-type impurity concentration of outer deep well region 182 may exceed the p-type impurity concentration of body region 141. The p-type impurity concentration of outer deep well region 182 may be lower than the p-type impurity concentration of body region 141.
The p-type impurity concentration of outer deep well region 182 may be equal to or less than the p-type impurity concentration of contact region 164. The p-type impurity concentration of outer deep well region 182 may be lower than the p-type impurity concentration of contact region 164. The p-type impurity concentration of the outer deep well region 182 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

Field limit structure 183 is formed in a region between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. In this embodiment, the field limit structures 183 are formed at intervals from the side surfaces 105A to 105D toward the diode region 181 side.
The field limit structure 183 includes one or more (for example, 2 or more and 20 or less) field limit areas 184. In this embodiment, the field limit structure 183 includes a field limit area group having a plurality (five) of field limit areas 184A, 184B, 184C, 184D, and 184E.

The field limit regions 184A to 184E are formed in this order at intervals along the direction away from the diode region 181. Each of the field limit regions 184A to 184E extends in a band along the periphery of the active region 111 in plan view.
More specifically, the field limit regions 184A to 184E are each formed in an endless shape (in this embodiment, a square ring) surrounding the active region 111 in plan view. Each of the field limiting areas 184A to 184E is also referred to as an FLR (Field Limiting Ring) area.

In this embodiment, the bottoms of field limit regions 184A to 184E are located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of diode region 181.
In this embodiment, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap with the above-described source routing wiring 123 in plan view.

The field limit region 184A is electrically connected to the source lead-out line 123 via the diode region 181. Field limit region 184A may form a part of pn junction diode Dpn. The field limit region 184A may form a part of the avalanche current absorption structure.
The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottoms of field limit regions 184A to 184E are located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

The field limit regions 184A to 184E may be formed at a depth position substantially equal to each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on substantially the same plane as the bottom of each deep well region 165 (outer deep well region 182).
The bottoms of the field limit regions 184A to 184E may be located on the outer main surface 172 side with respect to the bottom of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 (outer deep well region 182).

  The width between the adjacent field limit regions 184A to 184E may be different from each other. The width between the field limit regions 184A to 184E adjacent to each other may increase in the direction away from the active region 111. The width between the field limit regions 184A to 184E adjacent to each other may decrease in the direction away from the active region 111.

The depths of the field limit regions 184A to 184E may be different from each other. The depths of the field limit regions 184A to 184E may decrease in a direction away from the active region 111. The depth of the field limit regions 184A to 184E may increase in a direction away from the active region 111.
The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the diode region 181.

The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the outer deep well region 182.
The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or higher than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A to 184E may be higher than the p-type impurity concentration of the outer deep well region 182.

The p-type impurity concentration of the field limit regions 184A to 184E may be 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less. It is preferable that p-type impurity concentration of diode region 181> p-type impurity concentration of outer deep well region 182> p-type impurity concentration of field limit regions 184A to 184E.
Field limit structure 183 reduces electric field concentration in outer region 112. The number, width, depth, p-type impurity concentration, and the like of the field limit region 184 can take various values according to the electric field to be relaxed.

In this embodiment, an example has been described in which the field limit structure 183 includes one or a plurality of field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.
However, field limit structure 183 has one or more regions formed in the region between active sidewall 174 and diode region 181 in plan view, instead of the region between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102. A plurality of field limit areas 184 may be included.

  The field limit structure 183 includes one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view, and the active sidewall 174 in plan view. And one or more field limit regions 184 formed in a region between the first and second diode regions 181.

An outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. The outer insulating layer 191 forms a part of the main surface insulating layer 113. The outer insulating layer 191 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113.
The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film shape along the active side wall 174 and the outer main surface 172. Outer insulating layer 191 is connected to gate insulating layer 148 on active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

Outer insulating layer 191 may include silicon oxide. The outer insulating layer 191 may include another insulating film such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same type of insulating material as the gate insulating layer 148.
The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active side wall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

The thickness of the second region 191b of the outer insulating layer 191 may be equal to or less than the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be smaller than the thickness of the first region 191a of the outer insulating layer 191.
The thickness of the first region 191a of the outer insulating layer 191 may be substantially equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be substantially equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 having a uniform thickness may be formed.

Referring to FIGS. 23 and 24, SiC semiconductor device 101 further includes sidewall 192 covering active sidewall 174. The sidewall 192 protects and reinforces the active plateau 173 from the outer region 112 side.
In addition, the sidewall 192 forms a step reduction structure that reduces a step formed between the active main surface 171 and the outer main surface 172. When an upper layer structure (covering layer) that covers the boundary region between the active region 111 and the outer region 112 is formed, the upper layer structure covers the sidewall 192. The sidewall 192 enhances the flatness of the upper layer structure.

The sidewall 192 may have an inclined portion 193 that is inclined downward from the active main surface 171 toward the outer main surface 172. By the inclined portion 193, the step can be appropriately reduced.
The inclined portion 193 of the sidewall 192 may be formed in a concavely curved shape toward the SiC semiconductor layer 102 side. The inclined portion 193 of the side wall 192 may be formed in a convex curved shape directed to the opposite side to the SiC semiconductor layer 102.

The inclined portion 193 of the sidewall 192 may extend in a plane from the active main surface 171 side to the outer main surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active main surface 171 side to the outer main surface 172 side.
The inclined portion 193 of the sidewall 192 may be formed in a step-like shape descending from the active main surface 171 to the outer main surface 172. That is, the inclined portion 193 of the sidewall 192 may have one or a plurality of steps depressed toward the outer main surface 172 side. The plurality of steps increase the surface area of the inclined portion 193 of the sidewall 192 and increase the adhesion to the upper layer structure.

The inclined portion 193 of the sidewall 192 may include a plurality of raised portions that are raised toward the outside of the sidewall 192. The plurality of raised portions increase the surface area of the inclined portion 193 of the sidewall 192, and increase the adhesion to the upper layer structure.
The inclined portion 193 of the sidewall 192 may include a plurality of recesses that are recessed toward the inside of the sidewall 192. The plurality of depressions increase the surface area of the inclined portion 193 of the sidewall 192, and increase the adhesion to the upper layer structure.

Sidewall 192 is formed in a self-aligned manner with respect to active main surface 171. More specifically, the side wall 192 is formed along the active side wall 174. In this embodiment, the side wall 192 is formed in an endless shape (a square ring in this embodiment) surrounding the active region 111 in a plan view.
The sidewall 192 preferably includes p-type polysilicon to which p-type impurities are added. In this case, the sidewall 192 can be formed at the same time as the gate electrode layer 149 and the source electrode layer 157.

  The p-type impurity concentration of sidewall 192 is equal to or higher than the p-type impurity concentration of body region 141. More specifically, the p-type impurity concentration of sidewall 192 is higher than the p-type impurity concentration of body region 141. The p-type impurity of the sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The p-type impurity concentration of the sidewall 192 may be 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The sheet resistance of the side wall 192 may be 10Ω / □ or more and 500Ω / □ or less (about 200Ω / □ in this embodiment).
The p-type impurity concentration of the sidewall 192 may be substantially equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be substantially equal to the sheet resistance of the gate electrode layer 149.

The sidewall 192 may include n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall 192 may include at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy instead of or in addition to the p-type polysilicon.
The sidewall 192 may include an insulating material. In this case, the insulating property of the active region 111 with respect to the outer region 112 can be increased by the sidewall 192.

  Referring to FIGS. 20 to 24, an interlayer insulating layer 201 is formed on first main surface 103 of SiC semiconductor layer 102. The interlayer insulating layer 201 forms a part of the main surface insulating layer 113. The interlayer insulating layer 201 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a stacked structure including the gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148 c of the gate insulating layer 148 and the outer insulating layer 191.
The interlayer insulating layer 201 is formed in a film shape along the active main surface 171 and the outer main surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

The interlayer insulating layer 201 is formed along the outer surface (inclined portion 193) of the sidewall 192 in a boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms a part of an upper layer structure that covers the sidewall 192.
The interlayer insulating layer 201 may include silicon oxide or silicon nitride. The interlayer insulating layer 201 may include PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

The interlayer insulating layer 201 may have a stacked structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The interlayer insulating layer 201 may have a stacked structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.
In the interlayer insulating layer 201, a gate contact hole 202, a source contact hole 203, and a diode contact hole 204 are formed. An anchor hole 205 is formed in the interlayer insulating layer 201.

The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a band shape along the gate wiring layer 150. The opening edge portion of the gate contact hole 202 is formed in a convex curved shape toward the inside of the gate contact hole 202.
Source contact hole 203 exposes source region 163, contact region 164 and trench source structure 162 in active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162 or the like. The opening edge of the source contact hole 203 is formed in a convex curved shape toward the inside of the source contact hole 203.

Diode contact hole 204 exposes diode region 181 in outer region 112. The diode contact hole 204 may be formed in a band shape (more specifically, an endless shape) extending along the diode region 181.
Diode contact hole 204 may expose outer deep well region 182 and / or field limit structure 183. The opening edge of the diode contact hole 204 is formed in a convex curved shape toward the inside of the diode contact hole 204.

  The anchor hole 205 is formed by digging down the interlayer insulating layer 201 in the outer region 112. The anchor hole 205 is formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view. More specifically, anchor hole 205 is formed in a region between field limit structure 183 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view.

Anchor hole 205 exposes first main surface 103 (outer main surface 172) of SiC semiconductor layer 102. An opening edge portion of the anchor hole 205 is formed in a convex curved shape toward the inside of the anchor hole 205.
Referring to FIG. 18, anchor hole 205 extends in a band along active region 111 in plan view. In this embodiment, the anchor hole 205 is formed in an endless shape (square ring in this embodiment) surrounding the active region 111 in plan view.

In this embodiment, one anchor hole 205 is formed in a portion of the interlayer insulating layer 201 that covers the outer region 112. However, a plurality of anchor holes 205 may be formed in a portion of the interlayer insulating layer 201 that covers the outer region 112.
On the interlayer insulating layer 201, a main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed. The main surface gate electrode layer 115 and the main surface source electrode layer 121 have a laminated structure including a barrier electrode layer 206 and a main electrode layer 207 laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102, respectively. ing.

The barrier electrode layer 206 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 206 may have a stacked structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.
The thickness of the main electrode layer 207 is larger than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance smaller than that of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, and an aluminum-copper alloy. In this embodiment, main electrode layer 207 includes an aluminum-silicon-copper alloy.
Outer gate fingers 117 of main surface gate electrode layer 115 enter gate contact holes 202 from above interlayer insulating layer 201. The outer gate finger 117 is electrically connected to the gate wiring layer 150 in the gate contact hole 202. Accordingly, an electric signal from the gate pad 116 is transmitted to the gate electrode layer 149 via the outer gate finger 117.

  Source pad 122 of main surface source electrode layer 121 enters source contact hole 203 and source subtrench 168 from above interlayer insulating layer 201. Source pad 122 is electrically connected to source region 163, contact region 164 and source electrode layer 157 in source contact hole 203 and source subtrench 168.

The source electrode layer 157 may be formed using a part of the source pad 122. The source electrode layer 157 may be formed by a part of the source pad 122 that enters each source trench 155.
Source routing wiring 123 of main surface source electrode layer 121 enters diode contact hole 204 from above interlayer insulating layer 201. The source routing wiring 123 is electrically connected to the diode region 181 in the diode contact hole 204.

The source connection portion 124 of the main surface source electrode layer 121 extends from the active region 111 across the sidewall 192 to the outer region 112. The source connection part 124 forms a part of an upper layer structure that covers the sidewall 192.
On the interlayer insulating layer 201, the above-mentioned passivation layer 125 is formed. The passivation layer 125 is formed in a film shape along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

The passivation layer 125 extends from the active region 111 across the sidewall 192 to the outer region 112. The passivation layer 125 forms a part of an upper layer structure that covers the sidewall 192.
Referring to FIG. 23, passivation layer 125 enters anchor hole 205 from above interlayer insulating layer 201 in outer region 112. Passivation layer 125 is connected to first main surface 103 (outer main surface 172) of SiC semiconductor layer 102 in anchor hole 205. In a region located above the anchor hole 205 on the outer surface of the passivation layer 125, a recess 211 that is depressed following the anchor hole 205 is formed.

On the passivation layer 125, the above-described resin layer 129 is formed. The resin layer 129 is formed in a film shape along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112 with the passivation layer 125 and the interlayer insulating layer 201 interposed therebetween.
The resin layer 129 extends from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms a part of an upper layer structure that covers the sidewall 192.

Referring to FIG. 23, resin layer 129 has an anchor portion which enters recess 211 of passivation layer 125 in outer region 112. As described above, the anchor structure for increasing the connection strength of the resin layer 129 is formed in the outer region 112.
The anchor structure includes an uneven structure (Uneven Structure) formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. More specifically, the uneven structure (anchor structure) includes unevenness formed using the interlayer insulating layer 201 covering the outer main surface 172. More specifically, the uneven structure (anchor structure) includes an anchor hole 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. Thereby, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be suppressed.
As described above, the same effect as the effect described for the SiC semiconductor device 1 can also be obtained by the SiC semiconductor device 101. Further, according to SiC semiconductor device 101, second boundary surface 104 of SiC semiconductor layer 102 extends from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 to the bottom wall of gate trench 142. The depletion layer can be expanded toward the side region.

  Thereby, the current path of the short-circuit current flowing between main surface source electrode layer 121 and drain electrode layer 133 can be narrowed. Further, the depletion layer extending from the boundary region between SiC semiconductor layer 102 and deep well region 165 can reduce feedback capacitance Crss in inverse proportion. Therefore, it is possible to provide the SiC semiconductor device 101 capable of improving short-circuit withstand capability and reducing the feedback capacitance Crss.

The depletion layer extending from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 may overlap the bottom wall of gate trench 142. In this case, a depletion layer extending from the bottom of deep well region 165 may overlap the bottom wall of gate trench 142.
Further, according to SiC semiconductor device 101, the area occupied by the depletion layer in SiC semiconductor layer 102 can be increased, so that feedback capacitance Crss can be inversely reduced. The feedback capacitance Crss is a capacitance between the gate electrode layer 149 and the drain electrode layer 133.

Further, according to SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102 is substantially constant. Thereby, it is possible to suppress the occurrence of variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.
Therefore, the withstand voltage (for example, breakdown strength) of the SiC semiconductor layer 102 can be suppressed from being limited by the form of the deep well region 165, so that the withstand voltage can be appropriately improved.

Further, according to SiC semiconductor device 101, diode region 181 is formed in outer region 112. This diode region 181 is electrically connected to main surface source electrode layer 121. Thus, the avalanche current generated in the outer region 112 can flow into the main surface source electrode layer 121 via the diode region 181.
That is, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the operation of the MISFET can be improved.

Further, according to SiC semiconductor device 101, outer deep well region 182 is formed in outer region 112. Thereby, in the outer region 112, the breakdown voltage of the SiC semiconductor layer 102 can be adjusted.
In particular, according to SiC semiconductor device 101, outer deep well region 182 is formed at a depth position substantially equal to deep well region 165. More specifically, the bottom of outer deep well region 182 is located substantially on the same plane as the bottom of deep well region 165.

The distance between the bottom of outer deep well region 182 and second main surface 104 of SiC semiconductor layer 102 is substantially equal to the distance between the bottom of deep well region 165 and second main surface 104 of SiC semiconductor layer 102.
Thereby, the distance between the bottom of outer deep well region 182 and second main surface 104 of SiC semiconductor layer 102 and the distance between the bottom of deep well region 165 and second main surface 104 of SiC semiconductor layer 102 are determined. It is possible to suppress the occurrence of the variation between them.

Therefore, it is possible to prevent the withstand voltage (for example, breakdown strength) of SiC semiconductor layer 102 from being limited by the form of outer deep well region 182 and the form of deep well region 165. As a result, it is possible to appropriately improve the breakdown voltage.
In particular, in SiC semiconductor device 101, outer region 112 is formed in a region on second main surface 104 side of SiC semiconductor layer 102 with respect to active region 111. Thus, the position of the bottom of outer deep well region 182 can be appropriately brought closer to the position of the bottom of deep well region 165.

That is, when the outer deep well region 182 is formed, it is not necessary to introduce a p-type impurity into a relatively deep position of the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Therefore, it is possible to appropriately suppress the position of the bottom of the outer deep well region 182 from being largely shifted from the position of the bottom of the deep well region 165.
Moreover, in SiC semiconductor device 101, outer main surface 172 of outer region 112 is located on substantially the same plane as the bottom wall of source trench 155. Therefore, when p-type impurities are introduced into the bottom wall of source trench 155 and outer main surface 172 of outer region 112 with the same energy, deep well region 165 and outer deep well region 182 are positioned at substantially equal depth positions. Can be formed.

As a result, it is possible to more appropriately suppress the position of the bottom of the outer deep well region 182 from being largely deviated from the position of the bottom of the deep well region 165.
According to the SiC semiconductor device 101, the field limit structure 183 is formed in the outer region 112. Thus, in the outer region 112, the effect of reducing the electric field by the field limit structure 183 can be obtained. Therefore, the breakdown strength of the SiC semiconductor layer 102 can be appropriately improved.

According to the SiC semiconductor device 101, the active region 111 is formed as a plateau-shaped active plateau 173. The active plateau 173 includes an active side wall 174 connecting the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.
In a region between the active main surface 171 and the outer main surface 172, a step reducing structure for reducing a step between the active main surface 171 and the outer main surface 172 is formed. The step reduction structure includes a sidewall 192.

  Thereby, the step between active main surface 171 and outer main surface 172 can be appropriately alleviated. Therefore, the flatness of the upper layer structure formed on the sidewall 192 can be appropriately improved. In the SiC semiconductor device 101, an interlayer insulating layer 201, a main surface source electrode layer 121, a passivation layer 125, and a resin layer 129 are formed as an example of an upper layer structure.

Further, according to SiC semiconductor device 101, an anchor structure for increasing the connection strength of resin layer 129 is formed in outer region 112. The anchor structure includes an uneven structure (Uneven Structure) formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112.
More specifically, the uneven structure (anchor structure) includes unevenness formed using the interlayer insulating layer 201 formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. More specifically, the uneven structure (anchor structure) includes an anchor hole 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. Thereby, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be appropriately suppressed.
Further, according to SiC semiconductor device 101, trench gate structure 161 in which gate electrode layer 149 is embedded in gate trench 142 with gate insulating layer 148 interposed therebetween is formed. In this trench gate structure 161, the gate electrode layer 149 is covered with the low-resistance electrode layer 167 in a limited space called the gate trench 142. According to such a structure, the effects described with reference to FIG. 25 can be obtained.

FIG. 25 is a graph for explaining the sheet resistance in the gate trench 142. In FIG. 25, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents items. FIG. 25 shows a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3.
The first bar graph BL1 represents the sheet resistance in the gate trench 142 in which the n-type polysilicon is buried. The second bar graph BL2 represents the sheet resistance in the gate trench 142 in which p-type polysilicon is buried.

The third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 are embedded. Here, a case where a low-resistance electrode layer 167 made of TiSi ₂ (p-type titanium silicide) as an example of polycide (silicide) is formed will be described.
Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 in which the n-type polysilicon is buried was 10Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 in which the p-type polysilicon is buried was 200Ω / □. Referring to third bar graph BL3, the sheet resistance in gate trench 142 in which gate electrode layer 149 (p-type polysilicon) and low-resistance electrode layer 167 were buried was 2Ω / □.

P-type polysilicon has a different work function than n-type polysilicon. According to the structure in which the p-type polysilicon is embedded in the gate trench 142, the gate threshold voltage Vth can be increased by about 1V.
However, p-type polysilicon has a sheet resistance several tens times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material of the gate electrode layer 149, the energy loss increases significantly as the parasitic resistance in the gate trench 142 (hereinafter, simply referred to as “gate resistance”) increases.

  On the other hand, according to the structure in which the low-resistance electrode layer 167 is formed on the gate electrode layer 149 (p-type polysilicon), the sheet resistance is reduced by 100/100 as compared with the case where the low-resistance electrode layer 167 is not formed. It can be reduced to 1 or less. That is, according to the structure having the low-resistance electrode layer 167, the sheet resistance can be reduced to 1/5 or less as compared with the gate electrode layer 149 including n-type polysilicon.

  As described above, according to the structure having the low-resistance electrode layer 167, the sheet resistance in the gate trench 142 can be reduced while increasing the gate threshold voltage Vth (for example, by about 1V). Thus, the gate resistance can be reduced, so that the current can be efficiently diffused along the trench gate structure 161. As a result, the switching delay can be reduced.

Further, according to the structure having the low resistance electrode layer 167, it is not necessary to increase the p-type impurity concentration of the body region 141 and the p-type impurity concentration of the contact region 164. Therefore, it is possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in channel resistance.
The low resistance electrode layer 167 may include at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ or WSi ₂ . In particular, among these species, NiSi, CoSi ₂ and TiSi ₂ are suitable as a polycide layer for forming the low-resistance electrode layer 167 because of their relatively small specific resistance and low temperature dependency.

As a result of further verification by the present inventors, when TiSi ₂ is used as the material of the low-resistance electrode layer 167, an increase in the leak current between the gate and the source when a low electric field is applied is observed. On the other hand, when CoSi ₂ was employed, no increase in leakage current between the gate and the source was observed when a low electric field was applied. Considering this point, it is considered that CoSi ₂ is most preferable as the polycide layer forming the low-resistance electrode layer 167.

Further, according to SiC semiconductor device 101, gate wiring layer 150 is covered with low-resistance electrode layer 167. Thus, the gate resistance of the gate wiring layer 150 can be reduced.
In particular, in a structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low-resistance electrode layer 167, current can be efficiently diffused along the trench gate structure 161. Therefore, it is possible to appropriately reduce the switching delay.

FIG. 26 is an enlarged view of a region corresponding to FIG. 19 and is an enlarged view showing the SiC semiconductor device 221 according to the fourth embodiment of the present invention. FIG. 27 is a sectional view taken along the line XXVII-XXVII shown in FIG. In the following, structures corresponding to structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and description thereof is omitted.
Referring to FIGS. 26 and 27, SiC semiconductor device 221 includes an outer gate trench 222 formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. The outer gate trench 222 extends like a band along the periphery of the active region 111.

The outer gate trench 222 is formed in a region directly below the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. Outer gate trench 222 extends along outer gate finger 117.
More specifically, outer gate trench 222 is formed along three side surfaces 105A, 105B, and 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (for example, a square ring) surrounding the inner region of the active region 111.

The outer gate trench 222 communicates with the contact trench 144 of each gate trench 142. Thus, the outer gate trench 222 and the gate trench 142 are formed by one trench.
The gate wiring layer 150 is embedded in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at a portion where the gate trench 142 and the outer gate trench 222 communicate with each other.

A low resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low-resistance electrode layer 167 covering the gate electrode layer 149 and the low-resistance electrode layer 167 covering the gate wiring layer 150 are located in one trench.
As described above, the same effects as those described for the SiC semiconductor device 101 can also be obtained by the SiC semiconductor device 221. Further, according to SiC semiconductor device 221, there is no need to extend gate wiring layer 150 above first main surface 103 of SiC semiconductor layer 102.

Thereby, at the opening edge portion 146 of the gate trench 142 (outer gate trench 222), the gate wiring layer 150 can be suppressed from facing the SiC semiconductor layer 102 with the gate insulating layer 148 interposed therebetween. As a result, concentration of an electric field at the opening edge 146 of the gate trench 142 (outer gate trench 222) can be suppressed.
FIG. 28 is an enlarged view of a region corresponding to FIG. 22, and is an enlarged view showing the SiC semiconductor device 231 according to the fifth embodiment of the present invention. In the following, structures corresponding to structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and description thereof is omitted.

Referring to FIG. 28, in this embodiment, SiC epitaxial layer 107 includes a high concentration region 108, a low concentration region 109, and a concentration gradient region 232 interposed between high concentration region 108 and low concentration region 109.
The concentration gradient region 232 is formed not only in the active region 111 but also in the outer region 112 in the SiC epitaxial layer 107. The concentration gradient region 232 is formed over the entire area of the SiC epitaxial layer 107.

  The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high concentration region 108 to the low concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low concentration region 109 to the high concentration region 108. The concentration gradient region 232 suppresses a rapid change in the n-type impurity concentration in a region between the high concentration region 108 and the low concentration region 109.

When SiC epitaxial layer 107 includes concentration gradient region 232, it is preferable that the n-type impurity concentration in high concentration region 108 be 1.5 times or more and 5 times or less than the n-type impurity concentration in low concentration region 109. The n-type impurity concentration of the high concentration region 108 may be three times or more and five times or less than the n-type impurity concentration of the low concentration region 109.
The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

Although a specific description is omitted, the above-described gate trench 142, source trench 155, deep well region 165, outer deep well region 182, and the like are formed in the high concentration region 108.
In other words, the gate trench 142, the source trench 155, the deep well region 165, the outer deep well region 182, and the like are located on the first main surface 103 with respect to the boundary region between the high concentration region 108 and the concentration gradient region 232 in the SiC semiconductor layer 102. Side region.

As described above, the same effects as those described for the SiC semiconductor device 101 can also be obtained by the SiC semiconductor device 231.
FIG. 29 is an enlarged view of a region corresponding to FIG. 19 and is an enlarged view showing the SiC semiconductor device 241 according to the sixth embodiment of the present invention. In the following, structures corresponding to structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 29, in this embodiment, gate trench 142 is formed in a lattice shape in plan view. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench portion 143.

The plurality of first gate trenches 242 are formed at intervals in the second direction Y, and are each formed in a band shape extending in the first direction X. The plurality of first gate trenches 242 are formed in a stripe shape as a whole in plan view.
The side wall forming the long side in each first gate trench 242 is formed by the a-plane of the SiC single crystal. The side wall forming the short side in each first gate trench 242 is formed by the m-plane of the SiC single crystal.

The plurality of second gate trenches 243 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. The plurality of second gate trenches 243 are formed in a stripe shape as a whole in plan view.
The side wall forming the long side in each second gate trench 243 is formed by the m-plane of the SiC single crystal. The side wall forming the short side in each second gate trench 243 is formed by the a-plane of the SiC single crystal.

The plurality of first gate trenches 242 and the plurality of second gate trenches 243 cross each other. Thus, one gate trench 142 having a lattice shape in a plan view is formed. In a region surrounded by the gate trench 142, a plurality of cell regions 244 are defined.
The plurality of cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in plan view. The plurality of cell regions 244 are formed in a square shape in plan view. In each cell region 244, body region 141 is exposed from the side wall of gate trench 142. Body region 141 is exposed from the side wall formed by m-plane and a-plane of the SiC single crystal in gate trench 142.

Of course, the gate trench 142 may be formed in a honeycomb shape as one mode of a lattice shape in plan view. In this case, the plurality of cell regions 244 may be arranged in a staggered manner at intervals in the first direction X and the second direction Y. In this case, the plurality of cell regions 244 may be formed in a hexagonal shape in a plan view.
Each source trench 155 is formed at the center of each cell region 244 in plan view. Each source trench 155 is formed in a pattern that appears on a cut surface that appears when each cell region 244 is cut along the first direction X. Further, each source trench 155 is formed in a pattern that appears on a cut surface that appears when each cell region 244 is cut along the second direction Y.

More specifically, each source trench 155 is formed in a square shape in plan view. Four side walls of each source trench 155 are formed by the m-plane and the a-plane of the SiC single crystal.
The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, a hexagonal shape, or a circular shape or an elliptical shape in plan view.

The cross-sectional view along the line XX-XX in FIG. 29 corresponds to the cross-sectional view shown in FIG. The cross-sectional view along the line XXI-XXI in FIG. 29 corresponds to the cross-sectional view shown in FIG.
As described above, the same effect as the effect described for the SiC semiconductor device 101 can also be obtained by the SiC semiconductor device 241.
Although the embodiments of the present invention have been described, the embodiments of the present invention can be embodied in other forms.

  In each of the above embodiments, side surfaces 5A and 105A and side surfaces 5C and 105C of SiC semiconductor layers 2 and 102 face the a-plane of the SiC single crystal, and side surfaces 5B and 105B and side surfaces 5D and 105D correspond to the m-plane of the SiC single crystal. Has been described. However, a form may be adopted in which side surfaces 5A and 105A and side surfaces 5C and 105C face the m-plane of the SiC single crystal, and side surfaces 5B and 105B and side surfaces 5D and 105D face the a-plane of the SiC single crystal.

  In each of the embodiments described above, the example in which the continuously extending strip-shaped reforming lines 22A to 22D are formed has been described. However, in each of the embodiments described above, the reforming lines 22 </ b> A to 22 </ b> D having a dashed band shape (dashed line shape) may be formed. That is, the reforming lines 22A to 22D may be formed in a band shape extending intermittently. In this case, one, two, or three of the reforming lines 22A to 22D may be formed in a dashed band shape, and the rest may be formed in a band shape.

In the above-described third to sixth embodiments, examples in which the plurality of gate trenches 142 (first gate trenches 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal have been described. .
However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction ) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 extending along the a-axis direction ([11-20] direction ) of the SiC single crystal are formed.

In the above-described third to sixth embodiments, examples in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 interposed therebetween have been described. However, the source electrode layer 157 may be directly buried in the source trench 155 without using the source insulating layer 156.
In the third to sixth embodiments described above, the example in which the source insulating layer 156 is formed along the side wall and the bottom wall of the source trench 155 has been described.

However, the source insulating layer 156 may be formed along the side wall of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the bottom wall of the source trench 155.
Further, source insulating layer 156 may be formed along the bottom wall of source trench 155 so as to expose the side wall of source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the side wall of the source trench 155.

  In the above-described third to sixth embodiments, the example in which the gate electrode layer 149 and the gate wiring layer 150 including p-type polysilicon to which p-type impurities are added has been described. However, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 149 and the gate wiring layer 150 may be replaced with or in addition to the p-type polysilicon, and may be made of n-type polysilicon doped with an n-type impurity. May be included.

In this case, the low-resistance electrode layer 167 may be formed by silicidizing a portion of the gate electrode layer 149 (n-type polysilicon) forming a surface layer portion with a metal material. That is, the low-resistance electrode layer 167 may include n-type polycide. In the case of such a structure, the gate resistance can be reduced.
In the third to sixth embodiments described above, ap ⁺ -type SiC semiconductor substrate (106) may be used instead of the n ⁺ -type SiC semiconductor substrate 106. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the “source” of the MISFET is read as the “emitter” of the IGBT, and the “drain” of the MISFET is read as the “collector” of the IGBT.

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be n-type, and the n-type portion may be p-type.
Each of the above embodiments can be applied to a semiconductor device using a semiconductor material different from SiC. The semiconductor material different from SiC may be a compound semiconductor material. The compound semiconductor material may be one or both of gallium nitride (GaN) and gallium oxide (Ga ₂ O ₃ ).

  For example, the third to sixth embodiments described above may be a compound semiconductor device including a vertical compound semiconductor MISFET in which a compound semiconductor material is used instead of SiC. In a compound semiconductor, magnesium may be employed as a p-type impurity (acceptor). Further, germanium (Ge), oxygen (O), or silicon (Si) may be employed as the n-type impurity (donor).

This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments can be combined in any mode and any mode between them. That is, a form in which the features shown in the first to sixth embodiments are combined in an arbitrary form and an arbitrary form may be adopted.
In addition, various design changes can be made within the scope of the matters described in the claims.

Reference Signs List 1 SiC semiconductor device 2 SiC semiconductor layer 3 First main surface of SiC semiconductor layer 4 Second main surface of SiC semiconductor layer 5A Side surface of SiC semiconductor layer 5B Side surface of SiC semiconductor layer 5C Side surface of SiC semiconductor layer 5D Side surface of SiC semiconductor layer 6 SiC semiconductor substrate 7 SiC epitaxial layer 22A Reforming line 22B Reforming line 22C Reforming line 22D Reforming line 25 First region 26 of reforming line Second region 27 of reforming line 27 Connection region 81 of reforming line SiC semiconductor Device 101 SiC semiconductor device 102 SiC semiconductor layer 103 First main surface of SiC semiconductor layer 104 Second main surface of SiC semiconductor layer 105A Side surface of SiC semiconductor layer 105B Side surface of SiC semiconductor layer 105C Side surface of SiC semiconductor layer 105D SiC semiconductor layer Side surface 106 SiC semiconductor substrate 107 SiC epitaxial layer θ Angle Z Normal direction X First direction (m-axis direction)
Y 2nd direction (a-axis direction)

Claims (22)

A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, each including an SiC single crystal; Yes and, and, for chromatic said second main surface and SiC semiconductor substrate forming a part of said side surface, and a multilayer structure including a SiC epitaxial layer forming part of the first major surface and said side SiC A semiconductor layer;
It is formed in a strip one layer in the portion made of the SiC semiconductor substrate at intervals in the second main surface side from Oite the SiC epitaxial layer on each of said side surfaces of the SiC semiconductor layer, with respect to the first major surface And a plurality of reforming lines that are modified to have properties different from those of the SiC single crystal. Each said reforming line, said that from the second main surface of the SiC semiconductor layer is formed at an interval on the first main surface, a SiC semiconductor device according to claim 1. Each of the reforming lines is configured such that, when viewed from a side normal to each of the side surfaces of the SiC semiconductor layer, each of the side surfaces of the SiC semiconductor layer is formed on the first main surface side region and the second main surface side. 3. The SiC semiconductor device according to claim 1, wherein the SiC semiconductor device is divided into two regions. The SiC semiconductor device according to any one of claims 1 to 3 , wherein each of the reforming lines includes a portion extending linearly. The SiC semiconductor according to any one of claims 1 to 4 , wherein each of the reforming lines includes a portion extending in a concavely curved shape from the first main surface to the second main surface of the SiC semiconductor layer. apparatus. The SiC semiconductor according to any one of claims 1 to 5 , wherein each of the reforming lines includes a portion of the SiC semiconductor layer extending from the second main surface toward the first main surface in a convexly curved shape. apparatus. Each of the reforming lines includes a portion extending in a convexly curved shape from the second main surface of the SiC semiconductor layer toward the first main surface , and a portion extending from the first main surface of the SiC semiconductor layer to the second main surface. The SiC semiconductor device according to any one of claims 1 to 6 , further comprising a portion extending in a concavely curved shape toward the surface. Each of the reforming lines is formed in a first region formed on the first main surface side of the SiC semiconductor layer, and is shifted from the first region on the second main surface side of the SiC semiconductor layer. The SiC semiconductor device according to any one of claims 1 to 7 , further comprising a second region, and a connection region extending obliquely so as to connect the first region and the second region. The first region of each of the reforming lines is located on the first main surface side of the SiC semiconductor layer with respect to an intermediate portion in the thickness direction of the SiC semiconductor layer,
The second region of each of the reforming lines is located on the second main surface side of the SiC semiconductor layer with respect to an intermediate portion in the thickness direction of the SiC semiconductor layer,
The SiC semiconductor device according to claim 8 , wherein the connection region of each of the reforming lines crosses a middle part of the SiC semiconductor layer in a thickness direction. The side surface of the SiC semiconductor layer is formed of a cleavage plane, SiC semiconductor device according to any one of claims 1-9. The SiC semiconductor layer has a thickness of 200μm or more 40 [mu] m, the SiC semiconductor device according to any one of claims 1-10. The SiC semiconductor device according to any one of claims 1 to 11 , wherein the second main surface of the SiC semiconductor layer comprises a ground surface. The SiC single crystal is composed of hexagonal, SiC semiconductor device according to any one of claims 1 to 12. The SiC semiconductor device according to claim 13 , wherein the SiC single crystal is made of a 2H (Hexagonal) -SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal. It said first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal, a SiC semiconductor device according to claim 13 or 14. It said first main surface of the SiC semiconductor layer has an off-angle that is tilted at an angle of 0 ° to 10 ° with respect to the c-plane of the SiC single crystal, either of claims 13-15 one Item 6. The SiC semiconductor device according to item 1. 17. The SiC semiconductor device according to claim 16 , wherein said off angle is an angle of 5 degrees or less. The off angle is an angle of less than 4 ° beyond the 0 °, SiC semiconductor device according to claim 16 or 17.   The SiC semiconductor device according to claim 1, further comprising an insulating layer formed on said first main surface so as to be continuous with each of said side surfaces.   20. The SiC semiconductor device according to claim 19, further comprising a first electrode formed on the insulating layer at an interval inward from each of the side surfaces.   21. The SiC semiconductor device according to claim 20, further comprising a resin layer formed on the insulating layer at an interval inward from each of the side surfaces and having an opening exposing the first electrode.   22. The SiC semiconductor device according to claim 1, further comprising a second electrode covering the second main surface.

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