JP6513626B2 - Substrate with built-in photonic crystal, method of manufacturing the same, and surface emitting quantum cascade laser - Google Patents

Description

  Embodiments of the present invention relate to a photonic crystal embedded substrate and a method of manufacturing the same, and a surface emitting quantum cascade laser.

  A laser having a photonic crystal layer can emit laser light above the active layer.

  A surface emitting quantum cascade laser can be manufactured by forming an active layer, a photonic crystal layer, an upper cladding layer, a contact layer, an upper electrode, and the like in this order on a semiconductor substrate. In this case, the photonic crystal layer includes a region constituting a lattice point of the two-dimensional diffraction grating and a region surrounding it and a region having a different refractive index.

  The manufacturing process of the surface emitting laser which crystal-grows the upper clad layer, the contact layer, etc. while leaving the void by forming the void by using the microfabrication process in the semiconductor layer and forming the lattice point is complicated and the yield is increased. It is difficult.

JP, 2009-111167, A

  Provided is a photonic crystal built-in substrate incorporating a two-dimensional diffraction grating easy to control the polarization direction, a method of manufacturing the same, and a mass-produced surface emitting quantum cascade laser.

The embodiment is a method of manufacturing a photonic crystal-embedded substrate in which a laminate including an active layer causing intersubband optical transition is crystal-grown. In the method of manufacturing a photonic crystal built-in substrate, a step of forming a dielectric film having a refractive index lower than that of the compound semiconductor substrate on the surface of a compound semiconductor substrate, patterning the dielectric film, and two-dimensional diffraction Forming dielectric layers constituting lattice points of the grating, each dielectric layer being patterned to have an asymmetric shape with respect to at least one of the sides of the two-dimensional diffraction grating; Crystal growth of a first semiconductor layer having a region lattice-matchable with the material of the compound semiconductor substrate on the surface side and the dielectric layer of the compound semiconductor substrate on the surface side, and a chemical mechanical polishing process And planarizing the region of the first semiconductor layer. The planarized surface of the region is the regrowth initiation surface of the stack .

FIG. 1 (a) is a schematic perspective view of a surface emitting quantum cascade laser according to a first embodiment, and FIG. 1 (b) is a schematic perspective view of a photonic crystal built-in substrate used in the first embodiment. FIGS. 2A to 2D are schematic views illustrating a method of manufacturing a photonic crystal built-in substrate. FIG. 3A is a schematic cross-sectional view illustrating the crystal growth direction of the first semiconductor layer, and FIG. 3B is a schematic cross-sectional view illustrating the boundary region between the dielectric layer and the first semiconductor layer. . FIGS. 4A and 4B are schematic views illustrating a method of manufacturing a surface emitting quantum cascade laser. Fig.5 (a) is a model perspective view of the surface emitting quantum cascade laser concerning a comparative example, FIG.5 (b) is a model top view of the comparative example of a two-dimensional diffraction grating. FIG. 1 is a schematic plan view illustrating the configuration of a two-dimensional diffraction grating of a surface emitting quantum cascade laser according to a first embodiment. FIG. 7 (a) is a band diagram of the photonic crystal, and FIG. 7 (b) is a graph illustrating the laser oscillation mode. It is a graph showing the wavelength dependence in vacuum to lattice spacing. FIG. 9 (a) is a schematic perspective view for explaining the shape of lattice points in the first embodiment, and FIG. 9 (b) is a diagram showing the electric field vector distribution in the near field near the saddle point. It is a figure showing the electromagnetic field distribution corresponding to B mode in a 1st embodiment. FIG. 11A is a schematic plan view of a first modified example of the two-dimensional diffraction grating, and FIG. 11B is a schematic plan view showing an arrangement example of a two-dimensional diffraction grating of one chip. 12 (a) is a schematic plan view of a second modification of the two-dimensional diffraction grating, FIG. 12 (b) is a schematic plan view of a third modification of the two-dimensional diffraction grating, and FIG. 12 (c) is a two-dimensional diffraction grating It is a model top view of the 4th modification of. FIGS. 13A and 13B are schematic side views of a two-dimensional diffraction grating including a triangular grating.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic perspective view of a surface emitting quantum cascade laser according to the first embodiment, and FIG. 1B is a schematic perspective view of a photonic crystal built-in substrate used in the first embodiment.
As shown in FIG. 1B, the photonic crystal embedded substrate 10 includes a compound semiconductor substrate 20, a dielectric layer 31, and a first semiconductor layer 40.

  The dielectric layer 31 is provided on the surface of the compound semiconductor substrate 20 and arranged at lattice points of the two-dimensional diffraction grating 34. Each dielectric layer 31 has an asymmetrical shape with respect to at least one side of the two-dimensional diffraction grating 34. Also, the refractive index is lower than the refractive index of the compound semiconductor substrate 20.

  The first semiconductor layer 40 covers the surfaces of the dielectric layer 31 and the compound semiconductor substrate 20, and has a flat first surface 40a. The layer constituting the first surface 40 a contains a material lattice-matchable with the material constituting the compound semiconductor substrate 20.

  The surface emitting quantum cascade laser 5 at least includes the photonic crystal embedded substrate 10 and the active layer 54. Further, as shown in FIG. 1A, the surface emitting quantum cascade laser 5 may further include a semiconductor stack 50, an upper electrode 60, and a lower electrode 62.

  The semiconductor stack 50 can have the lower cladding layer 52, the active layer 54, the upper cladding layer 56, and the like from the side of the photonic crystal embedded substrate 10 side. The semiconductor laminate 50 is grown on the first surface 40 a of the photonic crystal embedded substrate 10 by using MOCVD (Metal Organic Chemical Vapor Deposition) method, MBE (Molecular Beam Epitaxy) method, or the like. In this case, when the layer forming the flat first surface 40 a and the material forming the compound semiconductor substrate 20 are lattice matched, good crystallinity can be obtained. Thereafter, the semiconductor stack 50 is grown so as to be lattice-matched with the layer constituting the first surface 40a, whereby the surface-emitting quantum cascade laser 5 with good crystallinity can be obtained.

  In the specification of the present application, lattice matching of the material of the layer constituting the first surface 40 a and the material of the compound semiconductor substrate 20 means that the layer of the first surface 40 a with respect to the lattice constant of the compound semiconductor substrate 20. Deviation of lattice constant is within ± 1%.

  The active layer 54 is provided on the first surface 40 a of the first semiconductor layer 40, and can emit the laser light 70 by the intersubband optical transition. Each dielectric layer 31 has an asymmetrical shape with respect to at least one side of the two-dimensional diffraction grating 34 and has a refractive index lower than that of the compound semiconductor substrate 20. The laser light 70 is emitted in the direction perpendicular to the surface of the active layer 54 as a single mode TM (Transverse Magnetic) wave whose polarization is uniform in a predetermined direction. The wavelength of the laser beam 70 is, for example, infrared to terahertz wave.

  In the surface emitting quantum cascade laser 5 according to the first embodiment, it is not necessary to crystal-grow the upper cladding layer or the contact layer above the holes and the like that constitute the two-dimensional diffraction grating. This facilitates the manufacturing process. In addition, since the dimensional accuracy of the two-dimensional diffraction grating can be enhanced, it becomes easy to obtain a high quality beam.

FIGS. 2A to 2D are schematic views illustrating a method of manufacturing a photonic crystal built-in substrate. 2 (a) is a schematic perspective view of a compound semiconductor substrate, FIG. 2 (b) is a schematic perspective view after forming a dielectric film on the compound semiconductor substrate, and FIG. 2 (c) is a dielectric film patterned FIG. 2D is a schematic perspective view of the first semiconductor layer after crystal growth.
The compound semiconductor substrate 20 shown in FIG. 2A can be InP, GaAs, or the like. The thickness of the wafer is, for example, 100 to 900 μm.

As shown in FIG. 2B, the dielectric film 30 is provided on the surface 20a of the compound semiconductor substrate 20, and may be a nitride film, an oxide film, or the like. Si ₃ N ₄ or the like can be used as the nitride film, and SiO ₂ or the like can be used as the oxide film. The dielectric film 30 can be formed, for example, using a CVD (Chemical Vapor Deposition) method, a sputtering method, an ECR (Electron Cyclotron Resonanse) sputtering method, or the like. The thickness is, for example, 300 nm to 1 μm. For example, the refractive index of Si ₃ N ₄ is about 2.0, the refractive index of SiO ₂ is about 1.43, and so on. When the compound semiconductor substrate 20 includes InP, the refractive index of the dielectric film 30 is lower than the refractive index of InP (for example, about 3.4).

  A photoresist (not shown) is applied on the dielectric film 30. The photoresist is exposed to remove unnecessary portions of the dielectric film 30 using a mask pattern of a two-dimensional diffraction grating. Thus, as shown in FIG. 2C, the dielectric layer 31 constituting the two-dimensional diffraction grating 34 is formed. An exemplary configuration of the two-dimensional diffraction grating 34 will be described in detail later. Unwanted portions of the dielectric film 30 can be easily removed by wet etching or dry etching.

  As shown in FIG. 2D, on the dielectric layer 31 and the compound semiconductor substrate 20, the first semiconductor layer 40 containing a material lattice-matchable with the material of the compound semiconductor substrate 20 is regrown, and the first semiconductor layer 40 is formed. The surface 40a is a flat and regrowthable surface. When the compound semiconductor substrate 20 is n-type InP, the first semiconductor layer 40 is made of n-type InP or a material such as n-type InGaAs capable of lattice matching with InP. For example, n-type InP is regrown from the exposed surface 20 a of the compound semiconductor substrate 20 to the height of the dielectric layer 31 to form the selective growth layer 40 b.

FIG. 3A is a schematic cross-sectional view illustrating the crystal growth direction of the first semiconductor layer, and FIG. 3B is a schematic cross-sectional view illustrating the boundary region between the dielectric layer and the first semiconductor layer. .
FIGS. 3A and 3B are schematic cross-sectional views taken along the line A-A in FIG. In FIG. 3A, crystal growth is started from the surface of the compound semiconductor substrate 20, and a selective growth layer 40b is stacked upward from the region of the compound semiconductor substrate 20 between the dielectric layers 31. The crystal growth direction is indicated by an arrow. When the thickness of the selective growth layer 40 b reaches the height of the dielectric layer 31, lateral growth proceeds along the surface of the dielectric layer 31. In the vicinity of the central portion of the top surface of the dielectric layer 31, the regions laterally grown from both sides are connected to form a domain boundary portion 40d. Furthermore, the crystal growth proceeds, so that the crystallinity becomes good, and an overgrown layer 40c whose surface is flattened is formed.

  When the surface after crystal growth is subjected to polishing or CMP (Chemical and Mechanical Polishing) process, the surface becomes flatter. Thus, the semiconductor stack 50 including the active layer 54 can be regrown while maintaining good crystallinity. The thickness of the first semiconductor layer 40 including the selective growth layer 40 b and the overgrowth layer 40 c can be, for example, 2 μm.

In addition, when the dielectric layer 31 is a silicon nitride layer or a silicon oxide layer, Si thermally decomposed during the crystal growth process is diffused into the first semiconductor layer 31. As a result, the first semiconductor layer 40 has a region 40 e in which the silicon concentration increases toward the dielectric layer 31. For example, 10 ¹⁵ to 10 ¹⁸ cm ⁻² of Si is doped within a distance of 100 nm from the surface of the dielectric layer 31.

  FIGS. 4A and 4B are schematic views illustrating a method of manufacturing a surface emitting quantum cascade laser. That is, FIG. 4A is a schematic perspective view of crystal growth of a semiconductor laminate including an active layer on a photonic crystal embedded substrate, and FIG. 4B is a surface emitting quantum cascade laser in which an upper electrode and a lower electrode are formed. It is a model perspective view of.

  The semiconductor stacked body 50 is regrown on the first surface 40 a of the first semiconductor layer 40 using the MOCVD method, the MBE method, or the like. The semiconductor laminate 50 has at least the lower cladding layer 52, the active layer 54, and the upper cladding layer 56 from the side of the photonic crystal embedded substrate 10 side. The active layer 54 has a structure in which a unit laminate including a pair of a light emitting quantum well layer and an injection quantum well layer is stacked with 30 to 200 layers or the like.

  The semiconductor stack 50 also includes a lower light guide layer (not shown) provided between the lower cladding layer 52 and the active layer 54, and an upper light provided between the active layer 54 and the upper cladding layer 56. It can further include a guide layer (not shown), a contact layer (not shown) provided between the upper cladding layer 56 and the upper electrode 60, and the like. The lower electrode 62 is provided on the back surface 20 b of the compound semiconductor substrate 20.

  When the carrier is an electron, the lower cladding layer 52 contains n-type InP, n-type InAlAs, n-type InGaAs or the like, and its thickness can be 2 to 4 μm or the like. The upper cladding layer 56 contains n-type InP, n-type InAlAs, n-type InGaAs or the like, and its thickness can be 2 to 4 μm or the like. Because the lower cladding layer 52 and the upper cladding layer 56 are thick, they are preferably lattice matched with the layers that make up the first surface 40a.

  The quantum well layer constituting the active layer 54 can include, for example, a well layer containing InGaAs and a barrier layer containing InAlAs. The thickness of the active layer 54 in which the unit stack including the light emitting quantum well layer and the injection quantum well layer is stacked can be 0.6 to 4 μm or the like.

  The semiconductor stack 50 including the active layer 54 may be regrown on the back surface 20 b of the photonic crystal embedded substrate 20. In this case, the thickness of the overgrowth layer 40c shown in FIG. 2D is increased to several hundred μm or the like to increase the mechanical strength. Thereafter, the back surface side of the compound semiconductor substrate 20 is thinned to, for example, several μm or less by polishing or the like. Also, the surface of the thin layer can be planarized using a CMP process or the like. The semiconductor stack 50 regrown on the back surface 20 b of the compound semiconductor substrate 20 can have higher crystallinity. Since the thickness of the original compound semiconductor substrate 20 is reduced to several μm or less, the distance between the active layer 54 and the photonic crystal is short. Therefore, optical resonance by the photonic crystal is facilitated.

Fig.5 (a) is a model perspective view of the surface emitting quantum cascade laser concerning a comparative example, FIG.5 (b) is a model top view of the comparative example of a two-dimensional diffraction grating. It is.
As shown in FIG. 5A, in the surface emitting quantum cascade laser according to the comparative example, at least the lower cladding layer 152, the active layer 154, and the photonic crystal layer 141 are crystal-grown in this order on the substrate 120. The photonic crystal layer 141 is provided with the holes 142 so as not to reach the active layer 154. The holes 142 constitute a two-dimensional diffraction grating. For example, the light guide layer 155, the upper cladding layer 156, the contact layer 157, and the like are regrown on the holes 142.

  The lattice point G of the square lattice of the photonic crystal of the comparative example is formed of a low refractive index medium (or including a hole) 142 whose plane shape is a circle.

  In the case of the comparative example, a submicron-order fine etching process is required for the semiconductor photonic crystal layer 141. Thereafter, the light guide layer 155, the upper cladding layer 156, the contact layer 157, etc. must be regrown so as not to fill the holes 142. For this reason, the manufacturing process is complicated and it is not easy to achieve high yield.

  On the other hand, in the structure in which the holes 142 are provided on the upper surface of the chip, it is necessary to form the upper electrode 160 on the surface provided with the periodic structure of the diffraction grating. Also in this case, the manufacturing process is complicated and it is not easy to achieve high yield.

  On the other hand, in the surface emitting quantum cascade laser 5 according to the first embodiment, the photonic crystal layer is formed on the compound semiconductor substrate 20 in advance. That is, it is not the holes but the dielectric layer 31 such as patterned silicon nitride that constitutes the two-dimensional diffraction grating 34. The process of performing the selective crystal growth on the dielectric layer 31 formed by the microfabrication is easier than the manufacturing process in the comparative example, and can have a high yield.

Next, a two-dimensional diffraction grating that constitutes a photonic crystal will be described.
FIG. 6 is a schematic plan view illustrating the configuration of the two-dimensional diffraction grating of the surface emitting quantum cascade laser according to the first embodiment.
The two-dimensional diffraction grating 34 is a square grating, and a grating interval is represented by a. At the lattice points G, for example, dielectric layers 31 whose plane shapes are right triangles are respectively arranged. In this figure, the center of gravity of the right triangle is represented in the vicinity of the lattice point G. The shape of the triangle is not limited to the right triangle.

FIG. 7 (a) is a band diagram of a photonic crystal, and FIG. 7 (b) is a graph illustrating an example of a laser oscillation mode.
In FIG. 7A, the vertical axis represents the relative normalized frequency obtained by multiplying the frequency of light by a / c, and the horizontal axis represents a wave number vector. Here, a is a lattice constant and c is the speed of light. At the saddle point of the wave number vector, there exist resonance modes A, B, C, and D at which the group velocity of light becomes zero.

  In FIG. 7B, the vertical axis represents relative electric field strength, and the horizontal axis represents normalized frequency. The electric field intensity and the amount of light bleeding in the vertical direction are substantially proportional. Thus, the relative field strength (log scale) can be considered to correspond to the relative gain. According to the simulation of the surface emitting quantum cascade laser having the diffraction grating of FIG. 6, the relative electric field strength of the resonant mode B having a wavelength of 4747 nm is the highest, and the light confinement effect is high. For this reason, it is preferable to oscillate in B mode. Further, since the relative electric field strength of the A mode is also higher than the relative electric field strength of the C and D modes, the A mode may be used.

FIG. 8 is a graph showing the wavelength dependence in vacuum with respect to the lattice spacing.
The vertical axis is the wavelength λ ₀ in vacuum, and the horizontal axis is the grating interval a. According to the inventors' simulation, when the dielectric layer 31 includes a silicon nitride layer and the periphery thereof is surrounded by InP, the oscillation wavelength λ ₀ and the lattice spacing a are approximately represented by a linear function. It turned out that The relationship can be expressed by equation (1).

a (μm) =-0.0222 + 0.3121 λ ₀ (1)

For example, when the lattice spacing a is 1.467 μm and the normalized frequency is 0.30746, the in-vacuum wavelength λ ₀ is 4.7713. Further, the vacuum within the wavelength lambda ₀ even if the following terahertz wave 300μm or 70 [mu] m, it is possible to apply the formula (1). The dielectric layer 31 is, the refractive index may be embedded in a medium of n _1, the medium wavelength lambda _m, of the formula (2).

λ _m = λ ₀ / n ₁ (2)

For example, when the medium is InP, the in-medium wavelength λ _m is shorter than in vacuum because the refractive index n ₁ is about 3.4.

  In the comparative example, as shown in FIG. 5B, the planar shape of the grid point G is a circle. Therefore, the shape of the low refractive index layer constituting the lattice point G is symmetrical with respect to the two sides EE and FF of the square lattice and isotropic with respect to light. For this reason, the near-field electromagnetic field distribution may rotate or be radial in the low refractive index layer. In this case, the far-field electromagnetic field distribution of light extracted above the chip rotates, for example, around the upper electrode 160 in the A mode, and radiates around the upper electrode 160 in the B mode. Therefore, the polarization direction is not aligned in a fixed direction on the chip surface, and it is difficult to achieve high output.

  On the other hand, in the first embodiment, as shown in FIG. 6, two sides sandwiching the right angle are parallel to the two sides E and F of the square lattice, and each dielectric layer 31 is , And has an asymmetrical shape with respect to sides E and F of the two-dimensional diffraction grating 34. Such a two-dimensional diffraction grating 34 has optical anisotropy.

FIG. 9A is a schematic perspective view for explaining the shape of the lattice points in the first embodiment, and FIG. 9B is a diagram showing the electric field vector distribution in the near field near the saddle point.
FIG. 9B is an electric field vector distribution (in the XY plane) analyzed using the 3D-FDTD (three-dimensional time domain finite difference) method. If there is a bias of the electric field due to asymmetry in the region of the dielectric layer 31 in the XY plane (it does not become zero when integrated in the region), light leaks in the Z-axis direction. As represented in FIG. 9 (a), represents the electric field vector of the radiation dielectric layer 31 is emitted in the Z-axis direction above when isosceles right triangle with E _V. A schematic plan view of the dielectric layer 31 is indicated by a broken line in FIG.

FIG. 10 is a diagram showing an electromagnetic field corresponding to the B mode in the first embodiment.
FIG. 10 is a B-mode electric field vector distribution (in the XY plane) analyzed using the 2D-FDTD (two-dimensional time domain finite difference) method. The laser beam 70 from the quantum cascade laser is a TM wave. Therefore, as shown in FIG. 10, the direction of the magnetic field vector H _V is aligned with the predetermined direction by the optical anisotropy. For this reason, the surface emitting quantum cascade laser 5 can emit a TM wave including a linearly polarized magnetic field vector H _V above the chip. As a result, even when the chip size is increased, the stable polarization direction can be maintained, so high-power laser light can be obtained.

FIG. 11A is a schematic plan view of a first modified example of the two-dimensional diffraction grating, and FIG. 11B is a schematic plan view showing an arrangement example of a two-dimensional diffraction grating of one chip.
As shown in FIG. 11A, the two-dimensional diffraction grating 34 is a square grating. The shape of the dielectric layer 31 is not limited to a triangular prism, and may be a right angled isosceles triangular weight or the like. The upper electrode 61 is provided, for example, in a frame shape on the upper surface of the chip. Table 1 is a numerical example of the chip planar shape.

  In Table 1, the wavelength is 4.1 to 4.55 μm. The side length L1 of the chip is, for example, 400 μm. The side length L2 of the region where the two-dimensional diffraction grating 34 is provided is 260 μm or the like. The lattice spacing is a, the length of two sides of the dielectric layer 31 which sandwich the right angle is B, and the number of repetitions of the unit is W.

  Thus, light shielding by the upper electrode 61 can be suppressed. Thus, high light output can be obtained. Although FIG. 11 (b) is an example of the middle and far infrared wavelength band, it may be a terahertz wavelength band. In that case, the lattice spacing can be, for example, 50 μm or less.

12 (a) is a schematic plan view of a second modification of the two-dimensional diffraction grating, FIG. 12 (b) is a schematic plan view of a third modification of the two-dimensional diffraction grating, and FIG. 12 (c) is a two-dimensional diffraction grating It is a model top view of the 4th modification of.
Although a square lattice is illustrated in FIG. 12 (a)-(c), an orthogonal lattice may be sufficient. The shapes of the dielectric layers 31 are all asymmetric with respect to the side F of the square lattice. As shown in FIGS. 12A and 12B, the shape of the dielectric layer 31 is not limited as long as it is asymmetric with respect to the side F of the two-dimensional diffraction grating 34. For example, the shape of the dielectric 31 can be an N square prism (where N is an odd number).

  Further, as shown in FIG. 12C, the dielectric layer 31 includes two dielectric layers 31a and 31b, and is asymmetric with respect to at least one of the sides E and F of the two-dimensional diffraction grating 34. May be

FIGS. 13A and 13B are schematic side views of a two-dimensional diffraction grating including a triangular grating.
In FIG. 13A, the dielectric layer 31 is a triangular prism, and in FIG. 13B, the dielectric layer 31 includes two cylinders (31a and 31b). The planar shape of the dielectric layer 31 is asymmetric with respect to at least one of the sides P, H, and I of the triangular lattice.

  According to this embodiment, a photonic crystal built-in substrate including a two-dimensional diffraction grating whose polarization direction can be easily controlled and a method of manufacturing the same are provided. In addition, a surface-emitting quantum cascade laser capable of controlling the polarization direction of TM waves and having high mass productivity is provided. The surface emitting quantum cascade laser according to the present embodiment can emit high-power laser light because the polarization direction of the TM wave is stable even if the chip size is increased. Therefore, it can be widely used for gas analysis, environment measurement, laser processing, and the like.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

5 surface emitting quantum cascade laser, 10 photonic crystal built-in substrate, 20 compound semiconductor substrate, 30 dielectric film, 31 dielectric layer, 31a, 31b, 31c (of dielectric layer) side, 34 two-dimensional diffraction grating, 40th 1 semiconductor layer 40a first surface 54 active layer 70 laser light E, F (for square lattice) side H, I, P (for triangular lattice) side G lattice point, a lattice spacing

Claims (4)

A method for producing a photonic crystal-embedded substrate, in which a laminate including an active layer causing an intersubband optical transition is crystal-grown.
Forming a dielectric film having a refractive index lower than that of the compound semiconductor substrate on the surface of the compound semiconductor substrate;
Patterning the dielectric film to form dielectric layers constituting lattice points of a two-dimensional diffraction grating, each dielectric layer being asymmetric with respect to at least one of the sides of the two-dimensional diffraction grating Patterned to have a shape,
Crystal-growing a first semiconductor layer having a region lattice-matchable with the material of the compound semiconductor substrate on the surface side and the dielectric layer of the compound semiconductor substrate;
Planarizing the region of the first semiconductor layer using a chemical mechanical polishing process;
Equipped with
The method for manufacturing a photonic crystal built-in substrate , wherein a planarized surface of the region is made a regrowth start surface of the laminate . The method according to claim 1, wherein the dielectric includes a nitride film or an oxide film. The method for manufacturing a photonic crystal embedded substrate according to claim 1, wherein a material of the compound semiconductor substrate is the same as a material of the surface of the first semiconductor layer. The method of manufacturing a photonic crystal built-in substrate according to any one of claims 1 to 3, wherein the compound semiconductor substrate contains InP.