JP6505815B2 - Level shifter - Google Patents

Description

  The present invention relates to a level shifter, for example, a level shifter suitable for high speed operation.

  The internal voltage of the semiconductor device is lowered with the reduction of power consumption. As a result, the potential difference between the internal voltage and the external voltage of the semiconductor device is large. A level shifter that interfaces the inside and the outside of a semiconductor device is required to operate at high speed without lowering the reliability even when the potential difference between the input voltage and the output voltage is large.

  Non-Patent Document 1 discloses a related art level shifter capable of realizing high-speed operation.

Wen-Tai Wang et al., "Level Shifters for High-speed 1-V to 3.3-V Interfaces in a 0.13-um Cu-Interconnection / Low-k CMOS Technology", IEEE, 2001, pp307-310

  However, in the level shifter disclosed in Non-Patent Document 1, there is a possibility that a voltage exceeding the withstand voltage is applied to the low withstand voltage MOS transistor used in the level shifter. As a result, the low withstand voltage MOS transistor is broken or deteriorated, which causes a problem that the reliability of the level shifter is lowered. Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the level shifter includes high voltage first and second PMOS transistors, and high voltage first and second depletion type NMOS transistors having first and second control signals supplied to their gates. And the first and second low-breakdown-voltage NMOS transistors whose third and fourth control signals are supplied to the respective gates, and the first control signal corresponding to the inverted signal of the input signal and the first control signal. And a timing control unit that generates the third control signal and generates the fourth control signal different from the second control signal corresponding to the non-inverted signal of the input signal and the second control signal. .

  According to the one embodiment, it is possible to provide a level shifter capable of realizing high-speed operation without lowering the reliability.

FIG. 2 is a view showing an example of the arrangement of a level shifter according to the first embodiment; 5 is a timing chart showing the operation of the level shifter according to the first embodiment. FIG. 7 is a diagram showing a first specific configuration example of the level shifter according to the first embodiment. It is a figure which shows the 1st modification of the level shifter shown in FIG. It is a figure which shows the 2nd modification of the level shifter shown in FIG. FIG. 7 is a diagram showing a second specific configuration example of the level shifter according to the first embodiment. It is a figure which shows the 1st modification of the level shifter shown in FIG. FIG. 7 is a diagram showing an example of configuration of a level shifter according to a second embodiment. FIG. 16 is a diagram showing a first specific configuration example of the level shifter according to the second embodiment. FIG. 16 is a diagram illustrating a second specific configuration example of the level shifter according to the second embodiment. It is a figure showing composition of a related art level shifter. It is a timing chart which shows operation of a related art level shifter.

<Review by inventor>
Before describing the level shifter according to the present embodiment, the contents examined by the inventor of the related art will be described.

  FIG. 11 is a diagram showing the configuration of the related art level shifter disclosed in Non-Patent Document 1. As shown in FIG. The level shifter shown in FIG. 11 includes high withstand voltage PMOS transistors P1 and P2, high withstand voltage depletion type NMOS transistors NA1 and NA2, and low withstand voltage NMOS transistors N1 and N2.

  The high withstand voltage MOS transistor is a MOS transistor which does not break down until the voltage between two terminals of the source, drain and gate reaches the high voltage power supply voltage VDDQ. The low withstand voltage MOS transistor is a MOS transistor which does not break down until the voltage between two terminals of the source, drain and gate reaches the low voltage power supply voltage VDD. The high-breakdown-voltage MOS transistor has, for example, a thicker gate insulating film than a low-breakdown-voltage MOS transistor. Also, the depletion type MOS transistor may be called a native MOS transistor or a 0-Vth type MOS transistor. The threshold voltage Vth of the depletion type MOS transistor is 0V to -0. It is about several volts.

  The level shifter shown in FIG. 11 is provided with low breakdown voltage NMOS transistors N1 and N2 as transistors receiving the low voltage input signals INL and INR. Thus, even when the voltage level of the power supply voltage VDD is low or the potential difference between the power supply voltages VDD and VDDQ is large, high-speed level shift operation is possible. Further, the level shifter shown in FIG. 11 includes high-voltage depletion type NMOS transistors NA1 and NA2 between low-voltage NMOS transistors N1 and N2 and a power supply voltage terminal to which high voltage power supply voltage VDDQ is supplied. Is equipped. As a result, the voltages of the nodes INT1 and INT2 are kept low, so that a voltage exceeding the withstand voltage is not applied to the low withstand voltage NMOS transistors N1 and N2. Thereby, the deterioration of the low breakdown voltage NMOS transistors N1 and N2 is suppressed.

  However, the inventor has found that a voltage exceeding the withstand voltage may be applied to the low breakdown voltage NMOS transistors N1 and N2 of the level shifter shown in FIG.

  FIG. 12 is a timing chart for explaining the problem of the related art level shifter. For example, when the input signal IN rises from L level (reference voltage VSS) to H level (power supply voltage VDD), the inverted signal INR of the input signal falls from H level to L level. Thereby, the gate voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the gate voltage of the low breakdown voltage NMOS transistor N2 simultaneously fall from the H level to the L level.

  Here, in general, the response speed of the low breakdown voltage MOS transistor is faster than the response speed of the high breakdown voltage MOS transistor. That is, the response speed of the low breakdown voltage NMOS transistor N2 is faster than the response speed of the high breakdown voltage depletion type NMOS transistor NA2. Therefore, when the low breakdown voltage NMOS transistor N2 is turned off, the on resistance of the high breakdown voltage depletion type NMOS transistor NA1 may not be sufficiently large. In that case, since the voltage of the node INT2 becomes high, a voltage exceeding the withstand voltage is applied to the low breakdown voltage NMOS transistor N2. For example, when the threshold voltage Vth of the high breakdown voltage depletion type NMOS transistor NA2 is -0.5 V and the power supply voltage VDD is 1.0 V, the voltage of the node INT2 becomes high as VDD-Vt = 1.5 V. A voltage exceeding the withstand voltage is applied to the transistor N2. As a result, the low breakdown voltage NMOS transistor N2 is degraded. As a result, the reliability of the level shifter is reduced.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the embodiment should not be narrowly interpreted based on the description of the drawings. In addition, the same reference numerals are given to the same elements, and duplicate explanations are omitted.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some of all the modifications, applications, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including the operation steps and the like) are not necessarily essential unless specifically stated and when it is considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above-described numbers and the like (including the number, the numerical value, the amount, the range and the like).

Embodiment 1
FIG. 1 is a view showing a configuration example of the level shifter 1 according to the first embodiment. The level shifter 1 according to the present embodiment applies a voltage exceeding the withstand voltage to the low withstand voltage NMOS transistor by controlling the conduction states of the low withstand voltage NMOS transistor and the high withstand voltage depletion type NMOS transistor by different control signals. I try not to be. Thereby, the deterioration of the low withstand voltage NMOS transistor is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing the reliability. The details will be described below.

  The level shifter 1 shown in FIG. 1 includes a level shift unit 11, a timing control circuit (first timing control circuit) 12, a timing control circuit (second timing control circuit) 13, and an inverter INV1. The timing control circuits 12 and 13 and the inverter INV1 constitute a timing control unit.

  The level shift unit 11 includes a high withstand voltage PMOS transistor (first PMOS transistor) P1, a high withstand voltage PMOS transistor (second PMOS transistor) P2, and a high withstand voltage depletion type NMOS transistor (first depletion type NMOS transistor) NA1. And a high withstand voltage depletion type NMOS transistor (second depletion type NMOS transistor) NA2, a low withstand voltage NMOS transistor (first NMOS transistor) N1, and a low withstand voltage NMOS transistor (second NMOS transistor) N2. .

  The high breakdown voltage PMOS transistors P1 and P2 are connected in parallel between a power supply voltage terminal (first power supply voltage terminal; hereinafter referred to as a power supply voltage terminal VDDQ) to which the high power supply voltage VDDQ is supplied and a reference voltage terminal VSS. , And their gates are connected to each other's drain.

  More specifically, in the high breakdown voltage PMOS transistor P1, the source is connected to the power supply voltage terminal VDDQ, the drain is connected to the node LSDL, and the gate is connected to the node LSDR. In the high breakdown voltage PMOS transistor P2, the source is connected to the power supply voltage terminal VDDQ, the drain is connected to the node LSDR, and the gate is connected to the node LSDL.

  The high breakdown voltage depletion type NMOS transistors NA1 and NA2 are respectively provided in series with the high breakdown voltage PMOS transistors P1 and P2 between the high breakdown voltage PMOS transistors P1 and P2 and the reference voltage terminal VSS.

  More specifically, in the high breakdown voltage depletion type NMOS transistor NA1, the source is connected to the node INT1, the drain is connected to the node LSDL, and the control signal (first control signal) IN1 is supplied to the gate. In the high breakdown voltage depletion type NMOS transistor NA2, the source is connected to the node INT2, the drain is connected to the node LSDR, and the control signal (second control signal) IN2 is supplied to the gate.

  The low withstand voltage NMOS transistors N1 and N2 are provided in series with the high withstand voltage depletion type NMOS transistors NA1 and NA2 respectively between the high withstand voltage depletion type NMOS transistors NA1 and NA2 and the reference voltage terminal VSS. .

  More specifically, in the low breakdown voltage NMOS transistor N1, the source is connected to the reference voltage terminal VSS, the drain is connected to the node INT1, and the control signal (third control signal) IN3 is supplied to the gate. In the low withstand voltage NMOS transistor N2, the source is connected to the reference voltage terminal VSS, the drain is connected to the node INT2, and the control signal (fourth control signal) IN4 is supplied to the gate.

  The timing control circuit 12 is connected between a power supply voltage terminal (second power supply voltage terminal; hereinafter referred to as a power supply voltage terminal VDD) to which a low power supply voltage VDD lower than the power supply voltage VDDQ is supplied and a reference voltage terminal VSS. , And inverts an input signal (hereinafter referred to as an input signal IN) supplied from the outside to the input terminal IN to generate control signals IN1 and IN3. That is, the timing control circuit 12 generates control signals IN1 and IN3 corresponding to the inverted signal of the input signal IN. However, the control signals IN1 and IN3 are different signals. The input signal IN indicates a potential within the range between the power supply voltage VDD and the reference voltage terminal VSS.

  The timing control circuit 13 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and inverts the inverted signal of the input signal IN to generate control signals IN2 and IN4. That is, the timing control circuit 13 generates control signals IN2 and IN4 corresponding to the non-inverted signal of the input signal IN. However, the control signals IN2 and IN4 are different signals.

  That is, the timing control unit including the timing control circuits 12 and 13 and the inverter INV1 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the control signal IN1 corresponding to the inverted signal of the input signal IN and the control signal A control signal IN3 different from IN1 is generated, and a control signal IN2 corresponding to a non-inverted signal of the input signal IN and a control signal IN4 different from the control signal IN2 are generated.

  For example, the timing control unit generates control signals IN1 and IN2 having a smaller slew rate at the rising edge than control signals IN3 and IN4, and a control signal IN3 having a smaller slew rate at the falling edge than control signals IN1 and IN2. , IN4 are generated. Thus, after the ON resistances of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 are increased to a predetermined value or more, the low breakdown voltage NMOS transistors N1 and N2 can be turned off. Also, the low breakdown voltage NMOS transistors N1 and N2 can be turned on before the ON resistances of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 are reduced to a predetermined value or less. As a result, it is possible to prevent the application of a voltage exceeding the withstand voltage to the low withstand voltage NMOS transistors N1 and N2.

(Operation of level shifter 1)
Subsequently, the operation of the level shifter 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the level shifter 1. In FIG. 2, Vgs (NA2) represents the gate-source voltage of the high breakdown voltage depletion type NMOS transistor NA2, and Vgs (N2) represents the gate-source voltage of the low breakdown voltage NMOS transistor N2. .

  First, the input signal IN falls from H level (power supply voltage VDD) to L level (reference voltage VSS). Thereby, the inversion signal INR of the input signal IN rises from the L level to the H level (time t0 to t1). At this time, the timing control circuit 13 lowers the control signal IN2 from H level to L level (time t0 to t1), and controls the control signal IN4 from H level to L level (slowly) at a smaller slew rate than the control signal IN2. It falls to the level (time t0 to t2). As a result, after the on resistance of the high breakdown voltage depletion type NMOS transistor NA2 becomes sufficiently large, the low breakdown voltage NMOS transistor N2 is turned off. As a result, the voltage of the node INT2 is kept small, so that no voltage exceeding the withstand voltage is applied to the low breakdown voltage NMOS transistor N2. Thereby, the deterioration of the low breakdown voltage NMOS transistor N2 is suppressed.

  The potential of the node INT2 can be obtained by subtracting the threshold voltage Vth (NA2) from the gate-source voltage Vgs (NA2) of the high breakdown voltage depletion type NMOS transistor NA2. Therefore, the potential of the node INT2 when the low breakdown voltage NMOS transistor N2 is turned off is approximately 0-Vth = | Vth |. Here, the threshold voltage Vth (NA2) is 0V to -0. Since the voltage is about several volts, no voltage exceeding the withstand voltage is applied to the low withstand voltage NMOS transistor N2.

  On the other hand, although not shown, the timing control circuit 12 raises the control signal IN3 from L level to H level (time t0 to t1) and controls the control signal IN1 at a slew rate smaller than that of the control signal IN3 B) raise from L level to H level (time t0 to t2). As a result, the low breakdown voltage NMOS transistor N1 is turned on while the on resistance of the high breakdown voltage depletion type NMOS transistor NA1 is large. As a result, the voltage of the node INT1 is kept small, so that a voltage exceeding the withstand voltage is not applied to the low breakdown voltage NMOS transistor N1. Thereby, the deterioration of the low breakdown voltage NMOS transistor N1 is suppressed.

  Since the low breakdown voltage NMOS transistor N2 is turned off and the low breakdown voltage NMOS transistor N1 is turned on, the potential of the node LSDR rises to about the power supply voltage VDDQ, and the potential of the node LSDL falls to about the reference voltage VSS. The voltage of the node LSDR is output from the output terminal OUT to the outside.

  Next, the input signal IN rises from the L level to the H level. As a result, the inverted signal INR of the input signal IN falls from H level to L level (time t3 to t5). At this time, the timing control circuit 13 raises the control signal IN4 from L level to H level (time t3 to t5), and controls the control signal IN2 from L level to H level (slowly) at a smaller slew rate than the control signal IN4. Start up to the level (time t3 to t6). As a result, while the on resistance of the high breakdown voltage depletion type NMOS transistor NA2 is large, the low breakdown voltage NMOS transistor N2 is turned on. As a result, the voltage of the node INT2 is kept small, so that no voltage exceeding the withstand voltage is applied to the low breakdown voltage NMOS transistor N2. Thereby, the deterioration of the low breakdown voltage NMOS transistor N2 is suppressed.

  As described above, the potential of the node INT2 can be obtained by subtracting the threshold voltage Vth (NA2) from the gate-source voltage Vgs (NA2) of the high breakdown voltage depletion type NMOS transistor NA2. Here, Vgs (NA2) is lower than the power supply voltage VDD because the voltage level of the control signal IN2 when the low breakdown voltage NMOS transistor N2 is switched from off to on has not yet reached the H level (power supply voltage VDD). . Therefore, the potential of the node INT2 is also lower than VDD. Therefore, no voltage exceeding the withstand voltage is applied to the low withstand voltage NMOS transistor N2.

  On the other hand, although not shown, the timing control circuit 12 lowers the control signal IN1 from the H level to the L level (time t3 to t5) and controls the control signal IN3 with a slew rate smaller than that of the control signal IN1 ) Falling from H level to L level (time t3 to t6). As a result, after the on resistance of the high breakdown voltage depletion type NMOS transistor NA1 becomes sufficiently large, the low breakdown voltage NMOS transistor N1 is turned off. As a result, the voltage of the node INT1 is kept small, so that a voltage exceeding the withstand voltage is not applied to the low breakdown voltage NMOS transistor N1. Thereby, the deterioration of the low breakdown voltage NMOS transistor N1 is suppressed.

  Since the low breakdown voltage NMOS transistor N1 is turned off and the low breakdown voltage NMOS transistor N2 is turned on, the potential of the node LSDL rises to about the power supply voltage VDDQ, and the potential of the node LSDR falls to about the reference voltage VSS. The voltage of the node LSDR is output from the output terminal OUT to the outside.

  More specifically, in the timing control circuit 13, the high breakdown voltage at the time when the gate-source voltage of the low breakdown voltage NMOS transistor N2 decreases and becomes lower than the threshold voltage of the low breakdown voltage NMOS transistor N2 (time t1 in FIG. 2) The control signals IN2 and IN4 are generated such that the gate-source voltage of the depletion type NMOS transistor NA2 is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the power supply voltage VDD. Furthermore, in the timing control circuit 13, the high withstand voltage depletion type at the time (time t4 in FIG. 2) when the gate-source voltage of the low withstand voltage NMOS transistor N2 rises and becomes equal to or higher than the threshold voltage of the low withstand voltage NMOS transistor N2. The control signals IN2 and IN4 are generated such that the gate-source voltage of the NMOS transistor NA2 is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the power supply voltage VDD.

  Similarly, in the timing control circuit 12, the gate-source voltage of the high breakdown voltage depletion type NMOS transistor NA1 at the time when the gate-source voltage of the low breakdown voltage NMOS transistor N1 drops and becomes lower than the threshold voltage of the low breakdown voltage NMOS transistor N1. The control signals IN1 and IN3 are generated such that the voltage between them is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA1 and the power supply voltage VDD. Furthermore, in the timing control circuit 12, the gate-source voltage of the high-breakdown voltage depletion type NMOS transistor NA1 at the time when the gate-source voltage of the low-breakdown voltage NMOS transistor N1 rises and becomes equal to or higher than the threshold voltage The control signals IN1 and IN3 are generated such that the voltage between them is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA1 and the power supply voltage VDD.

  As described above, the level shifter 1 according to the present embodiment controls the conduction states of the low breakdown voltage NMOS transistors N1 and N2 and the high breakdown voltage NMOS transistors NA1 and NA2 with different control signals, respectively. A voltage exceeding the withstand voltage is not applied to N1 and N2. Thereby, the deterioration of the low breakdown voltage NMOS transistors N1 and N2 is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing the reliability.

(First Specific Configuration Example of the Level Shifter 1)
FIG. 3 is a view showing a first specific configuration example of the level shifter 1 as the level shifter 1 a. In FIG. 3, the timing control circuit 12 has a low breakdown voltage PMOS transistor (third PMOS transistor) P11, a low breakdown voltage NMOS transistor (third NMOS transistor) N11, and a resistance element (first resistance element) R1. The timing control circuit 13 has a low breakdown voltage PMOS transistor (fourth PMOS transistor) P13, a low breakdown voltage NMOS transistor (fourth NMOS transistor) N13, and a resistance element (second resistance element) R2.

  In the timing control circuit 12, the low withstand voltage PMOS transistor P11 and the low withstand voltage NMOS transistor N11 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the input signal IN is supplied to their respective gates. There is. The resistance element R1 is provided between the low breakdown voltage PMOS transistor P11 and the low breakdown voltage NMOS transistor N11. Then, the timing control circuit 12 generates the voltage of the node between the low breakdown voltage PMOS transistor P11 and the resistance element R1 as the control signal IN3, and controls the voltage of the node between the low breakdown voltage NMOS transistor N11 and the resistance element R1. It generates as a signal IN1. Thereby, the timing control circuit 12 generates the control signal IN1 having a smaller slew rate at the rising edge than the control signal IN3, and generates the control signal IN3 having a smaller slew rate at the falling edge than the control signal IN1. it can. The slew rate of the control signals IN1 and IN3 can be adjusted by adjusting the size of the low breakdown voltage PMOS transistor P11, the size of the low breakdown voltage NMOS transistor N11, and the resistance value of the resistance element R1.

  In the timing control circuit 13, the low breakdown voltage PMOS transistor P13 and the low breakdown voltage NMOS transistor N13 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the inverted signal of the input signal IN is applied to their gates. It is supplied. The resistance element R2 is provided between the low breakdown voltage PMOS transistor P13 and the low breakdown voltage NMOS transistor N13. Then, the timing control circuit 13 generates the voltage of the node between the low breakdown voltage PMOS transistor P13 and the resistance element R2 as the control signal IN4, and controls the voltage of the node between the low breakdown voltage NMOS transistor N13 and the resistance element R2. It generates as a signal IN2. Thus, the timing control circuit 13 generates the control signal IN2 having a smaller slew rate at the rising edge than the control signal IN4, and generates the control signal IN4 having a smaller slew rate at the falling edge than the control signal IN2. it can. The slew rate of the control signals IN2 and IN4 can be adjusted by adjusting the size of the low breakdown voltage PMOS transistor P13, the size of the low breakdown voltage NMOS transistor N13, and the resistance value of the resistance element R2.

  The inverter INV1 includes a low breakdown voltage PMOS transistor P15 and a low breakdown voltage NMOS transistor N15. The low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS. The inverter INV1 receives the input signal IN at the gates of the low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15, and inputs the voltage of the node between the low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15. Output as an inverted signal of IN.

  The other configuration of the level shifter 1a shown in FIG. 3 is the same as that of the level shifter 1 shown in FIG.

(First Modified Example of Level Shifter 1a)
FIG. 4 is a view showing a first modification of the level shifter 1a shown in FIG. 3 as the level shifter 1b. The timing control circuits 12 and 13 shown in FIG. 4 include transfer gates T1 and T2 as resistance elements R1 and R2, respectively, as compared with the timing control circuits 12 and 13 shown in FIG.

  The transfer gate T1 includes a low breakdown voltage PMOS transistor P12 and a low breakdown voltage NMOS transistor N12. The transfer gate T2 includes a low breakdown voltage PMOS transistor P14 and a low breakdown voltage NMOS transistor N14. The other configuration of the level shifter 1b shown in FIG. 4 is the same as that of the level shifter 1a shown in FIG.

(Second Modified Example of Level Shifter 1a)
FIG. 5 is a view showing a second modification of the level shifter 1a shown in FIG. 3 as the level shifter 1c. The level shift unit 11 shown in FIG. 5 further includes high breakdown voltage PMOS transistors P3 and P4 as compared with the level shift unit 11 shown in FIG.

  The high breakdown voltage PMOS transistor P3 is provided between the drain of the high breakdown voltage PMOS transistor P1 and the node LSDL, and the control signal IN3 is supplied to its gate. The high breakdown voltage PMOS transistor P4 is provided between the drain of the high breakdown voltage PMOS transistor P2 and the node LSDR, and the control signal IN4 is supplied to its gate. The other configuration of the level shifter 1c shown in FIG. 5 is the same as that of the level shifter 1a shown in FIG.

  The level shifter 1c shown in FIG. 5 can exhibit the same effect as the level shifter 1a shown in FIG.

(Second Specific Configuration Example of the Level Shifter 1)
FIG. 6 is a view showing a second specific configuration example of the level shifter 1 as the level shifter 1 d. 6, the timing control circuit 12 includes a low breakdown voltage PMOS transistor (third PMOS transistor) P21, a low breakdown voltage PMOS transistor (fourth PMOS transistor) P22, a low breakdown voltage NMOS transistor (third NMOS transistor) N21, and a low breakdown voltage NMOS transistor (Fourth NMOS transistor) N22. The timing control circuit 13 includes a low breakdown voltage PMOS transistor (fifth PMOS transistor) P23, a low breakdown voltage PMOS transistor (sixth PMOS transistor) P24, a low breakdown voltage NMOS transistor (fifth NMOS transistor) N23, and a low breakdown voltage NMOS transistor (sixth NMOS transistor). And N24).

  In the timing control circuit 12, the low withstand voltage PMOS transistor P21 and the low withstand voltage NMOS transistor N21 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the input signal IN is supplied to their respective gates. There is. The low breakdown voltage PMOS transistor P22 and the low breakdown voltage NMOS transistor N22 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the inverted signal of the input signal IN is supplied to their gates. Then, the timing control circuit 12 generates the voltage of the node between the low breakdown voltage PMOS transistor P21 and the low breakdown voltage NMOS transistor N21 as the control signal IN1, and the node between the low breakdown voltage PMOS transistor P22 and the low breakdown voltage NMOS transistor N22. Voltage is generated as a control signal IN3. Here, the drivability of the low breakdown voltage PMOS transistor P21 is smaller than the drivability of the low breakdown voltage PMOS transistor P22. On the other hand, the drivability of the low breakdown voltage NMOS transistor N21 is larger than the drivability of the low breakdown voltage NMOS transistor N22. Thereby, the timing control circuit 12 generates the control signal IN1 having a smaller slew rate at the rising edge than the control signal IN3, and generates the control signal IN3 having a smaller slew rate at the falling edge than the control signal IN1. it can. The slew rate of the control signals IN1 and IN3 can be adjusted by adjusting the drive capability of the transistors P21, P22, N21 and N22.

  In the timing control circuit 13, the low withstand voltage PMOS transistor P23 and the low withstand voltage NMOS transistor N23 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the input signal IN is supplied to their respective gates. There is. The low breakdown voltage PMOS transistor P24 and the low breakdown voltage NMOS transistor N24 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the inverted signal of the input signal IN is supplied to their gates. Then, the timing control circuit 13 generates the voltage of the node between the low breakdown voltage PMOS transistor P23 and the low breakdown voltage NMOS transistor N23 as the control signal IN2, and the node between the low breakdown voltage PMOS transistor P24 and the low breakdown voltage NMOS transistor N24. Is generated as the control signal IN4. Here, the drive capability of the low breakdown voltage PMOS transistor P23 is smaller than the drive capability of the low breakdown voltage PMOS transistor P24. On the other hand, the drivability of the low breakdown voltage NMOS transistor N23 is larger than the drivability of the low breakdown voltage NMOS transistor N24. Thus, the timing control circuit 13 generates the control signal IN2 having a smaller slew rate at the rising edge than the control signal IN4, and generates the control signal IN4 having a smaller slew rate at the falling edge than the control signal IN2. it can. The slew rate of the control signals IN2 and IN4 can be adjusted by adjusting the drive capability of the transistors P23, P24, N23 and N24.

  The other configuration of the level shifter 1d shown in FIG. 6 is the same as that of the level shifter 1a shown in FIG.

  In the level shifter 1 d shown in FIG. 6, each timing control circuit generates two different control signals from two inverters. Thus, the level shifter 1d shown in FIG. 6 can easily adjust the timing between the control signals IN1 and IN3 and the timing between the control signals IN2 and IN4.

(Modified example of the level shifter 1d)
FIG. 7 is a view showing a modification of the level shifter 1 d shown in FIG. 6 as the level shifter 1 e. The level shift unit 11 shown in FIG. 7 further includes high breakdown voltage PMOS transistors P3 and P4 as compared to the level shift unit 11 shown in FIG.

  The high breakdown voltage PMOS transistor P3 is provided between the drain of the high breakdown voltage PMOS transistor P1 and the node LSDL, and the control signal IN3 is supplied to its gate. The high breakdown voltage PMOS transistor P4 is provided between the drain of the high breakdown voltage PMOS transistor P2 and the node LSDR, and the control signal IN4 is supplied to its gate. The other configuration of the level shifter 1e shown in FIG. 7 is the same as that of the level shifter 1d shown in FIG.

  The level shifter 1 e shown in FIG. 7 can exhibit the same effect as the level shifter 1 d shown in FIG. 6.

Second Embodiment
FIG. 8 is a view showing a configuration example of the level shifter 1 f according to the second embodiment. Compared to the level shifter 1 shown in FIG. 1, the level shifter 1 f shown in FIG. 8 has only the timing control circuit 12 of the timing control circuits 12 and 13 and has inverters INV2 and INV3 instead of the inverter INV1. The timing control circuit 12 and the inverters INV2 and INV3 constitute a timing control unit.

  The timing control circuit 12 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and generates control signals IN1 and IN3 corresponding to inverted signals of the input signal IN. However, the control signals IN1 and IN3 are different signals.

  The inverters INV2 and INV3 have the same circuit configuration as the inverter INV1, and respectively output inverted signals of the control signals IN1 and IN3 as control signals IN4 and IN2. Since the control signals IN1 and IN3 are different signals, it can be said that the control signals IN2 and IN4 are also different signals.

  That is, the timing control unit including the timing control circuit 12 and the inverters INV2 and INV3 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and the control signal IN1 corresponding to the inverted signal of the input signal IN and the control signal A control signal IN3 different from IN1 is generated, and a control signal IN2 corresponding to a non-inverted signal of the input signal IN and a control signal IN4 different from the control signal IN2 are generated.

  For example, the timing control unit generates control signals IN1 and IN2 having a smaller slew rate at the rising edge than control signals IN3 and IN4, and a control signal IN3 having a smaller slew rate at the falling edge than control signals IN1 and IN2. , IN4 are generated. As a result, before the low breakdown voltage NMOS transistors N1 and N2 are turned off, the on resistance of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 can be set to a predetermined value or more. Further, after the low breakdown voltage NMOS transistors N1 and N2 are turned on, the on resistance of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 can be set to a predetermined value or more. As a result, it is possible to prevent the application of a voltage exceeding the withstand voltage to the low withstand voltage NMOS transistors N1 and N2.

  The operation of the level shifter 1 f shown in FIG. 8 is the same as that of the level shifter 1 shown in FIG.

  The level shifter according to the present embodiment can exhibit the same effects as the level shifter according to the first embodiment.

(First Specific Configuration Example of the Level Shifter 1f)
FIG. 9 is a view showing a first specific configuration example of the level shifter 1 f as the level shifter 1 g. In FIG. 9, the timing control circuit 12 has a low breakdown voltage PMOS transistor P11, a low breakdown voltage NMOS transistor N11, and a resistance element R1. The specific connection relationship is the same as that of the timing control circuit 12 shown in FIG. The resistance element R1 may be a transfer gate or the like.

(Second Specific Configuration Example of the Level Shifter 1f)
FIG. 10 is a view showing a second specific configuration example of the level shifter 1 f as the level shifter 1 h. In FIG. 10, the timing control circuit 12 includes a low breakdown voltage PMOS transistor P21, a low breakdown voltage PMOS transistor P22, a low breakdown voltage NMOS transistor N21, and a low breakdown voltage NMOS transistor N22. The specific connection relationship is the same as that of the timing control circuit 12 shown in FIG.

As described above, the level shifter according to the above embodiments controls the low breakdown voltage NMOS transistor by controlling the conduction states of the low breakdown voltage NMOS transistor and the high breakdown voltage NMOS transistor with different control signals. The voltage exceeding the voltage is prevented from being applied. Thereby, the deterioration of the low withstand voltage NMOS transistor is suppressed. As a result, the level shifter according to the above embodiment can realize high-speed operation without reducing the reliability.

As described above, the level shifter 1 according to the present embodiment controls the conduction states of the low breakdown voltage NMOS transistors N1 and N2 and the high breakdown voltage NMOS transistors NA1 and NA2 with different control signals, respectively. A voltage exceeding the withstand voltage is not applied to N1 and N2. Thereby, the deterioration of the low breakdown voltage NMOS transistors N1 and N2 is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing the reliability.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the embodiment mentioned already, A various change in the range which does not deviate from the gist It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Level shifter 1a-1h Level shifter 11 Level shift part 12, 13 Timing control circuit INV1-INV3 Inverter P1-P4 High voltage PMOS transistor N1, N2 Low voltage NMOS transistor NA1, NA2 High voltage depletion type NMOS transistor P11-P15 Low voltage PMOS Transistor N11 to N15 Low voltage NMOS transistor P21 to P24 Low voltage PMOS transistor N21 to N24 Low voltage NMOS transistor R1, R2 Resistance element

Claims (12)

First and second MOS transistors provided in parallel between the first power supply voltage terminal and the reference voltage terminal, with their gates connected to each other's drain,
Third and fourth MOS transistors provided respectively between the first and second MOS transistors and the reference voltage terminal and having first and second control signals supplied to their respective gates;
Fifth and sixth MOS transistors respectively provided between the third and fourth MOS transistors and the reference voltage terminal, the third and fourth control signals being supplied to respective gates of the third and fourth MOS transistors;
Provided between a second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal is supplied, and the reference voltage terminal, corresponding to the inverted signal of the input signal A timing control unit that generates the first control signal and the third control signal, and generates the second control signal and the fourth control signal corresponding to a non-inverted signal of the input signal;
Equipped with
The first to fourth control signals are switched between the first MOS transistor and the reference voltage terminal and between the second MOS transistor and the reference voltage terminal by switching the predetermined high level and the predetermined low level, respectively. Control switching of non-conduction
At the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, it is faster for the first control signal to go to the predetermined low level than to the third control signal to go to the predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, it is faster for the second control signal to go to the predetermined low level than to the fourth control signal to go to the predetermined low level.
In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal goes to a predetermined high level earlier than the first control signal goes to a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, it is faster for the fourth control signal to go to a predetermined high level than to the second control signal to go to a predetermined high level,
The gate oxide thicknesses of the fifth and sixth MOS transistors are smaller than the gate oxide thicknesses of the first to fourth MOS transistors,
The timing control unit
The gate-source voltage of the third MOS transistor at the time when the gate-source voltage of the fifth MOS transistor decreases and becomes lower than the threshold voltage of the fifth MOS transistor is the threshold voltage of the third MOS transistor and the second voltage. The voltage between the gate and the source of the third MOS transistor at a time when the voltage between the gate and the source of the fifth MOS transistor rises and becomes higher than the threshold voltage of the fifth MOS transistor so as to be lower than the sum with the power supply voltage. Generating the first and third control signals such that the sum is lower than the sum of the threshold voltage of the third MOS transistor and the second power supply voltage,
The gate-source voltage of the fourth MOS transistor at the time when the gate-source voltage of the sixth MOS transistor decreases and becomes lower than the threshold voltage of the sixth MOS transistor is the threshold voltage of the fourth MOS transistor and the second voltage. The voltage between the gate and the source of the fourth MOS transistor at a time when the voltage between the gate and the source of the sixth MOS transistor rises and becomes higher than the threshold voltage of the sixth MOS transistor so as to be lower than the sum with the power supply voltage. Generating the second and fourth control signals such that the second control signal is lower than the sum of the threshold voltage of the fourth MOS transistor and the second power supply voltage .
Les Berushifuta. First and second MOS transistors provided in parallel between the first power supply voltage terminal and the reference voltage terminal, with their gates connected to each other's drain,
Third and fourth MOS transistors provided respectively between the first and second MOS transistors and the reference voltage terminal and having first and second control signals supplied to their respective gates;
Fifth and sixth MOS transistors respectively provided between the third and fourth MOS transistors and the reference voltage terminal, the third and fourth control signals being supplied to respective gates of the third and fourth MOS transistors;
Provided between a second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal is supplied, and the reference voltage terminal, corresponding to the inverted signal of the input signal A timing control unit that generates the first control signal and the third control signal, and generates the second control signal and the fourth control signal corresponding to a non-inverted signal of the input signal;
Equipped with
The first to fourth control signals are switched between the first MOS transistor and the reference voltage terminal and between the second MOS transistor and the reference voltage terminal by switching the predetermined high level and the predetermined low level, respectively. Control switching of non-conduction
At the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, it is faster for the first control signal to go to the predetermined low level than to the third control signal to go to the predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, it is faster for the second control signal to go to the predetermined low level than to the fourth control signal to go to the predetermined low level.
In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal goes to a predetermined high level earlier than the first control signal goes to a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, it is faster for the fourth control signal to go to a predetermined high level than to the second control signal to go to a predetermined high level,
The gate oxide thicknesses of the fifth and sixth MOS transistors are smaller than the gate oxide thicknesses of the first to fourth MOS transistors,
The timing control unit
A first timing control circuit that generates the first and third control signals;
A second timing control circuit that generates the second and fourth control signals;
The first timing control circuit is
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with the input signal;
A first resistance element provided between the seventh and eighth MOS transistors;
The second timing control circuit
Ninth and tenth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with inverted signals of the input signal;
A second resistance element provided between the ninth and tenth MOS transistors;
The first timing control circuit generates a voltage of a node between the seventh MOS transistor and the first resistance element as the third control signal, and a node between the eighth MOS transistor and the first resistance element Voltage as the first control signal,
The second timing control circuit generates a voltage of a node between the ninth MOS transistor and the second resistive element as the fourth control signal, and between the tenth MOS transistor and the second resistive element. Generating the voltage of the second node as the second control signal,
The gate oxide film thickness of the seventh to tenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors .
Les Berushifuta. The seventh and ninth MOS transistors are PMOS transistors, and the eighth and tenth MOS transistors are NMOS transistors.
The level shifter according to claim 2 . Each of the first and second resistance elements is a transfer gate formed of a PMOS transistor and an NMOS transistor having a gate oxide thickness thinner than the gate oxide thickness of the first to fourth MOS transistors.
The level shifter according to claim 2 . First and second MOS transistors provided in parallel between the first power supply voltage terminal and the reference voltage terminal, with their gates connected to each other's drain,
Third and fourth MOS transistors provided respectively between the first and second MOS transistors and the reference voltage terminal and having first and second control signals supplied to their respective gates;
Fifth and sixth MOS transistors respectively provided between the third and fourth MOS transistors and the reference voltage terminal, the third and fourth control signals being supplied to respective gates of the third and fourth MOS transistors;
Provided between a second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal is supplied, and the reference voltage terminal, corresponding to the inverted signal of the input signal A timing control unit that generates the first control signal and the third control signal, and generates the second control signal and the fourth control signal corresponding to a non-inverted signal of the input signal;
Equipped with
The first to fourth control signals are switched between the first MOS transistor and the reference voltage terminal and between the second MOS transistor and the reference voltage terminal by switching the predetermined high level and the predetermined low level, respectively. Control switching of non-conduction
At the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, it is faster for the first control signal to go to the predetermined low level than to the third control signal to go to the predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, it is faster for the second control signal to go to the predetermined low level than to the fourth control signal to go to the predetermined low level.
In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal goes to a predetermined high level earlier than the first control signal goes to a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, it is faster for the fourth control signal to go to a predetermined high level than to the second control signal to go to a predetermined high level,
The gate oxide thicknesses of the fifth and sixth MOS transistors are smaller than the gate oxide thicknesses of the first to fourth MOS transistors,
The timing control unit
A first timing control circuit that generates the first and third control signals;
A second timing control circuit that generates the second and fourth control signals;
The first timing control circuit is
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with the input signal;
And a ninth MOS transistor and a tenth MOS transistor provided in series between the second power supply voltage terminal and the reference voltage terminal, the gate being supplied with the input signal.
The second timing control circuit
Eleventh and twelfth MOS transistors, which are provided in series between the second power supply voltage terminal and the reference voltage terminal, and whose gates are supplied with inverted signals of the input signal.
And 13th and 14th MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with inverted signals of the input signal,
The drivability of the seventh MOS transistor is smaller than the drivability of the ninth MOS transistor, and the drivability of the eighth MOS transistor is larger than the drivability of the tenth MOS transistor.
The drivability of the eleventh MOS transistor is smaller than the drivability of the thirteenth MOS transistor, and the drivability of the twelfth MOS transistor is larger than the drivability of the fourteenth MOS transistor.
The first timing control circuit generates a voltage of a node between the seventh MOS transistor and the eighth MOS transistor as the first control signal, and a node between the ninth MOS transistor and the tenth MOS transistor Voltage as the third control signal,
The second timing control circuit generates a voltage of a node between the eleventh MOS transistor and the twelfth MOS transistor as the second control signal, and a node between the thirteenth MOS transistor and the fourteenth MOS transistor Voltage as the fourth control signal,
The gate oxide film thickness of the seventh to fourteenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors .
Les Berushifuta. The seventh, ninth, eleventh and thirteenth MOS transistors are PMOS transistors, and the eighth, tenth, twelfth and fourteenth MOS transistors are NMOS transistors.
The level shifter according to claim 5 . First and second MOS transistors provided in parallel between the first power supply voltage terminal and the reference voltage terminal, with their gates connected to each other's drain,
Third and fourth MOS transistors provided respectively between the first and second MOS transistors and the reference voltage terminal and having first and second control signals supplied to their respective gates;
Fifth and sixth MOS transistors respectively provided between the third and fourth MOS transistors and the reference voltage terminal, the third and fourth control signals being supplied to respective gates of the third and fourth MOS transistors;
Provided between a second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal is supplied, and the reference voltage terminal, corresponding to the inverted signal of the input signal A timing control unit that generates the first control signal and the third control signal, and generates the second control signal and the fourth control signal corresponding to a non-inverted signal of the input signal;
Equipped with
The first to fourth control signals are switched between the first MOS transistor and the reference voltage terminal and between the second MOS transistor and the reference voltage terminal by switching the predetermined high level and the predetermined low level, respectively. Control switching of non-conduction
At the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, it is faster for the first control signal to go to the predetermined low level than to the third control signal to go to the predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, it is faster for the second control signal to go to the predetermined low level than to the fourth control signal to go to the predetermined low level.
In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal goes to a predetermined high level earlier than the first control signal goes to a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, it is faster for the fourth control signal to go to a predetermined high level than to the second control signal to go to a predetermined high level,
The gate oxide thicknesses of the fifth and sixth MOS transistors are smaller than the gate oxide thicknesses of the first to fourth MOS transistors,
The timing control unit
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with the input signal;
A first resistance element provided between the seventh and eighth MOS transistors;
The timing control unit generates a voltage of a node between the seventh MOS transistor and the first resistive element as the third control signal, and a voltage of the node between the eighth MOS transistor and the first resistive element Is generated as the first control signal, an inverted signal of the third control signal is generated as the second control signal, and an inverted signal of the first control signal is generated as the fourth control signal,
The gate oxide film thickness of the seventh and eighth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors .
Les Berushifuta. The seventh MOS transistor is a PMOS transistor, and the eighth MOS transistor is an NMOS transistor.
The level shifter according to claim 7 . The first resistance element is a transfer gate formed of a PMOS transistor and an NMOS transistor having a gate oxide thickness thinner than the gate oxide thickness of the first to fourth MOS transistors.
The level shifter according to claim 7 . First and second MOS transistors provided in parallel between the first power supply voltage terminal and the reference voltage terminal, with their gates connected to each other's drain,
Third and fourth MOS transistors provided respectively between the first and second MOS transistors and the reference voltage terminal and having first and second control signals supplied to their respective gates;
Fifth and sixth MOS transistors respectively provided between the third and fourth MOS transistors and the reference voltage terminal, the third and fourth control signals being supplied to respective gates of the third and fourth MOS transistors;
Provided between a second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal is supplied, and the reference voltage terminal, corresponding to the inverted signal of the input signal A timing control unit that generates the first control signal and the third control signal, and generates the second control signal and the fourth control signal corresponding to a non-inverted signal of the input signal;
Equipped with
The first to fourth control signals are switched between the first MOS transistor and the reference voltage terminal and between the second MOS transistor and the reference voltage terminal by switching the predetermined high level and the predetermined low level, respectively. Control switching of non-conduction
At the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, it is faster for the first control signal to go to the predetermined low level than to the third control signal to go to the predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, it is faster for the second control signal to go to the predetermined low level than to the fourth control signal to go to the predetermined low level.
In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal goes to a predetermined high level earlier than the first control signal goes to a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, it is faster for the fourth control signal to go to a predetermined high level than to the second control signal to go to a predetermined high level,
The gate oxide thicknesses of the fifth and sixth MOS transistors are smaller than the gate oxide thicknesses of the first to fourth MOS transistors,
The timing control unit
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, the gates of which are supplied with the input signal;
And a ninth MOS transistor and a tenth MOS transistor provided in series between the second power supply voltage terminal and the reference voltage terminal, the gate being supplied with the input signal.
The drivability of the seventh MOS transistor is smaller than the drivability of the ninth MOS transistor, and the drivability of the eighth MOS transistor is larger than the drivability of the tenth MOS transistor.
The timing control unit generates a voltage of a node between the seventh MOS transistor and the eighth MOS transistor as the first control signal, and a voltage of the node between the ninth MOS transistor and the tenth MOS transistor is A third control signal is generated, an inverted signal of the first control signal is generated as the fourth control signal, and an inverted signal of the third control signal is generated as the second control signal.
The gate oxide film thickness of the seventh to tenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors .
Les Berushifuta. The seventh and ninth MOS transistors are PMOS transistors, and the eighth and tenth MOS transistors are NMOS transistors.
A level shifter according to claim 10 . The first and second MOS transistors are PMOS transistors, the third and fourth MOS transistors are depletion type NMOS transistors, and the fifth and sixth MOS transistors are NMOS transistors.
The level shifter as described in any one of Claims 1-11 .

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