JP6595827B2 - Imaging apparatus, imaging method, and control circuit - Google Patents

Description

  The present invention provides a CMOS type image pickup element having diagonal square lattice-like pixels in which flicker generated when imaging with a frame frequency of 120 Hz is reduced under illumination with an intensity change of 100 Hz in a power supply frequency range of 50 Hz. The present invention relates to an imaging apparatus, an imaging method, and an image frame readout control circuit used.

  In a power supply frequency range of 50 Hz, a lighting device such as a fluorescent lamp shows a change in illumination intensity according to 100 Hz which is a pulsation frequency after rectification. Under such illumination intensity, when imaging with an imaging frame frequency of 60 Hz is performed, flicker occurs because the frequency of illumination intensity change is not an integral multiple of the imaging frame frequency.

Therefore, as a countermeasure against such flicker, the electronic shutter period is set to (1/100) second (=
10 milliseconds) (see Patent Documents 1 to 3). This is based on the knowledge that no matter how the phase of the illumination intensity change and the phase of the electronic shutter are deviated, the amount of light incident during 10 milliseconds is kept constant, so that no flicker occurs.

By the way, in recent years, a CMOS type image pickup device has been announced for the purpose of mounting in a super high-definition system (Non-Patent Document 1), and in this document, pixels arranged in an oblique square lattice shape are used.
In recent years, the development of Super Hi-Vision has been activated, and the construction of countermeasures against the flicker is urgently needed. Therefore, if the above-described method can be used for the CMOS image sensor having the diagonal square-shaped pixels. The existing technology can be used efficiently.

JP-A-5-091373 JP-A-6-125495 JP 2000-299822 A

T. Toyama et al., “A 17.7Mpixel 120fps CMOS Image Sensor with 34.8Gb / s Readout,” ISSCC Digest of Technical Papers, pp. 420-422, 2011.

However, when imaging is performed with an imaging frame frequency of 120 Hz, which is a standard of Super Hi-Vision, under illumination with an illumination intensity change of 100 Hz, flicker of 20 Hz occurs. In this case, the imaging frame interval is (1/120) seconds = 8.3.
Since it is 33 milliseconds, when the electronic shutter period is set to 10 milliseconds, the electronic shutter period with respect to the imaging frame interval is set to 6/5, which is larger than 1, so that the execution of imaging itself becomes difficult. .

The present invention has been made in view of the above circumstances, and imaging was performed at an imaging frame frequency of 120 Hz when the illumination intensity change was 100 Hz even when the pixels were arranged in an oblique square lattice pattern. An object of the present invention is to provide an image pickup apparatus, an image pickup method, and an image frame readout control circuit capable of reducing flicker that sometimes occurs.

The imaging apparatus of the present invention
A photoelectric conversion unit that is formed corresponding to a plurality of pixels arranged in an oblique square lattice and generates a charge according to incident light;
A CMOS type image pickup having a row selection circuit unit that selects and drives an address of a Y row for the photoelectric conversion unit, and an image frame read control unit that includes a column parallel read circuit unit that reads a signal for each X column. A device,
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame reading control unit uses a non-progressive method, sets a divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and stores one charge accumulation time of each pixel in the photoelectric conversion unit. Is set to 10 milliseconds.

  Here, “the plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction” above and below. "The plurality of pixels are physically set to any one of 7680 pixels in the X direction, 4320 pixels in the Y direction, and 3840 pixels in the X direction and 2160 pixels in the Y direction". The number of pixels of the plurality of pixels is expanded to 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction by the signal processing of the signal processing unit. Shall be included.

  In addition, the latter includes a case where the pixel interpolation processing is performed using software or the like and is expanded to the respective numbers of pixels in the X and Y directions (for example, non-patent literature) 1).

  Further, here, the “diagonal square lattice shape” means that each of the two axes of the square pixel array intersecting on the element surface of the image sensor is inclined by 45 degrees from both the X direction and the Y direction. The square pixels are arranged in both directions. The same applies to the case of “diagonal square lattice” in the configuration described below.

  The “non-progressive method” refers to a so-called interlaced scanning method, which is different from a progressive method that is a method in which scanning is sequentially performed from one direction of the image sensor. A scanning method in which the scanning is interlaced scanning, such as a method of performing scanning by skipping a plurality of pixels for each pixel, is also included.

  Also, generally, in the “image frame”, a group of lines formed by interlaced scanning, for example, a frame consisting of only odd rows (odd frame: conceptually corresponding to the first field by NTSC) or even rows only. Frames (even frames: conceptually corresponding to the second field by NTSC), and not only between odd frames or even frames but also between odd frames and even frames may be referred to as image frame intervals. Many. However, if this is done in the present specification, it may be confused in the essential part of the invention, so the interval between odd frames or even frames is called an image frame interval, but the interval between odd frames and even frames. Is referred to as a divided image frame interval for convenience.

The image frame readout control unit is preferably configured to control so that one charge accumulation time of each pixel with respect to the image frame interval is 6/10.
The non-progressive method is preferably an interlace method.

  It is preferable that the photoelectric conversion unit is configured to share a pixel in a plurality of pixels arranged in an oblique square lattice pattern.

Moreover, the imaging method of the present invention includes:
For a pixel circuit provided corresponding to a plurality of pixels arranged in an oblique square lattice, photoelectric conversion is performed so that charges corresponding to light incident on the plurality of pixels are generated,
This is an imaging method using a CMOS type imaging device that reads out image frames in a predetermined order by designating a Y row address and an X column address for a plurality of pixels arranged in a diagonal square lattice. And
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
Image frame reading uses a non-progressive method, sets a divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and stores one charge of each pixel in the photoelectric conversion unit that performs the photoelectric conversion. The time is set to 10 milliseconds.

The image frame readout control circuit of the present invention is
A circuit that transmits an image frame read control signal to a photoelectric conversion unit that is formed corresponding to a plurality of pixels arranged in an oblique square lattice and generates a charge in response to incident light. Image frame reading including a row selection circuit unit for selecting an address to drive a pixel included in the Y row and a column parallel reading circuit unit for selecting an address in the X column and reading a signal from the pixel included in the X column In the image frame readout control circuit in the CMOS type imaging device provided with the control unit,
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout by the image frame readout control unit uses a non-progressive method, sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and sets each pixel in the photoelectric conversion unit. At least a storage start instruction signal and a storage end instruction signal corresponding to the plurality of pixels are transmitted from the image frame read control unit to the photoelectric conversion unit. The output is in order.

The imaging device of the present invention is configured such that effective pixels are output as either 7680 pixels and 4320 pixels or 3840 pixels and 2160 pixels in the X and Y directions,
Drive by non-progressive method such as interlace method, frame frequency is 120Hz, electronic shutter period is set to 10ms, image frame interval between odd frames or even frames is 16.667ms, odd frames The signal readout is performed with the interval between the divided image frames of the even frames being 8.333 milliseconds, and the accumulation time of each pixel is 10 milliseconds.

  That is, when imaging is performed with an imaging frame frequency of 120 Hz, which is a standard of Super Hi-Vision, under illumination with an illumination intensity change of 100 Hz, flicker of 20 Hz occurs. To prevent this, when the electronic shutter speed is set to 10 milliseconds, the imaging frame interval (divided image frame interval) is (1/120) seconds = 8.333 milliseconds. Since the electronic shutter period with respect to (image frame interval) is set to 6/5, which is larger than 1, it becomes difficult to perform imaging.

However, in the present invention, even if the electronic shutter speed is 10 milliseconds and the imaging frame interval is (1/120) seconds = 8.333 milliseconds, a non-progressive method such as an interlace method is employed as the scanning method. Therefore, the electronic shutter period with respect to the imaging frame interval (image frame interval (interval of divided image frame interval: interval between odd frames or even frames)) is set to a value smaller than 1 (6 / in the case of the interlace method). 10), even if the pixels are arranged in an oblique square lattice, the occurrence of flicker that occurs when imaging at 120 Hz is performed under a change in illumination intensity of 100 Hz with a power supply frequency of 50 Hz. Can be blocked.

FIG. 5 is an equivalent circuit diagram of a pixel circuit of the 4-pixel sharing type according to the first and second embodiments of the present invention and using 1.75 transistors per pixel. FIG. 2 is a block diagram showing an imaging apparatus including a pixel array having the pixel circuit shown in FIG. 1 in an oblique square lattice shape and an image frame readout control circuit. FIG. 3 is a diagonal square pixel arrangement diagram illustrating an example of pixel arrangement according to the first embodiment of the present invention. FIG. 4 is a time chart of an input signal to the pixel circuit when signal readout is performed using the first embodiment of the pixel arrangement shown in FIG. 3. FIG. It is the schematic which shows the odd-numbered line (solid line) and the even-numbered line (broken line) at the time of performing signal read-out using an interlace system in an image sensor. It is a time chart which shows an example of illumination intensity change of 100 Hz. It is a time chart which shows the time-sequential relationship of the image | video from the odd-numbered line and the even-numbered line of 120Hz interlace scanning. It is a diagonal square-like pixel arrangement | positioning figure which shows the pixel arrangement example which concerns on the 2nd Embodiment of this invention. 10 is a time chart of an input signal to a pixel circuit when signal readout is performed using the second embodiment of the pixel arrangement shown in FIG. 8. FIG. 10 is a circuit diagram showing an equivalent circuit of a pixel circuit using four transistors per pixel according to a third embodiment of the present invention. It is a diagonal square-like pixel arrangement | positioning figure which shows the pixel arrangement example which concerns on the 3rd Embodiment of this invention. 11 is a time chart of an input signal to a pixel circuit when signal readout is performed using the third embodiment shown in FIG. 10. FIG. 10 is a circuit diagram showing an equivalent circuit of a pixel circuit of a two-pixel sharing type according to a fourth embodiment of the present invention and using 2.5 transistors per pixel. It is a diagonal square-like pixel arrangement | positioning figure which shows the pixel arrangement example which concerns on the 4th Embodiment of this invention. FIG. 14 is a time chart of an input signal to the pixel circuit when signal readout is performed using the fourth embodiment shown in FIG. 13. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, an equivalent circuit diagram of a pixel circuit using four transistors per pixel used in the CMOS type imaging device according to the first embodiment will be described with reference to FIG. Note that the pixel circuit 100 shown in this equivalent circuit diagram is provided corresponding to each pixel (or each pixel group) of the pixel array of the CMOS imaging device (not limited to one-to-one correspondence).

As shown in FIG. 1, the pixel circuit 100 includes four photodiodes (PD) 111A.
To D, four charge transfer transistors (TX) 112A to D, a floating diffusion capacitor (FD) 113,
It comprises a reset transistor (RST) 114, a source follower amplifier (amplification transistor: SF) 115, a selection transistor (SEL) 116, a pixel power supply unit (VDD) 117, and a pixel output unit (OUT) 118.

The pixel circuit 100 includes a pixel array 201 that is arranged in a large number of diagonal square lattices inclined by 45 degrees from the X direction (row direction) and the Y direction (column direction).
As shown in FIG. 2, the pixel array constitutes an imaging device (image sensor) 200 together with a Y direction scanning unit 202, an X direction scanning unit 203, a timing generator 204, and an output circuit 205. In the imaging apparatus 200, the Y-direction scanning unit 202, the X-direction scanning unit 203, the timing generator 204, and the output circuit 205 constitute an image frame readout control circuit according to the present invention.

In each pixel circuit 100, the PDs 111A to 111D accumulate negative charges in an amount corresponding to the intensity of incident light. The anodes of the PDs 111A to 111D are grounded, and the cathodes are connected to the gate of the SF 115 via the TXs 112A to 112D. The gate of TX112A~D is connected to the signal line _{L T} from Y direction scanning unit 202, the transfer signal.

SF 115 and SEL 116 are connected in series between VDD 117 and output unit 118. The gate of SEL116 is connected to the signal line _{L S} from the Y-direction scanning unit 202, a selection signal is input. The RST 114 is connected between the VDD 117 and the gate of the SF 115. The gate of the RST114 is connected to the signal line _{L R} from the Y direction scanning unit 202, is inputted to the reset signal.
The FD 113 is connected to the gate of the SF 115.

  In order to reset the PDs 111A-D, the TXs 112A-D and the RST 114 are turned on while the SEL 116 is off. As a result, the negative charges accumulated in the PDs 111A to 111D are released to the VDD 117 via the TXs 112A to D and the RST 114, and the reset operation is completed.

  Charge accumulation due to incident light starts from the end of the reset operation of the PDs 111A to 111D. That is, when the transfer signal and the reset signal are in the “L” state and the TXs 112A to D and the RST 114 are turned off, an amount of charge corresponding to the intensity of the incident light is accumulated in the PDs 111A to D, and the charge accumulation time starts.

  On the other hand, the accumulation time is terminated as follows. That is, first, the FD 113 is reset by setting the selection signal to the “H” level to turn on the SEL 116 and setting the reset signal to the “H” level for a predetermined time to turn on the RST 114. Next, by setting the transfer signal to the “H” level state for a predetermined time to turn on the TXs 112A to D, the accumulated charges in the PDs 111A to 111D are transferred to the FD 113, and when the TXs 112A to D are turned off, the PDs 111A to The D accumulation time ends.

2 sends a row selection address signal and a drive control signal to the Y-direction scanning unit 202, and sends a column selection address signal and a read control signal to the X-direction scanning unit 203. The Y-direction scanning unit 202 has a function of a Y-direction scanning circuit and a voltage level shift circuit, and sequentially selects a predetermined plurality of rows of the pixel array 201 in accordance with the input row selection address signal and drive control signal. Then, a transfer signal, a reset signal, and a selection signal are sent to each pixel circuit 100 of the row through the signal lines L _T , L _R , and L _S of the selected row.

The X direction scanning unit 203 has functions of an X direction scanning circuit and a column circuit, and a plurality of Y direction signal lines L from a plurality of pixel circuits 100 in a predetermined row selected by the Y direction scanning unit 202. _The current output to _V is converted into a plurality of predetermined signals.
Further, the output circuit 205 outputs a plurality of pixel signals generated by the X-direction scanning unit 203 to the outside.

FIG. 3 shows a pixel arrangement and a pixel group arrangement relationship according to the first embodiment. That is, in the first embodiment, four pixels corresponding to each of the TX transistors 112A to 112D are pixel-shared, and these TX transistors 112A.
~ D corresponding to four pixels (1.1, 1.2, 1.3, 1.4 (pixel group 1)) or (2.1, 2.2, 2.3, 2.4 (pixel group) 2)) are arranged in a crank shape.

Note that each pixel in the diagonal square shape shown in FIG. 3 has a first axis that is a pixel arrangement axis from the upper left to the lower right, and a second axis that is a pixel arrangement axis from the upper right to the lower left. So that these two axes are at right angles to each other and form an angle of 45 ° with the X axis (axis extending in the horizontal direction in FIG. 3) and the Y axis (axis extending in the vertical direction in FIG. 3). Arranged.
According to such a pixel arrangement according to the first embodiment, when a moving body that moves at high speed is imaged, it is possible to read an image with less jagged edges in the image edge portion.

  FIG. 4 is a time chart showing an input signal of each transistor when signal readout is performed using the pixel circuit 100 shown in FIG. In the present embodiment (and the second embodiment below), the image frame rate is 120 Hz, and non-progressive scanning such as interlace scanning is employed.

  In FIG. 4, each graph shows the signal waveforms of SEL 116, RST 114, and TX 112, and the numbers in parentheses after the SEL, RST, and TX indicate the corresponding pixels in FIG. The accumulation time of each corresponding pixel is indicated by a black belt. In the first embodiment, n is set to 4320/4 = 1080.

In this pixel circuit 100, first, in order to reset the PD 111A for the (1.1) th pixel, the SEL 116 is turned off (SEL (1.x) is at “L” level), and the RST 114 and the TX 112A are simultaneously turned on. State (RST (1.x) and TX (1.1) are “H”
At the same time, the state is turned off (RST (1.x) and TX (1.1) are at “L” level) (see arrow A in FIG. 4). As a result, the signal charges of the PD 111A and the FD 113 are discharged to the VDD 117 via the TX 112A and the RST 114, and the reset process of the PD 111A is completed. Immediately after this, the accumulation time of the PD 111A is started.

  In addition, after the accumulation time is started, the SEL 116 is turned on (SEL (1.x) is at “H” level) (see arrow B in FIG. 4), so that the pixel is selected. Further, when the RST 114 is turned on (RST (1.x) is “H” level), the FD 113 is reset, and when the RST 114 is turned off (RST (1.x) is “L” level), A value (reset potential) in a state where electric charges are released is read out.

Next, when TX 112A is turned on (TX (1.1) is “H” level) after RST 114 is turned off (RST (1.1) is “L” level) during the accumulation time, PD1
When the signal charge stored in 11A moves to FD 113 and TX 112A is turned off (TX (1.1) is at “L” level), the potential at this time is read (SEL in FIG. 4). (1.x), RST (1.x), TX (1.1), accumulation time (1.1) time chart: see arrow C). At this time, the accumulation time of the PD 111A ends. In this way, the time from when the pixel is selected until the TX 112A is turned off after the RST 114 is turned off is one accumulation time of each pixel. The accumulation time is, for example, (1/10
0) seconds (= 10 milliseconds).

  After this, the (1.1) th odd-numbered row (1.3) th, (2.1) th, (2.3) th, (n.1) th, (n.3) The same operation is sequentially performed for the second pixel.

  On the other hand, for the (1.2) th signal, the same signal reading process as the (1.1) th process is performed (SEL (1.x), RST (1.x), TX ( 1.2) and the accumulation time (1.2) time chart), the (1.2) th overall signal reading is completed. Thereafter, the signal reading processing of other even-numbered rows such as (1.4) th, (2.2) th, (2.4) th,... (N.2) th, (n.4) th, etc. Are sequentially performed in the same manner.

  That is, in the imaging apparatus according to the present embodiment, the reading operation is performed by interlace scanning. First, the (1.1) th, (1.3) th,... (N.1) th, (n.3) ) Are sequentially selected to read out signals, read out signals in all odd rows, and output image signals recorded in the odd rows. Subsequently, the (1.2) th, (1.4) th,... (N.2) th, (n.4) th are sequentially selected to read the signals of all even rows, and are recorded in the even rows. Output the image signal.

Note that the time interval (divided image frame interval) between frames composed of odd rows (odd frames) and frames composed of even rows (even frames) is set to (1/120) seconds = 8.333 milliseconds. The time interval (image frame interval) between frames composed of odd rows (odd frames) and frames composed of even rows (even frames) is (1/60) seconds = 16.
. Set to 667 milliseconds.

  Further, the interval between the (1.1) th and (1.2) th divided image frames is 8.333 milliseconds as described above, and when one is accumulating charges, the other reads out a signal. It is configured. The same applies to the (1.3) th and (1.4) th relationships and the (n.1) th and (n.2) th relationships. In addition, the accumulation time of the odd-numbered row and the subsequent even-numbered row is set to partially overlap each other, while setting each accumulation time to 10 milliseconds, This is because the interval (image frame interval) is set to 16.667 milliseconds (60 Hz).

Hereinafter, the switching timing in the first embodiment will be described with reference to FIG.
As described above, in this embodiment, pixel readout scanning of the pixel array 201 is performed using the interlace method. That is, as shown in FIG. 5, for all the rows of the pixel array 201, only an odd-numbered row (represented by a solid line in FIG. 5) pixel readout operation and an even-numbered row (represented by a broken line in FIG. 5) The operations for performing the pixel readout are alternately performed. This interlace method is used in the NTSC method and is also called interlaced scanning.

  According to the first embodiment, as shown in FIG. 6 and FIG. 7, an image sensor (imaging device) can be obtained by adopting an interlace method when an illumination device or the like adopts an illumination intensity of 100 Hz (power frequency is within 50 Hz). ) One pixel charge accumulation time of 200 pixels (photodiodes) is set to 10 milliseconds, and the imaging frame frequency is set to 120 Hz to prevent the occurrence of flicker while conforming to Super Hi-Vision.

  That is, when the electronic shutter speed is set to 10 milliseconds in order to prevent the occurrence of flicker, the imaging frame interval (division image frame interval) is (1/120) seconds = 8.333 milliseconds. The electronic shutter period with respect to the imaging frame interval is set to 6/5, which is larger than 1.

Therefore, in this embodiment, even if the electronic shutter speed is 10 milliseconds and the divided image frame interval is (1/120) seconds = 8.333 milliseconds, the interlace method is adopted, Since the electronic shutter period for the interval (odd frames or even frames) can be set to a value smaller than 1 (6/10 because the interlace method is adopted in this embodiment), the power supply frequency is 50 Hz and 100 Hz. It is possible to prevent the occurrence of flicker when imaging at 120 Hz under a change in illumination intensity.

<Second Embodiment>
In the second embodiment, since there are many portions that overlap with the first embodiment, such portions will be briefly described as appropriate. In particular, the circuit configuration shown in FIG. 1, the device configuration based on FIG. 2, and the basic principles shown in FIGS.

In the second embodiment, as shown in FIG. 8, four pixels corresponding to each of the TX transistors 112A to 112D (see FIG. 1) are shared, and these four pixels (1 .1, 1.2, 1.3, 1.4 (pixel group 1)), (2.1, 2.2, 2.3, 2.4 (pixel group 2)), (3.1, 3 .2, 3.3, 3.4 (pixel group 3)) and (4.1, 4.2, 4.3, 4.4 (pixel group 4)) each construct a diagonal square block. Is arranged.
According to the pixel arrangement according to the second embodiment as described above, the layout design of the pixel array becomes extremely easy because the block is a diagonal square block grouped for each pixel group.

FIG. 9 is a time chart showing the input signal of each transistor when signal readout is performed using the pixel circuit shown in FIG. 1 and the pixel arrangement shown in FIG. In each graph, the number in parentheses indicates the number of pixels in the arrangement. For example, SEL (1.x, 2.x) and RST (1.x, 2.x) are described as the (1.x) th and (2.x) th four pixels share pixels Indicates that TX represented as TX (1.1, 2.1) indicates the (1.1) th and (2.1) th pixel arrangement. The accumulation time (1.1, 2.1) indicates the accumulation time of the (1.1) th and (2.1) th PD 111A. The accumulation time for each row is indicated by a black belt.

  In the second embodiment, n is set to 4320/2.

  In this pixel arrangement, the same drive waveform is given to the (1.x) th and (2.x) th, the same drive waveform is given to the (3.x) th and (4.x) th, and (n-1. The same drive waveform is given to the (x) th and (nx) th. Reading is performed in parallel in the X-axis direction, and the same output wiring is connected to the (1.x) th, (3.x) th, (n−1.x) th, (2.x) th, (4. x) Connect the same output wiring to the (n.x) th. Thus, (1.x) th and (2.x) th, (3.x) th and (4.x) th, (n−1.x) th and (nx) th are simultaneously performed, and , (1.x) th, (3.x) th, (n−1.x) th, (2.x) th, (4.x) th, (nx) th Read sequentially. In the column-parallel reading lined up in the X-axis direction, column-parallel reading circuits may be arranged in opposite directions between adjacent columns.

9 will be described in comparison with FIG. 4 showing a time chart of the input signal of the first embodiment. In both these two embodiments, four pixels are shared, but differ in the pixel arrangement as shown in FIGS.
That is, in the first embodiment, the four shared pixels are arranged in a crank shape as shown in FIG. 3, whereas in the second embodiment, the four shared pixels are As shown in FIG. 8, they are arranged so as to form diagonal square blocks.
Thus, in the second embodiment, a drive waveform is given as shown in SEL (1.x, 2.x), RST (1.x, 2.x), TX (1.1, 2.1). The position of the pixel is different from that in the first embodiment.

As described above, in the imaging apparatus according to the second embodiment, first, (1.1) (2.1) th, (1.3) (2.3) th,. 1) (n.1) th, (n-1.3) (n.3) th are sequentially selected to read out signals, read out signals in all odd rows, and output image signals recorded in odd rows. . Subsequently, (1.2) (2.2) th, (1.4) (2.4) th,..., (N-1.2) (n.2) th, (n-1.4) ) The (n.4) th is sequentially selected to read all even rows of signals and output the image signals recorded in the even rows. Note that the time interval (divided image frame interval) between frames composed of odd rows (odd frames) and frames composed of even rows (even frames) is set to (1/120) seconds = 8.333 milliseconds.

  Thereby, in the second embodiment, it is possible to prevent the occurrence of flicker when imaging at 120 Hz under a change in illumination intensity of 100 Hz in the power supply frequency range of 50 Hz.

<Third Embodiment>
Note that in this embodiment and the fourth embodiment described below, there are many portions that overlap with the first embodiment, and therefore, such portions will be briefly described as appropriate. In particular, the apparatus configuration based on FIG. 2 and the basic principle according to FIGS.

  A main configuration of the pixel circuit in the imaging apparatus according to the third embodiment will be described with reference to FIG. 10 which is an equivalent circuit diagram of a pixel circuit using four transistors per pixel.

10, the functions of the signal lines L _T , L _R , and L _S from the Y-direction scanning unit 202 (see FIG. 2) connected to the gates of the transistors TX312, RST314, and SEL316 will be described with reference to FIG. Since the functions are the same as those described above, only the corresponding reference numerals are given in the drawings, and a detailed description thereof is omitted (the fourth embodiment described below is also omitted in the same manner).

  As shown in FIG. 10, the pixel circuit 300 includes a photodiode (PD) 311, a charge transfer transistor (TX) 312, a floating diffusion capacitor (FD) 313, a reset transistor (RST) 314, and a source follower amplifier (SF) 315. , A selection transistor (SEL) 316, a pixel power supply unit (VDD) 317, and a pixel output unit (OUT) 318.

  One PD 311 and one TX 312 are provided, and one FD 313, RST 314, SF 315, SEL 316, VDD 317, and OUT 318 are also provided. That is, four transistors are formed per pixel, and the number of transistors per pixel is 2.25 more than that in the first and second embodiments.

  FIG. 11 shows a pixel arrangement according to the third embodiment. That is, in the third embodiment, pixels corresponding to the TX transistors 312 are driven, and the pixels 1, 2,... Corresponding to the TX transistors 312 are arranged in an oblique square lattice shape. Has been.

In addition, each diagonal square-shaped pixel shown in FIG. 11 has a first axis that is a pixel arrangement axis from the upper left to the lower right, and a second axis that is a pixel arrangement axis from the upper right to the lower left. These two axes are orthogonal to each other, and the X-axis (axis extending in the lateral direction (not shown) in FIG. 11) and the Y-axis (axis extending in the vertical direction in FIG. 11 (not shown) )) And an angle of 45 °.
According to the third embodiment configured as described above, since the electronic shutter period with respect to the imaging frame interval can be set to a value smaller than 1, imaging at 120 Hz under a change in illumination intensity of 100 Hz with a power frequency of 50 Hz. It is possible to prevent the occurrence of flicker that occurs when performing.

  FIG. 12 is a time chart showing an input signal of a transistor when signal readout is performed using the pixel circuit 300 shown in FIG. In each graph, the numbers in parentheses indicate the number of rows, and are described as, for example, SEL (1) ... SEL (n), RST (1) ... RST (n). Indicates that it is the first row ... n-th row, while TX312 represented as TX (1) ... TX (n) is the first row-n-th row without pixel sharing. Further, accumulation time (1) to accumulation time (n) indicate the accumulation time of the first row to the n-th row of the PD 311.

  The accumulation time for each row is indicated by a black belt. In this embodiment, n is set to 4320 (row).

In this pixel circuit 300, first, in order to reset the PD 311 for the pixels in the first row (odd row), the SEL 316 is in an off state (SEL (1) is “L” level), and the RST 314 and the TX 312 are simultaneously in an on state. (RST (1) and TX (1) are at “H” level), and then simultaneously off (RST (1) and TX (1) are at “L” level) (see arrow A in FIG. 12). . As a result, the signal charges of the PD 311 and the FD 313 are released to the VDD 317 via the TX 312 and the RST 314, and the reset process of the PD 311 is completed.
Immediately after this, the accumulation time of the PD 311 starts.

  In addition, after the accumulation time is started, the SEL 316 is turned on (SEL (1) is at “H” level) (see arrow B in FIG. 12), and the pixel is selected. When RST 314 is turned on (RST (1) is at “H” level), FD 313 is reset, and a value (reset potential) in a state where a predetermined amount of charge of FD 313 is released is read.

Next, when the TX 312 is turned on (TX (1) is “H” level) after the RST 314 is turned off (RST (1) is “L” level) during the accumulation time, the signal accumulated in the PD 311 is stored. When the charge moves to the FD 313 and the TX 312 is turned off (TX (1) is at “L” level), the potential at this time is read (SEL (1), RST (1), TX in FIG. 12). (1) Time chart of accumulation time (1): See particularly arrow C). At this time, the accumulation time of the PD 311 ends. Thus, the time from when the pixel is selected until the TX 312 is turned off after the RST 314 is turned off is one accumulation time of each pixel. This accumulation time is set to, for example, (1/100) second (= 10 milliseconds).

  Thereafter, the signal readout process is performed in the same manner for the other pixels in the first row. Further, the same processing is performed in the same manner for the pixels in other odd-numbered rows (first row, third row,..., N−1 row).

  On the other hand, for the second row, the same signal read-out processing as the above-mentioned processing of the first row is performed (time of SEL (2), RST (2), TX (2) and accumulation time (2) in FIG. The signal reading of the entire second row is completed. Thereafter, the signal reading processing of other even lines such as the fourth line,... N line is sequentially performed in the same manner.

  That is, in the imaging apparatus according to the present embodiment, the reading operation is performed by interlaced scanning. First, the first row, the third row,. Are read out, and the image signal recorded in the odd-numbered rows is output. Subsequently, the second row, the fourth row,..., The n-th row are sequentially selected to read all even rows of signals, and the image signals recorded in the even rows are output.

<Fourth Embodiment>
An equivalent circuit diagram of a pixel circuit in an imaging apparatus according to the fourth embodiment will be described with reference to FIG. That is, this pixel circuit is a two-pixel shared type and uses 2.5 transistors per pixel. Note that the pixel circuit shown in this equivalent circuit diagram is provided corresponding to two pixels arranged in parallel in the column direction (the direction from the upper left to the lower right). It may be provided corresponding to two pixels arranged in parallel in the column direction (direction from upper right to lower left).

In FIG. 13, the functions of the signal lines L _T , L _R , and L _S from the Y-direction scanning unit 202 connected to the gates of the respective transistors TX412A, B, RST 414, and SEL 416 are the same as those described in FIG. Since these are the same, only the corresponding reference numerals are given in the drawings, and detailed description thereof is omitted (the same is true for the embodiments and modified examples described below).

  As described above, the pixel circuit 400 is a two-pixel shared type, and includes two photodiodes (PD) 411A and B, two charge transfer transistors (TX) 412A and B, a floating diffusion capacitor (FD) 413, The pixel includes a reset transistor (RST) 414, a source follower amplifier (SF) 415, a selection transistor (SEL) 416, a pixel power supply unit (VDD) 417, and a pixel output unit (OUT) 418.

PD 411A, B and TX 412A, B are provided side by side, and FD 413, RST 414, SF 415, SEL 416, VDD 417, and OUT 418 are configured to share two pixels. That is, since the two pixels are composed of five transistors, it can be composed of 2.5 transistors per pixel.
There are 0.75 more transistors per pixel than in the second embodiment.

In the fourth embodiment, two pixels corresponding to the two TX transistors 412A and 4B are shared by two pixels. As shown in FIG. , 1.2 (pixel group 1)), (2.1, 2.2 (pixel group 2)), (3.1, 3.2 (pixel group 3)) and (4.1, 4.2 ( The pixel groups 4)) are arranged so as to construct a diagonal rectangular block.
According to the pixel arrangement according to the fourth embodiment as described above, the layout of the pixel arrangement is facilitated because the block is a diagonal rectangular block grouped for each pixel group.

FIG. 15 is a time chart showing the input signal of each transistor when signal readout is performed using the pixel circuit 400 shown in FIG. In each graph, the numbers in parentheses indicate the number of lines. For example, the accumulation time (1.1) indicates the accumulation time of the PD 411A, and the accumulation time (1.2) indicates the accumulation time of the PD 411B.
Note that x in () represents both cases 1 and 2.

  The accumulation time for each row is indicated by a black belt. In this embodiment, n is set to 4320/2 = 2160 (row).

In the pixel circuit 400, first, in order to reset the PD 411A, the RST 414 and the TX 412A are simultaneously turned on (RST (1.x) when the SEL 416 is in the off state (SEL (1.x) is at the “L” level). x) and TX (1.1) are “H” level)
After that, it is simultaneously turned off (RST (1.x) and TX (1.1) are “L” level). Thereby, charge accumulation is started in the PD 411A from the end of the reset (see arrow A in FIG. 15).

Next, in order to reset the PD 411B, the SEL 416 is turned off (SEL (2.x
) Is at “L” level), RST 414 and TX 412 B are simultaneously turned on (
RST (2.x) and TX (2.1) are set to “H” level, and thereafter, the OFF state is simultaneously set (RST (2.x) and TX (2.1) are set to “L” level). . As a result, charge accumulation is started in the PD 411B from the end of the reset (see arrow A ′ in FIG. 15).

Further, when the SEL 416 is turned on (SEL (1.x) is “H” level), the pixel is selected (see an arrow B in the drawing), and the RST 414 is turned on (RST (1.x)). FD 413 is reset when RST 414 becomes “H” level, and TX 412A is turned on (TX (1.1) after RST 414 is turned off (RST (1.x) is “L” level)).
Charge goes to FD 413 and voltage is read, and when TX 412A is in the off state (TX (1.1) is at "L" level), the loading time of PD 411A ends (in the figure) See arrow C). This accumulation time is (1/100) second (=
10 milliseconds).

Further, when the SEL 416 is turned on (SEL (1.x) is “H” level), the pixel is selected (see the arrow B ′ in the drawing), and the RST 414 is turned on (RST (1.x). ) Is set to “H” level), FD 413 is reset, and TX 412B is turned on (TX (1.2 (x)) after RST 414 is turned off (RST (1.x) is set to “L” level).
) Becomes “H” level), the charge moves to the FD 413 and the voltage is read out.
Is turned off (TX (1.2) is at “L” level), the stocking time of PD 411B ends (see arrow C ′ in the figure). This accumulation time is set to (1/100) seconds (= 10 milliseconds) as in the first embodiment.

As described above, in the imaging apparatus according to the present embodiment, the reading operation is performed by interlace scanning. First, the (1.1) line, the (2.1) line,..., (N.1) The rows are sequentially selected to read out signals, read out signals from all odd rows, and output image signals recorded in the odd rows. Subsequently, the (1.2) line, (2.2) line,..., (N.2) line are sequentially selected to read out the signals of all even lines, and the image signals recorded in the even lines Is output. Note that the time interval (divided image frame interval) between frames composed of odd rows (odd frames) and frames composed of even rows (even frames) is set to (1/120) seconds = 8.333 milliseconds.

  As a result, in the present embodiment, it is possible to prevent the occurrence of flicker when imaging at 120 Hz under a change in illumination intensity of 100 Hz in the power supply frequency range of 50 Hz.

  Furthermore, the imaging apparatus, imaging method, and image frame readout control circuit of the present invention are not limited to those in the above-described embodiments, and various other aspects can be adopted. For example, in the above-described embodiment, examples of a shared type element include a two-pixel shared type element shared by two pixels and a four-pixel shared type element shared by four pixels. Other than the above, signal readout can be performed using an element shared by a plurality of pixels.

  In the above embodiment, the plurality of pixels constituting the imaging device are physically set to either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction. However, instead of this, pixel interpolation processing is performed on a plurality of pixels using hardware or software, and 7680 pixels in the X direction and 4320 pixels in the Y direction, or in the X direction. Even if the number of pixels is expanded (increased) so that the number of pixels is 3840 pixels and any of 2160 pixels in the Y direction, the same effect as in the above embodiment can be obtained.

  In the above-described embodiment, the image frame interval is 1/120 seconds = 8.333 milliseconds. Alternatively, 1/120 seconds × 1001/1000 = 8.342 milliseconds may be used instead. The same effects as those of the embodiment can be obtained. Moreover, in the said embodiment, although the frame frequency is 120 Hz, it can replace with this and can show an effect substantially the same as the thing of the said embodiment also by setting it as 120 * 1000/1001 = 119.88Hz.

  Furthermore, it is possible to mount a global shutter function (global shutter transistor), in which case the shutter operation can be performed simultaneously for all pixels (actually, odd frame pixels and even frame pixels simultaneously). All pixels can be read simultaneously. As a result, image distortion can be reduced particularly for a subject that moves at high speed.

100, 300, 400 Pixel circuits 111A-D, 311, 411A, B Photodiode (PD)
112A to D, 312, 412A, B Charge transfer transistor (TX)
113, 313, 413 Floating diffusion capacitance (FD)
114, 314, 414 Reset transistor (RST)
115, 315, 415 Source follower amplifier (SF)
116, 316, 416 Select transistor (SEL)
117, 317, 417 Pixel power supply (VDD)
118, 318, 418 Pixel output section (OUT)
DESCRIPTION OF SYMBOLS 200 Imaging device 201 Pixel array 202 Y direction scanning part 203 X direction scanning part 204 Timing generator 205 Output circuit

Claims (5)

A photoelectric conversion unit that is formed corresponding to a plurality of pixels arranged in an oblique square lattice and generates a charge according to incident light;
A CMOS type image pickup having a row selection circuit unit that selects and drives an address of a Y row for the photoelectric conversion unit, and an image frame read control unit that includes a column parallel read circuit unit that reads a signal for each X column. A device,
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout control unit uses a non-progressive method, sets a divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and stores one charge in each pixel in the photoelectric conversion unit. An imaging apparatus characterized in that the time is set to 10 milliseconds.   2. The image frame readout control unit is configured to control so that a charge accumulation time of each pixel is 6/10 with respect to a readout period of each image frame. Imaging device.   The imaging apparatus according to claim 1, wherein the non-progressive method is an interlace method. For a pixel circuit provided corresponding to a plurality of pixels arranged in an oblique square lattice, photoelectric conversion is performed so that charges corresponding to light incident on the plurality of pixels are generated,
This is an imaging method using a CMOS type imaging device that reads out image frames in a predetermined order by designating a Y row address and an X column address for a plurality of pixels arranged in a diagonal square lattice. And
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
Image frame reading uses a non-progressive method, sets a divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and stores one charge of each pixel in the photoelectric conversion unit that performs the photoelectric conversion. An imaging method, wherein the time is set to 10 milliseconds. A circuit that transmits an image frame read control signal to a photoelectric conversion unit that is formed corresponding to a plurality of pixels arranged in an oblique square lattice and generates charges according to incident light,
A row selection circuit unit that selects an address of the Y row and drives a pixel included in the Y row; and a column parallel readout circuit unit that selects an address of the X column and reads a signal from the pixel included in the X column In an image frame readout control circuit in a CMOS type imaging device provided with an image frame readout control unit,
The plurality of pixels are configured to be output as either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout operation by the image frame readout control unit uses a non-progressive method, sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, At least an accumulation start instruction signal and an accumulation end instruction signal corresponding to the plurality of pixels are directed from the image frame read control unit to the photoelectric conversion unit so that one charge accumulation time of the pixel can be set to 10 milliseconds. And outputting the image frame in a predetermined order.