JP6568461B2 - Nonvolatile semiconductor memory storage device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory storage device that prevents leakage of stored data after disposal.

  An SSD (Solid State Disk) device composed of a flash memory or the like has been increased in capacity so as to follow the hard disk device. Since the flash memory is a non-volatile semiconductor memory, the leakage of stored data after the SSD device is discarded as in the hard disk device becomes a problem. In the case of an SSD device, the erasure time of stored data is not as long as in the case of a hard disk device, but as the storage capacity increases, the need for means for easily destroying stored data in a shorter time is increasing.

  Patent Document 1 discloses an example of an IC card that ensures the security of information stored in a flash memory. According to the description of FIG. 1 and the like of Patent Document 1, the microcomputer 2 mounted on the IC card 1A includes the booster circuit 11 that boosts the power supply voltage VDD in the internal power supply circuit 10, and the booster circuit 11 has an element breakdown voltage. Generate a VPP. The CPU 8 of the microcomputer 2 inputs an authentication error signal to the power supply circuit 10 when determining that an illegal attack has been repeatedly performed from the outside. Upon receiving the authentication error signal, the power supply circuit 10 supplies at least the element breakdown voltage VPP to the RAM 3 and the flash memory 7 instead of the normal power supply voltage VDD. Since the circuit elements constituting the RAM 3 and the flash memory 7 are destroyed by the supply of the element breakdown voltage VPP, security regarding leakage of information (data and program) stored in the IC card 1A is ensured.

JP 2010-140129 A

  However, the technique disclosed in Patent Document 1 is basically a technique applied to an internal circuit of one integrated circuit chip such as a one-chip microcomputer. Therefore, when this technology is applied to a nonvolatile semiconductor memory storage device mounted on a printed circuit board such as an SSD device composed of a plurality of integrated circuit chips, several problems arise. Incidentally, a plurality of flash memory chips and one microcomputer chip, that is, a plurality of integrated circuit chips are usually mounted on a printed circuit board constituting the SSD device.

  When the technique of Patent Document 1 is applied to a printed circuit board on which a plurality of integrated circuit chips are mounted, the current to be supplied from the necessity of supplying the element breakdown voltage VPP to the power supply terminals of the plurality of flash memory chips. The amount increases. Therefore, there arises a problem that the booster circuit for generating the element breakdown voltage VPP becomes large, that is, the number of circuits to be added increases.

  Further, when the element breakdown voltage VPP is simply supplied to the power supply wiring of the power supply voltage VDD, the power supply wiring is connected not only to the flash memory chip but also to the microcomputer chip, so that the circuit elements constituting the microcomputer chip are also elements. It is destroyed by the breakdown voltage VPP. Therefore, the information reading function in the SSD device is also lost.

  The loss of the information reading function in the SSD device means that the means for confirming whether or not the information stored in the flash memory chip has been reliably destroyed by supplying the element breakdown voltage VPP is lost. means. Therefore, the user cannot confirm whether or not the information stored in the SSD device has been reliably destroyed. If only the circuit element of the microcomputer chip is destroyed and the circuit element of the flash memory chip is not destroyed, there is a possibility that information stored in the flash memory chip is leaked.

  The present invention has been made in view of the above-described problems of the prior art, and is a nonvolatile semiconductor memory storage that can easily prevent information leakage at the time of disposal without requiring a large additional circuit. To provide an apparatus.

  In view of the above-described problems of the prior art, the nonvolatile semiconductor memory storage device according to the present invention includes a nonvolatile semiconductor memory chip capable of electrically writing and erasing data, and the nonvolatile semiconductor via a plurality of control signals. A control circuit that controls reading / writing of data to / from the memory chip and a power supply voltage supplied from the outside are boosted, and an element breakdown voltage that is higher than the absolute maximum rated voltage set in the nonvolatile semiconductor memory chip is obtained. A non-volatile semiconductor memory among the control signals output from the control circuit to the non-volatile semiconductor memory chip based on an element breakdown voltage application instruction signal output from the control circuit. The signal line of the first control signal for controlling the timing of reading data from the chip and the nonvolatile to be controlled At least one signal line of the signal line of the second control signal for selecting a semiconductor memory chip, and applying the device breakdown voltage generated by the booster circuit.

  According to the present invention, there is provided a nonvolatile semiconductor memory device capable of preventing information leakage at the time of disposal without requiring a large additional circuit.

The figure which showed the example of a structure of the SSD apparatus which concerns on the 1st Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the modification of the 1st Embodiment of this invention. The figure which showed the example of the process sequence performed by the control circuit in order to make it impossible to read the data of a flash memory chip more reliably in the 1st Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the 2nd Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the modification of the 2nd Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the 3rd Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the 4th Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the 5th Embodiment of this invention. The figure which showed the example of a structure of the SSD apparatus which concerns on the modification of the 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, common constituent elements are denoted by the same reference numerals, and redundant description is omitted. Here, the embodiment will be described by taking a storage device constituted by a flash memory, which is a typical nonvolatile semiconductor memory, that is, an SSD device as an example.

<First Embodiment>
FIG. 1 is a diagram showing an example of the configuration of the SSD device 1 according to the first embodiment of the present invention. As shown in FIG. 1, the SSD device 1 includes a plurality of (for example, 20) flash memory chips 11, a control circuit 12, a booster circuit 13, backflow protection diodes 14 and 15, and the like. It is configured on the printed circuit board. Here, the flash memory chip 11 refers to, for example, a semiconductor chip in which 16 Gbit flash memory cells are integrated and contained in one package such as a TSOP (Thin Small Outline Package). In FIG. 1, only three flash memory chips 11 are depicted, but the number is not limited to three. Further, the number of flash memory chips 11 is not limited to a plurality and may be one.

  The SSD device 1 is connected to the host computer 2 via an interface cable 21 such as so-called S-ATA (Serial Advanced Technology Attachment) or USB (Universal Serial Bus), and is used as an auxiliary storage device of the host computer 2. That is, the SSD device 1 stores the data transferred from the host computer 2 in the flash memory chip 11 and reads out the data stored in the flash memory chip 11 under the instruction of the host computer 2. To the host computer 2. Note that the host computer 2 refers to a general personal computer, a workstation, and an information processing apparatus attached to various devices.

  The SSD device 1 is supplied with a power supply voltage Vdd (for example, 5 V) from an external power supply circuit 3 such as an AC adapter, and the power supply voltage Vdd is supplied to the flash memory chip 11, the control circuit 12, and the booster circuit in the SSD device 1. 13 and so on. Note that, inside the SSD device 1, the power supply voltage Vdd (for example, 5V) may be appropriately converted to 3V or the like according to the specification of the power supply voltage required by the flash memory chip 11 or the like.

  The control circuit 12 is between the host computer 2 and the flash memory chip 11, mediates writing of data to the flash memory chip 11 and reading of data from the flash memory chip 11 by the host computer 2, and controls the mediation. . That is, the control circuit 12 adjusts the difference in the interface between the host computer 2 and the flash memory chip 11.

  The control circuit 12 has a temporary storage memory (not shown) composed of a RAM (Random Access Memory) or the like in order to adjust the difference between the two interfaces. That is, the data transferred from the host computer 2 is temporarily stored in the temporary storage memory and then written to the flash memory chip 11 by the control circuit 12. The data read from the flash memory chip 11 by the control circuit 12 is temporarily stored in the temporary storage memory and then transferred to the host computer 2.

  The host computer 2 regards the SSD device 1 as a virtual hard disk device, and reads and writes S data. Therefore, the host computer 2 designates a track address and a sector address, which are data storage locations in the hard disk device, when reading / writing data from / to the SSD device 1. Therefore, the control circuit 12 also plays a role of converting a track address and a sector address designated by the host computer 2 into a physical address (page address or block address) of the flash memory chip 11.

  As shown in FIG. 1, the control circuit 12 and the flash memory chip 11 are connected by an address / data bus (A / D bus), and the control circuit 12 receives various control signals for reading and writing data. Output to the flash memory chip 11. In FIG. 1, among the various control signals, a signal for controlling the data read timing is represented as a control signal RE, and a signal for selecting the flash memory chip 11 to be controlled from the plurality of flash memory chips 11 is controlled. Signals CS1, CS2, and CS3 are represented, and other control signals are represented as control signals CNT.

  The control circuit 12 configured as described above can be realized as a compact circuit by using a one-chip type microcomputer, FPGA (Field Programmable Gate Array), or the like.

  The booster circuit 13 receives the supply of the power supply voltage Vdd (for example, 5V) from the external power supply circuit 3, boosts the power supply voltage Vdd, and sets the absolute maximum rated voltage (for example, the flash memory chip 11). 7V), a device breakdown voltage Vds (for example, 20V) having a voltage higher than 7V) is output. However, here, the booster circuit 13 operates when the boost instruction signal BS output from the control circuit 12 becomes active, that is, outputs the element breakdown voltage Vds. The control circuit 12 activates the boost instruction signal BS when receiving an element destruction command for the flash memory chip 11 from the host computer 2. The boost instruction signal BS is made inactive after a predetermined time.

  In this embodiment, the control signal RE among the control signals output from the control circuit 12 to the flash memory chip 11 is connected to the input terminal of the flash memory chip 11 via the diode 14. Furthermore, the wiring to which the element breakdown voltage Vds output from the booster circuit 13 is applied is connected to a point P between the diode 14 and the input terminal of the flash memory chip 11 on the signal line of the control signal RE via the diode 15. It is connected to the. That is, the diode 15 is arranged on the wiring connecting the booster circuit 13 and the point P on the signal line of the control signal RE. Further, a pull-down resistor R is connected between the wiring portion including the signal line point P and the ground.

  Here, the diode 14 is provided such that the direction from the control circuit 12 side to the flash memory chip 11 side is the forward direction, and the reverse breakdown voltage is higher than the element breakdown voltage Vds. The diode 15 is provided such that the direction from the booster circuit 13 side to the point P side is the forward direction. The reverse breakdown voltage of the diode 15 only needs to be higher than the absolute maximum rated voltage of the power supply voltage Vdd. As the diodes 14 and 15, normal pn junction diodes may be used, but it is preferable to use Schottky barrier diodes (SBD) having excellent high frequency characteristics, high switching speed, and small forward voltage drop. .

  At this time, when the element breakdown voltage Vds is applied to the point P from the booster circuit 13, the element breakdown voltage Vds is applied to the input terminal of the control signal RE of the flash memory chip 11. Therefore, the application of the element breakdown voltage Vds destroys the input gate in the flash memory chip 11, and the control signal RE is not transmitted to the inside of the flash memory chip 11 behind the input gate. Therefore, in the flash memory chip 11, it becomes impossible to generate a data read signal from the memory cell, and thus the control circuit 12 cannot read data from the flash memory chip 11.

  On the other hand, even if the element breakdown voltage Vds is applied from the booster circuit 13 to the point P, the application of the element breakdown voltage Vds to the control circuit 12 is blocked by the diode 14, so that the control circuit 12 is destroyed by the element breakdown voltage Vds. It will never be done.

  The diode 15 serves to separate the control signal RE from the booster circuit 13 during normal operation, that is, when the boost instruction signal BS is inactive (when the booster circuit 13 is not operating).

  As described above, in the present embodiment, when receiving the boost command from the host computer 2, the control circuit 12 activates the boost command signal BS and outputs the active boost command signal BS to the boost circuit 13. When the booster circuit 13 receives the active boost instruction signal BS, the booster circuit 13 starts a boost operation to generate the element breakdown voltage Vds, and the generated element breakdown voltage Vds is transmitted to the control signal RE via the diode 15. Apply to point P on the signal line. Since the input gate in the flash memory chip 11 is destroyed by the application of the element breakdown voltage Vds, the control circuit 12 cannot read data from the flash memory chip 11.

  Therefore, when discarding the SSD device 1, the host computer 2 can make it impossible to read data stored in the SSD device 1 by outputting a boost command to the SSD device 1. That is, according to the present embodiment, it is possible to prevent information leakage from the discarded SSD device 1 simply by adding the booster circuit 13, the diodes 14 and 15 and the pull-down resistor R to the conventional general SSD device. become. In addition, the processing on the host computer 2 side required at that time can be as simple as outputting a boost command.

  In this embodiment, the element breakdown voltage Vds is not supplied to the power supply terminal of the flash memory chip 11 as shown in Patent Document 1, but is supplied to the input terminal of the control signal RE. Unlike the power supply terminal, the input terminal of the control signal RE has a large input impedance. Therefore, the current capacity of the element breakdown voltage Vds necessary for destroying the gate of the input circuit may be small. This means that the scale of the booster circuit 13 can be small.

  In the present embodiment, even when the element breakdown voltage Vds is applied to the signal line of the control signal RE, the diode 14 can prevent the control circuit 12 from being destroyed. Therefore, even after the element breakdown voltage Vds is applied to the signal line of the control signal RE, the control circuit 12 operates normally if the application of the element breakdown voltage Vds is released. As a result, after the input circuit of the flash memory chip 11 is destroyed by the element breakdown voltage Vds, the control circuit 12 reads data from the flash memory chip 11 to confirm that the input circuit of the flash memory chip 11 is destroyed. It becomes possible to do.

  Incidentally, the data read from the flash memory chip 11 in which the input circuit of the control signal RE is destroyed becomes meaningless data (including all bits 0). In the case of the SSD device 1, when reading data from the flash memory chip 11, the control circuit 12 reads page data as a unit. The page data is added with error check correction code data such as Reed-Solomon code. Yes. Therefore, the control circuit 12 can check the presence or absence of errors in the read data using the data of the error check and correction code. When the input circuit of the control signal RE is destroyed, the error check correction code data is also meaningless data. Therefore, in this error check, the read page data is naturally determined to have an error.

  Therefore, when the control circuit 12 reads all the page data from the flash memory chip 11 included in the SSD device 1 and it is determined that there is an error in the error check correction code check for all the page data, It can be determined that normal data cannot be read from the flash memory chip 11. Therefore, the control circuit 12 can confirm whether normal data cannot be read from the flash memory chip 11. Furthermore, this means that the host computer 2 can confirm that normal data reading from the flash memory chip 11 has become impossible.

<Modification of First Embodiment>
FIG. 2 is a diagram showing an example of the configuration of the SSD device 1a according to the modification of the first embodiment of the present invention. The configuration of the SSD device 1a according to this modification is different from the SSD device 1 shown in FIG. 1 in the following two points.

(1) The wiring for conducting the element breakdown voltage Vds output from the booster circuit 13 is not directly connected to the diode 15 but connected to the diode 15 via the switch 16. That is, the switch 16 is disposed in the middle of the wiring connecting the booster circuit 13 and the diode 15. The switch 16 may be a junction type or MOS (Metal Oxide Semiconductor) type field effect transistor (FET), or may be a mechanical switch such as a relay.
(2) The control circuit 12 outputs the switch-on signal SWA to the switch 16 instead of outputting the boost instruction signal BS (see FIG. 1) to the booster circuit 13. Here, when the switch-on signal SWA becomes active, the switch 16 becomes conductive, and when the switch-on signal SWA becomes inactive, the switch 16 becomes non-conductive. The switch-on signal SWA is controlled to be inactive after being active for a predetermined time. In this case, the booster circuit 13 may always generate the element breakdown voltage Vds.

  In this modification, the booster circuit 13 may generate the element breakdown voltage Vds before the switch-on signal SWA from the control circuit 12 is active. In that case, when the switch-on signal SWA is activated from the control circuit 12, the element breakdown voltage Vds is immediately applied to the signal line of the control signal RE via the switch 16 and the diode 15. Therefore, since the voltage of the control signal RE is suddenly changed to the high voltage side, the input circuit of the control signal RE in the flash memory chip 11 is easily destroyed due to the rapid change.

  Except for the above points, the operation and effect of the SSD device 1a shown in FIG. 2 are almost the same as the operation and effect of the SSD device 1 shown in FIG. To do.

<Second Modification of First Embodiment>
The illustration of the second modification is omitted. In the second modification, the booster circuit 13 is configured to output a plurality of predetermined element breakdown voltages (for example, 20V, 30V, 50V, etc.). Then, according to an instruction from the control circuit 12, one of the plurality of types of element breakdown voltages is selected and output as the element breakdown voltage Vds. Therefore, the boost instruction signal BS output from the control circuit 12 toward the booster circuit 13 is preferably not a single signal but a plurality of boost command signals BS. For example, when the booster circuit 13 can output three types of element breakdown voltages such as 20 V, 30 V, and 50 V, the control circuit 12 has three boost instruction signals BS (BS1, BS1, BS1, BS2) having the same number as the number of types of the element breakdown voltages. One of the element breakdown voltages is selected using BS2, BS3).

  The booster circuit 13 as described above can be realized by, for example, a booster circuit including a multi-stage booster church pump. That is, when the element breakdown voltage Vds to be output is instructed, the output voltage of the charge pump of the number of stages corresponding to the voltage is selected, and the output voltage from the charge pump is set as the element breakdown voltage Vds of the booster circuit 13. can do.

  Naturally, also in this modification, the input circuit of the control signal RE of the flash memory chip 11 can be destroyed by applying the element breakdown voltage Vds to the point P on the signal line of the control signal RE. However, a protection circuit is generally incorporated in the input circuit of the flash memory chip 11 to protect against static electricity and the like. Therefore, even if an element breakdown voltage Vds (for example, 20 V) is applied to the point P on the signal line of the control signal RE, it is sufficiently possible that the input circuit of the control signal RE of the flash memory chip 11 is not destroyed. .

  On the other hand, since the diode 14 having a reverse breakdown voltage higher than the applied element breakdown voltage Vds is provided on the control circuit 12 side on the control signal RE, even if the element breakdown voltage Vds is applied to the point P. The control circuit 12 is not destroyed.

  Therefore, in this modification, for example, the element breakdown voltage Vds of 20 V, for example, is applied from the booster circuit 13 to the point P on the signal line of the control signal RE, and the input circuit of the control signal RE of the flash memory chip 11 is destroyed. Thereafter, the control circuit 12 reads all the data in the flash memory chip 11 and determines whether or not the reading is possible. As a result of the determination, if data can be read out even if partly, the element breakdown voltage Vds applied to the point P is set to a higher voltage (for example, 30 V). Then, the high element breakdown voltage Vds is applied again to the point P on the signal line of the control signal RE to destroy the input circuit of the control signal RE of the flash memory chip 11. As described above, in the present modification, the control circuit 12 repeatedly executes the above-described procedure, whereby the data of the flash memory chip 11 can be more reliably read out.

  FIG. 3 is a diagram showing an example of a processing procedure executed by the control circuit in order to make it impossible to read data of the flash memory chip 11 more reliably in the first embodiment of the present invention. In this processing procedure, the control circuit 12 first sets an initial value (for example, 20 V) of the element breakdown voltage Vds to be output by the booster circuit 13 (step S11). Of the input circuit of the flash memory chip 11

  Next, the control circuit 12 instructs the booster circuit 13 to apply the element breakdown voltage Vds to the point P on the signal line of the control signal RE (step S12). That is, the control circuit 12 activates the boost instruction signal BS (for example, the boost instruction signal BS1 associated with 20V). Then, after elapse of a predetermined time (for example, 5 seconds), the control circuit 12 instructs the booster circuit 13 to stop applying the element breakdown voltage Vds to the point P on the signal line of the control signal RE (step). S13). That is, the control circuit 12 inactivates an active boost instruction signal BS (for example, the BS1).

  Subsequently, the control circuit 12 reads all the data stored in the flash memory chip 11 (step S14). Then, for each data (page data) corresponding to a page in the hard disk device at the time of this data reading, an error check is performed on the read data using an error check correction code attached to the page data to determine the presence or absence of an error ( Step S15). As a result of the determination, if it is determined that there is an error for all the page data (Yes in step S15), the control circuit 12 has not been able to correctly read all the data in the flash memory chip 11. Therefore, it is determined that data reading from the flash memory chip 11 is impossible, and the processing of FIG.

  On the other hand, if it is determined in step S15 that there is no error in the error check correction code check for some pages of data (No in step S15), the input circuit of the control signal RE in the flash memory chip 11 Means that it is not fully destroyed. Therefore, in this case, the control circuit 12 changes the value of the high voltage to be output to the booster circuit 13 to, for example, a higher voltage from 20 V to 30 V (step S16), and repeats the processing from step S12 onward. Run.

  That is, according to the second modification of the first embodiment described above, the control circuit 12 applies the element breakdown voltage Vds that destroys the input circuit of the control signal RE in the flash memory chip 11 and determines the breakdown result. If the breakdown is insufficient, the process of further increasing the applied element breakdown voltage Vds is repeated. Therefore, the input circuit for the control signal RE in the flash memory chip 11 is more reliably destroyed. Therefore, leakage of information stored in the flash memory chip 11 can be prevented more reliably.

  Note that the iterative process after step S12 can be repeated only for the number of element breakdown voltages Vds that can be output by the booster circuit 13. Therefore, if all the input circuits for the control signal RE in the flash memory chip 11 cannot be destroyed even by the highest voltage among the element breakdown voltages Vds that can be output by the booster circuit 13, the control circuit 12 It is advisable to report that fact to the host computer 2. In that case, the host computer 2 can inform the operator that the SSD device 1 should be destroyed, for example, physically or mechanically.

<Second Embodiment>
FIG. 4 is a diagram showing an example of the configuration of the SSD device 1b according to the second embodiment of the present invention. The configuration of the SSD device 1b according to the second embodiment is different from the SSD device 1 shown in FIG. 1 in the following two points.

(1) The element breakdown voltage Vds output from the booster circuit 13 is not applied to the point P on the signal line of the control signal RE, but passes through the independent diodes 15 to control signals CS1, CS2, CS3, respectively. Applied to the points P1, P2 and P3 on the signal line.
(2) The diode 14 is not on the signal line of the control signal RE but between the points P1, P2, P3 on the signal lines of the control signals CS1, CS2, CS3 and the output terminals of the control signals CS1, CS2, CS3 of the control circuit 12. Between. In addition, pull-down resistors R1, R2, and R3 are respectively connected between the wiring portion including the signal line points P1, P2, and P3 of the control signals CS1, CS2, and CS3 and the ground.

  Here, the control signals CS1, CS2 and CS3 are all signals that do not become active at the same time. Then, when one of them becomes active, the input and output signals of the flash memory chip 11 to which the activated control signals CS1, CS2 and CS3 are connected are validated. Therefore, data cannot be read from the flash memory chip 11 to which the control signals CS1, CS2, and CS3 are connected unless the control signals CS1, CS2, and CS3 are activated. That is, the control signals CS1, CS2, and CS3 can be said to be signals for selecting the flash memory chip 11 to be controlled by the control circuit 12 for data reading and writing.

  Therefore, in the second embodiment, when the element breakdown voltage Vds is applied to each of the points P1, P2, and P3 on the signal lines of the control signals CS1, CS2, and CS3, the element breakdown voltage Vds causes the inside of the flash memory chip 11 to be generated. The input circuits corresponding to the control signals CS1, CS2 and CS3 are destroyed. Therefore, when these input circuits are destroyed, even if the control signals CS1, CS2, and CS3 are activated by the control circuit 12, the activated control signals CS1, CS2, and CS3 are stored in the flash memory chip 11. Not transmitted to. As a result, the control circuit 12 cannot read the data stored in the flash memory chip 11, and the data read formally becomes completely meaningless data.

  Therefore, the operation and effect of the SSD device 1b according to the second embodiment are almost the same as the operation and effect of the SSD device 1 according to the first embodiment shown in FIG. To do.

<Modification of Second Embodiment>
FIG. 5 is a diagram showing an example of the configuration of an SSD device 1c according to a modification of the second embodiment of the present invention. The configuration of the SSD device 1c according to this modification is different from the SSD device 1b shown in FIG. 4 in the following two points.

(1) The wiring through which the element breakdown voltage Vds output from the booster circuit 13 is conducted is not directly connected to the diode 15, but is connected to the diode 15 via the switch 16c. Here, the switch 16c may be formed of a junction-type or MOS-type field effect transistor, or may be formed of a mechanical switch such as a relay.
(2) The control circuit 12 does not output the boost instruction signal BS (see FIG. 1) to the booster circuit 13, but outputs a switch-on signal SWA to the switch 16c. Here, when the switch-on signal SWA becomes active, the switch 16c becomes conductive, and when the switch-on signal SWA becomes inactive, the switch 16c becomes non-conductive. In this case, the booster circuit 13 may always generate the element breakdown voltage Vds.

  In this modification, the booster circuit 13 may generate the element breakdown voltage Vds before the switch-on signal SWA is output from the control circuit 12. In this case, when the switch-on signal SWA is output from the control circuit 12, the element breakdown voltage Vds is immediately applied to the signal lines of the control signals CS1, CS2, and CS3 via the switch 16c and the diode 15. Accordingly, since the voltages of the control signals CS1, CS2, and CS3 are rapidly changed to high voltages, the input circuit of the control signals CS1, CS2, and CS3 in the flash memory chip 11 is easily destroyed due to the rapid change.

  Except for the above points, the operation and effect of the SSD device 1c shown in FIG. 5 are almost the same as the operation and effect of the SSD device 1b shown in FIG. .

<Third Embodiment>
FIG. 6 is a diagram showing an example of the configuration of an SSD device 1d according to the third embodiment of the present invention. The configuration of the SSD device 1d according to the third embodiment is different from the SSD device 1 according to the first embodiment (see FIG. 1) in the following two points.

(1) The element breakdown voltage Vds output from the booster circuit 13 passes through independent diodes 15 on not only the point P on the signal line of the control signal RE but also on the signal lines of the control signals CS1, CS2, and CS3. It is also applied to points P1, P2 and P3.
(2) The independent diode 14 is not only between the point P on the signal line of the control signal RE and the output terminal of the control signal RE of the control circuit 12, but also on the signal line of the control signals CS1, CS2, CS3. Provided between P2 and P3 and the output terminals of the control signals CS1, CS2 and CS3 of the control circuit 12.

  The configuration of the SSD device 1d according to the third embodiment is substantially the same as the SSD device 1 according to the first embodiment (see FIG. 1) and the SSD device 1b according to the second embodiment (FIG. 2). Therefore, it is possible to expect an effect that the certainty that data cannot be read from the flash memory chip 11 is increased accordingly. Since other operations and effects are almost the same as those of the first embodiment and the second embodiment, repeated description thereof is omitted.

<Fourth Embodiment>
FIG. 7 is a diagram showing an example of the configuration of an SSD device 1e according to the fourth embodiment of the present invention. The configuration of the SSD device 1e according to the fourth embodiment is that the SSD button 1 according to the first embodiment (FIG. 1) is added in that a discard button 17 and a discard protection switch 18 that can be operated manually are added. It is different from reference).

  The discard button 17 is pressed when the user of the SSD device 1e or the discarder discards the SSD device 1e. When the discard button 17 is pressed, the control circuit 12 outputs the boost instruction signal BS to the booster circuit 13 and applies the element breakdown voltage Vds from the booster circuit 13 to the point P on the signal line of the control signal RE. As a result, the input circuit of the control signal RE in the flash memory chip 11 is destroyed, and the stored data cannot be read from the flash memory chip 11. Accordingly, leakage of information stored in the SSD device 1e is substantially prevented.

  By providing the discard button 17, even if the SSD device 1e is not connected to the host computer 2, if the power supply voltage Vdd is supplied from the power supply circuit 3 such as an AC adapter, the flash memory chip 11 is manually added. It becomes possible to make it impossible to read the data stored in the memory. Therefore, the user of the SSD device 1e can safely discard the SSD device 1e while preventing the leakage of information stored in the stored content by an extremely simple operation.

  If it is impossible to read from the flash memory chip 11 of the SSD device 1e by a simple operation as described above, it is necessary to take countermeasures against erroneous operations by the user. Therefore, in the present embodiment, the discard button 17 is provided in a thin through hole formed in a part of the housing of the SSD device 1e. For example, if a member such as a needle is not inserted into the through term, The discard button 17 cannot be pressed. Alternatively, the discard button 17 is a button that pushes a cracker plate that cannot be broken by a normal force.

  In addition to the discard button 17, a discard protection switch 18 may be provided. It is assumed that the discard protection switch 18 is normally on. As long as the discard protection switch 18 is not turned off, the control circuit 12 does not output the boost instruction signal BS to the booster circuit 13 even when the discard button 17 is pressed. Similarly, when the discard protection switch 18 is not turned off, the control circuit 12 does not output the boost instruction signal BS to the booster circuit 13 even if it receives a boost command from the host computer 2. Accordingly, the discard protection switch 18 is effective not only for preventing erroneous operation of the user's discard button 17 but also for preventing erroneous output of the boost command from the host computer 2.

  Here, as a case, it is assumed that a plurality of SSD devices 1 e are connected to the host computer 2. Here, the discard protection switch 18 of the SSD device 1e to be discarded is turned off, and the discard protection switch 18 of the SSD device 1e not to be discarded is kept on. In this case, the user of the host computer 2 can safely output a boost command to the SSD device 1e to be discarded and instruct the discarding. That is, it is possible to prevent the SSD device 1e that is not discarded from being erroneously discarded due to an erroneous operation of the user's host computer 2.

  In the present embodiment, as in the first embodiment, the control circuit 12 operates normally even after the device breakdown voltage Vds is applied to the flash memory chip 11, and the data read from the flash memory chip 11. The presence or absence of an error can be inspected. Therefore, a light-emitting diode or the like is further provided in the SSD device 1e, and all page data read from the flash memory chip 11 is inspected using an error check and correction code. If the inspection determines that there is an error, the light emitting diode may be turned on. As a result, the user can easily confirm whether or not data from the flash memory chip 11 cannot be normally read, that is, whether or not the function of reading data from the SSD device 1e is destroyed. In addition, a speaker, a buzzer, or the like may be provided to easily confirm whether or not the data reading function is destroyed by sound.

<Fifth Embodiment>
FIG. 8 is a diagram showing an example of the configuration of an SSD device 1f according to the fifth embodiment of the present invention. The configuration of the SSD device 1f according to the fifth embodiment is different from the SSD device 1 shown in FIG. 1 in the following two points.

(1) Between the output terminal of the control signal RE of the control circuit 12 and the point P to which the element breakdown voltage Vds is applied, an FET switch 19 is provided instead of the diode 14 (see FIG. 1). The FET switch 19 may be a MOS type or a junction type, but is depicted as an N-channel MOS type in FIG. Further, it is assumed that the drain-source breakdown voltage of the FET switch 19 is larger than the element breakdown voltage Vde. In this case, the pull-down resistor R that pulls down the signal line of the control signal RE is not necessary.
(2) An inverter circuit 20 for driving the FET switch 19 is added. The inverter circuit 20 can output a voltage sufficient to turn on the FET switch 19 when the boost instruction signal BS is inactive.

  In the present embodiment, when the boost instruction signal BS output from the control circuit 12 is inactive, the FET switch 19 is in an on state, that is, a conductive state. Therefore, the control signal RE output from the control circuit 12 passes through the FET switch 19 and reaches the input terminal of the flash memory chip 11. At this time, since the booster circuit 13 does not operate, the element breakdown voltage Vde is not applied to the point P on the signal line of the control signal RE.

  On the other hand, when the boost instruction signal BS output from the control circuit 12 becomes active, the FET switch 19 is turned off, that is, non-conductive. Therefore, the point P on the signal line of the control signal RE to which the element breakdown voltage Vde is applied and the output terminal of the control signal RE of the control circuit 12 are electrically disconnected. Therefore, since the element breakdown voltage Vde is not applied to the output terminal of the control circuit 12, the control circuit 12 is not broken by the element breakdown voltage Vde.

  Except for the above points, the operation and effect of the SSD device 1f shown in FIG. 8 are almost the same as the operation and effect of the SSD device 1 shown in FIG. To do.

<Modification of Fifth Embodiment>
FIG. 9 is a diagram showing an example of the configuration of an SSD device 1g according to a modification of the fifth embodiment of the present invention. The configuration of the SSD device 1g according to this modification is different from the SSD device 1f shown in FIG. 8 in the following two points.

(1) The wiring through which the element breakdown voltage Vds output from the booster circuit 13 is connected is connected to the point P on the signal line of the control signal RE via the FET switch 19a, not the diode 15. The FET switch 19a may be a MOS type or a junction type, but is depicted as an N-channel MOS type in FIG. Further, it is assumed that the drain-source breakdown voltage of the FET switch 19a is larger than the element breakdown voltage Vde.
(2) The control circuit 12 does not output a boost instruction signal BS (see FIG. 8) to the booster circuit 13, but outputs a switch-on signal SWA to the FET switch 19a. Here, when the switch-on signal SWA becomes active, the FET switch 19a becomes conductive, and when the switch-on signal SWA becomes inactive, the FET switch 19a becomes non-conductive. In this case, the booster circuit 13 may always generate the element breakdown voltage Vds.

  In the modification of this embodiment, it can be said that the SSD device 1f (see FIG. 8) according to the fifth embodiment is applied to the SSD device 1a (see FIG. 2) according to the modification of the first embodiment. Here, the diode 15 shown in FIG. 2 is omitted. Even in such a case, when the switch-on signal SWA is inactive, the FET switch 19a is in a non-conductive state. Therefore, even when the booster circuit 13 does not operate, the voltage fluctuation of the control signal RE is transmitted to the booster circuit 13. Never happen.

  Except for the above points, the operation and effect of the SSD device 1g shown in FIG. 9 are almost the same as the operation and effect of the SSD device 1f shown in FIG. To do.

  As a further modification, the SSD device 1f according to the fifth embodiment described in FIGS. 8 and 9 and the SSD device 1g according to the modification operate mechanically instead of the FET switches 19 and 19a. A switch such as a relay may be used.

  The present invention is not limited to the above-described embodiments and modifications, and further includes various modifications. For example, the above-described embodiments and modified examples describe the present invention in detail in an easy-to-understand manner, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of an embodiment or modification can be replaced with the configuration of another embodiment or modification, and further, the configuration of another embodiment or modification can be replaced with another embodiment or modification. It is also possible to add the following configuration.

1, 1a, 1b, 1c, 1d, 1e SSD device (nonvolatile semiconductor memory storage device)
2 Host computer 3 Power supply circuit 11 Flash memory chip (nonvolatile semiconductor memory chip)
12 Control circuit 13 Booster circuit 14 Diode (first diode)
15 Diode (second diode)
16, 16c Switch 17 Discard button 18 Discard protection switch 19 FET switch (first switch)
19a FET switch (second switch)
20 Inverter circuit 21 Interface cable R Pull-down resistor Vdd Power supply voltage Vds Element breakdown voltage CNT Control signal RE Control signal (first control signal)
CS1, CS2, CS3 control signal (second control signal)
BS, BS1, BS2, BS3 Boost instruction signal (element breakdown voltage application instruction signal)
SWA switch-on signal (element breakdown voltage application instruction signal)

Claims (10)

A nonvolatile semiconductor memory chip capable of electrically writing and erasing data; and
A control circuit that controls reading and writing of data with respect to the nonvolatile semiconductor memory chip via a plurality of control signals;
A booster circuit that boosts a power supply voltage supplied from the outside and generates an element breakdown voltage that is higher than an absolute maximum rated voltage set in the nonvolatile semiconductor memory chip;
With
Based on the element breakdown voltage application instruction signal output from the control circuit, the timing for reading data from the nonvolatile semiconductor memory chip is controlled among the control signals output from the control circuit to the nonvolatile semiconductor memory chip. The element breakdown voltage generated by the booster circuit on at least one signal line of the signal line of the first control signal and the signal line of the second control signal that selects the nonvolatile semiconductor memory chip to be controlled A non-volatile semiconductor memory storage device, wherein: A first diode having a reverse breakdown voltage higher than the element breakdown voltage between an element breakdown voltage application point on the signal line to which the element breakdown voltage is applied and an output terminal of the signal line of the control circuit 2. The nonvolatile semiconductor memory device according to claim 1, wherein a direction from the output terminal side to the element breakdown voltage application point side is a forward direction. A second diode having a reverse breakdown voltage higher than the power supply voltage is provided in the middle of the wiring from the element breakdown voltage output terminal of the booster circuit to the element breakdown voltage application point on the signal line. The nonvolatile semiconductor memory storage device according to claim 2, wherein a direction from the breakdown voltage output terminal side to the element breakdown voltage application point side is a forward direction. When the element breakdown voltage application instruction signal is active, in the middle of the wiring from the element breakdown voltage output terminal of the booster circuit to the second diode, the element breakdown voltage application instruction signal is inactive. The nonvolatile semiconductor memory device according to claim 3, further comprising a switch that is in a non-conducting state at the time. Between the element breakdown voltage application point on the signal line to which the element breakdown voltage is applied and the output terminal of the signal line of the control circuit, when the element breakdown voltage application instruction signal is inactive, the conductive state, The non-volatile semiconductor memory storage device according to claim 1, further comprising a first switch that is turned off when the element breakdown voltage application instruction signal is active. In the middle of the wiring from the output terminal of the element breakdown voltage of the booster circuit to the element breakdown voltage application point on the signal line, the element breakdown voltage application instruction signal is in a conductive state when active, and the element breakdown voltage application The non-volatile semiconductor memory device according to claim 5, further comprising a second switch that is turned off when the instruction signal is inactive. The control circuit applies a first breakdown voltage to at least one of the signal line of the first control signal and the signal line of the second control signal via the booster circuit, and then the nonvolatile semiconductor memory When data is read from the chip and all of the read data is not in error, a second breakdown voltage higher than the first breakdown voltage is again applied to the first control signal via the booster circuit. The nonvolatile semiconductor memory storage device according to claim 2, wherein the nonvolatile semiconductor memory storage device is applied to at least one of a signal line and a signal line of the second control signal. The control circuit outputs the element breakdown voltage application instruction signal to the booster circuit when receiving an element breakdown command of the nonvolatile semiconductor memory chip output from a host computer connected to the outside. The non-volatile semiconductor memory storage device according to claim 1. A disposal button that is manually operated is further provided.
9. The nonvolatile circuit according to claim 1, wherein when the discard button is pressed, the control circuit outputs the element breakdown voltage application instruction signal to the booster circuit. 10. Semiconductor memory storage device. A waste protection switch that is manually operated is further provided.
When the discard protection switch is on, output of the element breakdown voltage application instruction signal from the control circuit is prohibited, and when the discard protection switch is off, the element breakdown voltage is applied from the control circuit. The non-volatile semiconductor memory device according to claim 1, wherein the output of the instruction signal is allowed.

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