JP6555381B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus that prevent deterioration of display quality.

  In recent years, various electro-optical devices using light-emitting elements such as organic light emitting diodes (hereinafter referred to as “OLEDs”) have been proposed. In such an electro-optical device, a pixel circuit is provided corresponding to the intersection of the scanning line and the data line. The pixel circuit generally has a configuration including the light emitting element, a writing transistor, and a driving transistor (see Patent Document 1).

JP 2007-310311 A

By the way, when the data line and the driving transistor approach each other, the degree of capacitive coupling increases. For this reason, when the potential of the data line fluctuates, the potential fluctuation changes the holding potential of each part of the driving transistor, particularly the gate, via the parasitic capacitance. Therefore, it has been pointed out that the target current cannot be supplied to the light emitting element, and the display quality is deteriorated.
The present invention has been made in view of the above-described problems, and one of its purposes is to prevent display quality from being deteriorated due to potential fluctuations in data lines.

  In order to solve the above problems, an electro-optical device according to the present invention includes a scanning line and a data line that intersect with each other, and a pixel circuit provided corresponding to the intersection between the scanning line and the data line. The pixel circuit includes a driving transistor, a writing transistor electrically connected between the data line and the gate of the driving transistor, a first storage capacitor connected to the gate of the driving transistor, and the driving A light emitting element that emits light at a luminance corresponding to the magnitude of current supplied from the transistor; and a first shield portion made of a conductive material, and includes a gate of the driving transistor orthogonal to the data line. In any first cut surface obtained by cutting the pixel circuit, the first shield portion is a line segment connecting the gate of the driving transistor and the data line. Intersect, characterized in that.

In the present invention, the first shield portion is provided so as to be located between the gate of the driving transistor and the data line at an arbitrary first cut plane that is orthogonal to the data line and includes the gate of the driving transistor. That is, in the electro-optical device described above, the first shield portion is disposed between the gate of the driving transistor and the data line. In other words, the first shield portion is located between the gate of the driving transistor and the data line when the pixel circuit is viewed in plan and when viewed in cross section along a cross section orthogonal to the data line.
Therefore, in the present invention, the first shield portion can reduce the influence of the potential fluctuation of the data line on the holding potential of the gate electrode of the driving transistor. That is, since the gate of the driving transistor can be electrically shielded from the data line, it is possible to prevent the display quality from being deteriorated due to the potential fluctuation of the data line.

In the electro-optical device described above, the first shield portion is formed on the first relay electrode formed on the same wiring layer as the data line, and on the same wiring layer as the gate of the driving transistor. It is preferable that a plurality of relay electrodes including two relay electrodes and a connection portion that connects the plurality of relay electrodes, and the relay electrode and the connection portion intersect the arbitrary first cut surface. .
According to the present invention, since the first shield portion is located between the gate of the driving transistor and the data line when viewed in a cross section perpendicular to the data line, the gate of the driving transistor is electrically connected to the data line from the data line. Can be shielded.
In the electro-optical device described above, the first shield part is formed of the conductive material arranged in at least two layers among the layers between the gate of the driving transistor and the data line. It is good.
Also in this case, since the first shield portion can be provided between the gate of the driving transistor and the data line, the gate of the driving transistor can be electrically shielded from the data line.

In the electro-optical device described above, the connection portion includes a plurality of contact holes, and two relay electrodes formed in mutually adjacent wiring layers among the plurality of relay electrodes include a plurality of contact holes. Of these, the contact holes are preferably connected by one contact hole, and the one contact hole intersects the arbitrary first cut surface.
According to the present invention, since the first shield portion is located between the gate of the driving transistor and the data line when viewed in a cross section perpendicular to the data line, the gate of the driving transistor is electrically connected to the data line from the data line. Can be shielded.

In the electro-optical device described above, the first storage capacitor is formed by a first electrode electrically connected to a gate of the driving transistor and a second electrode electrically connected to a source of the driving transistor. The potential of the first connection wiring formed and electrically connecting the gate of the driving transistor and the first electrode, and the second connection wiring electrically connecting the source of the driving transistor and the second electrode is maintained. The first shield part connects the potential holding part and the data line at an arbitrary second cut surface obtained by cutting the pixel circuit so as to include the potential holding part perpendicular to the data line. It is preferable to intersect the line segment.
According to the present invention, the first shield portion is provided so as to be positioned between the potential holding portion and the data line on an arbitrary second cut surface that is orthogonal to the data line and includes the potential holding portion. In other words, the first shield part is located between the potential holding part and the data line when the pixel circuit is viewed in plan and when the cross-sectional view is taken along a cross section orthogonal to the data line.
The potential holding portion is a wiring connected to the gate of the driving transistor and a wiring connected to the source. Therefore, in the present invention, since the potential holding portion, that is, the gate and the source of the driving transistor can be electrically shielded from the data line by the first shield portion, the display due to the potential fluctuation of the data line is displayed. Degradation can be prevented.

In the electro-optical device described above, it is preferable that a fixed potential is supplied to the first shield part.
In this case, since the first shield part can electrically shield the gate of the driving transistor from the data line, it is possible to prevent the display quality from being lowered due to the potential fluctuation of the data line.

In the electro-optical device described above, the pixel circuit includes a second storage capacitor having one end electrically connected to one of the source and the drain of the driving transistor and the other end electrically connected to a power supply line. Preferably, the light emitting element is electrically connected to one of a source and a drain of the driving transistor, and the first shield part is electrically connected to the power supply line.
For example, when a signal having a fixed potential or a small fluctuation range of the potential is supplied to the power supply line, the first shield portion can electrically shield the gate of the driving transistor from the data line. It is possible to prevent the display quality from deteriorating due to the potential fluctuation.

In the electro-optical device described above, the pixel circuit has a second shield part made of a conductive material, and the gate of the driving transistor is interposed between the first shield part and the second shield part. It is preferable to be provided.
According to the present invention, when the pixel circuit is provided between the two data lines, it is possible to prevent the potential fluctuation generated in the two data lines from propagating to the gate of the driving transistor included in the pixel circuit. Therefore, it is possible to prevent the display quality from being deteriorated due to the potential fluctuation of the data line.

In the electro-optical device described above, the plurality of scanning lines, the plurality of data lines intersecting with the plurality of scanning lines, and the intersections of the plurality of scanning lines and the plurality of data lines are provided. A plurality of the pixel circuits, and the second shield part included in the pixel circuit provided between the two adjacent data lines among the plurality of the pixel circuits. Of the two data lines adjacent to each other on the cut surface, one data line located on the opposite side of the first shield portion from the gate of the driving transistor is connected to the gate of the driving transistor. It is preferable to intersect the line segment.
According to the present invention, since the gate of the driving transistor can be electrically shielded from the data line by the first shield part and the second shield part, the display quality is lowered due to the potential fluctuation of the data line. Can be prevented.

  The electro-optical device according to the invention can be applied to various electronic apparatuses. Typically, it is a display device, and examples of the electronic device include a personal computer and a mobile phone. In particular, the present invention makes it difficult for fluctuations in the potential of the data line to affect the gate (source) potential of the driving transistor in the pixel circuit, thereby preventing deterioration in display quality. It is suitable for a small display device such as a projector. However, the use of the electro-optical device according to the invention is not limited to the display device. For example, the present invention can also be applied to an exposure apparatus (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment. It is a figure which shows the equivalent circuit of the pixel circuit in an electro-optical apparatus. It is a figure which shows the display operation of an electro-optical apparatus. It is a top view which shows the structure of the pixel circuit which concerns on embodiment. It is a fragmentary sectional view showing the composition of the pixel circuit concerning an embodiment. It is a fragmentary sectional view showing the composition of the pixel circuit concerning an embodiment. It is explanatory drawing explaining the range in which the shield part which concerns on embodiment is provided. 10 is a plan view showing a configuration of a pixel circuit according to Modification 1. FIG. 10 is a plan view illustrating a configuration of a pixel circuit according to Modification 2. FIG. It is explanatory drawing explaining the range in which the shield part which concerns on the modification 2 is provided. 14 is a plan view showing a configuration of a pixel circuit according to Modification 3. FIG. 10 is a plan view showing a configuration of a pixel circuit according to Modification 4. FIG. It is a figure which shows the electronic device (the 1) to which an electro-optical apparatus is applied. It is a figure which shows the electronic device (the 2) to which an electro-optical apparatus is applied. It is a figure which shows the electronic device (the 3) to which an electro-optical apparatus is applied. It is a top view which shows the structure of the pixel circuit which concerns on contrast. It is a fragmentary sectional view which shows the structure of the pixel circuit which concerns on contrast. 14 is a partial cross-sectional view illustrating a configuration of a pixel circuit according to Modification Example 10. FIG.

Hereinafter, an electro-optical device according to an embodiment of the invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the embodiment. As shown in this figure, the electro-optical device 1 includes a display unit 100, a scanning line driving circuit 210, a power line driving circuit 220, and a data line driving circuit 230.
Among them, the display unit 100 is provided with m rows of scanning lines 112 along the horizontal (X) direction in the drawing, and n columns of data lines 114 along the vertical (Y) direction and each scanning. The wires 112 are provided so as to be electrically insulated from each other.
The pixel circuit 110 represents one pixel of an image to be displayed, and is provided corresponding to the intersection of the m rows of scanning lines 112 and the n columns of data lines 114. Therefore, in this embodiment, the pixel circuits 110 are arranged in a matrix and an image of horizontal n pixels × vertical m pixels is displayed. Note that m and n are both natural numbers.

  The display unit 100 is provided with individual power supply lines 116 and power supply lines 117 for each row. Although omitted in FIG. 1, a common electrode is provided over each pixel circuit 110 as will be described later, and the lower potential Vct of the element power supply is supplied. In order to distinguish rows such as the scanning lines 112 and the pixel circuits 110 for the sake of convenience, they may be referred to as 1, 2, 3,..., (M−1), m-th rows in order from the top in FIG. Similarly, in order to distinguish the columns of the data lines 114 and the pixel circuits 110 for convenience, they may be referred to as 1, 2, 3,..., (N−1), n-th column in order from the left in FIG.

  In the electro-optical device 1, a control circuit 200, a scanning line driving circuit 210, a power line driving circuit 220, and a data line driving circuit 230 are provided around the display unit 100 in which the pixel circuits 110 are arranged in a matrix. The control circuit 200 controls the operation of the scanning line driving circuit 210, the power supply line driving circuit 220, and the data line driving circuit 230, and also specifies gradation data that specifies the gradation (luminance) of the pixel to be expressed by each pixel circuit 110. Is supplied to the data line driving circuit 230.

  The scanning line driving circuit 210 applies scanning signals Gw (1), Gw (2), Gw (3),..., Gw to the scanning lines 112 of 1, 2, 3,. (m-1) and Gw (m) are supplied to sequentially scan the 1st to mth rows in each frame. In this description, the frame means a period required to display an image for one cut (frame) on the electro-optical device 1, and if the vertical scanning frequency is 60 Hz, 16.67 for one cycle. A period of milliseconds.

The power line driver circuit 220 supplies signals Vel (1), Vel (2), Vel (3),..., Vel (1, 2) to the power lines 116 of 1, 2, 3,. m-1) and Vel (m) are supplied, and the potentials of these signals are switched between a lower potential Vel_L and a higher potential Vel_H in synchronization with scanning by the scanning line driving circuit 210. In addition, the power supply line driving circuit 220 supplies ramp signals Vrmp (1), Vrmp (2), Vrmp (3), ..., Vrmp (m-1), Vrmp (m) are supplied in synchronization with scanning by the scanning line driving circuit 210.
Note that this embodiment can be applied to a mode in which a fixed potential is supplied to the power supply line 117 for at least a certain period depending on a driving method of the pixel circuit.

  The data line driver circuit 230 supplies an initialization potential or a data signal having a potential corresponding to the gradation data of the pixel circuit 110 to the pixel circuit 110 located in the row scanned by the scanning line driver circuit 210. It is supplied via the line 114. For convenience, the data signals supplied to each of the data lines 114 of 1, 2, 3,..., (N−1) and the n-th column are represented by Vd (1), Vd (2), Vd (3), respectively. , ..., Vd (n-1), Vd (n).

  An equivalent circuit of the pixel circuit 110 will be described with reference to FIG. In FIG. 2, the (i + 1) -th row scanning line 112 adjacent to the i-th row and the i-th row, and the (j + 1) -th column data line 114 adjacent to the j-th column and the j-th row are shown. A pixel circuit 110 corresponding to a total of 4 pixels of 2 × 2 corresponding to the intersections is shown. Here, i and (i + 1) are symbols for generally indicating the rows in which the pixel circuits 110 are arranged, and are integers of 1 or more and m or less. Similarly, j and (j + 1) are symbols for generally indicating a column in which the pixel circuit 110 is arranged, and are integers of 1 or more and n or less.

As shown in FIG. 2, each pixel circuit 110 includes N-channel transistors 130 and 140, capacitor elements 135 and 137, and a light emitting element 150. Here, since each pixel circuit 110 has the same configuration when viewed electrically, the pixel circuit 110 is representatively described as being located in i rows and j columns.
In the transistor 130, the gate is electrically connected to the i-th scanning line 112,
The drain is electrically connected to the data line 114 in the j-th column, and the source is connected to one end of the capacitive element 135 (hereinafter sometimes referred to as “first electrode”) and the gate of the transistor 140. That is, the transistor 130 is electrically connected between the data line 114 and the transistor 140 and functions as a writing transistor that controls the electrical connection between the data line 114 and the transistor 140.
The drain of the transistor 140 is connected to the i-th power line 116. The source of the transistor 140 is electrically connected to the other end of the capacitor 135 (hereinafter also referred to as a “second electrode”), one end of the capacitor 137, and the anode of the light-emitting element 150. ing. The transistor 140 functions as a driving transistor that passes a current according to the voltage between the gate and the source of the transistor 140.
As described above, the capacitor element 135 includes the first electrode electrically connected to the gate of the transistor 140 and the second electrode electrically connected to the source of the transistor 140. In other words, the capacitor 135 functions as a first storage capacitor that holds a voltage between the gate and the source of the transistor 140.
One end of the capacitor 137 is electrically connected to the source of the transistor 140, and the other end is electrically connected to the i-th feeder line 117. That is, the capacitive element 137 functions as a second storage capacitor that is electrically interposed between the source of the transistor 140 and the power supply line 117.
Note that the sources and drains of the transistors 130 and 140 in the above may be interchanged depending on the channel type and potential relationship of the transistors 130 and 140. The transistor may be a thin film transistor or a field effect transistor.

  Hereinafter, a connection wiring that electrically connects the drain of the transistor 130 and the scanning line 112 is referred to as a drain node D of the transistor 130, and a connection wiring that electrically connects the drain of the transistor 140 and the power supply line 116. May be referred to as the drain node d of the transistor 140. In addition, a connection wiring (first connection wiring) that electrically connects the gate of the transistor 140, the source of the transistor 130, and one end of the capacitor 135 may be referred to as a gate node g of the transistor 140. Further, a connection wiring (second connection wiring) that electrically connects the source of the transistor 140, the other end of the capacitor 135, the anode of the light emitting element 150, and one end of the capacitor 137 is connected to the source node s of the transistor 140. Sometimes called.

  The anode of the light emitting element 150 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the light emitting element 150 is commonly connected across the pixel circuit 110 to the common electrode 118 maintained at the potential Vct. The light-emitting element 150 is an OLED having a structure in which a light-emitting layer made of an organic EL material is sandwiched between an anode and a cathode facing each other, and emits light with a luminance corresponding to a current flowing from the anode toward the cathode. Further, a capacitive component 152 is generated between the anode and the cathode of the light emitting element 150.

In FIG. 2, Gw (i) and Gw (i + 1) indicate scanning signals supplied to the scanning lines 112 in the i and (i + 1) th rows, respectively. Vel (i) and Vel (i + 1) indicate signals supplied to the power line 116 in the i and (i + 1) th rows, respectively, and Vrmp (i) and Vrmp (i + 1) are i and ( The ramp signal supplied to the power supply line 117 in the (i + 1) th row is shown. Vd (j) and Vd (j + 1) represent data signals supplied to the data lines 114 in the j and (j + 1) th columns, respectively.
In this embodiment, the gate and source of the transistor 140 are shielded from the adjacent data line 114, and details of this structure will be described later.

The operation of the electro-optical device 1 will be described with reference to FIG. FIG. 3 is a diagram for explaining the operation of each unit in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 210 switches the potentials of the scanning signals Gw (1) to Gw (m) under the control of the control circuit 200, thereby scanning the 1st to mth rows in one frame. The line 112 is sequentially scanned every horizontal scanning period (H).
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, the following description will be made focusing on the pixel circuit 110 in the j-th column of the i-th row when the i-th scanning line 112 is scanned.

  In this embodiment, the scanning period of each scanning line 112 is roughly divided into an initialization period, a set period, and a writing period in order of time. Among these, the initialization period and the set period are continuous in time, and the set period and the write period are discontinuous in time.

  Here, the scanning line driving circuit 210 outputs the following scanning signal Gw (i) under the control of the control circuit 200. That is, the scanning line driving circuit 210 sets the scanning signal Gw (i) to the H level in the initialization period and the set period in the scanning period of the i-th scanning line 112, and starts the writing period from the end of the set period. It is set to L level in the period up to the time, H level is again set in the writing period, and L level is set from the end of the writing period to the initial period of the i-th row in the next frame.

The power line drive circuit 220 outputs the following signal Vel (i) and ramp signal Vrmp (i) according to the control by the control circuit 200, respectively.
That is, the power supply line driving circuit 220 sets the signal Vel (i) supplied to the power supply line 116 in the i-th row to the potential Vel_L that is the first power supply potential in the initialization period, and the second power supply potential after the set period. A certain potential Vel_H is set. Note that the timing at which the potential Vel (i) transitions from the potential Vel_H to the potential Vel_L is at the start of the initialization period in FIG. 3, but for the purpose of shortening the light emission period of the light-emitting element 150, In some cases, the potential Vel_L may be shifted to the previous timing.

  Further, the power supply line driving circuit 220 applies the ramp signal Vrmp (i) supplied to the i-th power supply line 117 from the potential Vx to the potential from the start to the end of the scanning period of the i-th scanning line 112. Decrease linearly to Vref (Vx> Vref). Note that the difference between the potential Vx and the potential Vref is actually very small, and the influence of the potential decrease of the ramp signal Vrmp (i) on each part of the pixel circuit 110 is so small that it can be ignored.

  The data line driving circuit 230 supplies the following data signals Vd (1) to Vd (n) to the corresponding data lines 114 in accordance with control by the control circuit 200, respectively. That is, the data line driving circuit 230 outputs the data signals Vd (1) to Vd (n) over the initialization period, the set period, and the period from the end of the set period to the timing Ts when the time T has elapsed. The initialization potential Vofs is set all at once, and the pixel corresponding to the intersection of the i-th row and the first to n-th columns is designated from the timing Ts until the scanning period of the next (i + 1) -th scanning line 112 starts. The potential is set according to the gradation data. Therefore, for example, the data signal Vd (j) supplied to the data line 114 in the j-th column becomes the initialization potential Vofs over the period from the start of the initialization period to the timing Ts, as shown in FIG. The potential Vsig corresponds to the gradation data specified for the pixel circuit 110 in the i row and j column over the period from the timing Ts until the scanning period of the next (i + 1) th scanning line 112 starts.

Now, in the initialization period of the i-th row, the potential Gw (i) of the scanning signal transitions to the H level and the transistor 130 is turned on, so that the gate node g of the transistor 140 is electrically connected to the data line 114. It will be in the state. Since the data signal Vd (j) supplied to the data line 114 in the initial period is at the potential Vofs, the gate node g is also at the potential Vofs.
On the other hand, the signal Vel (i) supplied to the i-th power line 116 is at the potential Vel_L. In the present embodiment, the difference voltage (Vofs−Vel_L) obtained by subtracting the potential Vel_L from the potential Vofs is set to sufficiently exceed the threshold voltage Vth_tr of the transistor 140. Therefore, since the transistor 140 is driven in the initialization period, the source node s (the anode of the light-emitting element 150) is initialized to the potential Vel_L.

  Accordingly, the voltage between the gate and the source of the transistor 140, that is, the voltage held by the capacitor 135 is initialized to a differential voltage between the potential Vofs and the potential Vel_L. Note that since the potential Vel_L is set so that the potential difference between the potential Vel_L and the potential Vct of the common electrode 118 is less than the light emission threshold voltage Vth_oled of the light emitting element 150, the light emitting element 150 in the initialization period It is an off state (non-light emitting state).

  Next, since the scanning signal Gw (i) is continuously at the H level in the set period of the i-th row, the transistor 130 continues to be on, so that the gate node g of the transistor 140 maintains the initialization potential Vofs. . Since the signal Vel (i) transitions to the higher potential Vel_H at the start of the set period, the current flows from the power supply line 116 to the drain and source of the transistor 140. As a result, the potential of the source node s of the transistor 140 increases. start. In addition, since the gate node g of the transistor 140 is maintained at the initialization potential Vofs, the voltage between the gate and the source of the transistor 140 gradually decreases. At this time, since the potential of the ramp signal Vrmp (i) changes with time, the current flowing between the drain and source of the transistor 140 branches to both sides of the light emitting element 150 side and the capacitor element 137 side. To do.

Among these, the current flowing to the light emitting element 150 side flows into the capacitive component 152 of the light emitting element 150 and starts to charge the capacitive component 152. When this charging is completed soon, the current flowing between the drain and source of the transistor 140 does not flow to the light emitting element 150 side but flows only to the capacitor element 137 side.
On the other hand, in this embodiment, the potential of the ramp signal Vrmp (i) decreases linearly and the rate of decrease is constant. For this reason, after the charging of the capacitive component 152 is completed, the current flowing through the path of the power supply line 116 → the drain d → the source s → the capacitive element 137 becomes substantially constant. Hereinafter, such a current flowing through the path of the power supply line 116 → the drain d → the source s → the capacitive element 137 will be referred to as a set current.

At the end of the set period, the voltage between the gate and the source of the transistor 140 becomes substantially equal to the voltage Vgs1 required for the set current to flow through the transistor 140. Therefore, the source node s of the transistor 140 is set to a potential (Vofs−Vgs1) that is lower than the initialization potential Vofs (the potential of the gate node g) by the voltage Vgs1.
In the present embodiment, the difference between the potential (Vofs−Vgs1) and the potential Vct, that is, the voltage across the light emitting element 150 is set to be lower than the light emission threshold voltage Vth_oled of the light emitting element 150. Accordingly, the light-emitting element 150 is in a non-light-emitting state even during the set period.

The voltage Vgs1 is expressed by the following equation (1).
Vgs1 = Vth_tr + Va (1)
In Expression (1), Vth_tr is a threshold voltage of the transistor 140, and Va is a voltage corresponding to the set current. Therefore, it can be said that the voltage between the gate and the source of the transistor 140 is set to a voltage corresponding to the threshold voltage of the transistor 140 in the set period.

  Subsequently, when the set period of the i-th row is completed, the scanning signal Gw (i) transitions to the L level, so that the transistor 140 is turned off, and the gate node g of the transistor 140 is in a floating (high impedance) state. It becomes. On the other hand, even if the set period is completed, the potential of the ramp signal Vrmp (i) decreases linearly, so that the set current continues to flow through the capacitive element 137. Here, as the mobility μ of the transistor 140 increases, the value of the current flowing through the transistor 140 increases and the amount of increase in the source potential also increases. Conversely, the smaller the mobility μ, the smaller the value of the current flowing through the transistor 140. In other words, as the mobility μ increases, the amount of decrease in the voltage between the gate and the source of the transistor 140 (negative feedback amount) increases. On the other hand, as the mobility μ decreases, the amount of decrease in the voltage between the gate and source (negative feedback). Amount) becomes smaller. Thereby, even if the mobility μ of the transistor 140 is different for each pixel circuit 110, the difference is compensated.

  In the present embodiment, as shown in FIG. 3, the data signal Vd (j) supplied to the j-th data line 114 at the timing Ts when the time T has elapsed from the end of the set period is the initialization potential Vofs. To the potential Vsig corresponding to the gradation data.

  In the writing period of the i-th row, the potential Gw (i) of the scanning signal transitions again to the H level and the transistor 130 is turned on, so that the gate node g of the transistor 140 is electrically connected to the data line 114. As a result, the potential Vsig of the data signal Vd (j) is obtained. For this reason, a current corresponding to the potential Vsig flows from the drain of the transistor 140 toward the source, so that the potential of the source node s rises. On the other hand, since the potential of the ramp signal Vrmp (i) continues to decrease, a current flows through the capacitive element 137. Then, the current that flows from the drain to the source in the transistor 140 branches and flows into the capacitor 135 and the capacitor 137. At this time, as the current flowing through the transistor 140 increases in accordance with the potential Vsig, the current flowing into the capacitor 135 increases, and as a result, the amount of increase in the potential of the source node s of the transistor 140 (that is, the decrease in the voltage between the gate and the source). Amount) also increases.

Further, as described above, the operation for compensating the mobility μ of the transistor 140 is continuously executed in this writing period. At the end of the writing period, the voltage between the gate and the source of the transistor 140 (the holding voltage of the capacitor 135) reflects the potential Vsig of the data signal Vd (j) and the characteristics (mobility μ) of the transistor 140. Is set to the specified value. Specifically, the gate-source voltage Vgs2 of the transistor 140 at the end of the writing period is expressed by the following equation (2).
Vgs2 = Vgs1 + ΔV = Vth_tr + Va + ΔV (2)
ΔV in Expression (2) is a value corresponding to the potential Vsig and the characteristics (mobility μ) of the transistor 140.
Further, at the end of the writing period, the difference between the potential of the source node s of the transistor 140 and the potential Vct, that is, the voltage across the light emitting element 150 is set to be lower than the light emission threshold voltage Vth_oled of the light emitting element 150. Accordingly, the light emitting element 150 is in a non-light emitting state even during the writing period.

When the writing period of the i-th row ends, the potential Gw (i) of the scanning signal transitions to the L level, so that the transistor 140 is turned off and the gate node g is in a floating state. Further, since the potential decrease of the ramp signal Vrmp (i) is also completed, the set current flowing through the capacitor element 137 becomes zero. Here, the voltage across the capacitor 135 (the voltage between the gate and the source of the transistor 140) is maintained at the voltage Vgs2 at the end of the writing period, so that a current corresponding to the voltage Vgs2 flows through the transistor 140. The potential of the source node s rises with time. Since the gate node g in the transistor 140 is in a floating state, the potential of the gate node g rises in conjunction with the potential of the source node s.
Eventually, the potential of the source node s rises with time while the voltage between the gate and the source of the transistor 140 is maintained at the voltage Vgs2 set at the end of the writing period.
When the voltage across the light emitting element 150, which is the difference between the potential of the source node s and the potential Vct, exceeds the light emission threshold voltage Vth_oled of the light emitting element 150, current starts to flow through the light emitting element 150, and the luminance corresponding to the current The light emission starts.

Assuming that the transistor 140 operates in the saturation region, the current Iel flowing through the light emitting element 150 is expressed by the following equation (3). Note that β is a gain coefficient of the transistor 140 transistor.
Iel = (β / 2) (Vgs2−Vth_tr) ² (3)
By substituting equation (2), equation (3) can be modified as follows.
Iel = (β / 2) (Vth_tr + Va + ΔV−Vth_tr) ²
= (Β / 2) (Va + ΔV) ²
Eventually, the current Iel flowing through the light emitting element does not depend on the threshold voltage Vth_tr of the transistor 140. Therefore, even if the threshold voltage Vth_tr is different for each pixel circuit 110, the difference is compensated and luminance unevenness is suppressed. become.

By the way, in this embodiment, in the scanning period of the i-th row, the scanning signal Gw (i) is at the L level from the end of the set period to the start of the writing period, and the transistor 130 is turned off. The gate of is floating. Here, since the data line 114 changes from the initialization potential Vofs to the potential Vsig at the timing Ts, the potential change propagates to the gate g and the source s of the transistor 140 via the parasitic capacitance (not shown), and the set period At the end, the voltage Vgs1 set between the gate and source of the transistor 140 is changed. For this reason, the occurrence of display spots, vertical stripes, etc. is caused, and this becomes a factor of greatly reducing the display quality.
Therefore, in the present embodiment, the pixel circuit 110 is configured as follows so that the pixel circuit 110 is less affected by potential fluctuations in the data line 114.

The structure of the pixel circuit 110 will be described with reference to FIGS.
4 is a plan view showing the configuration of the pixel circuit 110 in i row and j column, FIG. 5 is a partial cross-sectional view taken along line E-e in FIG. 4, and FIG. It is the fragmentary sectional view cut | disconnected by f line | wire. In FIG. 4, the FF line is perpendicular to the Y axis. Here, the Y axis is a direction parallel to the data line. That is, FIG. 6 shows a cut surface obtained by cutting the pixel circuit 110 in a plane orthogonal to the Y axis (that is, the data line 114) in FIG.
FIG. 4 shows a wiring structure when the pixel circuit 110 having the top emission structure is viewed in plan from the observation side. For simplification, the pixel circuit 110 is formed after the pixel electrode (anode) in the light emitting element 150. The structure is omitted. 5 and FIG. 6, only the pixel electrode of the light emitting element 150 is shown, and the subsequent structures are omitted. In addition, in each of the following drawings, the scales may be varied in order to make each layer, each member, each region, etc., recognizable.

As shown in FIG. 5, each element constituting the pixel circuit 110 is formed on the substrate 2. In the present embodiment, the substrate 2 is a plate-like member made of various insulating materials such as glass and plastic.
As shown in FIG. 5, semiconductor layers 130 a and 140 a are provided on the substrate 2. The semiconductor layer 130a functions as a semiconductor layer of the transistor 130, and the semiconductor layer 140a functions as a semiconductor layer of the transistor 140.

  As shown in FIGS. 5 and 6, a gate insulating layer L <b> 1 (first insulating layer) is provided so as to cover the semiconductor layer 130 a, the semiconductor layer 140 a, and the substrate 2. By patterning a wiring layer made of a conductive material such as aluminum on the surface of the gate insulating layer L1, a scanning line 112, a branch portion 112a, a relay node N11, a relay node Sa1, and a relay node Sb1 are formed. Is done. Hereinafter, the plurality of elements formed on the surface of the gate insulating layer L1 may be collectively referred to as a first wiring layer.

As shown in FIG. 4, the scanning line 112 extends in the X direction intersecting with the Y-axis direction, and has a portion (branching portion 112 a) branched in the Y direction for each pixel circuit 110.
The branch portion 112a is a part of the branch portion 112a and the central portion of the semiconductor layer 130a when viewed in plan (that is, when the pixel circuit 110 is viewed from a direction perpendicular to the surface of the substrate 2 where the pixel circuit 110 is disposed). Are provided so as to overlap each other. A portion of the branch portion 112 a that overlaps the semiconductor layer 130 a when viewed in plan corresponds to the gate 130 g of the transistor 130. In addition, a portion of the semiconductor layer 130 a that overlaps with the branch portion 112 a when seen in a plan view corresponds to the channel region 130 c of the transistor 130.
In FIG. 4, a region of the semiconductor layer 130a located on the negative side in the X direction from the channel region 130c (that is, the left side in the drawing) corresponds to the drain region 130d of the transistor 130, and is closer to the X direction than the channel region 130c. A region located on the positive side (that is, the right side in the drawing) corresponds to the source region 130 s of the transistor 130.

Further, the relay node N11 is provided between the relay node Sa1 and the relay node Sb1 when viewed in a plan view, and a part of the relay node N11 and the central portion of the semiconductor layer 140a are overlapped ( (See FIG. 4). A portion of the relay node N11 that overlaps the semiconductor layer 140a when seen in a plan view corresponds to the gate 140g of the transistor 140.
In addition, a portion of the semiconductor layer 140 a that overlaps with the relay node N <b> 11 in plan view corresponds to the channel region 140 c of the transistor 140.
Note that in FIG. 4, a region of the semiconductor layer 140 a located on the positive side in the Y direction (that is, the lower side in the drawing) of the channel region 140 c corresponds to the drain region 140 d of the transistor 140. A region located on the negative side of the direction (that is, the upper side in the drawing) corresponds to the source region 140 s of the transistor 140.

  As shown in FIG. 4, the relay node Sa1 is formed in a rectangle extending in the Y direction along the j-th data line 114 formed later when viewed in plan. In the present specification, the rectangle extending in the Y direction means a shape whose width in the X direction is shorter than the width in the Y direction. The relay node Sa1 corresponds to a second relay electrode formed in the same wiring layer (first wiring layer) as the gate 140g of the transistor 140. The relay node Sb1 is formed in a rectangle extending in the Y direction along the data line 114 of the (j + 1) th column to be formed later when viewed in plan.

  As shown in FIGS. 5 and 6, the second insulating layer L2 is formed so as to cover the scanning line 112, the branching portion 112a, the relay nodes N11, Sa1, Sb1, and the gate insulating layer L1. The relay nodes N21 to N27, the relay node Sa2, and the relay node Sb2 are formed on the surface of the second insulating layer L2 by patterning a wiring layer made of a conductive material. Hereinafter, the plurality of elements formed on the surface of the second insulating layer L2 may be collectively referred to as a second wiring layer.

As shown in FIG. 4, the relay nodes N21 and N22 are provided so as to be positioned between the relay node Sa1 and the relay node Sb1 when viewed in plan.
Although not shown, when viewed in plan, the relay node Sa2 is formed in a rectangle extending in the Y direction along the j-th data line 114 to be formed later, and the relay node Sb2 Is formed in a rectangle extending in the Y direction along the data line 114 of the (j + 1) th column to be formed later.

As shown in FIG. 5, the relay node N23 is electrically connected to the drain region 130d of the transistor 130 through a contact hole H21 that penetrates the gate insulating layer L1 and the second insulating layer L2. Similarly, the relay node N24 is electrically connected to the source region 130s of the transistor 130 via the contact hole H22, and the relay node N25 is electrically connected to the relay node N11 via the contact hole H23. The relay node N26 is electrically connected to the source region 140s of the transistor 140 through the contact hole H24, and the relay node N27 is electrically connected to the drain region 140d of the transistor 140 through the contact hole H25. .
As shown in FIG. 6, the relay node Sa2 is electrically connected to the relay node Sa1 through a contact hole Hsa2 that penetrates the second insulating layer L2. Similarly, relay node Sb2 is electrically connected to relay node Sb1 through contact hole Hsb2.
In FIG. 4, the contact hole is a portion where different wiring layers overlap each other, a portion where “□” is marked with “□” (for example, contact hole H51), or a portion where hatching is given (for example, This is shown as a contact hole Hsa4).

  As shown in FIGS. 5 and 6, the third insulating layer L3 is formed so as to cover the relay nodes N21 to N27, Sa2, Sb2, and the second insulating layer L2. Relay nodes N31 to N37, relay nodes Sa3 and Sb3, branch portions 117a and 117b, and a feeder line 117 are formed on the surface of the third insulating layer L3 by patterning a wiring layer made of a conductive material. Is done. Hereinafter, the plurality of elements formed on the surface of the third insulating layer L3 may be collectively referred to as a third wiring layer.

As shown in FIG. 4, the power supply line 117 extends in the X direction and has a portion (a branching portion 117 a and a branching portion 117 b) branched in the Y direction for each pixel circuit 110.
The branch part 117a is provided so that a part of the branch part 117a and a part of the relay node N22 overlap each other when seen in a plan view. A part of the branching part 117a and a part of the relay node N22 sandwich the third insulating layer L3, so that the capacitive element 137 is formed. That is, the relay node N22 functions as one end of the capacitive element 137, and the branch portion 117a functions as the other end of the capacitive element 137.

  As shown in FIG. 4, the relay node N31 is provided so that a part of the relay node N21 and a part of the relay node N31 overlap each other when seen in a plan view. Then, a part of the relay node N21 and a part of the relay node N31 sandwich the third insulating layer L3, whereby the capacitive element 135 is formed. That is, the relay node N21 functions as the first electrode of the capacitor 135, and the relay node N31 functions as the second electrode of the capacitor 135.

  Although not shown, the relay node Sa3 is formed in a rectangle extending in the Y direction along the j-th data line 114 to be formed later in plan view, and the relay node Sb3. Are formed in a rectangle extending in the Y direction along the data line 114 of the (j + 1) th column to be formed later when viewed in a plan view.

As shown in FIG. 5, the relay node N32 is electrically connected to the relay node N23 through a contact hole H31 that penetrates the third insulating layer L3. Similarly, the relay node N33 is electrically connected to the relay node N24 via the contact hole H32, and the relay node N34 is electrically connected to the relay node N25 via the contact hole H33. Is electrically connected to relay node N21 via contact hole H34, relay node N36 is electrically connected to relay node N26 via contact hole H35, and relay node N37 connects contact hole H36. Via the relay node N27.
As shown in FIG. 6, the relay node Sa3 is electrically connected to the relay node Sa2 through a contact hole Hsa3 that penetrates the third insulating layer L3. Similarly, the relay node Sb3 is electrically connected to the relay node Sb2 through the contact hole Hsb3.

  As shown in FIGS. 5 and 6, the fourth insulating layer L4 is formed so as to cover the relay nodes N31 to N37, Sa3 and Sb3, the branching portions 117a and 117b, the feeder line 117, and the third insulating layer L3. The By patterning a wiring layer made of a conductive material, the relay nodes N41 to N43, the relay nodes Sa4 and Sb4, the power supply line 116, and the branch portion 116a are formed on the surface of the fourth insulating layer L4. . Hereinafter, the plurality of elements formed on the surface of the fourth insulating layer L4 may be collectively referred to as a fourth wiring layer.

  As shown in FIG. 4, the power supply line 116 extends in the X direction and has a portion (branch portion 116 a) branched in the Y direction for each pixel circuit 110.

As shown in FIG. 5, the relay node N43 is electrically connected to the relay node N32 via a contact hole H41 that penetrates the fourth insulating layer L4.
The relay node N41 is electrically connected to the relay node N33 via the contact hole H42, is electrically connected to the relay node N34 via the contact hole H43, and is connected to the relay node N35 via the contact hole H44. Is electrically connected. Therefore, the gate 140g of the transistor 140 is electrically connected to the source region 130s of the transistor 130 via the relay nodes N11, N25, N34, N41, N33, and N24, and the relay nodes N11, N25, N34, It is electrically connected to the relay node N21 (first electrode of the capacitive element 135) via N41 and N35.
That is, the relay nodes N11, N25, N34, N41, N33, N24, N35, and N21 and the contact hole that connects them correspond to the gate node g (first connection wiring) of the transistor 140.

Relay node N42 is electrically connected to relay node N31 via contact hole H45, and is also electrically connected to relay node N36 via contact hole H46. Therefore, the source region 140s of the transistor 140 is
It is electrically connected to the relay node N31 (second electrode of the capacitive element 135) via the relay nodes N26, N36, and N42 (see FIG. 5), and also connected to the relay node via the relay nodes N26, N36, and N42. N22 (one end of the capacitor 137) is electrically connected (see FIG. 4).
That is, the relay nodes N26, N36, N42, N31, and N22 and the contact hole that connects them correspond to the source node s (second connection wiring) of the transistor 140.
Note that the gate-source voltage of the transistor 140 is held by the capacitor 135. That is, the gate node g (first connection wiring) and the source node s (second connection wiring) of the transistor 140 correspond to a potential holding unit that holds a voltage between the gate and the source of the transistor 140.

  Branch 116a is electrically connected to relay node N37 via contact hole H47. For this reason, the drain region 140d of the transistor 140 is electrically connected to the power supply line 116 through the relay nodes N27 and N37 and the branching portion 116a. That is, the relay nodes N27 and N37, the branch part 116a, and the contact hole connecting them correspond to the drain node d of the transistor 140.

  As shown in FIG. 4, the relay node Sa4 is formed in a rectangle extending in the Y direction along the j-th data line 114 formed later when viewed in plan. Further, the relay node Sb4 is formed in a rectangle extending in the Y direction along the data line 114 of the (j + 1) th column to be formed later when viewed in plan.

As shown in FIG. 6, the relay node Sa4 is electrically connected to the relay node Sa3 via a contact hole Hsa4 that passes through the fourth insulating layer L4, and also has a contact hole Ha that passes through the fourth insulating layer L4. Is electrically connected to the branching portion 117a. Similarly, the relay node Sb4 is electrically connected to the relay node Sb3 via the contact hole Hsb4 and is also electrically connected to the branching portion 117b via the contact hole Hb.
Further, as shown in FIG. 6, the contact hole Hsa4 is formed in a rectangular shape extending in the Y direction along the j-th data line 114 to be formed later in plan view. Hsb4 is formed in a rectangle extending in the Y direction along the data line 114 of the (j + 1) th column to be formed later when viewed in a plan view.
The contact holes Hsa2, Hsa3, Hsb2, and Hsb2 described above are also formed in a rectangular shape that extends in the Y direction along the data line 114, similarly to the contact holes Hsa4 and Hsb4.

  As illustrated in FIGS. 5 and 6, the fifth insulating layer L5 is formed so as to cover the relay nodes N41 to N43, Sa4 and Sb4, the power supply line 116, the branching portion 116a, and the fourth insulating layer L4. A relay node N51, relay nodes Sa5 and Sb5, and a data line 114 are formed on the surface of the fifth insulating layer L5 by patterning a wiring layer made of a conductive material. Hereinafter, the plurality of elements formed on the surface of the fifth insulating layer L5 may be collectively referred to as a fifth wiring layer.

  As shown in FIG. 4, the data line 114 extends in the Y direction. Of the two data lines 114 shown in FIG. 4, the data line 114 located on the left side (the negative side in the X direction) is the jth column data line 114 and the right side (the positive side in the X direction). The data line 114 located at is the (j + 1) th column data line 114.

  As shown in FIG. 5, the data line 114 in the j-th column is electrically connected to the relay node N43 through a contact hole H51 that penetrates the fifth insulating layer L5. Therefore, the drain region 130d of the transistor 130 is electrically connected to the j-th data line 114 via the relay nodes N23, N32, and N43. That is, the relay nodes N23, N32, and N43 and the contact hole that connects them correspond to the drain node D of the transistor 130.

  As shown in FIG. 4, the relay node Sa5 is formed in a rectangle extending in the Y direction along the j-th data line 114 when viewed in plan. The relay node Sb5 is formed in a rectangle extending in the Y direction along the data line 114 in the (j + 1) th column when viewed in plan. The relay node Sa5 and the relay node Sb5 correspond to a first relay electrode formed in the same wiring layer (fifth wiring layer) as the data line 114.

As shown in FIG. 6, the relay node Sa5 is electrically connected to the relay node Sa4 via a contact hole Hsa5 that penetrates the fifth insulating layer L5. Similarly, the relay node Sb5 is electrically connected to the relay node Sb4 through the contact hole Hsb5.
The contact hole Hsa5 is formed in a rectangle extending in the Y direction along the j-th data line 114 when viewed in plan, and the contact hole Hsb5 is (j + 1) when viewed in plan. ) Along the data line 114 in the column, a rectangular shape whose length extends in the Y direction is formed.

As described above, the relay nodes Sa1 to Sa5 and the contact holes Hsa2 to Hsa5 are electrically connected to the feeder line 117 via the contact hole Ha and the branch portion 117a. Therefore, the relay nodes Sa1 to Sa5 and the contact holes Hsa2 to Hsa5 include the first shield part Sa that electrically shields the relay node N11 including the gate 140g and the relay nodes N21 and N22 from the j-th data line 114. Function as.
Of the first shield part Sa, each of the relay nodes Sa1 to Sa5 may be referred to as a relay electrode, and the contact holes Hsa2 to Hsa5 connecting the relay nodes Sa1 to Sa5 may be referred to as connection parts. That is, the first shield part Sa includes a plurality of relay electrodes and a connection part.
Further, the relay nodes Sb1 to Sb5 and the contact holes Hsb2 to Hsb5 are electrically connected to the feeder line 117 through the contact hole Hb and the branching portion 117b. Therefore, the relay nodes Sb1 to Sb5 and the contact holes Hsb2 to Hsb5 are the second shield that electrically shields the relay node N11 including the gate 140g and the relay nodes N21 and N22 from the data line 114 in the (j + 1) th column. It functions as the part Sb.
Of the second shield part Sb, each of the relay nodes Sb1 to Sb5 may be referred to as a relay electrode, and the contact holes Hsb2 to Hsb5 connecting the relay nodes Sb1 to Sb5 may be referred to as connection parts. That is, the second shield part Sb includes a plurality of relay electrodes and a connection part.

Here, the shapes of the first shield part Sa and the second shield part Sb will be described in detail with reference to FIG. FIG. 7 is a diagram showing a wiring structure when the pixel circuit 110 in the i row and j column is viewed in the same manner as FIG.
As shown in FIG. 7, the first shield part Sa (relay nodes Sa1 to Sa5 and contact holes Hsa2 to Hsa5) and the second shield part Sb (relay nodes Sb1 to Sb5 and contact holes Hsb2 to Hsb5) are respectively in the Y direction. In FIG. 5, the range ΔYs including the range ΔY1 is included. Here, the range ΔY1 is a range where the gate 140g of the transistor 140 exists in the Y direction of FIG. Therefore, the cut surface cut along line F1-f1 shown in FIG. 7 and the cut surface cut along line F2-f2 are equal to the cut surface cut along line Ff shown in FIG. That is, when a cut surface obtained by cutting the pixel circuit 110 so as to be orthogonal to the data line 114 and including the gate 140g of the transistor 140 is a first cut surface, FIG. 6 shows a partial cross section at an arbitrary first cut surface. Represents the figure. In other words, the first shield part Sa (the relay nodes Sa1 to Sa5 and the contact holes Hsa2 to Hsa5) and the second shield part Sb (the relay nodes Sb1 to Sb5 and the contact holes Hsb2 to Hsb5) at any first cut surface. Appears.
In an arbitrary first cut plane shown in FIG. 6, the line segment Ln1 connecting the data line 114 in the j-th column and the gate 140g intersects the first shield part Sa. Therefore, when viewed in cross section at an arbitrary first cut surface, the first shield part Sa is provided between the data line 114 in the j-th column and the gate 140g. As shown in FIG. 4, when viewed in plan, the first shield portion Sa is provided between the data line 114 in the j-th column and the gate 140g. Therefore, the first shield part Sa shields the gate 140g from the j-th column data line 114 in both a plan view and a cross-sectional view.
Similarly, the line segment Ln2 connecting the data line 114 and the gate 140g in the (j + 1) -th column intersects the second shield part Sb on any first cut surface. Therefore, when viewed in cross section at an arbitrary first cut surface, the second shield part Sb is provided between the data line 114 and the gate 140g in the (j + 1) th column. As shown in FIG. 4, when viewed in plan, the second shield portion Sb is provided between the data line 114 in the (j + 1) th column and the gate 140g.
Therefore, the second shield part Sb shields the gate 140g from the data line 114 in the (j + 1) th column, both in plan view and in cross section.

As shown in FIGS. 5 and 6, the sixth insulating layer L6 is formed so as to cover the relay node N51, the relay nodes Sa5 and Sb5, the data line 114, and the fifth insulating layer L5. The anode of the light emitting element 150 is formed on the surface of the sixth insulating layer L6 by patterning a conductive wiring layer such as aluminum or ITO (Indium Tin Oxide). The anode of the light emitting element 150 is an individual pixel electrode for each pixel circuit 110, and is electrically connected to the relay node N51 through a contact hole H61 penetrating the sixth insulating layer L6. That is, the anode of the light emitting element 150 is electrically connected to the source region 140s of the transistor 140 via the relay nodes N51, N42, N36, and N26, as shown in FIG.
In the electro-optical device 1, the structure after the anode of the light emitting element 150 is not shown, but a light emitting layer made of an organic EL material is laminated on the anode of the light emitting element 150 for each pixel circuit 110. Is done. On the light emitting layer, a cathode (common electrode 118) which is a common transparent electrode is provided over all of the plurality of pixel circuits 110. That is, the light emitting element 150 sandwiches the light emitting layer between the anode and the cathode facing each other, and emits light with a luminance corresponding to the current flowing from the anode toward the cathode. Of the light emitted from the light emitting element 150, the light traveling in the opposite direction to the substrate 2 (that is, upward in FIG. 5) is visually recognized as an image by the observer (top emission structure). In addition, a sealing material or the like for shielding the light emitting layer from the atmosphere is provided, but the description is omitted.

In the electro-optical device 1 according to the present embodiment, before referring to the effect of providing the first shield part Sa and the second shield part Sb, the first shield part Sa and the second shield part Sb are not compared. The problem in is explained.
FIG. 16 is a plan view showing the configuration of the pixel circuit 110a in proportion to each other, and FIG. 17 is a partial cross-sectional view taken along the line ZZ in FIG. The pixel circuit 110a according to the comparison does not have the first shield part Sa and the second shield part Sb unlike the pixel circuit 110 according to the embodiment shown in FIG. Therefore, when the potential of the data line 114 fluctuates, the potential fluctuation propagates to the gate 140g of the transistor 140, the relay node N22, and the like as shown in FIG. The relay node N22 is connected to the source region 140s of the transistor 140 via the relay node N42. Therefore, when viewed in the pixel circuit 110a in the j column, not only the j column corresponding to itself but also the adjacent (j + 1) column data line 114 has a potential variation, the potential variation is caused by the gate of the transistor 140. The voltage propagates to 140 g and the source region 140 s and fluctuates the voltage set between the gate and the source of the transistor 140, which causes the display quality to be greatly reduced.

In contrast, the pixel circuit 110 according to the present embodiment includes a first shield part Sa and a second shield part Sb.
The ramp signal Vrmp (i) is supplied to the first shield part Sa and the second shield part Sb via the feeder line 117. As described above, the difference between the potential Vx and the potential Vref is very small. In addition, the power supply line driving circuit 220 linearly and gently decreases the ramp signal Vrmp (i) from the potential Vx to the potential Vref from the start to the end of the scanning period of the i-th scanning line 112. In addition, a constant potential is maintained from the end of the scanning period of the i-th scanning line 112 to the start of the next i-th scanning line 112. Therefore, the first shield part Sa and the second shield part Sb to which the ramp signal Vrmp (i) is supplied cause the gate 140g of the transistor 140 to be connected to the j-th data line 114 and the (j + 1) -th data. It becomes possible to electrically shield from the line 114.
As described above, in this embodiment, even if the potential of the data line 114 in the j-th column and the (j + 1) -th column fluctuates, the potential variation is difficult to propagate to the gate 140g of the transistor 140. Can be prevented.
In particular, when the pixel size is further miniaturized, the distance between the wirings is narrowed, and it is easy to be affected by voltage fluctuations of adjacent wirings. For this reason, when the potential of the data line varies in a proportional manner, the potential variation propagates to the gate 140g and the source region 140s of the transistor 140. Then, the voltage set between the gate and the source of the transistor 140 fluctuates, and the problem that the display quality is greatly lowered becomes remarkable. On the other hand, with the configuration as in this embodiment, the potential fluctuation of the data line is propagated to the gate 140g and the source region 140s of the transistor 140, and the voltage set between the gate and the source of the transistor 140 is changed. The display quality can be prevented from deteriorating due to fluctuations in the potential of the data line. The present invention is particularly effective for an electro-optical device having a fine pixel with a pixel size of about 1 to 10 μm.

  As is apparent from FIGS. 4 and 6, the relay nodes N11, N21, N22, N31, and N42 are provided between the first shield part Sa and the second shield part Sb. Accordingly, the first shield part Sa and the second shield part Sb connect the source node s of the transistor 140 electrically connected to the relay node N42 to the j-th data line 114 and the (j + 1) -th data line 114, respectively. Shield from. As a result, even if the potential of the data line 114 in the j-th column and the (j + 1) -th column fluctuates, the potential variation is difficult to propagate to the source node s of the transistor 140, so that deterioration in display quality can be prevented. it can.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Modification 1>
In the embodiment described above, the ramp signal Vrmp (i) is supplied to the first shield part Sa and the second shield part Sb via the feeder line 117, but a fixed potential may be supplied.
FIG. 8 is a plan view illustrating a configuration of the pixel circuit 110 included in the electro-optical device according to the first modification. The electro-optical device according to the first modification includes a power supply line 119 for each row, and a fixed potential is supplied to the power supply line 119. As shown in FIG. 8, the power supply line 119 has a portion (a branch portion 119 a and a branch portion 119 b) branched in the Y direction for each pixel circuit 110. The branching unit 119a is connected to the relay node Sa1, and the branching unit 119b is connected to the relay node Sb1. That is, the first shield part Sa and the second shield part Sb are set to a fixed potential via the feeder line 119 (and the branch parts 119a and 119b).
In the pixel circuit 110 according to the first modification, the gate 140g and the source region 140s of the transistor 140 are connected to the j-th data line 114 and (j + 1) by the first shield part Sa and the second shield part Sb to which a fixed potential is supplied. It becomes possible to electrically shield from the data line 114 in the column. As a result, even if the potential of the data line 114 in the j-th column and the (j + 1) -th column fluctuates, the potential variation is difficult to propagate to the gate 140g and the source region 140s of the transistor 140, thereby preventing deterioration in display quality. can do.

<Modification 2>
In the pixel circuit 110 according to the embodiment and the modification described above, the first shield part Sa and the second shield part Sb are provided so as to shield the source region 140s and the gate 140g of the transistor 140 from the data line 114. The present invention is not limited to such a form. For example, the first shield part Sa and the second shield part may be provided to shield the source node s and the gate node g from the data line 114.
FIG. 9 is a plan view illustrating a configuration of a pixel circuit 110 according to Modification Example 2. FIG. 10 illustrates a range in which the first shield part Sa and the second shield part Sb provided in the pixel circuit 110 according to Modification Example 2 are provided. It is explanatory drawing for demonstrating.
As shown in FIG. 10, the first shield part Sa and the second shield part Sb are each provided so as to include a range ΔYs2 including the range ΔY2 in the Y direction of FIG. Here, the range ΔY2 is a range in which the potential holding portion (the gate node g and the source node s of the transistor 140) exists in the Y direction in FIG. That is, the pixel circuit 110 according to the second modification includes the gate node g (that is, the relay nodes N11, N21, N41, N24, N25, N33, and the like) of the transistor 140 between the first shield part Sa and the second shield part Sb. N34, N35, and a contact hole connecting them) and a source node s of the transistor 140 (that is, relay nodes N22, N31, N42, N26, N36, and a contact hole connecting them) are provided.
Therefore, when the pixel circuit 110 according to the second modification is viewed in plan, the first shield part Sa is provided between the data line 114 in the jth column and the potential holding unit, and the data line in the (j + 1) th column. A second shield part Sb is provided between 114 and the potential holding part.
Further, when a cut surface obtained by cutting the pixel circuit 110 so as to be orthogonal to the data line 114 and including the potential holding portion is a second cut surface, the data line 114 in the j-th column in any second cut surface. The line segment connecting the potential holding unit and the first shield unit Sa intersect, and the line segment connecting the data line 114 and the potential holding unit in the (j + 1) th column intersects the second shield unit Sb. Therefore, the first shield part Sa shields the potential holding part from the j-th data line 114 in both the plan view and the cross-sectional view, and the second shield part Sb places the potential holding part in the (j + 1) th column. The data line 114 is shielded.
As a result, even if the potential of the data line 114 in the j-th column and the (j + 1) -th column fluctuates, the potential variation is difficult to propagate to the potential holding unit (source node s and gate node g). A decrease can be prevented.

<Modification 3>
In the embodiment and the modification described above, the pixel circuit 110 includes the first shield part Sa and the second shield part Sb. However, the pixel circuit 110 does not include the second shield part Sb, and does not include the first shield part Sa. Only the part Sa may be provided.
FIG. 11 is a plan view showing the configuration of the pixel circuit 110 according to the third modification. The pixel circuit 110 according to the modification 3 includes the first shield part Sa between the gate 140g and the source region 140s of the transistor 140 and the data line 114 in the j-th column, but includes the gate 140g and the source region 140s (j + 1). ) No shield part is provided between the data line 114 in the column. Even in this case, the potential fluctuation of the data line 114 in the j-th column is difficult to propagate to the gate 140g and the source region 140s of the transistor 140, so that the display quality can be prevented from being deteriorated.

<Modification 4>
In the embodiment and the modification described above, each of the contact holes Hsa2 to Hsa5 is one contact hole. For example, as shown in FIG. 12, each of the contact holes Hsa2 to Hsa5 is a plurality of contacts. It may be a hall. Even in this case, the potential fluctuation of the data line 114 in the j-th column is difficult to propagate to the gate 140g and the source region 140s of the transistor 140, so that the display quality can be prevented from being deteriorated.
Similarly, each of the contact holes Hsb2 to Hsb5 may be a plurality of contact holes.

<Modification 5>
In the embodiment and the modification described above, the potential of the ramp signal supplied to the power supply line 117 decreases linearly. However, the present invention is not limited to this, and the mode of change of the potential output to the power supply line 117 is arbitrary. It is. For example, the waveform of the potential output to the feeder line 117 may be curved. In short, as long as the set current is supplied to the transistor 140, the potential output to the power supply line 117 only needs to change over time from the set period to the writing period. Further, if mobility compensation is not regarded as important, there is little need to flow a set current. Therefore, a configuration in which the feeder line 117 is set to a constant potential, that is, a configuration in which DC is supplied may be employed.

<Modification 6>
In the embodiment and the modification described above, a plate-like member made of various insulating materials such as glass and plastic is used as the substrate 2, but a semiconductor substrate may be used as the substrate 2.

<Modification 7>
In the embodiment and the modification described above, the transistor 130 and the transistor 140 in the pixel circuit 110 are unified with the N-channel type, but may be unified with the P-channel type. Further, the P channel type and the N channel type may be appropriately combined.

<Modification 8>
The pixel circuit 110 according to the embodiment and the modification described above includes five wiring layers from the first wiring layer to the fifth wiring layer. However, the present invention is not limited to such a form. The wiring layer may be configured with fewer wiring layers. For example, the second wiring layer and the third wiring layer may be the same layer. In this case, for example, the relay nodes N21 and N22 may be provided in the first wiring layer. For example, the fourth wiring layer and the fifth wiring layer may be the same layer. In this case, for example, the power supply line 116 may be provided in the first wiring layer or the second wiring layer. The third wiring layer, the fourth wiring layer, and the fifth wiring layer may be the same layer. In this case, for example, the power supply line 116 and the power supply line 117 may be provided in the first wiring layer or the second wiring layer.
Further, layers other than the five wiring layers from the first wiring layer to the fifth wiring layer and the six insulating layers from the first insulating layer to the sixth insulating layer may be provided. For example, a light shielding layer may be separately provided between the first wiring layer and the substrate 2. Further, for example, a wiring layer (hereinafter referred to as “0th wiring layer”) may be provided on the substrate 2 side with respect to the first wiring layer including the relay node N11 (gate 140g), and the data line 114 may be included. A wiring layer (hereinafter referred to as “sixth wiring layer”) may be separately provided on the anode side of the light emitting element 150 with respect to the fifth wiring layer.

<Modification 9>
In the embodiment and the modification described above, the first shield part Sa (and the second shield part Sb) is provided from the first wiring layer to the fifth wiring layer, but the present invention is limited to such a form. However, it may be formed only in a part of the first to fifth wiring layers.
Further, when the pixel circuit 110 includes wiring layers other than the five wiring layers from the first wiring layer to the fifth wiring layer as in the above-described modification 8, the first shield portion Sa (second shield portion) Sb) may also be formed to include wiring layers other than the five wiring layers from the first wiring layer to the fifth wiring layer. For example, the first shield part Sa (second shield part Sb) may be provided from the 0th wiring layer to the 6th wiring layer.
In any case, the first shield is formed such that the line segment Ln1 (Ln2) connecting the data line 114 and the gate 140g intersects the first shield part Sa (second shield part Sb) at an arbitrary first cut surface. A portion Sa (second shield portion Sb) may be provided. In this case, the first shield portion Sa (second shield) is arranged such that the line segment connecting the data line 114 and the potential holding portion intersects the first shield portion Sa (second shield portion Sb) at any second cut surface. A shield part Sb) may be provided.

<Modification 10>
In the embodiment and the modification described above, the first shield portion Sa is formed by a plurality of relay nodes Sa1 to Sa5 and a plurality of contact holes Hsa2 to Hsa5 that electrically connect each of the plurality of relay nodes. However, the present invention is not limited to such a form, and a part or all of the first shield part Sa may be formed by a contact plug.
FIG. 18 is a cross-sectional view of the pixel circuit 110 according to Modification 10 cut along a first cut surface that is orthogonal to the data line 114 and includes the gate 140g of the transistor 140. As illustrated in FIG. 18, the first shield unit Sa according to the modified example 10 includes the relay node Sa1 and the relay node Sa4 through the contact holes Hsa2, Hsa3, and Hsa4 instead of including the relay node Sa2 and the relay node Sa3. It is different from the first shield part Sa according to the embodiment shown in FIG. 6 in that it includes a contact plug CPa that is electrically connected. As shown in FIG. 18, the contact plug CPa is provided by injecting a conductive material into a plurality of contact holes provided at the same position when viewed in plan. Therefore, the contact plug CPa has a rectangular shape having a long side in the thickness direction (Z direction in the drawing) and a short side in the horizontal direction (X direction in the drawing) as shown in FIG. It becomes.
The first shield part Sa shown in FIG. 18 has a configuration in which the relay nodes Sa2 and Sa3 shown in FIG. 6 are replaced with contact plugs CPa, but all of the relay nodes Sa1 to Sa5 shown in FIG. 6 are used as contact plugs CPa. Alternatively, the first shield part Sa may be formed. In this case, since the width in the lateral direction (X direction in FIG. 4 and the like) of the first shield part Sa can be made narrower than that of the first shield part Sa according to the embodiment, the pixel circuit 110 can be further downsized. Is possible.
Further, as shown in FIG. 18, a part or all of the second shield part Sb may be formed by a contact plug CPb.

<Modification 11>
The pixel circuit 110 according to the embodiment and the modification described above includes the transistors 130 and 140, the capacitor elements 135 and 137, and the light emitting element 150, but the present invention is not limited to such a form. The capacitor 137 may not be provided.

<Modification 12>
As the light emitting element 150, in addition to the OLED, an element that emits light with luminance corresponding to a current, such as an inorganic EL element or an LED (Light Emitting Diode) element, can be used.

<Application example>
Next, an electronic apparatus using the electro-optical device 1 according to the embodiment will be described with an example.
FIG. 13 is a diagram illustrating an appearance of a personal computer as an electronic apparatus (part 1) in which the electro-optical device 1 according to the above-described embodiment is applied to a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.
In the electro-optical device 1, when an OLED is used for the light emitting element 150, an easy-to-view screen display with a wide viewing angle becomes possible.

  FIG. 14 is a diagram illustrating an appearance of a mobile phone that is an electronic apparatus (part 2) in which the electro-optical device 1 according to the embodiment is applied to a display device. The cellular phone 3000 includes the electro-optical device 1 described above together with the earpiece 3003 and the mouthpiece 3004 in addition to a plurality of operation buttons 3001 and direction keys 3002. By operating the direction key 3002, the screen displayed on the electro-optical device 1 is scrolled.

  FIG. 15 is a diagram illustrating an appearance of a personal digital assistant (PDA) as an electronic apparatus (part 3) in which the electro-optical device 1 according to the embodiment is applied to a display device. A portable information terminal 4000 includes the above-described electro-optical device 1 in addition to a plurality of operation buttons 4001 and direction keys 4002. In the portable information terminal 4000, various information such as an address book and a schedule book is displayed on the electro-optical device 1 by a predetermined operation, and the displayed information is scrolled in accordance with an operation of the direction key 4002.

  The electronic apparatus to which the electro-optical device according to the invention is applied includes, in addition to the examples shown in FIGS. 13 to 15, a television, a car navigation device, a pager, an electronic notebook, electronic paper, a calculator, a word processor, a work Stations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with a touch panel, and the like. In particular, examples of the micro display include a head-mounted display and an electronic viewfinder of a digital still camera or a video camera.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 110 ... Pixel circuit, 112 ... Scanning line, 114 ... Data line, 116 ... Power supply line, 117 ... Power supply line, 118 ... Common electrode, 130 ... Transistor, 135, 137 ... Capacitance element, 140 ... Transistor , 150... Light emitting element, 210... Scanning line driving circuit, 220... Power line driving circuit, 230... Data line driving circuit, Sa. s: source node, g: gate node.

Claims (8)

A scan line extending in a first direction;
A data line extending in a second direction intersecting the first direction;
A pixel circuit provided corresponding to the intersection of the scanning line and the data line;
With
The pixel circuit includes:
A driving transistor;
A capacitive element having one end electrically connected to the drive transistor and the other end electrically connected to a power supply line;
A light emitting element that emits light with a luminance corresponding to the magnitude of current supplied from the driving transistor;
A first shield part and a second shield part made of a conductive material;
Have
The capacitive element is provided between the first shield part and the second shield part.
An electro-optical device. The first shield part is
Intersects with a line segment connecting the capacitive element and the data line at an arbitrary pixel cut surface obtained by cutting the pixel circuit so as to include the capacitive element perpendicular to the data line;
The electro-optical device according to claim 1. The said 1st shield part is formed including the said electroconductive material arrange | positioned at at least 2 layer among the layers between the said capacitive element and the said data line, The said 1st shield part is formed. Or the electro-optical device according to 2; The first shield part is
A plurality of relay electrodes including a first relay electrode formed on the same wiring layer as the data line and a second relay electrode formed on the same wiring layer as the gate of the driving transistor; and the plurality of relays A connecting portion for connecting electrodes,
The relay electrode and the connection portion intersect the arbitrary pixel cut surface,
The electro-optical device according to claim 2. The connecting portion is
With multiple contact holes,
Of the plurality of relay electrodes, two relay electrodes formed in mutually adjacent wiring layers are connected by one contact hole among the plurality of contact holes,
The one contact hole intersects the arbitrary pixel cut surface.
The electro-optical device according to claim 4. A fixed potential is supplied to the first shield part.
The electro-optical device according to claim 1, wherein the electro-optical device is any one of the above. Before Symbol light-emitting element,
Electrically connected to one of the source or drain of the driving transistor;
The first shield part is
Electrically connected to the feeder line,
The electro-optical device according to claim 1, wherein the electro-optical device is any one of the above. An electronic apparatus comprising the electro-optical device according to claim 1.

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