JP6555379B2 - Electronic device and time display control method - Google Patents

Description

  The present invention relates to an electronic device having a display unit and a time display control method.

  2. Description of the Related Art Conventionally, there is an electronic device (electronic display device) that has a display unit and can display various types of information. In the electronic display device, various displays can be performed according to the improvement of the display screen. Conventionally, there is a technology that has a plurality of display units and uses a plurality of display units in accordance with display contents (for example, Patent Document 1).

JP 2006-101505 A

  However, in the case where a plurality of display screens are used, there is a problem in that these control operations need to be performed optimally in various situations in order to display them in various ways.

  An object of the present invention is to provide an electronic device and a time display control method capable of appropriately using various time displays.

In order to achieve the above object, the present invention provides:
A first processor;
A second processor;
A first display unit;
A second display;
With
The first processor can be set to any one of a normal mode, a low power mode, and a sleep mode,
In the normal mode or the low power mode, the first processor performs control to cause the first display unit to display time, and the second processor causes the second display unit to display time. Do no control and
In the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time .

  According to the present invention, there is an effect that various time displays can be properly used properly in an electronic device.

It is a front view of the smartwatch which is embodiment of the electronic device of this invention. It is a block diagram which shows the function structure of a smart watch. It is a front view which shows the example of the display state in case a smartwatch is in each power consumption mode. It is a flowchart which shows the control procedure of the display control process which main CPU performs. It is a flowchart which shows the control procedure of the display control process by sub CPU. It is a flowchart which shows the control procedure of the display control process of the modification 1 by main CPU. It is a flowchart which shows the control procedure of the display control process of the modification 1 by sub CPU. It is a flowchart which shows the control procedure of the display control process of the modification 2 by main CPU. It is a flowchart which shows the control procedure of the display control process of the modification 3 by main CPU. It is a flowchart which shows the control procedure of the display control process of the modification 3 by sub CPU.

Hereinafter, an embodiment in which the electronic device of the present invention is realized as a smart watch will be described with reference to the drawings.
FIG. 1 is a front view of a smart watch 100 that is an embodiment of the electronic apparatus of the present invention.

  As shown in FIG. 1A, the smart watch 100 is an arm-mounted electronic device that can mount the main body 1 on the user's arm using the band 2. The main body 1 of the smart watch 100 includes a frame 3, a display screen 4, a push button switch B1, and the like.

  The push button switch B1 is provided on the side surface of the frame 3 and accepts a user's pressing operation. The push button switch B1 is returned to a normal mode from a low power mode or a sleep mode, which will be described later, when pressed.

On the display screen 4, two display portions are stacked. As shown in FIG. 1B, a display screen 12a of the first display unit 12 (see FIG. 2) is provided at the lower part, and a display screen 22a of the second display unit 22 (see FIG. 2) is provided at the upper part. Is provided. That is, FIG. 1A shows a state where display is performed by the first display unit 12 and the display screen 22a of the second display unit 22 transmits the display by the first display unit 12.
A touch sensor (not shown) is provided at a further upper portion of the second display unit 22 and can accept a user operation together with the push button switch B1.

The first display unit 12 has a color liquid crystal display screen based on a dot matrix, and switches various displays related to various functions and / or performs them in parallel according to a user input operation or various program operations.
The second display unit 22 has a display screen that can display the time by simplified display with lower power consumption than the first display unit 12, and performs, for example, a monochrome liquid crystal display by a segment method. Alternatively, the display screen 22a of the second display unit 22 may be a memory in-pixel liquid crystal (MIP liquid crystal), a PN liquid crystal (Polymer Network), or the like. Further, the display screen 22a of the second display unit 22 can transmit the display contents of the first display unit 12 upward without applying any display by applying a predetermined voltage.

FIG. 2 is a block diagram showing a functional configuration of the smart watch 100 of the present embodiment.
The smart watch 100 includes a main microcomputer 11, a first display unit 12 (first display unit), an operation reception unit 13, a wireless communication controller 14, a satellite radio wave reception module 15, a sub-microcomputer 21, a second microcomputer A display unit 22 (second display unit), a switch 23, a PMIC 31 (Power Management IC), and the like are provided.

  The main microcomputer 11 is a main control unit including a main CPU 111 (first processor), a RAM 112, a storage unit 113, and the like. The main microcomputer 11 receives power supply from the power source under the control of the PMIC 31 and controls operations of the first display unit 12, the operation reception unit 13, the wireless communication controller 14, the satellite radio wave reception module 15, and the like.

The main CPU 111 performs various arithmetic processes and controls the operation of the smart watch 100 in a normal operation state.
The RAM 112 provides a working memory space to the main CPU 111 and stores temporary data. The RAM 112 stores and holds time information counted by the main CPU 111 as first clock means based on a clock signal (not shown). Hereinafter, the description of “time” may mean “date and time” including a date part.
The storage unit 113 is a non-volatile memory such as a flash memory that stores a control program executed by the main CPU 111 and setting data.

  The first display unit 12 described above is controlled mainly by the main microcomputer 11 (main CPU 111 (see FIG. 2)), but the display control is also performed by the sub microcomputer 21 (sub CPU 211 (see FIG. 2)). It is possible.

  The operation reception unit 13 includes the above-described push button switch B1 and the touch sensor, receives a user input operation, converts the operation content into an electric signal, and outputs the electric signal to the main CPU 111.

  The wireless communication controller 14 is a controller for performing wireless communication with an external electronic device. The wireless communication standard is not particularly limited, and examples thereof include short-range wireless communication such as Bluetooth (registered trademark: Bluetooth), wireless LAN (IEEE 802.11), and the like. The main microcomputer 11 (main CPU 111) can acquire necessary information, programs, update data, and the like from the outside via the wireless communication controller 14. Examples of external electronic devices that are communication connection targets include smartphones, mobile phones, tablet terminals, and PDAs (Personal Digital Assistants). Among these, in particular, in smartphones and mobile phones, time information is synchronized when connected to a base station, and time accuracy is maintained. When the main CPU 111 performs communication connection with a smartphone or a mobile phone, the main CPU 111 can acquire time information from these external devices, and can correct the counting time based on the acquired time information.

  The satellite radio wave receiving module 15 captures, receives and demodulates radio waves from positioning satellites, here at least radio waves from GPS (Global Positioning System) satellites (GPS satellites), and acquires time and performs positioning. It is a module that can be used. The satellite radio wave receiving module 15 has an antenna (not shown), and receives radio waves in the L1 band (1.57542 GHz for GPS satellites) based on the control of the main microcomputer 11 (main CPU 111) to perform reverse spectrum spreading. The navigation message is acquired, decoded, and output in a predetermined format.

  The sub microcomputer 21 includes a sub CPU 211 (second processor), an RTC 212 (real time clock, second clock means), and the like. The sub-microcomputer 21 operates by receiving power supply from the power source under the control of the PMIC 31 and mainly controls the operation of the second display unit 22.

  The sub CPU 211 performs various arithmetic processes and controls the operation of the sub microcomputer 21. The sub CPU 211 may have lower power consumption than the main CPU 111 and may have lower capacity than the main CPU 111. For example, the sub CPU 211 operates only when a predetermined predetermined operation is performed, or when an input from the main CPU 111 or the switch 23 is detected, and waits in a standby state during other periods. It's okay.

  The RTC 212 is a normal one that performs timekeeping operation, and preferably has low power consumption.

  As described above, the second display unit 22 consumes less power than the first display unit 12 and is used for displaying time during the display operation. When the MIP liquid crystal is used for the display screen, the sub CPU 211 can reduce the update frequency of the display content, so that it can be in a standby state during the update interval.

  The switch 23 is an on switch that accepts a predetermined user operation for restarting the main microcomputer 11 when the main microcomputer 11 is in a dormant state. The switch 23 may be provided exclusively or may be used in combination with the push button switch B1.

  The PMIC 31 controls power supply from the power source to the main microcomputer 11 and the sub-microcomputer 21. The PMIC 31 includes, for example, a switch for determining whether or not power can be output to the main microcomputer 11 and the sub-microcomputer 21, a DC / DC converter that adjusts an output voltage, and the like, and supplies appropriate power when the main microcomputer 11 and the sub-microcomputer 21 operate. Supply to these.

The PMIC 31 includes a counter 311 (first count unit) and an RTC 312 (third clock unit).
The counter 311 counts a predetermined clock signal and outputs a signal periodically (at a predetermined time interval) for each set count number. As the clock signal, an oscillation signal of an oscillator provided in the RTC 312 or a signal obtained by dividing the oscillation signal can be used.
The RTC 312 is a normal one that performs an operation of counting time. This RTC 312 may be of the same type as the RTC 212 or may be of a different type.

Next, the display operation and power control in the smart watch 100 of this embodiment will be described.
In this smart watch 100, three levels of power consumption modes (operation states) can be set. As the power consumption mode, a low power mode in which power consumption is smaller than that in the normal mode and a sleep mode in which power consumption is further smaller than that in the low power mode are defined for the normal mode in which normal operation is performed.

FIG. 3 is a front view showing an example of a display state when the smartwatch 100 is in each power consumption mode.
The normal mode is a mode in which all normal interactive functions included in the smartwatch 100 can be executed. In the normal mode, the main microcomputer 11 mainly operates, and various display operations are performed on the first display unit 12 under the control of the main CPU 111 as illustrated in FIG. The display content on the first display unit 12 may include a time display. In this time display, the hour hand, the minute hand, and the second hand are drawn, and the time display is updated in units of one second (first time interval) by the movement of the second hand. In the smart watch 100, when a specific function operation is performed, it is possible to temporarily prevent the time display.

The low power mode is a power consumption mode that transits temporarily when the standby state continues during the operation in the normal mode, and when a user input operation to the operation receiving unit 13 is detected, When the display content related to the function being executed in step 1 is updated, the normal mode is quickly restored. In the low power mode, as shown in FIG. 3B, the time is displayed on the first display unit 12 under the control of the CPU 111, but the display color, brightness, update interval, and the like are different from the display state in the normal mode. By being limited, power consumption related to display is reduced. For example, here, the drawing of the second hand is deleted, and the drawing of the hour / minute hand is updated to a predetermined time interval, for example, 10 seconds or 1 minute.
As an example of the time display in FIGS. 3A and 3B, an analog clock display in which hands are drawn on the display screen is shown, but a normal digital display in which a time value is displayed is shown. A clock display may be used.

  In the sleep mode, the operation of the main microcomputer 11 is stopped and only the sub-microcomputer 21 is operated. As the operation of the main microcomputer 11 is suspended, the operation of the first display unit 12 is also suspended, and the second display unit 22 performs time display under the control of the sub CPU 211 of the sub microcomputer 21 as shown in FIG. Here, the display of the time is updated in units of one second, but the power consumption related to the display by the operation of the second display unit 22 and the sub CPU 211 with low power consumption is the first display unit 12 and the main display in the low power mode. It is smaller than the power consumption related to the display by the operation of the CPU 111. The hibernation mode is transitioned to when an explicit command is received by a predetermined operation by the user, or when it is difficult to maintain stable operation of the main microcomputer 11 due to insufficient power supplied from the power source. Further, the smart watch 100 returns to the normal mode when the switch 23 is pressed in the sleep mode.

FIG. 4 is a flowchart showing a control procedure of display control processing executed by the main CPU 111 in the smart watch 100 of the present embodiment.
This display control process is continuously executed until the main CPU 111 is started and turned off.

  First, the main CPU 111 performs activation processing of the main microcomputer 11 (step S101). The main CPU 111 sends a control signal to the sub CPU 211 to request time information, and starts counting time based on the time data of the RTC 212 received from the sub CPU 211 (step S102). The main CPU 111 starts the display on the first display unit 12 in the normal mode, and causes the sub CPU 211 to mainly control the control signal so as to stop the display on the second display unit 22 so that the second display unit 22 is in a transparent state ( Step S103).

  The main CPU 111 determines whether or not an input operation to the operation receiving unit 13 has been detected, or whether or not there has been an input related to a display update operation related to the function being operated (step S104). If it is determined that none exists ("NO" in step S104), the main CPU 111 determines whether or not there is no input operation detection or display update operation input for a reference time or more (step S105). If it is determined that it is not the reference time or longer ("NO" in step S105), the processing of the main CPU 111 returns to step S104. If it is determined that the time is equal to or longer than the reference time (“YES” in step S105), the processing of the main CPU 111 proceeds to step S106.

  If it is determined in the determination processing in step S104 that an input operation has been detected or a display update operation has been input ("YES" in step S104), the main CPU 111 determines that the input detection content is a transition command to the low power mode. It is determined whether or not (step S115). If it is determined that the instruction is a transition instruction to the low power mode (“YES” in step S115), the processing of the main CPU 111 proceeds to step S106.

  If it is determined that the command is not a transition command to the low power mode (“NO” in step S115), the main CPU 111 determines whether or not the input detection content is a command to transition to the sleep mode (step S125). ). If it is determined that the command is not a transition command to the sleep mode (“NO” in step S125), the main CPU 111 causes the operation and display according to other detected contents (step S126). Then, the process of the main CPU 111 proceeds to step S104.

  After shifting from the processing of steps S105 and S115 to the processing of step S106, the main CPU 111 changes the power consumption mode to the low power mode and changes the display on the first display unit 12 to the display state of the low power mode (step S106). ). The main CPU 111 updates the time display by the first display unit 12 every minute (step S107), and determines whether or not an input operation is detected or a display update operation is input (step S108). If it is determined that there is none (“NO” in step S108), the processing of the main CPU 111 returns to step S107. If it is determined that any of them is present (“YES” in step S108), the main CPU 111 changes the power consumption mode to the normal mode and changes the display on the first display unit 12 to the normal mode display state. (Step S109). Then, the processing of the main CPU 111 returns to step S104.

  When it is determined in the determination process in step S125 that the instruction to transition to the sleep mode is detected (“YES” in step S125), the main CPU 111 stops the display operation of the first display unit 12 and A control signal is output to the CPU 211 to cause the sub CPU 211 to start and control the display operation of the second display unit 22 (step S131).

  The main CPU 111 outputs a control signal to the sub CPU 211 and the PMIC 31, and corrects the time counted by the RTC 212 and the RTC 312 based on the time counted (step S132). The main CPU 111 executes an operation stop process for the main microcomputer 11, stops the operation of the main microcomputer 11 including the main CPU 111 (step S 133), and ends the display control process.

FIG. 5 is a flowchart showing a control procedure of display control processing by the sub CPU 211.
This display control process is executed continuously when the sub CPU 211 is activated. In the smart watch 100 of the present embodiment, the sub-microcomputer 21 is not turned off unless the power is removed or the battery runs out after activation.

  The sub CPU 211 performs activation processing of the sub microcomputer 21 (step S201). Then, the sub CPU 211 waits until any input related to the control operation is detected (step S202). The standby process in this case is waiting for an interrupt signal, and it is not necessary to actively perform a standby operation.

  When an interrupt signal is input, the sub CPU 211 determines the input content. The sub CPU 211 determines whether the time is input from the RTC 212 and the second display unit 22 is in the display operation state (step S203). When it is determined that the time is input and the second display unit 22 is in the display operation state (“YES” in step S203), the sub CPU 211 controls to update the time display on the second display unit 22. The signal is output to the second display unit 22 (step S204). Then, the processing of the sub CPU 211 returns to step S202.

  If it is determined that the input content is not time or the second display unit 22 is not in the display operation state (“NO” in step S203), the sub CPU 211 receives a request for time information from the main CPU 111. It is determined whether or not (step S205). If it is determined that a request for time information has been input (“YES” in step S205), the sub CPU 211 acquires the time from the RTC 212 and outputs the time to the main CPU 111 (step S206). Then, the processing of the sub CPU 211 returns to step S202.

  When it is determined that the time information request is not input from the main CPU 111 (“NO” in step S205), the sub CPU 211 makes a request to start the display operation of the second display unit 22 from the main CPU 111. It is determined whether or not an input has been made (step S207). When it is determined that a request for starting the display operation of the second display unit 22 has been input (“YES” in step S207), the sub CPU 211 starts the display operation of the second display unit 22 (step S208). . Then, the processing of the sub CPU 211 returns to step S202.

  When it is determined that a request for starting the display operation of the second display unit 22 is not input from the main CPU 111 (“NO” in step S207), the sub CPU 211 receives the second display unit 22 from the main CPU 111. It is determined whether or not a request for ending the display operation is input (step S209). If it is determined that a request to end the display operation of the second display unit 22 has been input (“YES” in step S209), the sub CPU 211 ends the display operation of the second display unit 22 and performs the second display. The unit 22 is brought into a transmissive state (step S210). Then, the processing of the sub CPU 211 returns to step S202.

If it is determined that the main CPU 111 has not input a request to end the display operation of the second display unit 22 (“NO” in step S209), the sub CPU 211 detects that the switch 23 has been pressed. It is determined whether or not (step S211). If it is determined that the pressing operation of the switch 23 is detected (“YES” in step S211), the sub CPU 211 performs an operation of starting the main CPU 111 (step S212). Then, the processing of the sub CPU 211 returns to step S202.
If it is determined that the pressing operation of the switch 23 has not been detected (“NO” in step S211), the sub CPU 211 performs processing according to other detected inputs (step S213). Then, the processing of the sub CPU 211 returns to step S202.

As described above, the smart watch 100 according to the present embodiment includes the main CPU 111, the sub CPU 211, the first display unit 12, and the second display unit 22, and the main CPU 111 and the sub CPU 211 cooperate with each other in time. During execution of a display operation including display, time display processing is performed on at least one of the first display unit 12 and the second display unit 22 according to the operation state.
As described above, the two CPUs control the two display units in cooperation, and display the time according to the operating state, so that various display patterns can be controlled more flexibly and appropriately. I can do it.

  In addition, since the main CPU 111 can be selectively set as one of a plurality of power consumption modes as an operation state, it is possible to improve operation efficiency by properly using an appropriate display unit or CPU according to power consumption.

  Further, the plurality of power consumption modes include a normal mode, a low power mode in which power consumption is lower than that in the normal mode, and a sleep mode in which the power consumption is lower than that in the low power mode and the main CPU 111 is suspended. As described above, each operation state is set for each power consumption, and an operation corresponding to the power consumption can be selected easily and appropriately by appropriately combining the display unit that performs the display operation and the CPU that performs the control operation. I can do it.

Further, in the normal mode or the low power mode, the main CPU 111 performs control to display the time on the first display unit 12, the sub CPU 211 performs control to prevent the second display unit 22 from displaying time, and in the sleep mode. The first display unit 12 is turned off, and the sub CPU 211 performs control to cause the second display unit 22 to display the time.
As described above, when the main CPU 111 is turned off, the first display unit 12 is also turned off, and the display is performed with the combination of the sub CPU 211 and the second display unit 22 with low power consumption. It is possible to display the minimum time with the power consumption.

The main CPU 111 counts the time using the RAM 112 under its own control as the first clock means, and the sub-microcomputer 21 counts the time separately from the time count by the main CPU 111 controlled by the main microcomputer 11. The main CPU 111 displays the time counted by itself on the first display unit 12, and the sub CPU 211 displays the time counted by the RTC 212 on the second display unit 22.
As described above, the timekeeping operation and time display operation in the main microcomputer 11 and the timekeeping operation and time display operation in the sub-microcomputer 21 are separated according to the power consumption mode. Time switching and time display according to power consumption can be performed easily and appropriately by switching the operation.

  In addition, when transitioning from the normal mode to the low power mode or the hibernation mode, the main CPU 111 corrects the time of the RTC 212 based on the time counted by the first clock means, so the time counting operation by the main CPU 111 is stopped. Even in such a case, it is possible to reduce the deviation of the RTC 212 and easily display the time with the same degree of time accuracy as the count by the main CPU 111 for a while.

  Similarly, when transitioning from the normal mode to the low power mode or the hibernation mode, the main CPU 111 corrects the time of the RTC 312 based on the time counted by the first clock means. As a result, the deviation of the counting time of the RTC 312 can be reduced similarly to the RTC 212, and the time display can be easily performed for a while with the same time accuracy as the counting time by the main CPU 111.

  Further, the display screen 22a of the second display unit 22 is stacked on the upper part of the display screen 12a of the first display unit 12, and is controlled so as to transmit the display content by the first display unit 12 in a state where the time is not displayed. . Therefore, it is possible to make the user properly use various displays without feeling uncomfortable by using one of the appropriate display units corresponding to the power consumption mode in the apparently single display screen 4. I can do it.

  The first display unit 12 has a liquid crystal display screen capable of color display. In other words, at least in the normal mode, various displays can be performed using color display. On the other hand, when operating with low power consumption, the second display unit 22 is not used in the first place without using such a color liquid crystal display screen. By performing drive control that causes display to be performed, it is possible to efficiently reduce power consumption.

  In addition, by performing display control of a plurality of display units with a plurality of CPUs by the above-described time display control method, it is possible to easily and appropriately perform various display use control.

[Modification 1]
Next, modification 1 of the display control process will be described.
In the display control process of the first modification, the main CPU 111, the wireless communication controller 14 (communication means), and the satellite radio wave reception module 15 (reception means) constitute time acquisition means. The time information with higher accuracy than the counting time is acquired, and the counting time is corrected.
FIG. 6 is a flowchart showing the control procedure of the display control process of Modification 1 by the main CPU 111.
This display control process is different from the display control process of the above embodiment except that the processes of steps S151 to S153 are added, and the process of steps S107a to S107c is performed instead of the process of step S107. The same processing contents are denoted by the same reference numerals, and description thereof is omitted.

After the process of step S103 is performed, the main CPU 111 performs communication connection with an external device, for example, a smartphone via the wireless communication controller 14, acquires time information from the external device, and counts the time being counted. Correction is made (step S151). The main CPU 111 determines whether or not the acquisition of time information has failed (step S152). If it is determined that the time has failed ("YES" in step S152), the main CPU 111 further includes the satellite radio wave reception module 15. To obtain time information from a positioning satellite such as a GPS satellite and correct the counting time (step S153). Then, the process of the main CPU 111 proceeds to step S104. The main CPU 111 may also correct the time of the RTC 312 based on the acquired time information. Further, the main CPU 111 may send the acquired time to the sub CPU 211 and cause the sub CPU 211 to correct the time counted by the RTC 212 or the RTC 312.
If it is determined that it has not failed (“NO” in step S152), the processing of the main CPU 111 proceeds to step S104.

  Further, when transitioning to the low power mode in the process of step S106, the main CPU 111 stores the counting time in the storage unit 113 as a storage unit (step S107a). Along with this, the main CPU 111 stops the time counting operation. When the main CPU 111 enters a standby state waiting for input (calling) and is called by the counter 311 of the PMIC 31 at predetermined time intervals, here, for example, every minute, this is stored at the time stored in the storage unit 113. A predetermined interval, that is, 1 minute is added, and the time stored in the storage unit 113 is updated at the time (step S107b). The main CPU 111 updates the time displayed on the first display unit 12 in accordance with the time stored in the storage unit 113 (step S107c), and then shifts the processing to step S108.

FIG. 7 is a flowchart illustrating a control procedure of display control processing according to the first modification performed by the sub CPU 211.
This display control process is different from the display control process of the above embodiment only in that the processes of steps S251 and S252 are added. The same processes are denoted by the same reference numerals and description thereof is omitted.

  When the determination processing in step S211 branches to “NO”, the sub CPU 211 determines whether or not the power consumption mode change condition related to the operation state of the sub CPU 211 is satisfied (step S251). If it is determined that the condition is not satisfied (“NO” in step S251), the processing of the sub CPU 211 proceeds to step S213. When it is determined that the time is satisfied (“YES” in step S251), the sub CPU 211 changes the setting of the time interval (second time interval) for inputting time information from the RTC 212 to the sub CPU 211 (step S252). . Then, the processing of the sub CPU 211 returns to step S202.

In the first modification, the sub CPU 211 is set to two modes, a normal operation mode (second normal mode) and a low power consumption mode (second low power mode). In the normal operation mode, the second display unit 22 is displayed. The time to be displayed is updated in units of 1 second, and in the low power consumption mode, the time to be displayed on the second display unit 22 is updated in units of 1 minute. That is, the time input from the RTC 212 to the sub CPU 211 in step S203 is set every second in the normal operation mode, and every minute in the low power consumption mode (that is, the time interval is wider than that in the normal operation mode). Is done. Correspondingly, as shown in FIG. 3 (d), in the low power consumption mode, the time displayed on the second display unit 22 is set to the minute digit, and the second digit value is displayed. The display is cleared.
The operation mode of the sub CPU 211 is determined separately from the power consumption mode described above. For example, the sub CPU 211 can be switched to the low power consumption mode in the normal mode.

As described above, the smart watch 100 that executes the display control process of the first modification includes the counter 311 that counts a predetermined time interval, here, one minute interval. In the normal mode, the main CPU 111 counts itself. The time is displayed on the first display unit 12 while being updated at a first time interval shorter than the predetermined time interval, in this case, at one second intervals. In the low power mode, the main CPU 111 causes the counter 311 to perform the update every predetermined time interval. To display the time on the first display unit 12.
Therefore, in the low power mode, the operation of the main CPU 111 can be made intermittent, and the power consumption can be effectively reduced by setting the interval wide.

In addition, the main CPU 111 includes a storage unit 113, and when the main CPU 111 transitions from the normal mode to the low power mode, the main CPU 111 stores the time counted by the main CPU 111 itself in the storage unit 113 and stops counting the time by the main CPU 111. When the counter 311 is called in the low power mode, the time stored in the storage unit 113 is read, a time obtained by adding a predetermined time interval to the time is calculated, and the calculated time is displayed on the first display unit 12. Let
As described above, the time counting itself by the main CPU 111 is stopped, and the necessary time information is acquired by being called intermittently as appropriate by the counting operation of the counter 311 that operates separately from the main CPU 111. Since the display is updated, the calculation processing amount of the main CPU 111 can be greatly reduced.

  Further, the sub CPU 211 can be selectively set as one of a plurality of power consumption modes as an operation state. In the plurality of power consumption modes, a normal operation mode in which the sub CPU 211 is normally operated and a sub CPU 211 in a normal operation. And a low power consumption mode that operates with lower power consumption than the mode. In this way, the power consumption of the sub CPU 211 can be adjusted according to the situation, so that appropriate display control can be performed more efficiently.

The sub-microcomputer 21 is provided with an RTC 212. The RTC 212 constitutes a counter (second counting means) that counts a second time interval (1 second, 1 minute, etc.). The counter is called at every second time interval to obtain the time counted by the RTC 212, and in the low power consumption mode of the sub CPU 211, the second time interval is set wider than that in the normal operation mode.
In this way, by expanding the time information acquisition interval and display update interval, necessary time information can be flexibly shown while adjusting to an appropriate power consumption at a necessary frequency according to the operation state.

  The main CPU 111 further includes time acquisition means for acquiring time information with higher accuracy than the timekeeping operation by the main CPU 111, and the main CPU 111 corrects the time counted by the main CPU 111 based on the time acquired by the time acquisition means. . Thereby, the time shift counted by the main CPU 111 can be eliminated as appropriate, and accurate time counting and display can be continued.

  In addition, when the main CPU 111 shifts from the low power mode or the hibernation mode to the normal mode, the time acquisition unit acquires the time and corrects the time counted by the main CPU 111 based on the acquired time. In 100, it is possible to appropriately and accurately count and display the time from the beginning when the operation in the normal mode is started.

  Further, the wireless communication controller 14 that communicates with the outside is provided, and the main CPU 111 acquires time information from the outside, in particular, a mobile device such as a smartphone or a mobile phone, by the wireless communication controller 14. Accurate time information can be obtained easily and promptly from an external device, and accurate time counting and display can be performed.

  In addition, the main CPU 111 includes a satellite radio wave reception module 15 that receives satellite radio waves from a positioning satellite including time information and acquires time information, and the main CPU 111 acquires time information obtained by the satellite radio wave reception module 15. The smart watch 100 can acquire accurate time information without transmitting radio waves or communicating with an external device. In particular, radio waves from positioning satellites can be received outdoors in various parts of the world on the earth, so accurate time information can be acquired over a wide range of the world without taking into account areas where communication radio waves can be transmitted and received. I can do it.

  Further, the sub CPU 211 can correct the time counted by the RTC 212 based on the time acquired by the time acquisition means. In this way, not only when the main CPU 111 counts the time but also the deviation from the accurate time at the time counted by the RTC 212 may be suppressed to improve the time counting and display accuracy in the sleep mode.

  Similarly, the sub CPU 211 can correct the time counted by the RTC 312 based on the time acquired by the time acquisition means. Thereby, the deviation from the accurate time at the time counted by the RTC 312 can be suppressed to a small value.

  Further, the first time interval related to the update of the time display in the normal mode by the main CPU 111 is 1 second, and the predetermined time interval related to the update of the time display in the low power mode is 1 minute. In this way, when the use of the smartwatch 100 by the user is not so active, even if the display update interval is widened, it does not cause a big problem for the user, and the difference in display state can be shown to the user. , Power consumption can be effectively reduced.

[Modification 2]
Next, modification 2 of the display control process will be described.
FIG. 8 is a flowchart showing the control procedure of the display control process of Modification 2 by the main CPU 111.
In the display control process according to the second modification, the process at step S107d is executed instead of the processes at steps S107a and S107b in the display control process according to the first modification. Other processing contents are the same in the first modification and the second modification, and the same processes are denoted by the same reference numerals and the description thereof is omitted.

When transitioning to the low power mode in the process of step S106, the main CPU 111 stops counting the current time and enters a standby state waiting for input (calling), and when called by the counter 311 of the PMIC 31 at predetermined time intervals, The main CPU 111 acquires the current time from the RTC 312 of the PMIC 31 (step S107d). Then, the process of the main CPU 111 proceeds to step S107c.
Note that the calling operation may be performed by the RTC 312 of the PMIC 31 directly sending time information to the main CPU 111 at predetermined time intervals.

  As described above, in the smartwatch 100 that executes the display control process of the second modification, the PMIC 31 includes the RTC 312 that counts the time separately from the time counted by the main CPU 111 and the RTC 212. In the low power mode, the main CPU 111 When the main CPU 111 stops counting time and is called by the counter 311, the time is acquired from the RTC 312 and displayed on the first display unit 12. As a result, the processing operation of the main CPU 111 can be greatly reduced to reduce power consumption. In addition, since the time information is acquired only from the RTC 312 that operates separately from the operation of the main microcomputer 11 and the sub-microcomputer 21 only at necessary timing and the time display of the first display unit 12 is updated, it is more than necessary. There is no need to operate the main microcomputer 11 and the sub-microcomputer 21.

  Since the RTC 312 is a real-time clock, the smart watch 100 uses a known IC chip or the like to count time efficiently with low power consumption regardless of the operations of the main microcomputer 11 and the sub-microcomputer 21. I can do it.

[Modification 3]
Next, modification 3 of the display control process will be described.
In the display control process of the modification 3, the sub CPU 211 performs display control of the first display unit 12 instead of the main CPU 111 in the low power mode. Although the display content itself on the first display unit 12 in the low power mode is the same as in the above-described embodiment and the first and second modifications, the displayed time is updated based on the time counted by the RTC 212.

FIG. 9 is a flowchart illustrating a control procedure of display control processing according to the third modification performed by the main CPU 111.
In the display control process of the modification 3, the processes of steps S107a to S107c in the display control process of the modification 1 are deleted, and the processes of steps S106e and S109e are performed instead of the processes of steps S106 and S109, respectively. The other processing contents are the same in the display control processes of the second modification and the third modification, and the same processes are denoted by the same reference numerals and description thereof is omitted.

  When branching to “YES” in the determination processing in step S105, the main CPU 111 performs various operations for transition to the low power mode. At this time, the main CPU 111 stops the display control of the first display unit 12, stops counting the time, and notifies the sub CPU 211 that the mode has been changed to the low power mode (step S106e). Then, the processing of the main CPU 111 proceeds to step S108 until an operation input is detected or an update input of display content related to the operation of a predetermined functional operation unit controlled by the main CPU 111 is detected. The process of step S108 is repeated or simply waited.

  When the process branches to “YES” in the process of step S108, the main CPU 111 performs various operations for shifting to the normal mode. At this time, the main CPU 111 sends a notification indicating the return to the normal mode to the sub CPU 211, acquires the time of the RTC 212, and restarts the time counting. Further, the main CPU 111 resumes the display control operation of the first display unit 12 (step S109e). Then, the process of the main CPU 111 returns to step S104.

FIG. 10 is a flowchart illustrating a control procedure of display control processing according to the third modification performed by the sub CPU 211.
In this display control process, the processes of steps S261 to S264 are added to the display control process of the first modification instead of the processes of steps S251 and S252, and the process of step S203f is executed instead of the process of step S203. Except for this point, it is the same as the display control process of the first modification, and the same processing contents are denoted by the same reference numerals and description thereof is omitted.

  When an input is detected in the process of step S202 and the process proceeds to the process of step S203f, the sub CPU 211 controls whether the input content is time information and the sub CPU 211 controls either the first display unit 12 or the second display unit 22. It is determined whether or not it is in a state to be performed (step S203f). When the time information is input and it is determined that the state is in the state of controlling the first display unit 12 (ie, the low power mode) or the state of controlling the second display unit 22 (ie, the sleep mode) ( In step S203f, “YES”), the sub CPU 211 updates the time display on the display unit under control (step S204). Then, the processing of the sub CPU 211 returns to step S202. When it is determined that the time information is not acquired or that the sub CPU 211 is not controlling any of the first display unit 12 and the second display unit 22 (“NO” in step S203f), the processing of the sub CPU 211 is performed. Proceeds to step S205.

  Further, when branching to “NO” in the determination process of step S211, the sub CPU 211 determines whether or not a notification of transition from the main CPU 111 to the low power mode has been acquired (step S261). If it is determined that the notification of transition to the low power mode has been acquired (“YES” in step S261), the sub CPU 211 starts display control of the first display unit 12 (step S262). Then, the processing of the sub CPU 211 returns to step S202.

When it is determined that the notification of transition to the low power mode has not been acquired (“NO” in step S261), the sub CPU 211 determines whether or not the notification of transition to the normal mode has been acquired from the main CPU 111. (Step S263). When it is determined that the notification of transition to the normal mode is acquired (“YES” in step S263), the sub CPU 211 ends the display control of the first display unit 12 (step S264). Then, the processing of the sub CPU 211 returns to step S202.
If it is determined that the notification of transition to the normal mode has not been acquired (“NO” in step S263), the processing of the sub CPU 211 proceeds to step S213.

As described above, in the display control process of Modification 3, in the normal mode, the main CPU 111 performs control to cause the first display unit 12 to display time, and the sub CPU 211 causes the second display unit 22 to display time. In the low power mode, the sub CPU 211 controls the first display unit 12 to display the time and the second display unit 22 does not display the time. In the sleep mode, the first display unit 12 Is turned off, and the sub CPU 211 controls the second display unit 22 to display the time.
As described above, power consumption is reduced by using the sub CPU 211 in the low power mode and reducing the power consumption by using the second display unit 22 in the sleep mode as compared to the normal mode using the main CPU 111 and the first display unit 12. Therefore, it is possible to easily and easily switch the control pattern according to the power consumption, and to obtain the smart watch 100 that uses various displays efficiently and appropriately.

Further, in the normal mode, the main CPU 111 displays the time counted by itself on the first display unit 12, and in the low power mode, the sub CPU 211 causes the first display unit 12 to display the time counted by the RTC 212 and pauses. In the mode, the sub CPU 211 displays the time counted by the RTC 212 on the second display unit 22.
In this way, by reducing the processing load related to the time counting and the processing load related to the time display step by step, the smart watch 100 reduces the power consumption while switching the power consumption efficiently and appropriately. Appropriate time display can be performed.

The present invention is not limited to the above-described embodiment, and various modifications can be made.
For example, in the above embodiment, the case where the display screen 22a of the second display unit 22 is stacked on the display screen 12a of the first display unit 12 has been described, but the order may be reversed, or Two display screens may be arranged in parallel. The display screen is not limited to a liquid crystal display, and an organic EL (Electro-Luminescent) display or the like may be used.

  Moreover, although the said embodiment demonstrated as the 1st display part 12 and the 2nd display part 22 one each, several 1st display part 12 (display screen 12a) and several 2nd display part are demonstrated. 22 (display screen 22a) may be provided.

  The satellite radio wave receiving module 15 as a receiving means has been described as being able to acquire time information by receiving radio waves from GPS satellites. However, it receives radio waves from other positioning satellites such as GLONASS to acquire time information. You may do it. In addition to receiving satellite radio waves, it may have a configuration capable of acquiring time information by receiving long-wavelength standard radio waves.

  Further, the acquisition of time information using the satellite radio wave reception module 15 may be performed prior to the acquisition of time information via the wireless communication controller 14, or accurate time information using only the satellite radio wave reception module 15. May be done.

  In the above embodiment, the satellite radio wave reception module 15 is connected to the main microcomputer 11 and the time information is acquired in the control of the main microcomputer 11. However, the satellite radio wave reception module 15 is connected to the sub microcomputer 21, and Time information may be acquired in the control of the microcomputer 21.

  Further, in the above embodiment, the date and time of the RTC 212 is acquired from the sub CPU 211 after the main microcomputer 11 is started, and then the main CPU 111 acquires time information with high accuracy from a smartphone or a GPS satellite and counts the RTC 212 and the RTC 312. Although the time is corrected, the time information with high accuracy may be acquired from the smartphone or GPS satellite immediately after the main microcomputer 11 is started, and then the time counted by the RTC 212 and the RTC 312 may be corrected.

  In the above embodiment, the sub-microcomputer 21 and the PMIC 31 have been described as having the RTCs 212 and 312, respectively, but a common RTC may be used. In the sub microcomputer 21, the sub CPU 211 may count the time without using the RTC.

  Moreover, in the said embodiment, although RTC312 shall have PMIC31, the main microcomputer 11 may have.

  Further, the time correction of the RTCs 212 and 312 is not limited to the case where the sub CPU 211 executes, but may be executed by the main CPU 111. Further, after the main CPU 111 corrects the time counted by itself once, the time of the RTCs 212 and 312 may be corrected based on the corrected time. In addition, the wireless communication controller 14 and the satellite radio wave receiving module 15 are connected to the sub microcomputer 21 so that the sub CPU 211 can acquire time information from the outside independently of the main CPU 111 and can be operated by the control of the sub CPU 211. May be.

  In addition, the selection and display control of the display units described in the above embodiment and each modification may be determined in any combination corresponding to each power consumption mode as long as they do not contradict each other. Further, the power consumption mode is not limited to the above-described three types, and may further include a mode corresponding to the middle of these three types.

  In addition, the above-described transition operation of the power consumption mode and the display control according to the change are all shown as being performed in cooperation with the main CPU 111 and the sub CPU 211 as a processor. The unit may be performed using a dedicated logic circuit.

  Moreover, only the main CPU 111 may grasp which power consumption mode the smart watch 100 is in the power consumption mode described above, or both the main CPU 111 and the sub CPU 211 may grasp.

Moreover, although the smart watch was mentioned as an example and demonstrated in the said embodiment as an electronic device, it is not restricted to this. The present invention can be preferably applied to other display terminals in general, in particular, a portable type or a body-mounted type.
In addition, specific details such as the configuration, the control procedure, and the display example shown in the above embodiment can be changed as appropriate without departing from the spirit of the present invention.

Although several embodiments of the present invention have been described, the scope of the present invention is not limited to the above-described embodiments, but includes the scope of the invention described in the claims and equivalents thereof.
The invention described in the scope of claims attached to the application of this application will be added below. The item numbers of the claims described in the appendix are as set forth in the claims attached to the application of this application.

[Appendix]
<Claim 1>
A first processor;
A second processor;
A first display unit;
A second display;
With
During the execution of the display operation including the time display in cooperation with the first processor and the second processor, to at least one of the first display unit and the second display unit according to the operation state An electronic device characterized in that the time display process is executed.
<Claim 2>
The electronic device according to claim 1, wherein the first processor can be selectively set to any one of a plurality of power consumption modes as the operation state.
<Claim 3>
The plurality of power consumption modes include a normal mode, a low power mode that consumes less power than the normal mode, and a sleep mode that consumes less power than the low power mode and pauses the first processor. The electronic device according to claim 2, wherein
<Claim 4>
In the normal mode or the low power mode, the first processor performs control to cause the first display unit to display time, and the second processor causes the second display unit to display time. Do no control and
4. The electronic device according to claim 3, wherein in the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time.
<Claim 5>
In the normal mode, the first processor performs control to display the time on the first display unit, and the second processor performs control to prevent the second display unit from displaying time.
In the low power mode, the second processor performs control to cause the first display unit to perform time display and to prevent the second display unit from performing time display,
4. The electronic device according to claim 3, wherein in the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time.
<Claim 6>
First clock means for counting time under the control of the first processor;
Second clock means for counting time separately from the first clock means;
With
The first processor displays the time counted by the first clock means on the first display unit,
The electronic device according to claim 4, wherein the second processor displays the time counted by the second clock means on the second display unit.
<Claim 7>
First clock means for counting time under the control of the first processor;
Second clock means for counting time separately from the first clock means;
With
In the normal mode, the first processor displays the time counted by the first clock means on the first display unit,
In the low power mode, the second processor displays the time counted by the second clock means on the first display unit,
6. The electronic apparatus according to claim 5, wherein, in the sleep mode, the second processor displays the time counted by the second clock means on the second display unit.
<Claim 8>
Comprising a first counting means for counting a predetermined time interval;
In the normal mode, the first processor displays the time counted by the first clock means on the first display unit while updating the time at a first time interval shorter than the predetermined time interval,
The said 1st processor is called for every said predetermined time interval by the said 1st count means in the said low power mode, The time is displayed on the said 1st display part. Electronic equipment.
<Claim 9>
A storage means,
The first processor is
When transitioning from the normal mode to the low power mode, the time counted by the first clock means is stored in the storage means, and the time counting by the first clock means is stopped,
When called by the first counting means in the low power mode, the time stored in the storage means is read, the time obtained by adding the predetermined time interval to the time is calculated, and the calculated time is calculated as the first time. The electronic device according to claim 8, wherein the electronic device is displayed on the display unit.
<Claim 10>
A third clock means for counting time separately from the first clock means and the second clock means;
In the low power mode, the first processor stops counting the time by the first clock means, and when called by the first count means, acquires the time from the third clock means. The electronic device according to claim 8, wherein the electronic device is displayed on the first display unit.
<Claim 11>
The second processor can be selectively set to any one of a plurality of power consumption modes as the operation state,
In the plurality of power consumption modes,
A second normal mode for normal operation of the second processor;
A second low power mode for operating the second processor with lower power consumption than in the second normal mode;
The electronic device according to claim 6, wherein the electronic device is included.
<Claim 12>
Comprising second counting means for counting the second time interval;
The second clock means is a real-time clock;
The second processor is called at every second time interval by the second counting means to obtain the time of the second clock means, and in the second low power mode, the second normal mode The electronic device according to claim 11, wherein the second time interval is set wider than the second time interval.
<Claim 13>
Time acquisition means for acquiring time information from the outside,
The said 1st processor correct | amends the time which the said 1st timepiece means counts based on the time acquired by the said time acquisition means. The Claim 1 characterized by the above-mentioned. Electronics.
<Claim 14>
The first processor, when transitioning from the low power mode or the hibernation mode to the normal mode, causes the time acquisition unit to acquire time, and based on the acquired time, counts the first clock unit. The electronic device according to claim 13, wherein the time to be corrected is corrected.
<Claim 15>
A communication means for communicating with the outside,
The electronic device according to claim 13 or 14, wherein the time acquisition unit acquires time information from outside by the communication unit.
<Claim 16>
Receiving means for receiving radio waves including time information and obtaining time information;
The electronic device according to claim 13 or 14, wherein the time acquisition unit acquires time information acquired by the reception unit.
<Claim 17>
When transitioning from the normal mode to the low power mode or the hibernation mode, the first processor corrects the time of the second clock means based on the time counted by the first clock means. The electronic device according to claim 6, wherein the electronic device is characterized.
<Claim 18>
When transitioning from the normal mode to the low power mode or the hibernation mode, the first processor corrects the time of the third clock means based on the time counted by the first clock means. 11. The electronic device according to claim 10, wherein
<Claim 19>
Time acquisition means for acquiring time information from the outside,
The said 2nd processor correct | amends the time which the said 2nd timepiece means counts based on the time acquired by the said time acquisition means. The one of Claim 6-12 characterized by the above-mentioned. Electronics.
<Claim 20>
Time acquisition means for acquiring time information from the outside,
The electronic device according to claim 10, wherein the second processor corrects the time counted by the third clock unit based on the time acquired by the time acquisition unit.
<Claim 21>
The first time interval is 1 second;
The electronic device according to any one of claims 8 to 10, 18, and 20, wherein the predetermined time interval is 1 minute.
<Claim 22>
21. The electronic device according to claim 10, wherein the third clock means is a real time clock.
<Claim 23>
The second display unit is stacked on an upper portion of the first display unit, and is controlled so as to transmit display contents of the first display unit when the time is not displayed. The electronic device according to any one of 1 to 22.
<Claim 24>
The electronic device according to any one of claims 1 to 23, wherein the first display unit includes a liquid crystal display screen capable of color display.
<Claim 25>
A display control method for an electronic device comprising a first processor, a second processor, a first display unit, and a second display unit,
During the execution of the display operation including the time display in cooperation with the first processor and the second processor, to at least one of the first display unit and the second display unit according to the operation state The time display control method characterized by performing the time display process of.

1 Main unit 2 Band 3 Frame 4 Display screen 11 Main microcomputer 111 Main CPU
112 RAM
113 Storage Unit 12 Display Unit 12a Display Screen 13 Operation Accepting Unit 14 Wireless Communication Controller 15 Satellite Radio Wave Reception Module 21 Sub-microcomputer 211 Sub-CPU
212 RTC
22 Display unit 22a Display screen 23 Switch 100 Smart watch 31 PMIC
311 Counter 312 RTC
B1 button switch

Claims (19)

A first processor;
A second processor;
A first display unit;
A second display;
With
The first processor can be set to any one of a normal mode, a low power mode, and a sleep mode,
In the normal mode or the low power mode, the first processor performs control to cause the first display unit to display time, and the second processor causes the second display unit to display time. Do no control and
In the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time . A first processor;
A second processor;
A first display unit;
A second display;
With
The first processor can be set to any one of a normal mode, a low power mode, and a sleep mode,
In the normal mode, the first processor performs control to display the time on the first display unit, and the second processor performs control to prevent the second display unit from displaying time.
In the low power mode, the second processor performs control to cause the first display unit to perform time display and to prevent the second display unit from performing time display,
In the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time.
An electronic device characterized by that. The second processor, the first low-power than the processor, and or, of claim 1 or 2, wherein the operating frequency in the operating lower than the operating frequency of the first processor Electronics. It said first processor, electronic device according to any one of claims 1-3, characterized in that it is possible selectively set to one of a plurality power mode as the operating state. The plurality of power consumption modes include a normal mode, a low power mode that consumes less power than the normal mode, and a sleep mode that consumes less power than the low power mode and pauses the first processor. The electronic apparatus according to claim 4, wherein First clock means for counting time under the control of the first processor;
Second clock means for counting time separately from the first clock means;
With
The first processor displays the time counted by the first clock means on the first display unit,
The second processor, the electronic device according to claim 1, wherein the displaying the time counted by said second clock means to the second display unit. First clock means for counting time under the control of the first processor;
Second clock means for counting time separately from the first clock means;
With
In the normal mode, the first processor displays the time counted by the first clock means on the first display unit,
In the low power mode, the second processor displays the time counted by the second clock means on the first display unit,
3. The electronic device according to claim 2 , wherein in the sleep mode, the second processor displays the time counted by the second clock means on the second display unit. Comprising a first counting means for counting a predetermined time interval;
In the normal mode, the first processor displays the time counted by the first clock means on the first display unit while updating the time at a first time interval shorter than the predetermined time interval,
Wherein in the low power mode, the first processor according to claim 6, wherein the displaying the time on the first display section is called for each of the predetermined time interval by said first counting means Electronic equipment. A storage means,
The first processor is
When transitioning from the normal mode to the low power mode, the time counted by the first clock means is stored in the storage means, and the time counting by the first clock means is stopped,
When called by the first counting means in the low power mode, the time stored in the storage means is read, the time obtained by adding the predetermined time interval to the time is calculated, and the calculated time is calculated as the first time. The electronic device according to claim 8 , wherein the electronic device is displayed on the display unit. A third clock means for counting time separately from the first clock means and the second clock means;
In the low power mode, the first processor stops counting the time by the first clock means, and when called by the first count means, acquires the time from the third clock means. The electronic device according to claim 8 , wherein the electronic device is displayed on the first display unit. The second processor is selectively settable to any one of the plurality power modes as operation state,
In the plurality of power consumption modes,
A second normal mode for normal operation of the second processor;
A second low power mode for operating the second processor with lower power consumption than in the second normal mode;
The electronic device according to claim 3 , wherein the electronic device is included. The second processor is selectively settable to any one of the plurality power modes as operation state,
In the plurality of power consumption modes,
A second normal mode for normal operation of the second processor;
A second low power mode for operating the second processor with lower power consumption than the second normal mode,
Comprising second counting means for counting the second time interval;
The second clock means is a real-time clock;
The second processor is called at every second time interval by the second counting means to obtain the time of the second clock means, and in the second low power mode, the second normal mode The electronic device according to claim 6, wherein the second time interval is set wider than the second time interval. Time acquisition means for acquiring time information from the outside,
The said 1st processor correct | amends the time which the said 1st timepiece means counts based on the time acquired by the said time acquisition means. Any one of Claims 6-10 , 12 characterized by the above-mentioned. The electronic device described. The first processor, when transitioning from the low power mode or the hibernation mode to the normal mode, causes the time acquisition unit to acquire time, and based on the acquired time, counts the first clock unit. The electronic device according to claim 13, wherein the time to be corrected is corrected. When transitioning from the normal mode to the low power mode or the hibernation mode, the first processor corrects the time of the second clock means based on the time counted by the first clock means. The electronic device according to any one of claims 6 to 10 and 12 to 14 . When transitioning from the normal mode to the low power mode or the hibernation mode, the first processor corrects the time of the third clock means based on the time counted by the first clock means. 11. The electronic device according to claim 10, wherein The second display unit is stacked on an upper portion of the first display unit, and is controlled so as to transmit display contents of the first display unit when the time is not displayed. The electronic device according to any one of 1 to 16 . A display control method for an electronic device comprising a first processor, a second processor, a first display unit, and a second display unit,
The first processor can be set to any one of a normal mode, a low power mode, and a sleep mode,
In the normal mode or the low power mode, the first processor performs control to cause the first display unit to display time, and the second processor causes the second display unit to display time. Do no control and
In the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to perform time display. A display control method for an electronic device comprising a first processor, a second processor, a first display unit, and a second display unit,
The first processor can be set to any one of a normal mode, a low power mode, and a sleep mode,
In the normal mode, the first processor performs control to display the time on the first display unit, and the second processor performs control to prevent the second display unit from displaying time.
In the low power mode, the second processor performs control to cause the first display unit to perform time display and to prevent the second display unit from performing time display,
In the sleep mode, the first display unit is turned off, and the second processor performs control to cause the second display unit to display a time.
A time display control method characterized by the above.

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