JP6554541B2 - 配線形成方法および配線形成装置 - Google Patents
配線形成方法および配線形成装置 Download PDFInfo
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- JP6554541B2 JP6554541B2 JP2017528029A JP2017528029A JP6554541B2 JP 6554541 B2 JP6554541 B2 JP 6554541B2 JP 2017528029 A JP2017528029 A JP 2017528029A JP 2017528029 A JP2017528029 A JP 2017528029A JP 6554541 B2 JP6554541 B2 JP 6554541B2
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- Prior art keywords
- wiring
- metal
- resin layer
- forming
- circuit board
- Prior art date
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- 238000000034 method Methods 0.000 title description 44
- 230000015572 biosynthetic process Effects 0.000 title description 28
- 229910052751 metal Inorganic materials 0.000 claims description 160
- 239000002184 metal Substances 0.000 claims description 160
- 239000011347 resin Substances 0.000 claims description 111
- 229920005989 resin Polymers 0.000 claims description 111
- 239000007788 liquid Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 16
- 238000007599 discharging Methods 0.000 claims description 11
- 239000010419 fine particle Substances 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 3
- 230000001131 transforming effect Effects 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 22
- 230000001070 adhesive effect Effects 0.000 description 22
- 239000010409 thin film Substances 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 14
- 238000007639 printing Methods 0.000 description 11
- 238000010304 firing Methods 0.000 description 6
- 238000007493 shaping process Methods 0.000 description 6
- 239000012530 fluid Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- -1 specifically Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Coating Apparatus (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
製造装置10では、上述した構成によって、回路基板70上に多層的な回路パターンが形成される。具体的には、ステージ52の基台60に回路基板70がセットされ、そのステージ52が、第1造形ユニット22の下方に移動される。そして、第1印刷部72において、インクジェットヘッド76によって回路基板70の上に金属インクが、回路パターンに応じて線状に吐出される。次に、焼成部74において、回路基板70に吐出された金属インクに、レーザ照射装置78によってレーザが照射される。これにより、金属インクが焼成し、図3に示すように、回路基板70の上に配線80が形成される。
Claims (2)
- 基材の上に金属微粒子を含有する金属含有液によって第1の配線を形成する第1配線形成工程と、
前記第1の配線の一部が露出する開口部を有する樹脂層を、前記第1の配線の上に形成する樹脂層形成工程と、
前記樹脂層の上に前記金属含有液によって第2の配線を形成する第2配線形成工程と、
前記開口部の内部容量に応じた複数の球状の導電性の金属塊を前記開口部に載置する工程と、
前記金属塊をレーザ照射により溶融し、前記開口部に応じた形状の導電体に変形する工程と、
前記第1の配線と前記第2の配線とを電気的に接続する電気的接続工程と
を含むことを特徴とする配線形成方法。 - 金属微粒子を含有する金属含有液を吐出する第1吐出装置と、
硬化性樹脂を吐出する第2吐出装置と、
導電性の金属塊を保持する保持装置と、
前記第1吐出装置と前記第2吐出装置と前記保持装置との各々の作動を制御する制御装置とを備え、
前記制御装置が、
基材の上に前記第1吐出装置によって前記金属含有液を吐出することで、第1の配線を成形する第1配線形成部と、
前記第1の配線の上に前記第2吐出装置によって硬化性樹脂を吐出することで、前記第1の配線の一部が露出する開口部を有する樹脂層を形成する樹脂層形成部と、
前記樹脂層の上に前記第1吐出装置によって前記金属含有液を吐出することで、第2の配線を成形する第2配線形成部と、
前記開口部の内部容量に応じた複数の球状の前記金属塊を前記保持装置によって前記開口部に載置する載置部と、
前記金属塊をレーザ照射により溶融し、前記開口部に応じた形状の導電体に変形する変形部と、
前記第1の配線と前記第2の配線とを電気的に接続する電気的接続部と
を有することを特徴とする配線形成装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/070005 WO2017009922A1 (ja) | 2015-07-13 | 2015-07-13 | 配線形成方法および配線形成装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2017009922A1 JPWO2017009922A1 (ja) | 2018-04-26 |
JP6554541B2 true JP6554541B2 (ja) | 2019-07-31 |
Family
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JP2017528029A Active JP6554541B2 (ja) | 2015-07-13 | 2015-07-13 | 配線形成方法および配線形成装置 |
Country Status (2)
Country | Link |
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JP (1) | JP6554541B2 (ja) |
WO (1) | WO2017009922A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6866198B2 (ja) * | 2017-03-16 | 2021-04-28 | 株式会社Fuji | 回路形成装置 |
CN112385322A (zh) * | 2018-07-13 | 2021-02-19 | 株式会社富士 | 电路形成方法及电路形成装置 |
US11171101B2 (en) * | 2020-03-31 | 2021-11-09 | Raytheon Company | Process for removing bond film from cavities in printed circuit boards |
JP7230276B2 (ja) * | 2020-04-03 | 2023-02-28 | 株式会社Fuji | 回路形成方法および回路形成装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0350888A (ja) * | 1989-07-19 | 1991-03-05 | Fujitsu Ltd | 導体ビアの修復方法 |
JPH03112965U (ja) * | 1990-03-05 | 1991-11-19 | ||
JPH0410494A (ja) * | 1990-04-26 | 1992-01-14 | Victor Co Of Japan Ltd | スルホールピンの半田付け方法 |
US5401911A (en) * | 1992-04-03 | 1995-03-28 | International Business Machines Corporation | Via and pad structure for thermoplastic substrates and method and apparatus for forming the same |
EP0878986A1 (fr) * | 1997-05-16 | 1998-11-18 | Mecanismos Auxiliares Industriales S.A. M.A.I.S.A. | Un système et un pin d'interconnexion pour des circuits imprimés à double face par un double procédé, vague et refusion |
JP2001156415A (ja) * | 1999-11-29 | 2001-06-08 | Mitsubishi Electric Corp | プリント配線基板及びその製造方法並びに多層プリント配線基板の製造方法 |
US6440835B1 (en) * | 2000-10-13 | 2002-08-27 | Charles W. C. Lin | Method of connecting a conductive trace to a semiconductor chip |
JP2004303956A (ja) * | 2003-03-31 | 2004-10-28 | Sekisui Chem Co Ltd | プリント基板の製造方法 |
WO2005104303A1 (ja) * | 2004-03-30 | 2005-11-03 | Mitsubishi Denki Kabushiki Kaisha | 配線分岐装置 |
JP4308716B2 (ja) * | 2004-06-09 | 2009-08-05 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
JP4207860B2 (ja) * | 2004-07-14 | 2009-01-14 | セイコーエプソン株式会社 | 層形成方法、配線基板、電気光学装置、および電子機器 |
JP4609072B2 (ja) * | 2005-01-12 | 2011-01-12 | デジタルパウダー株式会社 | 基板両面の導通方法及び配線基板 |
JP2007088356A (ja) * | 2005-09-26 | 2007-04-05 | Matsushita Electric Ind Co Ltd | 層間接続用導電体およびその製造方法 |
DE102009028744A1 (de) * | 2009-08-20 | 2011-03-31 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Herstellung einer elektrischen Verbindung zwischen Leiterplatten |
JP5427547B2 (ja) * | 2009-10-20 | 2014-02-26 | フリージア・マクロス株式会社 | 電子部品搭載用基板の製造方法及び電子部品搭載用基板 |
JP2011091116A (ja) * | 2009-10-20 | 2011-05-06 | Freesia Makurosu Kk | 電子部品搭載用基板の製造方法及び電子部品搭載用基板 |
US20150208506A1 (en) * | 2012-08-10 | 2015-07-23 | Telefonaktiebolaget L M Ericsson (Publ) | A printed circuit board arrangement and a method for forming electrical connection at a printed circuit board |
JP2014146650A (ja) * | 2013-01-28 | 2014-08-14 | Murata Mfg Co Ltd | 配線基板およびその製造方法 |
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2015
- 2015-07-13 WO PCT/JP2015/070005 patent/WO2017009922A1/ja active Application Filing
- 2015-07-13 JP JP2017528029A patent/JP6554541B2/ja active Active
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Publication number | Publication date |
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JPWO2017009922A1 (ja) | 2018-04-26 |
WO2017009922A1 (ja) | 2017-01-19 |
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