JP6545802B2 - Techniques for power management associated with processing of received packets in network devices - Google Patents

Description

  The examples described herein are generally associated with network packet processing.

  A data plane development kit (DPDK) is a set of software libraries and drivers that is used to network computing based on a processor architecture such as Intel® processor architecture. May facilitate user space packet processing for the DPDK has been deployed in data center networks worldwide to support high performance network packet processing applications. These network packet processing applications include, but are not limited to, firewall applications, virtual private network (VPN) applications, network address translation (NAT) applications, deep packet inspection (DPI) applications, or load balancer applications May be. For example, one may implement these firewall applications, VPN applications, NAT applications, DPI applications, or load balancer applications on a standard x86 server platform, including, but not limited to Intel 10 [] Gb] / 40 [Gb] (10G / 40G) network interface cards (NICs) may include an Intel Xeon® processor connected to the network interface cards (NICs). Using the DPDK to support high performance network packet processing applications makes it possible to replace at least some expensive and inflexible physical components of network devices.

Figure 1 illustrates one example of a system. FIG. 7 illustrates one example of a first logic flow. An example of the first process is illustrated. An example of the second process is illustrated. An example of the third process is illustrated. FIG. 1 illustrates one example of a block diagram of one device. FIG. 7 illustrates one example of a second logic flow. FIG. 7 illustrates one example of a third logic flow. Figure 1 illustrates one example of a storage medium. Figure 1 illustrates one example of a computing platform.

  In some instances, DPDK implementations for high-performance packet processing applications may use polling mode drivers (PMDs) to configure and / or operate network (NW) I / O devices such as Intel 1G / 10G / 40G NICs. May include the development of In these examples, PMD deployment is the highest processor / network protocol application based on DPDK, without triggering interrupts to receive, process, and transmit packets in a high performance and low latency manner. It may be possible to access resources (e.g., receive (Rx) and transmit (Tx) queues) of the NW I / O device at the core frequency or at the maximum processor / core frequency. However, in data center networks, a well-known phenomenon called "tidal effects" occurs. Tidal effects can be attributed to significant changes in network traffic patterns that occur in multiple different geographic areas over a time period. In this way, DPDK-based applications ("DPDK polling threads") running on the x86 processing core are still running for periods of time that they handle very little network traffic or no network traffic at all. , May be busy waiting (eg, polling continuously instead of processing network packets). Waiting for network packets can waste considerable amounts of computing resources as well as considerable amounts of power.

  The operating system (OS) power management subsystem or module may also provide several techniques (primarily control of performance states (P-states) and power states (C-states) in OS kernel space) Well, some of those techniques adjust processor power during periods of either peak network traffic or low network traffic. In a standard OS (e.g., Linux (R) or Windows (R)), the OS power management module will be able to pick the appropriate processor or core to take by periodically sampling CPU usage. The processor voltage and / or frequency, operating point (P-state) and processor idle state (C-state) may be determined respectively. However, due to the fact that the OS power management module can not determine whether the DPDK polling thread is actually processing a packet or is busy waiting, the above approach is based on the DPDK polling thread Not suitable for PMD based packet processing applications. The inability of the OS power management module to determine the operating state of the DPDK polling thread means that processors or processors that support these DPDK polling threads may be used to conserve power in data center networks affected by "tidal effects" Problems can arise in determining the proper power state for the core to take. It is with respect to these issues that several examples described herein are required.

  According to a first plurality of examples, techniques for power management associated with processing received packets at an NW I / O device include multiple polling iterations for a given DPDK polling thread And monitoring the available received packet descriptors held in the receive queue of the NW I / O device. These first examples determine the level of fullness of the receive queue based on the available packet descriptors held in the receive queue after each polling iteration, and receive It may include the step of increasing the trend count based on the level of queue filling. The first plurality of examples may include transmitting the performance indicator to the OS power management module based on whether the trending count exceeds the trending threshold. The above performance indicators may allow the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

  According to a second plurality of examples, the techniques for power management associated with processing received packets at the NW I / O device are performed by the NW I over multiple polling iterations for its DPDK polling thread. Monitoring the available received packet descriptors held in the receive queue of the / O device. These second examples illustrate, after each polling iteration, the number of packets received in the reception queue for each polling iteration based on the available packet descriptors held in the reception queue. And determining the idle count to be increased by a count of 1 if the number of packets received for successive numbers of polling iterations above a continuous threshold is zero. These second plurality of examples are based on whether the idle count is above or below the first idle count threshold, and during the first time period or the second time period. During one of the steps, the DPDK polling thread may be put to sleep. The second time period may be longer than the first time period.

  FIG. 1 illustrates an exemplary system 100. In some examples, as shown in FIG. 1, system 100 includes NW I / O device 110, which receives or transmits packets included in NW traffic 105. Configured as. The preflow load balancer 120 may distribute packets to the receive (Rx) queues 130-1 through 130-n, where "n" is any positive integer greater than one. In these examples, Rx queues 130-1 through 130-n may be configured to at least temporarily hold received packets for processing by DPDK polling threads 140-1 through 140-n, respectively. . Each DPDK polling thread 140-1 to 140-n executes at least portions of a network packet processing application including, but not limited to, a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application It may be possible. Each DPDK polling thread 140-1 to 140-n may include a respective polling mode driver 142-1 to 142-n and may receive a process or transmit received packets in the NW traffic 105 Rx queue 130- Allows access to 1-130-n without interruption in certain polling mode operations.

  As shown in FIG. 1, according to some examples, system 100 is configured to operate with DPDK power management component 150 and kernel space 102 configured to operate in user space 101. An OS power management module 160 may be included. As described in more detail below, the DPDK power management component 150 is available at the Rx queues 130-1 to 130-n for processing by the DPDK polling threads 140-1 to 140-n. May include logic and / or features capable of monitoring received packet descriptors. The logic and / or features in DPDK power management component 150 may monitor sleep time or idle time for DPDK polling threads 140-1 through 140-n.

  In some instances, the state algorithm 154 of the DPDK power management component 150 utilizes monitored information to cause the DPDK polling threads 140-1 through 140-n to be put to a temporary sleep state ( Send an interrupt turn-on hinter message to the NW I / O device 110 via the one-shot Rx interrupt on hint 180 and cause a change of operation from polling mode to interrupt mode or library 152 allows C-state (Sleep) hints or indicators or P-state (performance) hints or indicators to be sent. As shown in FIG. 1, in these examples, C-state hints or P-state hints may be sent to processor element (PE) idle 162 or PE frequency 164 of OS power management module 160. The elements of the OS power management module 160 may be configured to include one or more Cs of one or more PEs 172-1 to 172-n included in one or more processors 170 based on the received C-state hint or P-state hint. A change to either -state or P-state may occur. Advanced Configuration and Power Interface (ACPI) Specification Revised 5.1 ("ACPI Specification") published in June 2014 by the Unified Extensible Firmware Interface Forum C-state or P-state may be changed or controlled according to one or more processor power management standards or specifications, such as

  According to some examples, one or more processors 170 may include a multi-core processor, and PEs 172-1 through 172-n may each be a core of a multi-core processor and / or a multi-core processor May be a virtual machine (VM) supported by one or more cores. Also, in these examples, it may be possible to execute the DPDK polling threads 140-1 to 140-n by the PEs 172-1 to 172-n. The one or more processors 170 may be, but are not limited to, AMD (R) processors, Athlon (R) processors, Duron (R) processors, Phenom (R) processors, and Opteron (R). Processor, Intel Atom (R) Core Processor, Celeron (R) Core (2) Processor, Duo Core i3 Processor, Core i5 Processor, Core i7 Processor, Pentium (R) Xeon or Xeon Phi (R) Processor It may include various types of commercially available x86 processors, including:

  According to some examples, the new API (NAPI) may be an interrupt mitigation technique for use in the kernel space 102 (e.g., the Linux kernel), which interrupt mitigation technique may be a DPDK polling thread It may support packet processing according to 140-1 to 140-n. NAPI is typically designed to improve the performance of high speed networking by incorporating polling mode capabilities for the OS and NIC or NW I / O drivers. Using NAPI, the NW I / O driver may operate in interrupt driven mode with default settings, and will only switch to polling mode if the flow of incoming packets exceeds a certain threshold. NAPI allows frequent mode switching, and network terminal endpoints (such as servers or personal computers, for example) may not have stringent low latency requirements and stringent jitter requirements, so frequent. Mode switching may be successfully accepted for these terminal endpoints. In contrast, certain types of network devices (eg, switches, routers, and L4 to L7 network equipment, etc.) can operate under strict delay requirements, stringent jitter requirements and stringent packet loss requirements. There is sex. For these types of network devices, frequent mode switching, providing interrupts, and waking up a suspended or suspended thread, or putting a thread to sleep are processor resources and It can be costly in terms of latency hits. These processor resources and latency hits may be unacceptable to network devices, such as in deployments such as in data center networks.

  According to some examples, polling mode drivers 142-1 through 142-n of DPDK polling threads 140-1 through 140-n may be designed or configured to operate in certain polling modes with default settings. Good. As described in more detail below, if the DPDK power management component 150 detects network traffic that has a declining trend, then the DPDK power management component 150 may be configured to perform one or more time periods. Meanwhile, the DPDK polling threads 140-1 to 140-n may be put to sleep, and a hint may be sent to the OS power management module 160. Based on those hints, the OS power management module 160 may cause the PEs 172-1 to 172-n to decrease the processor frequency according to a certain percentage, or to change a transition to an idle state or a sleep state. It may be reduced to save power. Polling mode drivers 142-1 through 142-n may switch from the default polling mode to an interrupt mode if DPDK power management component 150 does not detect any traffic during certain duration thresholds. In this manner, DPDK polling threads 140-1 through 140-n can operate primarily in a polling mode environment to better meet performance requirements when processing packets, and thus frequent mode Switching can be avoided.

  FIG. 2 illustrates one example of the first logic flow. As shown in FIG. 2, an exemplary first logic flow includes logic flow 200. According to some examples, logic flow 200 may be a logic flow for power management associated with processing received packets for an NW device (eg, located at a data center) . In these examples, at least some components of system 100 shown in FIG. 1 may be capable of implementing multiple portions of logic flow 200. However, the exemplary logic flow 200 is not limited to using the components of the system 100 illustrated or described in FIG.

  As shown in FIG. 2, in some examples, the DPDK power management component may be initialized at step S202. In these examples, the DPDK polling thread (e.g., DPDK polling thread 140-1) continues polling the packets from the Rx queue (e.g., Rx queue 130-1) for the NW I / O device. You may start a continuous loop. The loop may continue until it is put to sleep or to an interrupt as described in detail below. In step S 204, for each polling iteration (eg, every 1 to 2 μs) (microseconds), the number of used and unrestricted packet descriptors held in the Rx queue, DPDK power management It may be acquired by a component. In step S206, if there are 0 packets received during a given polling iteration, then in step S208 the number of polling iterations with 0 received packets; It may compare to a continuous number of thresholds, such as iterations. In some instances, if the continuous number of thresholds is not exceeded, the logic flow returns to step S204.

  According to some examples, the "idle" count may be increased by one at step S210 based on the number of polling iterations where the number of received packets is zero. In step S212, a determination is made as to whether the "idle" count is below the threshold "THRESHOLD_1", ie, whether the "idle" count is less than the threshold "THRESHOLD_1". If the "idle" count is less than the threshold "THRESHOLD_1", then in step S214, the DPDK polling thread is put to sleep by the DPDK power management component for a short period of time (eg, a few [μs]). You may In step S216, if the "idle" count is less than the threshold "THRESHOLD_2", then in step S218 the DPDK polling thread sleeps for a relatively long period of time (e.g., tens of microseconds). It may be placed.

  In some examples, the short sleep period may be a short number of [μs] sleep periods, and may reduce power consumption as compared to a continuous spin loop. Thus, having the DPDK polling thread avoid the use of expensive context switches during times when traffic trends are not yet discernible. The relatively long sleep period may be a sleep period if a lower traffic trend is already identified. In the above case, the DPDK power management component may put the DPDK polling thread to sleep for a longer period of time, and even send a long sleep indicator or C-state hint to the OS power management module. Good. The OS power management module may then cause the PE supporting the DPDK polling thread to be in ACPI C1 power state. The above C1 power state allows the PE to power up quickly to the C0 power state when new NW traffic arrives. Also, if new NW traffic arrives, the "idle" count is reset to a factor of zero.

  According to some examples, the threshold "THRESHOLD_1" may be a fraction of the length compared to the threshold "THRESHOLD_2", and after a relatively short period of zero packets in the Rx queue, The DPDK polling thread may be put to sleep. On the other hand, if the "idle" count exceeds the threshold "THRESHOLD_2", then one-shot Rx interrupt may be enabled in step S220. When an incoming packet is received by the NW I / O device, a single interrupt is triggered in step S222 so that the single interrupt switches the suspended DPDK polling thread from interrupt mode back to polling mode. You may An "idle" count above the threshold "THRESHOLD_2" may indicate periods of slow network traffic or periods of no network traffic. Also, interrupting the DPDK polling thread allows the OS power management module to put the PE that runs the DPDK polling thread into a deeper C-state with lower power usage than the C1 power state Make it In fact, the DPRK polling thread may currently be operating in interrupt mode, which may switch back to polling mode in response to receiving network traffic again.

  In some examples, if a packet is received at the Rx queue, the level of Rx queue fullness may be determined. For example, if the Rx queue is nearly empty (eg, 25% to 50% full, etc.) in step S224, then the "trend" count may be increased by a small number in step S226. . If, in step S234, the Rx queue is half full (eg, 51% to 75% full), then in step S236 the "trend" count may be increased by a large number. Also, in step S228, the DPDK power management component may send a performance indicator or P-state hint to the OS power management module if the "trend" count exceeds the trend count threshold. The performance index may be such that the OS power management module may increase the operating frequency for the PE executing the DPDK polling thread, or may increase the ACPI P-state in step S230. Good. An incremental increase in network traffic can be detected and, in step S232, while processing the received packets, gradually increase the P-state for the PE, between power saving and performance. The "trend" count may be set so that it is possible to balance.

  According to some examples, if the Rx queue is substantially filled (e.g., filled with a percentage greater than 76%, etc.) at step S238, then the Rx queue is at step S240. The continuous number of substantially satisfied polling iterations may be compared to a continuous threshold (e.g., 5 polling iterations). In these examples, the DPDK power management component may send a high performance indicator or high P-state hint to the OS power management module if the above continuous threshold is exceeded. A high performance indicator may allow the OS power management module to increase the operating frequency for the PE executing the DPDK polling thread to the highest frequency according to a percentage, in step S242, or It may be possible to raise the ACPI P-state for the PE running the DPDK polling thread to the highest performance P-state. Increasing to the highest performance P-state according to a percentage allows the OS power management module to react quickly to high network traffic loads, thus processing the received packets in step S232. Allows PEs running DPDK polling threads to switch from a balance between power savings and performance to a purely performance-based operating state.

  In some examples, the DPDK power management component periodically monitors the length of time the DPDK polling thread is in sleep. In these examples, the DPDK power management component may initialize a periodic timer in step S244, and step S244 may start a timer period, and monitoring of the sleep state of the DPDK polling thread is: It may be performed during the timer period. Following expiration of the timer in step S246, the DPDK power management component determines whether the DPDK polling thread has been put to sleep for more than 25% of the multiple polling iterations. You may judge. As explained above, based on whether the "idle" count is less than the threshold "THRESHOLD_1" or less than the threshold "THRESHOLD_2", the DPDK polling thread continues to be put to sleep for various periods of time May be If the DPDK power management component finds that the DPDK polling thread has been sleeping for more than 25% of the multiple polling iterations, then the DPDK power management component In step S252, the performance indicator or P-state hint may be sent to the OS power management module. As a result of the transmission of the performance indicator, the OS power management module may cause the PEs executing the DPDK polling thread to operate at a reduced or reduced operating frequency. In other words, the ACPI P-state for that PE may be reduced to a lower performance P-state.

  According to some examples, if the DPDK polling thread has not been put to sleep for more than 25% of the plurality of polling iterations, then the DPDK power management component, in step S250 It may be determined whether the average number of packets per iteration for packets received during the time period is less than the expected average number of packets per iteration threshold. If the average number of packets per iteration for packets received during that time period is below the expected average number of packets per iteration threshold, then the DPDK power management component, in step S252, Performance indicators or P-state hints may be sent to the power management module. The DPDK polling thread has been put to sleep for longer than 25% of multiple polling iterations, or the average number of packets per iteration for packets received during that time period is expected Having the PE lower the P-state of the PE in response to being smaller than the average number of packets per iteration threshold is a performance savings based on the information being monitored. It can be said that there is one way to lower the state at a constant rate, and the information being monitored indicates that the network traffic itself or packets from the network traffic are at least degraded to process. ing.

  FIG. 3 illustrates one example of a first process 300. As shown in FIG. 3, the first process includes process 300. According to some examples, process 300 illustrates how multiple different elements of system 100 can implement multiple portions of logic flow 200 described above for FIG. There is. In particular, these parts are associated with sleep operation, idle operation or interrupt operation taken by the DPDK power management component (PMC). In these examples, at least some of the components of system 100 shown in FIG. 1 may be associated with process 300. However, the exemplary process 300 is not limited to implementations using components of the system 100 shown or described in FIG.

  Starting with process 3.1 (receiving packets), the NW I / O device 110 receives a plurality of packets and at least temporarily stores them in the Rx queue 130.

  Moving to process 3.2, the DPDK polling thread 140 may be able to poll the Rx queue 130 and process those packets if they are received at the Rx queue 130. It is also good.

  Moving to process 3.3 (monitoring available received packet descriptors), the DPDK power management component 150 may include logic and / or features, the logic and / or features comprising a plurality of DPDK polling threads 140 The available received packet descriptors held in the Rx queue 130 are monitored over multiple polling iterations.

  (The number of packets received for consecutive number of polling iterations above the continuous threshold is zero) Moving to process 3.4, the DPDK power management component 150 may include logic and / or features that logic and The feature may determine whether the number of packets being received is zero for a number of polling iterations (e.g., 5 polling iterations) that exceed a continuous threshold.

  Moving to process 3.5 (increasing idle count), the DPDK power management component 150 may include logic and / or features, which logic and / or features poll a continuous number of consecutive thresholds above threshold If the number of packets received for a repetition of 0 is 0, then increase the idle count by a count that is 1.

  Moving to process 3.6A (sleep for a short period of time), the DPDK power management component 150 may include logic and / or features whose logic and / or features have increased idle count (eg, such as THRESHOLD_1, etc.) The DPDK polling thread 140 is put to sleep for a short period of time (e.g., a few microseconds) if it is considered to be less than the first idle count threshold. The above process may then end.

  Moving to the first alternative process in (long-duration sleep) process 3.6B, the DPDK power management component 150 may include logic and / or features whose logic and / or features include increased idle count. If it is considered to be greater than the first idle count threshold but smaller than the second idle count threshold (THRESHOLD_2), DPDK polling during a relatively long sleep period (eg, several tens of μs) Put thread 140 to sleep.

  Moving to process 3.7B (indicator of long sleep), the DPDK power management component 150 may include logic and / or features, which may be included in the OS power management module (PMM) 160 for long sleep An indicator may be sent to indicate that the DPDK polling thread 140 has been put to sleep for a long sleep period.

  Moving to process 3.8B (sleep mode for a long period of time), the OS power management module 160 may place one or more PEs 172 in sleep mode for up to a long sleep period. In some examples, the sleep mode may include an ACPI C1 power state. The above process may then end for this first alternative process.

  Moving to the second alternative process in process 3.6C (turn on one-shot Rx interrupts), the DPDK power management component 150 may include logic and / or features that logic and / or features Sends an interrupt turn-on hinter message to the NW I / O device 110 based on the idle count exceeding a second idle count threshold (eg, THRESHOLD_2, etc.).

  Moving to process 3.7C (switch to interrupt mode), the polling mode driver 142 may switch from operating on the NW I / O device 110 in polling mode to an interrupt mode. The above mode switching may cause the DPDK polling thread 140 to be suspended.

  Moving to process 3.8C (receiving a packet), network traffic 105 may, at this stage, include the packet for processing by DPDK thread 140.

  Turning to process 3.9C, the polling mode driver 142 may switch back to operation on the NW I / O device 110 in polling mode, and the process then proceeds with this second alternative process. You may end with

  FIG. 4 illustrates one example of the second process 400. As shown in FIG. 4, the second process includes process 400. Similar to process 300, process 400 may describe how different elements of system 100 implement the portions of logic flow 200 described above with respect to FIG. In particular, these portions monitor the percentage of sleep state sleeps or the average number of packets per iteration of the DPDK polling thread to determine whether to degrade the performance state of one or more PEs 172. It is related. In these examples, at least some of the components of system 100 shown in FIG. 1 may be associated with process 400. However, the exemplary process 400 is not limited to implementations using components of the system 100 described in FIG.

  Starting with process 4.1 (initializing a timer), the DPDK power management component 150 may include logic and / or features, which logic and / or features initialize a timer having a timer period or May start. In some examples, the timer period may be approximately 100 ms (milliseconds).

  Moving to process 4.2 (monitoring activity and determining percentage of sleep states), the DPDK power management component 150 may include logic and / or features, which may be DPDK polled. Monitor how often thread 140 has been put to sleep.

  Moving to process 4.3 (the timer ends), the timer ends after the timer period described above.

  (Performance Indicator (Sleep%)) Moving to process 4.4A, the DPDK power management component 150 may include logic and / or features that cause the DPDK polling thread 140 to It is determined whether the computer has been in a sleep state for a period of percentage time exceeding a percentage threshold during a period. If the percentage that the DPDK polling thread 140 is in sleep state is above or exceeds the above percentage threshold (eg, greater than 25%), then the DPDK power management component 150 will perform the OS power management module 160 performance. You may send an indicator.

  (Lower Performance State) Moving to process 4.5A, the OS power management module 160 may cause one or more PEs 172 to lower the performance state or P-state. The above process may then end.

  Moving to the first alternative processing in process 4.4B (performance indicator (number of packets per average iteration)), the DPDK power management component 150 may include logic and / or features, which may be logic and / or features Determine whether the average number of packets per iteration is greater or smaller than the packet average threshold. In some examples, the DPDK power management component 150 may send the performance indicator to the OS power management module 160 if the average number of packets per iteration is below the packet average threshold.

  (Lower Performance State) Moving to process 4.5B, the OS power management module 160 may cause one or more PEs 172 to lower the performance state or P-state. The above process may end with this first alternative process.

  FIG. 5 illustrates one example of a third process 500. As shown in FIG. 5, the third process includes process 500. According to some examples, process 500 may describe how different components of system 100 implement portions of logic flow 200 described above with respect to FIG. In particular, these parts are related to monitoring the level of Rx queue fullness to determine if and when to increase the performance of one or more PEs . In these examples, at least some of the components of system 100 shown in FIG. 1 may be associated with process 500. However, the exemplary process 500 is not limited to implementations using components of the system 100 shown or described in FIG.

  Starting from process 5.1 (receiving packets), the NW I / O device 100 may receive packets and store them at least temporarily in the Rx queue 130.

  Moving to process 5.2, the DPDK polling thread 140 may be able to poll the Rx queue 130 and, if packets are being received at the Rx queue 130, those packets. It may be processed.

  Moving to process 5.3 (monitoring available received packet descriptors), the DPDK power management component 150 may include logic and / or features, which may be determined by the DPDK polling thread 140. The available received packet descriptors held in the Rx queue 130 are monitored over multiple polling iterations.

  Turning to process 5.4 (determining the level of Rx queue fullness), the DPDK power management component 150 may include logic and / or features, which may be included after each polling iteration. , Determine the level of Rx queue 130 fullness based on the available packet descriptors held in Rx queue 130.

  Moving to process 5.5 (increasing trend count), the DPDK power management component 150 may include logic and / or features, the logic and / or features being for the logic flow 200 shown in FIG. Based on the determined level of fulfillment of Rx queue 130 as described above, the trend count is increased by a single factor or a larger factor.

  Performance Indicators Turning to process 5.6A, the DPDK power management component 150 may include logic and / or features that indicate that the increased trend count has exceeded the thread count threshold. The performance indicator may be sent to the OS power management module 160 based on

  Moving to process 5.7A (increasing the operating frequency incrementally), the OS power management module 160 may cause one or more PEs 172 to increase the performance state or P-state. In some instances, the performance state of one or more PEs 172 may be increased incrementally or by a single P-state, raising the performance state when executing the DPDK polling thread 140 The operating frequency of one or more PEs 172 can be increased. The above process may then end.

  Turning to the first alternative process (high performance indicator) process 5.6B, the DPDK power management component 150 may include logic and / or features that may be received by the Rx queue 130 (eg, The OS power management module 160 is sent a high performance indicator in response to a continuous number of polling iterations that are determined to be substantially full, such as greater than 75%.

  Moving to process 5.7 B (increasing the operating frequency to the highest frequency), the OS power management module 160 causes the performance state or P-state of one or more PEs 172 to be the highest P-state or the largest P-state. May be increased. In some instances, raising the performance state or P-state of PE 172 to the highest P-state or maximum P-state results in one or more when running DPDK polling thread 140 To raise their PEs 172 to their highest or highest operating frequency. The above process may then end with this first alternative process.

  FIG. 6 illustrates one example of a block diagram of an apparatus 600. While the device 600 shown in FIG. 6 has a limited number of elements in one connection configuration, the device 600 may use alternative connection configurations as described for a given implementation. May contain more or less elements of.

  According to some examples, apparatus 600 may be supported by circuit 620, which may be maintained at or as a computing platform or network device, and as a data center The computing platforms or network devices may be deployed within. The circuit 620 may be configured to execute one or more modules or components 622-a implemented by software or implemented by firmware. It should be noted that "a", "b", "c", and similar specifiers used herein are intended to be variables that represent any positive integer. is there. Thus, for example, if an implementation sets the value as a = 6, then the complete set of software or firmware for multiple components 622-a may be configured 622- 622- 622-. 3, 622-4, 622-5, and 622-6. The examples presented are not limited to the above context, and different variables used throughout the specification may represent the same integer value or different integer values. Also, these "components" may be software / firmware stored in a computer readable storage medium, the plurality of components being a plurality of individual components as shown in FIG. Although shown as a box, this does not limit these components to storage within a plurality of different computer readable media components (e.g., separate memories, etc.).

  According to some examples, circuitry 620 may include a processor or processor circuitry. The circuit 620 includes, but is not limited to, an AMD processor, Athlon processor, Duron processor, Phenom processor, and Opteron processor, Intel Atom processor, Celeron processor, Core (2) Duo processor, Core i3 processor, Core i5 processor, Core It may be any of a variety of commercially available processors, including i7 processors, Pentium processors, Xeon or Xeon Phi processors, and the like. According to some examples, circuit 620 may include an application specific integrated circuit (ASIC), wherein at least some of the example components 622-a are implemented as hardware components of the ASIC May be

  In some examples, apparatus 600 may include queue component 622-1. Queue component 622-1 is executed by circuit 620 to maintain available received packet descriptions held in the receive queue for the NW I / O device over multiple polling iterations for the DPDK polling thread. You may monitor the child. The available received packet descriptors may be included in the available received packet descriptors 610 (eg, as in a data structure such as a look-up table (LUT), etc.) It may be held by the queue component 622-1 in the Rx queue information 623-a. Queue component 622-1 may determine the level of fulfillment for its receive queue based on the available packet descriptors held in the receive queue after each polling iteration. It is also good. The level of the satisfaction may be held in the Rx queue information 623-a.

  In some examples, queue component 622-1 determines the number of packets received in the receive queue during each polling iteration based on the information contained in Rx queue information 623-a. It is also good.

  According to some examples, apparatus 600 may include an augment component 622-2. The increment component 622-2 may be performed by the circuit 620 to increase the trend count after each polling iteration based on the level of fulfillment for that receive queue. In these examples, the trend count may be held by the increment component 622-2 in the trend count 624-b (eg, as in a LUT). If the queue component 622-1 determines that the number of packets being received for consecutive number of polling iterations above the continuous threshold is zero, then the increase component 622-2 The idle count may be increased by a count that is at least one. The idle count may be held by the increment component 622-2 in the idle count 625-c (eg, as in a LUT).

  In some examples, apparatus 600 may include performance component 622-3. The performance component 622-3 may be executed by the circuit 620 to send the performance indicator 640 to the OS power management module based on whether the trending count is above the trending threshold. Performance indicator 640 may allow the OS power management module to increase the performance state of the processing element executing the DPDK polling thread. In these examples, the trend counting threshold described above may be held by performance component 622-3 within trend counting threshold 626-d (eg, as in a LUT).

  According to some examples, in response to the queue component 622-1 determining that its receive queue is substantially full during successive numbers of polling iterations above a continuous threshold. The performance component 622-3 may send high performance indicators to the OS power management module. The high performance indicator 645 may allow the OS power management module to increase the performance state of the processing element to the highest performance state by increasing the operating frequency of the processing element to the highest operating frequency. In these examples, the above continuous threshold may be held by performance component 622-3 within continuous threshold 627-e (eg, as in a LUT).

  In some examples, apparatus 600 may include sleep component 622-4. The sleep component 622-4 may be implemented by the circuit 620. The idle count increased by the increase component 622-2 and held by the idle count 625-c is held by the sleep component 622-4 within the idle count threshold 630-h (eg, as in the LUT) Based on whether the first idle counting threshold is exceeded or less than the first idle counting threshold, the sleep component 622-2 selects one of the first time period or the second time period. In the meantime, the DPDK polling thread may be put to sleep. In these examples, the second time period may be longer than the first time period. Sleep 615 may include an instruction or command to put the DPDK polling thread to sleep.

  According to some examples, sleep component 622-4 puts the DPDK polling thread to sleep for a second period of time based on the idle count exceeding the first idle count threshold. It may also send a long sleep indicator 650 to the OS power management module. The long sleep indicator 650 may allow the OS power management module to put the processing element executing the DPDK polling thread in sleep mode for up to a second time period.

  According to some examples, apparatus 600 may include an interrupt control component 622-5. The interrupt control component 622-4 is executed by the circuit 620 so that the idle count increased by the increase component 622-2 is held by the sleep component 622-5 using the idle count threshold 630-h A message may be sent to the NW I / O device to enable the one-shot Rx interrupt based on whether the second idle count threshold is exceeded. In these examples, the above messages may be included in the one-shot Rx interrupt 635.

  Apparatus 600 may include timer component 622-6. Timer component 622-6 is a timer that is executed by circuit 620 and has a timer period held by timer component 622-6 within timer period 632-j (eg, as in a LUT) You may start

  In some instances, in response to the expiration of the timer initiated by the timer component 622-6, the sleep component 622-4 may repeat that the DPDK polling thread was asleep during that timer period. The percentage of may be determined. The percentage may be held by sleep component 622-4 using sleep information 631-i. In these examples, the performance component 622-3 may send the performance indicator 640 to the OS power management module based on whether the percentage is above the percentage threshold. The performance indicator 640 may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may reduce the operating frequency of the processing element or its processing element It may include reducing the operating voltage. The percentage threshold used in the above determination may be held by performance component 622-3 using percentage threshold 628-f (eg, as in a LUT).

  According to some examples, in response to the timer started by the timer component 622-2 expiring, the queue component 622-1 may receive information about packets received in the receive queue during that timer period. The average number of packets per iteration may be determined. The average number of packets per iteration determined by queue component 622-1 may be maintained (within) using Rx queue information 623-a. In these examples, performance component 622-3 may send performance indicator 640 to OS power management module based on whether the average number of packets per iteration is greater than the packet average threshold. Performance indicator 640 may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may also include reducing the operating frequency of the processing element Good. The packet average threshold may be maintained by performance component 622-3 using average threshold 629-g (eg, as in a LUT).

  The various components of the apparatus 600 and the devices, nodes or logical servers implementing the apparatus 600 may be communicatively coupled to one another by various types of communication media to coordinate multiple operations. Their coordination may involve a one-way or two-way exchange of information. For example, the components described above may communicate information in the form of signals communicated via a communication medium. The information may be implemented as signals assigned to the various signal lines. In such an assignment, each message may be the signal itself. However, further embodiments may alternatively employ data messages. Such data messages may be sent via various connections. Exemplary connections may include parallel interfaces, serial interfaces, and bus interfaces.

  Included herein is a set of logical flows that represent a plurality of exemplary methods for carrying out the new aspects of the disclosed architecture. Although one or more methods are shown and described as a series of acts to simplify the description, one of ordinary skill in the art would recognize that the one or more methods described above are not limited by the order of their acts. It will be understood and correctly recognized. In accordance with the above, some of these operations may be performed in an order different from that shown and described herein, and / or may be performed concurrently with other operations. . For example, one skilled in the art will understand and appreciate that certain methods may alternatively be represented as a series of interrelated states or events as in a state diagram. Furthermore, not all operations described in a method may require a new implementation.

  One logical flow may be implemented by software, firmware, and / or hardware. In software and firmware embodiments, computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium, such as an optical storage device, a magnetic storage device, or a semiconductor storage device. May implement one particular logic flow. These embodiments are not limited to the above context.

  FIG. 7 illustrates one example of the second logic flow. As shown in FIG. 7, the second logic flow example includes logic flow 700. Logic flow 700 may represent some or all of the operations performed by one or more logic, features, or devices described herein, such as apparatus 600. More specifically, the logical flow 700 may be implemented by at least a queue component 622-1, an increase component 622-2, or a performance component 622-3.

  According to some examples, logic flow 700 received at block 702 available available held in a receive queue for an NW I / O device over multiple polling iterations for a DPDK polling thread. Packet descriptors may be monitored. In these examples, queue component 622-1 may monitor its receive queue.

  In some examples, logic flow 700 determines the level of fulfillment of its receive queue at block 704 based on the available packet descriptors held in its receive queue after each polling iteration. You may In these examples, queue component 622-1 may determine the level of fulfillment.

  According to some examples, logic flow 700 may increase the trend count at block 706 based on the level of its receive queue fullness. In these examples, increasing component 622-2 may increase the trend count.

  In some examples, the logic flow 700 may send a performance indicator to the OS power management module based on whether the trending count exceeds the trending threshold at block 708, the performance indicator being the OS The power management module may also be able to increase the performance state of the processing element executing the DPDK polling thread. In these examples, performance component 622-3 may send performance indicators.

  FIG. 8 illustrates one example of the third logic flow. As shown in FIG. 8, the above example of the third logic flow includes logic flow 800. Logic flow 800 may represent some or all of the operations performed by one or more logic, features, or devices described herein, such as apparatus 600. More specifically, logic flow 800 may be implemented by at least queue component 622-1, increase component 622-2, or sleep component 622-4.

  According to some examples, logic flow 800 received at block 802 available available held in a receive queue for the NW I / O device over multiple polling iterations for the DPDK polling thread. Packet descriptors may be monitored. In these examples, queue component 622-1 may monitor its receive queue.

  In some examples, logic flow 800 determines its receive queue for each polling iteration based on the available packet descriptors held in its receive queue after each polling iteration at block 804. The number of packets received at may be determined. In these examples, queue component 622-1 may determine the number of packets received in its receive queue.

  According to some examples, logic flow 800 may only count 1 if the number of packets received for successive numbers of polling iterations above a continuous threshold is 0 at block 806. The idle count may be increased. In these examples, the increase component 622-2 may increase its idle count.

  In some examples, logic flow 800 determines, at block 808, the first time period or the first time period based on whether the idle count is greater than or less than the first idle count threshold. The DPDK polling thread may be put to sleep for one of two time periods, and the second time period is longer than the first time period. In these examples, sleep component 622-4 may put the DPDK polling thread to sleep.

  FIG. 9 illustrates one example of a storage medium 900. As shown in FIG. 9, the first storage medium includes a storage medium 900. The storage medium 900 may include a product. In some examples, storage medium 900 may include any non-transitory computer readable medium or machine readable medium, such as an optical storage device, a magnetic storage device, or a semiconductor storage device. Storage medium 900 may store various types of computer-executable instructions, such as instructions to implement logic flow 700 or logic flow 800. Examples of computer readable storage media or machine readable storage media may include any tangible media capable of storing electronic data, which tangible media are volatile. Memory or non-volatile memory, removable memory or non-removable memory, erasable memory or non-erasable memory, writable memory or rewritable memory, and the like. Examples of computer-executable instructions may be any suitable type of source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. It may contain code. These examples are not limited to the above context.

  FIG. 10 illustrates one example of a computing platform 1000. In some examples, as shown in FIG. 10, computing platform 1000 may include processing component 1040, other platform components 1050, or communication interface 1060. According to some examples, computing platform 1000 may house power management elements and / or performance management elements (e.g., DPDK power management components and OS power management modules) that are managed The element and / or performance management element may provide power management and / or performance management functions to a system having a DPDK polling thread, such as the system 100 of FIG. The computing platform 1000 may be a single physical network device or a configured logical network device, and the configured logical network device may be deployed deployed in a data center It may include a plurality of distributed physical components or a combination of elements comprised of a shared pool of computing resources.

  According to some examples, processing component 1040 may perform processing operations or logic for device 600 and / or storage medium 900. Processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (eg, transistors, resistors, capacitances, inductances, and similar elements), integrated circuits, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), Memory Unit, Logic Gate, Register, Semiconductor Device, Chip, Microchip, Chipset, And others may be included. Examples of software elements are software components, programs, applications, computer programs, application programs, device programs, system drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions , A method, a procedure, a software interface, an application programming interface (API), an instruction set, a computing code, a computer code, a code segment, a computer code segment, a word, a value, a symbol, or any combination thereof. The decision as to whether an embodiment should be implemented using hardware and / or software components depends on the desired computational speed, power level, thermal tolerance, depending on the requirements for a given implementation. It may vary according to a number of factors, such as processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

  In some instances, other platform components 1050 may include one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio Common computing elements such as cards, multimedia input / output (I / O) components (e.g., digital displays), power supplies, and the like may also be included. Examples of memory units include, but are not limited to, read only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), Static RAM (SRAM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash Memory, Ferroelectric Polymer Memory Device, Ovonic Memory, Phase Change or Ferroelectric Memory Memory, polymer memory devices such as memory with silicon-oxide-nitride-oxide-silicon (SONOS) structure, arrays of devices such as magnetic card or optical card, redundant array (RAID) devices consisting of individual disks , Solid state memory devices (eg, USB memory, solid state devices (SSDs), etc.), and any suitable for storing information Various types of computer readable storage media and machine readable storage media in the form of one or more high speed memory units such as other types of storage media may also be included.

  In some examples, communication interface 1060 may include logic and / or features that support communication interfaces. In these examples, communication interface 1060 may include one or more communication interfaces, which operate according to various communication protocols or standards to communicate network communication links. You may communicate via or directly. Direct communication may be performed by using multiple communication protocols or standards, which may be such as industry standards associated with the PCIe specification (including successors and changes) It is described in one or more industry standards. Network communication may be performed by using a plurality of communication protocols or standards, which may be one or more Ethernets (IEEE), as promulgated by the Institute of Electrical and Electronics Engineers (IEEE). It may be the protocol or standard described in the registered trademark standard. For example, one such Ethernet standard may be IEEE 802.3. Network communication may occur according to one or more open flow specifications, such as the open flow hardware abstraction API specification. Network communication may be performed according to the Infiniband architecture specification or the TCP / IP protocol.

  As noted above, computing platform 1000 may be implemented within a single network device or within a logical network device, where the logical network device is a pool of configurable computing resource shares. May consist of a plurality of distributed physical components or elements. Thus, among the various embodiments of the computing platform 1000, the functionality and / or specific features of the computing platform 1000 described herein, as appropriate to physical network devices or logical network devices. The configuration may be included or omitted.

  Components and features of computing platform 1000 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASIS), logic gates and / or single chip architectures. Further, features of computing platform 1000 may be implemented using a microcontroller, a programmable logic array, and / or a microprocessor, or a combination of any of the above components. It should be noted that, herein, hardware, firmware, and / or software components may be collectively or individually referred to as "logic" or "circuits."

  It should be understood that the exemplary computing platform 1000 shown in the block diagram of FIG. 10 may represent one functionally described example of many possible implementations. . Thus, dividing up, omitting, or including multiple block features illustrated in the accompanying drawings is intended to provide a plurality of hardware components, circuits, software, and / or elements for implementing those features. It does not imply that it will necessarily be split, omitted or included in embodiments of the invention.

  One or more aspects of the at least one example may be implemented by a plurality of expressive instructions stored in at least one machine readable medium, the plurality of expressive instructions being a processor To express various logic in the machine, computing device, or system, and configure the logic to execute the techniques described herein into the machine, computing device, or system when read by the machine, computing device, or system You may Such representations, known as "IP cores", may be stored in tangible machine-readable media, and provide those representations to various customer equipment or production equipment, They may be loaded into manufacturing machines, which may actually create the logic or processor described above.

  Various examples may be implemented using multiple hardware elements, software elements, or a combination of both. In some instances, hardware elements may be devices, components, processors, microprocessors, circuits, circuit elements (eg, transistors, resistors, capacitances, inductances, and the like), integrated circuits, specific applications Integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, and more The same may be included. In some instances, software elements include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, A procedure, software interface, application programming interface (API), instruction set, computing code, computer code, code segment, computer code segment, word, value, symbol, or any combination thereof may be included. The decision as to whether an embodiment should be implemented using hardware and / or software components depends on the desired computational speed, power level, thermal tolerance, depending on the requirements for a given implementation. It may vary according to a number of factors such as processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

  Some examples may include the product or at least one computer readable medium. Computer readable media may also include non-transitory storage media storing logic. In some instances, non-transitory storage media may include one or more types of computer readable storage media capable of storing electronic data, the computer readable storage media May include volatile memory, non-volatile memory, removable memory, non-removable memory, erasable memory, non-erasable memory, writable memory, or re-writable memory. In some instances, logic may be software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures May also include various software elements such as, software interfaces, application programming interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. Good.

  According to some examples, a computer readable storage medium may include a non-transitory storage medium, the non-transitory storage medium storing or holding a plurality of instructions, the plurality of instructions May cause the machine, computing device or system to perform a plurality of methods and / or actions according to the described examples when being executed by the machine, computing device or system. The plurality of instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The plurality of instructions described above may be implemented according to a predefined computer language, manner, or syntax for instructing a machine, computing device, or system to perform a certain function. Using any suitable high-level programming language, low-level programming language, object-oriented programming language, visual programming language, compiled programming language, and / or interpreted programming language, the above plurality of Instructions may be implemented.

  Some examples may be described using their derivatives in conjunction with the expressions "one example" or "an example". These terms are meant to mean that at least one example includes certain features, configurations, or characteristics described in connection with that example. Where the description "in one example" appears in various places in the specification, not all of them necessarily refer to the same example. .

  Some examples may be described using their derivatives in conjunction with the expressions "coupled" and "connected." These terms are not necessarily intended as synonyms for each other. For example, the description using "coupled" and / or "connected" indicates that two or more elements are in direct physical or electrical contact with each other It is also good. However, the term "coupled" may mean that two or more elements are not in direct contact with each other but cooperate or interact with each other.

  The following examples relate to additional ones of the examples disclosed herein.

  Example 1: One exemplary device may include a circuit and queue component located on a host computing platform, the queue component being executed by the circuit to generate multiple polls for the DPDK polling thread The available received packet descriptors held in the receive queue for the NW I / O device may be monitored over the iterations of. The queue component may determine the level of fulfillment for the receive queue based on the available packet descriptors held in the receive queue after each polling iteration. The above apparatus may include an increment component, which is executed by the above circuit to, after each polling iteration, trend count based on the level of satisfaction for the receive queue. It may be increased. The above apparatus may include a performance component, which is executed by the above circuit to provide the OS power management module with a performance indicator based on whether the trend count exceeds the trend count threshold. You may send it. The performance indicator may allow the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

  Example 2: In the apparatus of Example 1, the fact that the OS power management module can increase the performance state of a processing element causes that OS power management module to increase the operating frequency of the processing element It may include that it is possible.

  Example 3: In the apparatus of Example 1, the level of fulfillment determined by the queue component may include one of approximately empty, half full, or near full.

  Example 4: In the apparatus of Example 3, if the queue component determines that the level of satisfaction is nearly empty, then the increase component is either a small number or half of the level of satisfaction with the queue component. If it is determined that the trend count may be increased by a large number, the large number is approximately 100 times the small number.

  Example 5: The apparatus of Example 3 has a performance configuration in response to the continuous number of polling iterations determined by the queue component that the receive queue is substantially full exceeds a continuous threshold. An element may include sending high performance indicators to the OS power management module. High performance indicators allow the OS power management module to increase the performance state of the processing element to the highest performance state by causing the operating frequency of the processing element to increase to the highest operating frequency. It is also good.

  Example 5-1: In the device of Example 3, substantially empty may be 25% to 50% full level, and half full may be 51% to 75% full level And may be substantially satisfied may be at a percentage filled level greater than 75%.

Example 6: In the apparatus of Example 1, the OS power management module may increase the performance state of the processing element according to one or more industry standards, including Advanced Configuration and Power Interface (ACPI) Specification Revision 5.1 It may be possible. In these examples, the OS power management module may be able to increase the performance state of the processing element to enter the P _n -1 performance state, where "n" results in the most of the processing elements It represents the lowest performance state leading to a lower operating frequency.

  Example 7: The device of Example 1 has received in the receive queue for each polling iteration the queue component based on the available packet descriptors held in the receiving queue after each polling iteration It may include determining the number of packets. The increment component may increase the idle count by a count of one if the number of packets received during successive number of polling iterations above a continuous threshold is zero. The apparatus may include a sleep component, the sleep component being executed by the circuit and based on whether the idle count is above or below the first idle count threshold. The DPDK polling thread may be put to sleep for one of a time period or a second time period. In these examples, the second time period is longer than the first time period.

  Example 8: The apparatus of Example 7 may include an interrupt control component, the interrupt control component being implemented by the circuit and based on whether the idle count exceeds a second idle count threshold, the NW I //. An interrupt turn on message may be sent to the O device, and the interrupt turn on message may enable a single receive (Rx) interrupt.

  Example 9: In the apparatus of Example 7, the sleep component causes the DPDK polling thread to sleep for a second period of time based on the idle count exceeding the first idle count threshold, and OS power management. The module may send a long sleep indicator. The long sleep indicator may allow the OS power management module to put the processing element executing the DPDK polling thread into sleep mode for up to a second time period.

  Example 10 The apparatus of Example 9 may include a timer component, which may be executed by the circuit to start a timer having a timer period. In response to the timer expiring, the sleep component may determine a percentage of the polling iteration that the DPDK polling thread was asleep for the timer period. The performance component may send a performance indicator to the OS power management module based on whether the percentage is greater than the percentage threshold. The performance indicator may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may reduce the operating frequency of the processing element or reduce the operating voltage May be included.

  Example 11 The apparatus of Example 9 may include a timer component, which may be executed by the circuit to start a timer having a timer period. In response to the timer expiring, the queue component may determine an average number of packets per iteration for packets received in the receive queue during the timer period. The performance component may send a performance indicator to the OS power management module based on whether the average number of packets per iteration is less than the packet average threshold. The performance indicator may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may include reducing the operating frequency of the processing element.

  Example 12: In the apparatus of Example 9, the OS power management module can place the processing element in sleep mode according to one or more industry standards, including Advanced Configuration and Power Interface (ACPI) Specification Revision 5.0 It may be In these examples, the OS power management module may be responsive to the sleep indicator to place the processing element in sleep mode by bringing the processing element into at least a C1 processor power state.

  Example 13: In the apparatus of Example 7, the continuous threshold may be 5 iterations, and each polling iteration may be performed approximately every 1 [μs].

  Example 14: In the apparatus of Example 13, the sleep indicator indicates that the idle count is less than the first idle count threshold, and the sleep indicator allows the DPDK polling thread to sleep for a first period of time. Good. In these instances, the first time period may last for approximately five polling iterations.

  Example 15: In the apparatus of Example 13, the sleep indicator indicates that the idle count is above the first idle count threshold, and the sleep indicator sleeps the DPDK polling thread for a second period of time. It is also good. In these examples, the second time period may last for approximately fifty polling iterations.

  Example 16: In the apparatus of Example 1, the processing element may include one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.

  Example 17: In the apparatus of Example 1, the DPDK polling thread may be capable of executing a network packet processing application, and the network packet processing application may process packets received by the NW I / O device. Good. The network packet processing application may include one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application.

  Example 18 The apparatus of Example 1 may include a digital display connected to the circuit to present a user interface view.

  Example 19: One exemplary method monitors available received packet descriptors held in the receive queue for NW I / O devices over multiple polling iterations for the DPDK polling thread It may include steps. The above method may also include the step of determining the level of fulfillment for the receive queue based on the available packet descriptors held in the receive queue after each polling iteration. The above method may further include the step of increasing the trend count based on the level of fulfillment for the receive queue. The method may further include the step of sending the performance indicator to the OS power management module based on whether the trend count exceeds the trend count threshold. The performance indicator may allow the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

  Example 20: In the method of Example 19, increasing the performance state of the processing element by the OS power management module may include enabling the OS power management module to increase the operating frequency of the processing element.

  Example 21: In the method of Example 19, the level of fulfillment may include one of near empty, half full, or near full.

  Example 22: In the method of Example 21, increasing the trend count by a small number if the level of satisfaction is almost empty, or by a large number if the level of satisfaction is half satisfied. May be included. In these instances, the large number may be approximately one hundred times the small number.

  Example 23: The method of Example 21 provides high performance to the OS power management module in response to the continuous number of polling iterations determined that the receive queue is nearly full exceeding the continuous threshold. It may include the step of sending an indicator. High performance indicators may allow the OS power management module to increase the performance state of the processing element to the highest performance state, and increasing to the highest performance state may result in the highest operating frequency of the processing element It may include increasing to the frequency.

  Example 24: In the method of Example 21, almost empty may be a level that is 25% to 50% full, and half full is a level that is 51% to 75% full. It may be sufficient that the percentage is greater than 75%.

Example 25: In the method of Example 19, the OS power management module may increase the performance state of the processing element according to one or more industry standards, including Advanced Configuration and Power Interface (ACPI) Specification Revision 5.0 It may be possible. In these examples, the OS power management module may be able to increase the performance state of the processing element to enter the P _n -1 performance state, where "n" results in the most of the processing elements It represents the lowest performance state leading to a lower operating frequency.

  Example 26 In the method of Example 17, the processing element may include one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.

  Example 27: In the method of Example 19, the DPDK polling thread may be capable of executing a network packet processing application, and the network packet processing application may process packets received by the NW I / O device. Good. The network packet processing application may include one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application.

  Example 28: One example of the at least one machine-readable medium may include a plurality of instructions, the plurality of instructions responsive to being executed by the system, of Examples 19-27. The system may execute the method according to any one of the above.

  Example 29 The apparatus may include means for performing the method of any one of Examples 19-27.

  Example 30: One example of the at least one machine-readable medium may include a plurality of instructions, the plurality of instructions being responsive to being executed by a system located on a host computing platform The system may be made to monitor available received packet descriptors held in the receive queue for the NW I / O device over multiple polling iterations for the DPDK polling thread. The above instructions also allow the system to determine the level of fulfillment for the receive queue based on the available packet descriptors held in the receive queue after each polling iteration. Good. The above instructions also cause the system to increase the trend count based on the level of satisfaction for the receive queue, and to the OS power management module based on whether the trend count exceeds the trend count threshold. Performance indicators may be sent. The performance indicator may allow the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

  Example 31: In at least one machine readable medium of Example 30, the OS power management module increasing the performance state of the processing element enables the OS power management module to increase the operating frequency of the processing element May be included.

  Example 32: In at least one machine readable medium of Example 30, the level of fulfillment may include one of near empty, half full, or near full.

  Example 33: In at least one machine-readable medium of Example 32, the plurality of instructions described above cause the system to reduce by a small number if the level of satisfaction is almost empty, or half the level of satisfaction. If so, trend counts may be increased by a large number. In these instances, the large number may be approximately one hundred times the small number.

  Example 34: In at least one machine readable medium of Example 32, the plurality of instructions further include: a continuous threshold for a continuous number of polling iterations determined that the receive queue is substantially full In response to the above, the system may cause the OS power management module to send high performance indicators. In these examples, a high performance indicator may allow the OS power management module to increase the performance state of the processing element to the highest performance state, and may increase the performance state to the highest performance state. It may include increasing the frequency to the highest operating frequency.

  Example 35: In at least one machine readable medium of Example 32, approximately empty may be at a level that is 25% to 50% full, and half full is 51% to 75%. The level may be satisfied, and the substantially satisfied may be a level satisfied by more than 75%.

Example 36: In at least one machine readable medium of Example 30, the OS power management module is configured to process one or more of the processing elements according to one or more industry standards, including Extended Configuration and Power Interface (ACPI) Specification Revision 5.0. It may be possible to increase the performance state. The OS power management module may be able to increase the performance state of the processing element to enter P _n -1 performance state, where "n" results in the lowest operating frequency of the processing element It represents the lowest performance state.

  Example 37: In at least one machine readable medium of Example 30, the processing element may include one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.

  Example 38: In at least one machine readable medium of Example 30, the DPDK polling thread may be capable of executing a network packet processing application, the network packet processing application receiving at the NW I / O device Packets may be processed. The network packet processing application may include one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application.

  Example 39: The exemplary method monitors the available received packet descriptors held in the receive queue for the NW I / O device over multiple polling iterations for the DPDK polling thread. May be included. The method also includes, after each polling iteration, determining the number of packets received in the reception queue for each polling iteration based on the available packet descriptors held in the reception queue. May be included. The method may further include the step of increasing the idle count by a count of one if the number of packets received during successive number of polling iterations above a continuous threshold is zero. . The method also determines whether the DPDK polling thread is out of the first time period or the second time period based on whether the idle count is greater than or less than the first idle count threshold. And sleep may be included during one of the steps. The second time period may be longer than the first time period.

  Example 40: The method of Example 39 also includes sending an interrupt turn-on hint to the NW I / O device based on the idle count exceeding the second idle count threshold, causing the DPDK polling thread to be suspended. Good.

  Example 41: The method of Example 39 may include the DPDK polling thread going to sleep for a second period of time based on the idle count exceeding the first idle count threshold. The method may include sending a long sleep indicator to the OS power management module. The long sleep indicator may allow the OS power management module to put the processing element executing the DPDK polling thread into sleep mode for up to a second time period.

  EXAMPLE 42 The method of Example 41 may include the step of starting a timer having a timer period. The method may include the step of determining, in response to the expiration of the timer, a percentage of repetition of polling that the DPDK polling thread was asleep during the timer period. The method may include sending a performance indicator to the OS power management module based on whether the percentage is greater than a percentage threshold. The performance indicator may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may reduce the operating frequency of the processing element or reduce the operating voltage May be included.

  Example 43: The method of Example 41 may include the step of starting a timer having a timer period. The method may include determining an average number of packets per iteration for packets received in the receive queue during the timer period in response to the timer having expired. The method may include sending the performance indicator to the OS power management module based on whether the average number of packets per iteration is less than the packet average threshold. The performance indicator may cause the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may include reducing the operating frequency of the processing element.

  Example 44: In the method of Example 41, the OS power management module can place the processing element in sleep mode according to one or more industry standards, including Advanced Configuration and Power Interface (ACPI) Specification Revision 5.0 It may be In these examples, the OS power management module may be responsive to the sleep indicator to place the processing element in sleep mode by bringing the processing element into at least a C1 processor power state.

  Example 45: In the method of Example 41, the processing element may include one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.

  Example 46: In the method of Example 39, the continuous threshold may be 5 iterations, and each polling iteration may be performed approximately every 1 [μs].

  Example 47: In the method of Example 46, the sleep indicator may indicate that the idle count is less than the first idle count threshold, and the sleep indicator sleeps the DPDK polling thread for a first period of time. You may The first time period may last for approximately five polling iterations.

  Example 48: In the method of Example 46, the sleep indicator may indicate that the idle count is above the first idle count threshold, and the sleep indicator sleeps the DPDK polling thread for a second period of time. It may be in the state. The second time period may last for approximately 50 polling iterations.

  Example 49: In the method of Example 39, the DPDK polling thread may be capable of executing a network packet processing application, and the network packet processing application may process packets received by the NW I / O device. Good. The network packet processing application may include one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application.

  Example 50: One example of the at least one machine-readable medium may include a plurality of instructions, the plurality of instructions being responsive to being executed by a system located on a host computing platform The system may execute the method according to any one of Examples 39 to 49.

  Example 51: An exemplary apparatus may include means for performing the method of any one of Examples 39-49.

  Example 52: One example of the at least one machine readable medium may comprise a plurality of instructions, the plurality of instructions being responsive to being executed by a system located on a host computing platform The system may be made to monitor available received packet descriptors held in the receive queue for the NW I / O device over multiple polling iterations for the DPDK polling thread. The above instructions cause the system to count the number of packets received in the receive queue for each polling iteration based on the available packet descriptors held in the receive queue after each polling iteration. You may decide to The above instructions cause the system to increase the idle count by a count of one if the number of packets received during consecutive number of polling iterations above the consecutive threshold is zero. May be The plurality of instructions may cause the system to receive the DPDK polling thread for a first time period or a second time period based on whether the idle count is greater than or less than the first idle count threshold. It may be caused to sleep during one of the time periods. The second time period may be longer than the first time period.

  Example 53: In at least one machine-readable medium of Example 52, the plurality of instructions as described above, wherein the system generates an NW I / O device based on the idle count exceeding the second idle count threshold. An interrupt turn on hint may be sent to cause the DPDK polling thread to be suspended.

  Example 54: In at least one machine-readable medium of Example 52, the DPDK polling thread sleeps for a second period of time based on the idle count exceeding the first idle count threshold. May be configured. The plurality of instructions above may cause the system to send a long sleep indicator to the OS power management module. The long sleep indicator may allow the OS power management module to put the processing element executing the DPDK polling thread into sleep mode for up to a second time period.

  Example 55: In at least one machine readable medium of Example 54, the plurality of instructions causes the system to start a timer having a timer period, and in response to the timer ending, for a timer period. Let the DPDK poll thread determine the percentage of polling iterations that were sleeping. The plurality of instructions may cause the system to send a performance indicator to the OS power management module based on whether the percentage is greater than the percentage threshold. The performance indicator may allow the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may reduce the operating frequency of the processing element or reduce the operating voltage May be included.

  Example 56: In at least one machine readable medium of Example 54, the plurality of instructions causes the system to start a timer having a timer period, and in response to the timer ending, for a timer period. The average number of packets per iteration may be determined for packets received in the receive queue. The plurality of instructions above may cause the system to send a performance indicator to the OS power management module based on whether the average number of packets per iteration is less than the packet average threshold. The performance indicator may cause the OS power management module to reduce the performance state of the processing element, and reducing the performance state of the processing element may include reducing the operating frequency of the processing element.

  Example 57: In at least one machine-readable medium of Example 54, the OS power management module processes the processing elements according to one or more industry standards, including Extended Configuration and Power Interface (ACPI) Specification Revision 5.0 It may be possible to put it in sleep mode. The OS power management module may be responsive to the sleep indicator to place the processing element in sleep mode by bringing the processing element to at least a C1 processor power state.

  Example 58: In at least one machine readable medium of Example 54, the processing element may include one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.

  Example 59: In at least one machine readable medium of Example 51, the continuous threshold may include 5 iterations, and each polling iteration may be performed approximately every 1 [μs] .

  Example 60: In at least one machine readable medium of Example 59, the sleep indicator may indicate that the idle count is less than the first idle count threshold, and the sleep indicator indicates that the DPDK polling thread Sleep for a period of time. The first time period may last for approximately five polling iterations.

  Example 61: In at least one machine-readable medium of Example 59, the sleep indicator may indicate that the idle count is above the first idle count threshold, and the sleep indicator includes the DPDK polling thread. It may sleep for a time period of two. The second time period may last for approximately 50 polling iterations.

  Example 62: In at least one machine readable medium of Example 52, the DPDK polling thread may be capable of executing a network packet processing application, the network packet processing application receiving at the NW I / O device Packets may be processed. The network packet processing application may include one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application.

  The abstract is written to comply with 37 C.FR 1.7 1.72 (b), which allows the reader to quickly uncover the nature of the technical disclosure. Note that you are requesting for the abstract. The abstract is not used to interpret or limit the scope or meaning of the claimed invention, since the abstract is submitted for understanding. Furthermore, it will be understood that, among the forms for carrying out the invention described above, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure content. . Such disclosed approach reflects the intention that the claimed invention portion of the embodiments requires more features than the features explicitly stated in each claim It should not be interpreted as a thing. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are incorporated into the Description of the Invention, with each claim standing on its own as a separate embodiment. In the appended claims, the words "including" and "in which" may be used as plain synonyms for "comprising" and "wherein", respectively. Furthermore, the ordinal adjectives "first", "second", and "third" etc. are only used as labels, and their ordinal adjectives It is not intended to add numerical requirements to the subject.

Although the subject matter of the present invention has been described in a specific description of the structural features and / or the operation of the method, the subject matter defined in the appended claims is not necessarily the specific one described above. It should be understood that the invention is not limited to the features or operations. Rather, those specific features and acts described above are disclosed in an exemplary form for implementing the claimed invention.

Claims (21)

A device,
Circuitry located on the host computing platform;
Available reception performed by the circuit and held in a receive queue for network input / output (NW I / O) devices over multiple polling iterations for a data plane deployment kit (DPDK) polling thread Queue component for monitoring different packet descriptors, wherein the queue component is configured for the reception queue based on available packet descriptors held in the reception queue after each polling iteration A receive queue component configured to determine the level of satisfaction of
An incrementing component that is executed by the circuit to increase the trend count after each polling iteration based on the level of satisfaction for the receive queue;
A performance component that is executed by the circuit to send performance indicators to an operating system (OS) power management module based on whether the trending count exceeds a trending threshold or not;
Including
The performance indicators, the operating system (OS) power management module, and possible to increase the performance state of the processing element running the data plane development kit (DPDK) polling thread,
The level of fulfillment determined by the queue component includes one of: substantially empty, half filled or nearly filled;
The increasing component determines that the queue component has fulfilled the level of fulfillment by a small number, or if the queue component has determined that the level of fulfillment is substantially empty. If so, it is arranged to increase the trend count by a large number, the large number being approximately 100 times the small number,
apparatus.   The operating system (OS) power management module may increase the performance state of the processing element such that the operating system (OS) power management module increases the operating frequency of the processing element The apparatus according to claim 1, comprising: Said performance component responsive to the fact that a continuous number of polling iterations determined by said queue component to be substantially full of said receive queue exceeds a continuous threshold. (OS) sending a high performance indicator to a power management module, said high performance indicator causing said operating system (OS) power management module to increase the operating frequency of said processing element to the highest operating frequency it by makes it possible to increase the performance state of the processing element to the highest performance state, the apparatus according to claim 1. Almost empty is a level that is 25% to 50% full, half full is a level that is 51% to 75% full, and almost full is more than 75% The apparatus according to claim 1 , wherein the apparatus is a large percentage full level. The operating system (OS) power management module is capable of increasing the performance state of the processing element in accordance with one or more industry standards, including Advanced Configuration and Power Interface (ACPI) Specification Revision 5.0. And the operating system (OS) power management module can increase the performance state of the processing element to enter P _n -1 performance state, where "n" is the lowest of the processing element The apparatus of claim 1 representing the lowest performance condition leading to an operating frequency. The device is
The queue component determines, after each polling iteration, the number of packets received in the reception queue for each polling iteration based on available packet descriptors held in the reception queue. Including
The increasing component is configured to increase the idle count by a count that is one if the number of packets received during successive number of polling iterations above a continuous threshold is zero;
The apparatus is executed by the circuit and the first time period or the second time period based on whether the idle count is above or below the first idle count threshold. 2. The method of claim 1, further comprising a sleep component causing the data plane deployment kit (DPDK) polling thread to sleep during one of the steps, wherein the second period of time is longer than the first period of time. Device described. Send an interrupt turn-on message to the network input / output (NW I / O) device based on whether or not performed by the circuit and based on whether the idle count exceeds a second idle count threshold to receive single-shot reception (Rx) 7. The apparatus of claim 6 , including an interrupt control component that enables interrupts. The apparatus sleeps the Data Plane Deployment Kit (DPDK) polling thread for the second period of time based on the idle count being greater than the first idle count threshold. And sending a long sleep indication to the operating system (OS) power management module, the long sleep indication indicating that the operating system (OS) power management module is operable for up to the second time period. 7. The apparatus of claim 6 , enabling the processing element executing the data plane deployment kit (DPDK) polling thread to be placed in sleep mode. The device is
Including a timer component implemented by said circuit to start a timer having a timer period,
In response to the timer expiring, the sleep component determines a percentage of polling iterations in which the Data Plane Deployment Kit (DPDK) polling thread was asleep during the timer period;
The performance component may send a performance indicator to the operating system (OS) power management module based on whether the percentage is greater than a percentage threshold, the performance indicator being OS) Allowing a power management module to reduce the performance state of the processing element, reducing the performance state of the processing element reduces the operating frequency of the processing element or reduces the operating voltage The apparatus according to claim 8 , comprising. The device is
Including a timer component implemented by said circuit to start a timer having a timer period,
In response to the timer expiring, the queue component determines an average number of packets per iteration for packets received in the receive queue during the timer period;
The performance component sends a performance indicator to the operating system (OS) power management module, based on whether the average number of packets per iteration is less than a packet average threshold, the performance indicator indicating system (OS) power management module, and enables to reduce the performance state of the processing element, lowering the performance state of the processing element comprises reducing the operating frequency of the processing elements, to claim 8 Device described. The device is
The operating system (OS) power management module may be capable of placing the processing element in sleep mode according to one or more industry standards, including Extended Configuration and Power Interface (ACPI) Specification Revision 5.0 The operating system (OS) power management module is configured to place the processing element in the sleep mode by bringing the processing element into at least a C1 processor power state in response to the sleep indicator. An apparatus according to claim 8 . The continuous threshold includes 5 iterations, and each polling iteration is performed approximately every 1 microsecond, and the sleep indicator is such that the idle count is less than the first idle count threshold. Indicate that the sleep indicator puts the data plane deployment kit (DPDK) polling thread to sleep for the first period of time, and the first period of time is approximately between five polling iterations. 9. The device of claim 8 which is persistent. The sleep indicator indicates that the idle count is above the first idle count threshold, and the sleep indicator sleeps the data plane deployment kit (DPDK) polling thread for the second period of time. The apparatus of claim 11 , wherein said second time period lasts for approximately fifty (50) polling iterations.   The apparatus of claim 1, wherein the processing element comprises one of a core of a multi-core processor or a virtual machine supported by one or more cores of the multi-core processor.   The Data Plane Deployment Kit (DPDK) polling thread can execute a network packet processing application, and the network packet processing application processes packets received by the network input / output (NW I / O) device The network packet processing application includes one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application. The device according to 1. Method,
Monitoring available received packet descriptors held in a receive queue for network input / output (NW I / O) devices over multiple polling iterations for a data plane deployment kit (DPDK) polling thread Step to
Determining the level of fulfillment for the receive queue based on available packet descriptors held in the receive queue after each polling iteration, the level of fulfillment being substantially empty some, including they meet half or are almost satisfied, one of the steps,
Increasing trend counts based on the level of fulfillment for the receive queue;
Based on whether the trend count exceeds the trend count threshold, a step of sending the performance indicators for the operating system (OS) power management module, the performance indicators, the operating system (OS) power management module, Enabling to increase the performance state of processing elements executing said data plane development kit (DPDK) polling thread;
Sending a high performance indicator to the operating system (OS) power management module in response to the continuous number of polling iterations determined that the receive queue is nearly full exceeding a continuous threshold Including the steps, wherein the high performance indicator enables the operating system (OS) power management module to increase the performance state of the processing element to the highest performance state, and to the highest performance state. Includes increasing the operating frequency of the processing element to the highest operating frequency,
Method. Method,
Monitoring available received packet descriptors held in a receive queue for network input / output (NW I / O) devices over multiple polling iterations for a data plane deployment kit (DPDK) polling thread Step to
Determining, after each polling iteration, the number of packets received in the reception queue for each polling iteration based on the available packet descriptors held in the reception queue;
Increasing the idle count by a count that is 1 if the number of packets received during successive number of polling iterations above a continuous threshold is zero;
The Data Plane Deployment Kit (DPDK) polling thread for a first time period or a second time based on whether the idle count is above or below a first idle count threshold. a step of the one during sleep state of period, the second time period is longer than said first time period, the steps,
Send an interrupt turn-on hint to the network input / output (NW I / O) device based on the idle count exceeding the second idle count threshold and suspend the data plane deployment kit (DPDK) polling thread Including the steps of
Method. The method is
Including the Data Plane Deployment Kit (DPDK) polling thread sleeping for the second period of time based on the idle count exceeding the first idle count threshold;
Sending a long sleep indication to an operating system (OS) power management module, wherein the long sleep indication indicates that the operating system (OS) power management module has received the data plane up to the second time period. The method according to claim 17 , enabling the processing element executing the deployment kit (DPDK) polling thread to be put into sleep mode. The method is
Starting a timer having a timer period;
Determining, in response to the expiration of the timer, a percentage of polling iterations in which the Data Plane Deployment Kit (DPDK) polling thread was asleep during the timer period;
Sending a performance indicator to the operating system (OS) power management module based on whether the percentage is greater than a percentage threshold, the performance indicator including: the operating system (OS) power management module but make it possible to reduce the performance state of the processing element, lowering the performance state of the processing element comprises reducing the or operating voltage reduces the operating frequency of the processing element, according to claim 18 The method described in. The method is
Starting a timer having a timer period;
Determining an average number of packets per iteration for packets received in the receive queue during the timer period in response to the timer expiring;
Sending a performance indicator to the operating system (OS) power management module based on whether the average number of packets per iteration is less than a packet average threshold, the performance indicator including: The method according to claim 18 , wherein operating system (OS) power management module reduces the performance state of the processing element, and reducing the performance state of the processing element includes reducing the operating frequency of the processing element. The method is
The operating system (OS) power management module may be capable of placing the processing element in sleep mode according to one or more industry standards, including Extended Configuration and Power Interface (ACPI) Specification Revision 5.0 The operating system (OS) power management module is configured to place the processing element in the sleep mode by bringing the processing element into at least a C1 processor power state in response to the sleep indicator. The method according to claim 18 .

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