JP6428890B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

  The present invention relates to a technique for manufacturing a semiconductor light emitting device having a full-surface electrode made of metal.

One method for mounting a semiconductor light emitting element on a mounting substrate is a flip chip mounting method. A semiconductor light emitting device used for flip chip mounting is connected to an n type semiconductor layer and a p type semiconductor layer formed on a substrate such as sapphire, and the n type semiconductor layer and the p type semiconductor layer, respectively. A p-side electrode and an n-side electrode formed on the same plane side. Then, the p-type semiconductor layer and the n-type semiconductor layer are disposed on the lower side, and the p-side electrode and the n-side electrode are opposed to the wiring electrode on the mounting substrate.
At this time, the light extraction surface from the semiconductor light emitting element is the substrate side opposite to the surface on which the semiconductor layers are stacked. For this reason, the semiconductor layer side is provided with a reflecting member for reflecting light to the substrate side.

For example, in Patent Documents 1 to 3, an n-type semiconductor layer and a p-type semiconductor layer are stacked in this order on a sapphire substrate, and the upper surface of the p-type semiconductor layer is made of Ag or an Ag alloy, In particular, there is described a semiconductor light-emitting element that is mounted in a flip chip type and has a metal reflective film having good reflectivity with respect to visible light. Further, in the semiconductor light emitting devices described in these patent documents, in order to prevent migration of Ag contained in the metal reflection film, a metal film that covers the metal reflection film is provided, and further, p is formed on the metal film. Side pad electrodes are provided.
In addition, the semiconductor light emitting devices described in Patent Document 2 and Patent Document 3 are covered with an insulating film made of oxide or nitride, including the metal film, except for the connection portion with the outside of the pad electrode.

JP 2007-80924 A JP 2006-245231 A JP 2012-238823 A

  An insulating film made of an oxide or the like and a metal film do not necessarily provide good adhesion, and there is a concern that the insulating film may be peeled off from the metal film or a gap may be formed at the joint. When the insulating film is peeled off from the metal film or a gap is formed, the metal film is exposed to moisture or oxygen in the atmosphere and deteriorates. As a result, when the Ag migration preventing function of the metal film is lowered, Ag migration occurs, and the function as a semiconductor light emitting element is impaired.

  Further, the metal film for preventing the migration described above is configured in consideration of the barrier property against Ag and the adhesiveness with the reflective film. For example, in the semiconductor light emitting devices described in Patent Document 2 and Patent Document 3, Ni, Pt, and Ti are used for the lowermost layer of the migration-preventing metal film in contact with the reflective film. However, since these metals have a relatively low reflectance with respect to visible light in particular, light cannot be sufficiently reflected at the surface where the metal film and the semiconductor layer are in contact with each other at the outer edge of the reflective film, which affects the light extraction efficiency. It was.

  The present invention was devised in view of such problems, and in a semiconductor light-emitting device including a reflective film containing Ag and a metal film that prevents migration of Ag contained in the reflective film, the present invention prevents migration. It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device that maintains good effects and improves light extraction efficiency.

  The method for manufacturing a semiconductor light emitting device according to the present invention includes a semiconductor stacked body forming step of forming a semiconductor stacked body by stacking an n-type semiconductor layer and a p-type semiconductor layer, and an upper surface of the p-type semiconductor layer. A first metal film forming step of forming a first metal film so as to be Ag or an alloy containing Ag as a main component, and covering the surface of the first metal film using Al or an alloy containing Al as a main component A second metal film forming step of forming the second metal film, and a metal oxide film covering at least the surface of the second metal film and containing at least an oxide of a metal material constituting the second metal film A metal oxide film forming step to be formed; and a second metal film exposing step of forming a recess in the second metal film so that a part of the surface of the second metal film is exposed from the metal oxide film by etching; A third metal film is formed on the recess of the second metal film. A third metal film forming step of forming, but was the procedure performed sequentially.

  In the semiconductor light emitting device manufactured by the method of manufacturing a semiconductor light emitting device according to the present invention, the second metal film that prevents migration of Ag contained in the first metal film that is the reflective film is used as the second metal film. The second metal film is prevented from being deteriorated by covering with a metal oxide film containing an oxide of a metal material constituting the metal and an insulating film made of oxide, and as a result, the migration preventing effect of the second metal film is reduced. Can be prevented. Moreover, since the reflectance at the surface where the second metal film and the semiconductor layer are in contact with each other is improved by using Al or a metal material containing Al as a main component as the second metal film, the light extraction efficiency of the semiconductor light emitting device is improved. To do.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, a semiconductor light emitting device having the above-described effects can be manufactured.

1 is a schematic plan view showing a structure of a semiconductor light emitting element according to a first embodiment of the present invention. It is typical sectional drawing in the BB line of FIG. 1A. It is typical sectional drawing in the CC line of FIG. 1A. It is an enlarged view of the area | region B of FIG. 1B. It is an enlarged view of the area | region C of FIG. 1C. It is typical sectional drawing in the A1-A2-A3-A4 line | wire of FIG. 1A. It is a typical expanded sectional view of the connection part of the cover electrode and p side electrode of the semiconductor light-emitting device which concerns on 1st Embodiment of this invention. It is a flowchart which shows the flow of the manufacturing method of the semiconductor light-emitting device concerning 1st Embodiment of this invention, and shows the whole manufacturing process. It is a flowchart which shows the flow of the manufacturing method of the semiconductor light-emitting device concerning 1st Embodiment of this invention, and shows the detail of a 2nd metal film exposure process. It is typical sectional drawing which shows a mode that the semiconductor laminated body was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the whole surface electrode was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the metal film used as a cover electrode was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the resist pattern for shaping a cover electrode was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the cover electrode was shape | molded in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the metal oxide film was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the level | step-difference part was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is typical sectional drawing which shows a mode that the insulating film was formed in the manufacturing process of the semiconductor light-emitting device concerning 1st Embodiment of this invention. It is a typical sectional view showing signs that a resist pattern for forming a p side electrode and an n side electrode was formed in a manufacturing process of a semiconductor light emitting element concerning a 1st embodiment of the present invention. In the manufacturing process of the semiconductor light emitting device according to the first embodiment of the present invention, it is a schematic cross-sectional view showing a state where the cover electrode and the n-type semiconductor layer are exposed. It is a typical sectional view showing signs that a metal film used as a p side electrode and an n side electrode was formed in a manufacturing process of a semiconductor light emitting element concerning a 1st embodiment of the present invention. It is a typical sectional view showing signs that the p side electrode and the n side electrode were shaped in the manufacturing process of the semiconductor light emitting element concerning a 1st embodiment of the present invention. It is a typical top view which shows the structure of the semiconductor light-emitting device concerning 2nd Embodiment of this invention. It is typical sectional drawing in the AA of FIG. 8A. It is the typical sectional view which changed the scale partially in the AA line of Drawing 8A. It is a flowchart which shows the flow of the manufacturing method of the semiconductor light-emitting device which concerns on 2nd Embodiment of this invention. It is typical sectional drawing which shows a mode that the 1st insulating film, the p side electrode, and the n side electrode were formed in the manufacturing process of the semiconductor light-emitting device concerning 2nd Embodiment of this invention. It is typical sectional drawing which shows a mode that the 2nd insulating film was formed in the manufacturing process of the semiconductor light-emitting device concerning 2nd Embodiment of this invention. It is typical sectional drawing which shows a mode that the pad electrode for eutectic was formed in the manufacturing process of the semiconductor light-emitting device concerning 2nd Embodiment of this invention. It is a typical top view showing the structure of the semiconductor light emitting element concerning a 3rd embodiment of the present invention. It is typical sectional drawing in the AA of FIG. 11A. It is the typical sectional view which changed the scale partially in the AA line of Drawing 11A. It is a typical top view showing the structure of the semiconductor light emitting element concerning a 4th embodiment of the present invention. It is typical sectional drawing in the AA of FIG. 12A. It is the typical sectional view which changed the scale partially in the AA line of Drawing 12A. It is a flowchart which shows the flow of the manufacturing method of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is typical sectional drawing which shows a mode that the cover electrode and the metal oxide film were formed in the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is typical sectional drawing which shows a mode that the n side electrode was formed in the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is typical sectional drawing which shows a mode that the insulating film was formed in the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is typical sectional drawing which shows a mode that the cover electrode and the n side electrode were exposed in the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is typical sectional drawing which shows a mode that the pad electrode for eutectic was formed in the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment of this invention. It is a typical top view showing the structure of the semiconductor light emitting element concerning a 5th embodiment of the present invention. It is typical sectional drawing in the AA of FIG. 16A. It is the typical sectional view which changed the scale partially in the AA line of Drawing 16A.

Hereinafter, a semiconductor light emitting device and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the drawings.
Note that the drawings referred to in the following description schematically show the present invention, and therefore the scale, spacing, positional relationship, etc. of each member are exaggerated, or some of the members are not shown. There is a case. In addition, the scale and interval of each member may not match in the plan view and the cross-sectional view thereof. Moreover, in the following description, the same name and the code | symbol are showing the same or the same member in principle, and suppose that detailed description is abbreviate | omitted suitably.

<First Embodiment>
[Configuration of Semiconductor Light Emitting Element]
The configuration of the semiconductor light emitting device according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1F. 1F is a cross-sectional view taken along a line connecting positions A1-A2-A3-A4 in FIG. 1A. In addition, FIG. 1F shows the width and arrangement interval of each member appropriately enlarged or reduced for easy understanding of the internal structure of the semiconductor light emitting element. Further, the positions A1 to A4 shown in FIG. 1F correspond to the positions A1 to A4 in FIG. 1A, respectively.
The semiconductor light emitting device 1 according to the first embodiment is an LED (light emitting diode) mounted in a flip chip type. As shown in FIGS. 1A to 1F, the semiconductor light emitting device 1 according to the first embodiment includes a substrate 2, a semiconductor stacked body 3 stacked on the substrate 2, an n-side electrode 4n, a full surface electrode 41, a cover. The electrode 42, the metal oxide film 43, the p-side electrode 4p, and the insulating film 6 are provided. In this example, both the n-side electrode 4n and the p-side electrode 4p are provided on the surface of the substrate 2 on the side where the semiconductor laminate 3 is provided so as to be suitable for flip chip mounting.

In FIG. 1A, illustration of the insulating film 6 and the metal oxide film 43 is omitted. Further, in the cross-sectional views shown in FIGS. 1B to 1F, hatching is omitted for each layer of the substrate 2 and the semiconductor stacked body 3.
Further, in this specification, “upper” means a direction perpendicular to the surface of the substrate 2 on which the semiconductor stacked bodies 3 are stacked and the direction in which the semiconductor stacked bodies 3 are stacked. For example, in FIG. 1B, it points upward in the figure.

(substrate)
The board | substrate 2 should just be a board | substrate material which can grow the semiconductor laminated body 3 epitaxially, and a magnitude | size, thickness, etc. are not specifically limited. When the semiconductor laminate 3 is made of a nitride semiconductor, the substrate material is an insulating substrate such as sapphire or spinel (MgA1 ₂ O ₄ ) whose main surface is any one of the C-plane, R-plane, and A-plane, In addition, examples include oxide substrates such as silicon carbide (SiC), silicon, ZnS, ZnO, GaAs, diamond, and lithium niobate and neodymium gallate that are lattice-bonded to a nitride semiconductor. In addition, since the semiconductor light emitting element 1 in the present embodiment is mounted in a flip chip type, the back surface of the substrate 2 is a light extraction surface. Therefore, since the light emitted from the semiconductor light emitting element 1 passes through the substrate 2 and is emitted from the light extraction surface, the substrate 2 is preferably at least transparent to the wavelength of this light.

(Semiconductor laminate)
The semiconductor stacked body 3 has a stacked structure in which an n-type semiconductor layer 31, an active layer 32, and a p-type semiconductor layer 33 are stacked in this order from the substrate 2 side. Further, in the present embodiment, a stepped portion in which all of the p-type semiconductor layer 33 and the active layer 32 and a part of the n-type semiconductor layer 31 are removed in the thickness direction in a part of the surface of the semiconductor stacked body 3. 3a and 3b are provided.

The step portion 3a is a region for providing the n-side electrode 4n. In this embodiment, as shown to FIG. 1A, the level | step difference part 3a is carrying out the substantially circular shape by planar view. That is, as the stepped portion 3 a, columnar concave portions are provided at nine locations of the semiconductor stacked body 3. Further, the step portion 3b is formed at the outer edge portion of the semiconductor stacked body 3, and is the remaining portion of the cleave region for chipping the semiconductor light emitting element 1 from the wafer in the manufacturing process.
Note that the number, shape, and location of the stepped portions 3a are not limited to this example, and one or more locations can be provided in any region in any shape.

The n-type semiconductor layer 31, the active layer 32, and the p-type semiconductor layer 33 are not particularly limited, but in the case of a nitride semiconductor, for example, In _X Al _Y Ga _1- XYN (0 ≦ X , 0 ≦ Y, X + Y ≦ 1), and the like, and gallium nitride compound semiconductors are preferably used. Each of the n-type semiconductor layer 31, the active layer 32, and the p-type semiconductor layer 33 may have a single layer structure, but may have a stacked structure of layers having different compositions and film thicknesses, a superlattice structure, or the like. In particular, the active layer 32 that is a light-emitting layer preferably has a single quantum well or multiple quantum well structure in which thin films that generate quantum effects are stacked, and the well layer is preferably a nitride semiconductor containing In. Note that the n-type semiconductor layer 31 may be formed on the substrate 2 through a base layer (not shown) such as a buffer layer for arbitrarily relaxing the lattice constant mismatch with the substrate 2.

  In the present invention, the method for forming the semiconductor layer is not particularly limited, but MOVPE (metal organic chemical vapor deposition), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecule). As a method for growing a nitride semiconductor such as a line epitaxy method, a known method can be suitably used. In particular, MOCVD is preferable because it can be grown with good crystallinity. Moreover, it is preferable that the semiconductor stacked body 3 is appropriately selected from various growth methods depending on the purpose of use of each layer.

(Full-surface electrode (first metal film))
The entire surface electrode 41 is provided on the p-type semiconductor layer 33 so as to cover substantially the entire surface of the p-type semiconductor layer 33, and a current supplied from the outside through the p-side electrode 4 p and the cover electrode 42 is supplied to the p-type semiconductor layer 33. This is an electrode for uniformly diffusing to the entire surface of the layer 33. In addition, in the semiconductor light emitting device 1 according to the present embodiment that is mounted in a flip chip type, it also functions as a reflection film for reflecting the light emitted from the active layer 32 to the back surface side of the substrate 2 that is the light extraction surface. Have.

  The full-surface electrode 41 is preferably an ohmic electrode that can be electrically connected to the p-type semiconductor layer 33 and has a good reflectivity with respect to at least the wavelength of light emitted from the active layer 32. preferable. For this reason, the entire surface electrode 14 in the present embodiment is a single layer film of Ag or an alloy containing Ag as a main component, Ni, Ti or the like whose uppermost layer is an alloy containing Ag or Ag as a main component. And a multilayer film can be suitably used. More preferably, a multilayer film of Ag / Ni / Ti / Ru with Ag as the lowermost layer (p-type semiconductor layer 33 side) can be used. The full surface electrode 41 can be formed by sequentially laminating these materials by, for example, sputtering or vapor deposition.

  The film thickness of the entire surface electrode 41 is not particularly limited. For example, in the case of forming with a single layer film of Ag or an alloy containing Ag as a main component, the film thickness that can effectively reflect light from the active layer 32, Specifically, it can be about 20 to 1000 nm, preferably about 50 to 300 nm, and more preferably about 100 nm. When the entire surface electrode 41 is a multilayer film, the total film thickness can be about 50 to 5000 nm, and preferably about 50 to 1000 nm, and within this range, Ag or an Ag alloy contained in the multilayer film The film thickness of the film can be adjusted appropriately. When the entire surface electrode 41 is a multilayer film, the Ag or Ag alloy film and the film laminated thereon may be formed in the same shape by patterning in the same process, but the lowermost layer Ag or Ag It is preferable to coat the alloy film with a film laminated thereon (preferably, a metal film made of Ni, Ti or the like that does not react with Ag). As a result, no matter what electrode material is formed as a part of the entire surface electrode 41 on the metal film that does not react with Ag, it is not in direct contact with Ag or the Ag alloy film, thereby preventing reaction with Ag. can do.

(Cover electrode (second metal film))
The cover electrode 42 is a metal film that covers the entire surface of the entire surface electrode 41, that is, the entire upper surface and side surfaces, and functions as a barrier layer for preventing the migration of the constituent material of the entire surface electrode 41, particularly Ag.
The cover electrode 42 is in contact with the upper surface of the p-type semiconductor layer 33 at the outer edge portion of the full-surface electrode 41, and functions as a reflective film at the contact surface with the p-type semiconductor layer 33.

  In the semiconductor stacked body 3 in the vicinity where the n-side electrode 4n is provided, the current density is high. For this reason, the emission intensity is high in the active layer 32 in a region facing the n-side electrode 4n in plan view. Therefore, in the region where the emission intensity is high, the light extraction efficiency can be improved by increasing the reflectance of the cover electrode 42 in contact with the p-type semiconductor layer 33 stacked on the active layer 32.

For this reason, as the cover electrode 42, it is preferable to use a material that satisfactorily prevents Ag migration of the entire surface electrode 41 and has a high reflectance with respect to the wavelength of light emitted from the active layer 32. As such a material, Al or an alloy containing Al as a main component can be used. As an alloy containing Al as a main component, for example, an Al—Cu alloy (for example, Cu: 2 mass%, Al: balance), an Al—Cu—Si alloy (for example, Cu: 2 mass%, Si: 1 mass%) Al: balance). The amount of additives such as Cu and Si can be appropriately adjusted. Cu can be contained in an amount of 0.1 to 10% by mass, and Si can be contained in an amount of 0.1 to 10% by mass. Moreover, the film thickness of the cover electrode 42 can be about 100-5000 nm.
Further, the cover electrode 42 is preferably provided up to a region about 2 to 10 μm away from the end of the full-surface electrode 41 in a plan view. Thereby, migration of Ag contained in the entire surface electrode 41 can be prevented more favorably.
The cover electrode 42 can be formed by, for example, a sputtering method or a vapor deposition method.

(Metal oxide film)
The metal oxide film 43 is an insulating film that covers the surface of the cover electrode 42 and is provided in contact with the side surface of the p-side electrode 4p. The metal oxide film 43 functions together with the insulating film 6 as a protective film that prevents damage in the manufacturing process of the cover electrode 42. Further, the metal oxide film 43 is provided so as to be in contact with the p-side electrode 4p, thereby preventing oxygen, moisture, and the like entering from the gap between the insulating film 6 and the p-side electrode 4p from coming into contact with the cover electrode 42. As a result, peeling of the insulating film 6 from the cover electrode 42 is effectively prevented.

The metal oxide film 43 is a film containing at least an oxide of a metal material that constitutes the cover electrode 42. The metal oxide film 43 is a film formed by oxidizing the surface of the cover electrode 42, and is preferably mainly composed of an oxide of Al. Thereby, the cover electrode 42 and the metal oxide film 43 can be satisfactorily adhered to each other. Further, when an oxide such as SiO ₂ or TiO ₂ is used as the insulating film 6, the adhesion to the cover electrode 42 made of metal is not necessarily high, but the cover electrode 42 is oxidized as in the present embodiment. It is presumed that the adhesion between the insulating film 6 and the cover electrode 42 is improved by covering with the metal oxide film 43 formed in this way.
The thickness of the metal oxide film 43 can be set to, for example, about 50 mm (5 nm).

(N-side electrode, p-side electrode)
The n-side electrode 4n is electrically connected to the n-type semiconductor layer 31, and the p-side electrode 4p is electrically connected to the p-type semiconductor layer 33 via the cover electrode 42 and the entire surface electrode 41, respectively. It is a pad electrode for supplying.
The n-side electrode 4 n is provided on the n-type semiconductor layer 31 that is the bottom surface of the stepped portion 3 a of the semiconductor stacked body 3. In the example shown in FIG. 1A, the n-side electrode 4 n is provided in each of the step portions 3 a provided in nine places of the semiconductor stacked body 3.
The p-side electrode 4p is provided on a part of the upper surface of the cover electrode 42. In the example shown in FIG. 1A, horizontally long p-side electrodes 4 p in a plan view are provided at four locations on the upper surface of the cover electrode 42.

For the n-side electrode 4n, it is preferable to use a material that has good adhesion to the n-type semiconductor layer 31, is capable of good ohmic connection, and has low electrical resistance. As such a material, a single layer or multilayer film of metals such as Au, Cu, Ni, Al, and Pt, or an alloy thereof can be used. Furthermore, the contact surface of the n-side electrode 4n with the n-type semiconductor layer 31 also functions as a reflective film that reflects light propagating in the semiconductor stacked body 3, so that the wavelength of light emitted by the active layer 32 is reduced. It is preferable to have a high reflectance. As such a material, Al or an alloy containing Al as a main component can be used. For example, an Al—Cu—Si alloy (for example, Cu: 2 mass%, Si: 1 mass%, Al: balance), Al-Cu alloys (for example, Cu: 2% by mass, Al: balance) can be mentioned. Among them, it is preferable to use an Al—Cu—Si alloy in which the forward voltage Vf is reduced. The amount of additives such as Cu and Si can be appropriately adjusted. Cu can be contained in an amount of 0.1 to 10% by mass, and Si can be contained in an amount of 0.1 to 10% by mass.
In consideration of the overall electrical resistance, connectivity with the outside, and the like, for example, an Al—Cu—Si alloy / Ti / Pt / Au / Ti multilayer film may be sequentially formed from the lower layer side.

  The p-side electrode 4p is preferably made of a material having good adhesion to the cover electrode 42 and low electrical resistance. As such a material, the same material as that of the n-side electrode 4n can be used. In particular, when Al or an alloy containing Al as a main component is used as the cover electrode 42, it is preferable to use an alloy containing Al or Al as a main component for at least the lowermost layer of the p-side electrode 4p in contact with the cover electrode 42. . Thereby, adhesiveness with the cover electrode 42 can be improved. In consideration of the overall electrical resistance, connectivity with the outside, and the like, for example, an Al—Cu—Si alloy / Ti / Pt / Au / Ti multilayer film may be sequentially formed from the lower layer side.

The n-side electrode 4n and the p-side electrode 4p can be formed by a vapor deposition method or a sputtering method using the metal material described above.
Further, metal bumps (not shown) made of Au, Au—Sn eutectic, or the like may be provided on the n-side electrode 4n and the p-side electrode 4p.

(Insulating film)
The insulating film 6 is an insulating film that covers the exposed surface of the semiconductor stacked body 3 (upper surface and side surfaces of the stepped portions 3 a and 3 b), and functions as a protective film and an antistatic film for the semiconductor light emitting element 1. As the insulating film 6, an oxide such as Si, Ti, Ta, or Nb can be used, and can be formed by a known method such as a vapor deposition method or a sputtering method. The thickness of the insulating film 6 is preferably 100 nm or more, and for example, SiO ₂ having a thickness of about 350 nm can be used.
In the present embodiment, the insulating film 6 does not cover the upper part (the upper surface part and the upper layer part of the side surface) of the n-side electrode 4n and the p-side electrode 4p that are pad electrodes. In this embodiment, since the insulating film 6 covers the cover electrode 42 via the metal oxide film 43, the insulating film 6 is in good contact with the cover electrode 42.

Here, with reference to FIG. 2 (refer to FIGS. 1A to 1F as appropriate), a connection portion between the cover electrode 42 and the p-side electrode 4p will be described.
As shown in FIG. 2, the p-side electrode 4 p is provided on a recess 42 a formed in a part of the upper surface of the cover electrode 42. Although details will be described later, the recess 42a is formed by further etching after removing the metal oxide film 43 and the insulating film 6 formed on the cover electrode 42 by etching. Further, the bottom surface of the recess 42a, which is a connection surface with the p-side electrode 4p, is roughened. Further, a residue 43a of the metal oxide film 43 that has not been removed by etching may be present on the bottom surface of the recess 42a. That is, the depth of the recess 42a can be set to such an extent that the metal oxide film 43 is substantially removed or more.
Further, by providing the p-side electrode 4p on the roughened recess 42a, the adhesion between the cover electrode 42 and the p-side electrode 4p is improved.

Further, as described above, the surface of the cover electrode 42 is covered with the metal oxide film 43, and the metal oxide film 43 is provided so that the end thereof is in contact with the side surface of the p-side electrode 4p. Further, the surface of the cover electrode 42 is further covered with the insulating film 6 via the metal oxide film 43. That is, the surface of the cover electrode 42 is double-coated with the metal oxide film 43 and the insulating film 6.
As a result, the cover electrode 42 is effectively protected from oxygen and moisture in the atmosphere, and deterioration is prevented. As a result, the function of preventing migration of Ag constituting the entire surface electrode 41 by the cover electrode 42 can be maintained over a long period of time, and the reliability of the semiconductor light emitting element 1 can be improved.

[Operation of semiconductor light emitting device]
Next, the operation of the semiconductor light emitting device 1 according to the first embodiment will be described with reference to FIGS. 1A to 1F.
In the semiconductor light emitting device 1, when an electric current is supplied to the n-side electrode 4 n and the p-side electrode 4 p from the outside through a metal bump or a bonding wire (not shown), the active layer 32 of the semiconductor stacked body 3 emits light. The light emitted from the active layer 32 is extracted from the back side of the substrate 2. Of the light emitted from the active layer 32, the light traveling in the direction opposite to the light extraction surface is the entire surface electrode 41 functioning as a reflective film, the contact surface of the cover electrode 42 with the p-type semiconductor layer 33, and the n-side electrode 4n. Are reflected by the contact surface with the n-type semiconductor layer 31 and extracted from the back surface side of the substrate 2 which is a light extraction surface.

[Nitride Semiconductor Light-Emitting Device Manufacturing Method]
Next, a method for manufacturing the semiconductor light emitting device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 3A and 3B.

As shown in FIG. 3A, the method for manufacturing the semiconductor light emitting device 1 according to the first embodiment includes a semiconductor stacked body forming step S11, a first metal film forming step S12, a second metal film forming step S13, and a metal oxide. A film forming process S14, an insulating film forming process S15, a second metal film exposing process S16, and a third metal film forming process S17 are included.
Further, as shown in FIG. 3B, the second metal film exposing step S16 includes a resist pattern forming step S161 and an insulating film etching step S162.

Hereinafter, each step will be described in detail with reference to FIGS. 4A to 7B (refer to FIGS. 1A to 3B as appropriate). In this example, a case where a nitride semiconductor is used as a semiconductor material will be described as an example.
4A to 7B, the description of hatching of each layer of the substrate 2 and the semiconductor stacked body 3 is omitted.

(Semiconductor laminate formation process)
First, in semiconductor laminated body formation process S11, as shown to FIG. 4A, the semiconductor laminated body 3 is formed with the well-known manufacturing method on the translucent board | substrates 2, such as sapphire. In the example shown in FIG. 4A, the semiconductor stacked body 3 is formed by sequentially stacking an n-type semiconductor layer 31, an active layer 32, and a p-type semiconductor layer 33.

  The semiconductor stacked body forming step S11 will be briefly described. First, nitride semiconductors constituting the n-type semiconductor layer 31, the active layer 32, and the p-type semiconductor layer 33 are grown on the substrate 2 made of sapphire or the like by using the MOVPE method. Thereafter, the substrate 2 (hereinafter referred to as a wafer as appropriate) on which each layer of the semiconductor stacked body 3 is grown is annealed at about 600 to 700 ° C. in a nitrogen atmosphere to reduce the resistance of the p-type semiconductor layer 33. Is preferred.

(First metal film forming step)
Next, in the first metal film formation step S12, as the full-surface electrode (first metal film) 41, a metal film having at least the lowest layer of Ag or an alloy containing Ag as a main component is patterned and formed. As such a metal film, for example, a multilayer film in which Ag / Ni / Ti / Ru is laminated in order from the lower layer side can be formed by a sputtering method. Then, an entire surface electrode 41 having a predetermined shape is formed by photolithography as shown in FIG. 4B.

(Second metal film forming step)
Next, in the second metal film forming step S13, a cover electrode (second metal film) 42 is formed.
In this step, as shown in FIG. 4C, first, as a cover electrode 42, for example, a metal film made of Al or an alloy containing Al as a main component, for example, an Al—Cu alloy is sputtered on the entire wafer. The film is formed by the method.
Subsequently, as shown in FIG. 5A, a resist pattern 71 for shaping the cover electrode 42 into a predetermined shape is formed on the metal film to be the cover electrode 42 by photolithography. That is, the region where the resist pattern 71 is provided coincides with the region where the cover electrode 42 having a predetermined shape is provided in plan view.
Then, as shown in FIG. 5B, the outer shape of the cover electrode 42 is shaped by removing the metal film in the unmasked region by etching using the resist pattern 71 as a mask. Thereafter, the resist pattern 71 is removed.

(Metal oxide film formation process)
Next, in the metal oxide film forming step S14, as shown in FIG. 5C, the exposed surface of the cover electrode 42 is oxidized to form a metal oxide film 43 mainly composed of an oxide of Al. The oxidation treatment of the cover electrode 42 includes, for example, (a) a method of treating with an oxidizing solution such as nitric acid or sulfuric acid, (b) ashing using ultraviolet light, (c) a method of cleaning using ozone, etc. d) A method of annealing in an oxygen atmosphere, (e) Hot water treatment, or the like.

Further, in the second metal film forming step S13, which is a previous step, after the cover electrode 42 is shaped, heat treatment is performed, or an oxidizing solution is used in the process of removing the resist pattern 71, whereby the metal oxidation is performed. It can also be set as film formation process S14.
Furthermore, Al, which is the main component of the cover electrode 42, is oxidized by leaving it in the atmosphere (that is, in the presence of oxygen) to form a metal oxide film 43 containing the oxide of Al as a main component. Can do.

Next, as shown in FIG. 5D, the stepped portion 3a for providing the n-side electrode 4n and the stepped portion 3b serving as a cleaved region of the semiconductor light emitting element 1 are exposed. A mask having a predetermined shape is formed on the annealed wafer with a photoresist, and the p-type semiconductor layer 33 and the active layer 32 are all removed in the thickness direction by reactive ion etching (RIE). A part of the n-type semiconductor layer 31 is removed to expose the n-type semiconductor layer 31. After the etching, the resist is removed.
In addition, the full surface electrode 41 is provided in the area | region to the position spaced apart from the edge part of level | step-difference part 3a, 3b so that a side surface may be coat | covered with the cover electrode 42. FIG.

  Note that any of the metal oxide film forming step shown in FIG. 5C and the step portions 3a and 3b forming step shown in FIG. 5D may be performed first.

(Insulating film formation process)
Next, in an insulating film forming step S15, as shown in FIG. 6A, an insulating oxide such as SiO ₂ is laminated on the entire surface of the wafer by, for example, sputtering or CVD, and the insulating film 6 is formed. Form.

(Second metal film exposure step)
Next, in the second metal film exposing step S16, the cover electrode (second metal film) 42 in the region where the p-side electrode 4p is provided is exposed by an etching method. In this embodiment, in this step, the n-type semiconductor layer 31 in the region where the n-side electrode 4n is provided is also exposed.
Therefore, as a sub-step of the second metal film exposure step S16, first, in a resist pattern forming step S161, a resist pattern 72 is formed as shown in FIG. 6B. The resist pattern 72 has an opening 72p in a region where the p-side electrode 4p is provided, and an opening 72n in a region where the n-side electrode 4n is formed.

As the next sub-step of the second metal film exposing step S16, in the insulating film etching step S162, as shown in FIG. 6C, the insulating film 6 in the openings 72p and 72n is removed by etching using the resist pattern 72 as a mask. Thus, openings 6p and 6n are formed in the insulating film 6.
As a result, the cover electrode (second metal film) 42 in the region in which the p-side electrode 4p is provided is exposed, and the n-type semiconductor layer 31 in the region in which the n-side electrode 4n is provided is exposed.

In addition, in the opening 72p, the metal oxide film 43 is removed, and etching is further advanced to remove a part of the cover electrode 42 in the thickness direction to form a recess 42a (see FIG. 2). At this time, the bottom surface of the recess 42a, that is, the exposed surface of the cover electrode 42 is preferably roughened.
The metal oxide film 43 may not be completely removed, and the residue 43a (see FIG. 2) may remain.
Further, although the concave portion 42a depends on the thickness of the cover electrode 42, it can be formed by removing the entire surface electrode 41, for example, by removing the cover electrode 42 about several nm to 2500 nm in the thickness direction.

  As an etchant for etching and roughening the cover electrode 42 made of Al or an alloy containing Al as a main component, for example, hydrofluoric acid or a mixed acid containing hydrofluoric acid can be used. Moreover, you may add buffering agents, such as ammonium fluoride, suitably. Further, the degree of roughening can be controlled by adjusting the temperature during etching.

  By roughening the exposed portion of the cover electrode 42, in the next third metal film forming step S17, the lowermost layer of the p-side electrode 4p is a metal material made of Al or an alloy containing Al as a main component. In this case, the metal material mainly composed of Al in the lowermost layer of the p-side electrode 4p grows while adhering to the entire exposed surface of the cover electrode 42 made of Al or an alloy mainly composed of Al. For this reason, the contact area of the cover electrode 42 and the p-side electrode 4p increases, and adhesiveness, ie, joint strength, can be improved more. Further, in addition to the increase in the contact area due to the roughening, the metal material of the cover electrode 42 and the metal material of at least the lowermost layer of the p-side electrode 4p both have Al as the main component, thereby further improving the bonding strength. be able to.

(Third metal film forming step)
Next, in the third metal film forming step S17, as shown in FIG. 7A, the p-side electrode (third metal film) 4p is formed on the entire wafer while holding the resist pattern 72 formed in the second metal film exposing step S16. And the metal film 40 used as the n side electrode 4n is formed. In this embodiment, at least the lowermost layer is formed using Al or an alloy containing Al as a main component. The metal film 40 may be a single layer film of Al or Al alloy, or may be a multilayer film in which different materials are stacked on the upper layer.
In the present embodiment, the n-side electrode 4n is formed using the same material as that of the p-side electrode 4p. However, the step of forming the n-side electrode 4n is separated and formed using a different material. You may do it.

Next, the resist pattern 72 is removed (lifted off) together with the metal film 40 laminated on the upper surface thereof, so that the p-side electrode 4p and the n-side electrode 4n are shaped into predetermined shapes as shown in FIG. 7B. The semiconductor light emitting device 1 is completed.
In addition, although illustration is abbreviate | omitted, the semiconductor light emitting element 1 can be chip-ized by cleaving the level | step-difference part 3b which is a cleaving area | region using a scribe method, a dicing method, etc. FIG.

Second Embodiment
[Configuration of Semiconductor Light Emitting Element]
Next, the configuration of the semiconductor light emitting device according to the second embodiment of the present invention will be described with reference to FIGS. 8A to 8C. The semiconductor light emitting element 1A according to the second embodiment is an LED that is mounted in a flip chip type. As shown in FIGS. 8A to 8C, a semiconductor light emitting device 1A includes a substrate 2, a semiconductor stacked body 3 stacked on the substrate 2, an n-side electrode 4n and an n-side eutectic pad electrode 8n, and a full surface electrode. 41, a cover electrode 42, a metal oxide film 43, a p-side electrode 4p and a p-side eutectic pad electrode 8p, and an insulating film 6. In this example, both the n-side electrode 4n and the p-side electrode 4p are provided on the surface of the substrate 2 on the side where the semiconductor laminate 3 is provided so as to be suitable for flip chip mounting.
The semiconductor light emitting device 1A according to the second embodiment further includes a p-side eutectic pad electrode 8p and an n-side eutectic for the semiconductor light emitting device 1 according to the first embodiment shown in FIGS. 1A to 1F. It differs in having pad electrode 8n.
In FIG. 8A, the insulating film 6 and the metal oxide film 43 are not shown. Further, in the cross-sectional views shown in FIGS. 8B and 8C, hatching is omitted for each layer of the substrate 2 and the semiconductor stacked body 3. FIG. 8C is a cross-sectional view taken along line AA in FIG. 8A, and shows the width and arrangement interval of each member appropriately enlarged or reduced for easy understanding of the internal structure of the semiconductor light emitting device. . Further, the regions A1 to A3 in FIG. 8C correspond to the regions A1 to A3 in FIG. 8B, respectively. That is, FIG. 8C shows the area A1 and the area A3 in an enlarged manner and the area A2 in a reduced manner in the horizontal direction with respect to FIG. 8B.

(P-side eutectic pad electrode, n-side eutectic pad electrode)
The p-side eutectic pad electrode (fifth metal film) 8p and the n-side eutectic pad electrode (fourth metal film) 8n are connected using Au—Sn eutectic solder or the like when mounted on the mounting substrate. Pad electrode. The p-side eutectic pad electrode 8p is electrically connected to the upper surface of the p-side electrode 4p in the opening 6p of the insulating film 6, and further on the insulating film 6 over a wide area in the left region in FIG. 8A. It is provided to extend. The n-side eutectic pad electrode 8n is electrically connected to the upper surface of the n-side electrode 4n in the opening 6n of the insulating film 6, and further on the insulating film 6 in the right region in FIG. 8A. It is provided to extend over a wide area. The p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n are both substantially the same height as viewed from the top surface of the substrate 2 on the insulating film 6 provided above the p-type semiconductor layer 33. It has been extended. Accordingly, the heights of the upper ends of the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n, which are connecting portions when performing flip-chip mounting, are uniform. There is no step between the electrode connection surface and the mounting reliability can be improved.

  Hereinafter, such a structure of the pad electrode will be appropriately referred to as a three-dimensional wiring structure. In the present embodiment, the electrodes for three-dimensional wiring in the semiconductor light emitting element are referred to as eutectic pad electrodes (p-side eutectic pad electrode 8p and n-side eutectic pad electrode 8n) for convenience. The connection at the time of mounting is not limited to the one using eutectic solder, and can be widely used as a pad electrode for external connection. The same applies to other embodiments having a three-dimensional wiring structure to be described later.

  The p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n have good adhesion to the p-side electrode 4p, the n-side electrode 4n and the insulating film 6 on which they are provided, and a metal film having a low electrical resistance as a whole. It is preferable that As such a metal film, for example, a multilayer film in which Ti / Ni / Au is laminated in order from the lower layer side can be used.

  Further, in the example shown in FIG. 8A, stepped portions 3a having a horizontally long shape in plan view are provided at two locations. The right end portion of each stepped portion 3a has a region swelled in a circular shape in plan view, and the n-side electrode 4n and the n-side eutectic pad electrode 8n are connected to the circular region. An opening 6n of the insulating film 6 is provided. The p-side electrode 4p provided on the p-type semiconductor layer 33 (the right side in FIGS. 8B and 8C) on which the n-side eutectic pad electrode 8n extends is directly connected to the p-side eutectic pad electrode 8p. Are not connected and can be omitted. However, it is preferable to provide the n-side eutectic pad electrode 8n and the p-side eutectic pad electrode 8p in order to make the height from the upper surface of the substrate 2 uniform.

Further, as in the present embodiment, the heat dissipation of the semiconductor light emitting device 1A can be improved by extending the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n over a wide range. The area and place where the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n extend can be appropriately designed in consideration of mountability and heat dissipation.
In the example shown in FIGS. 8A to 8C, the p-side eutectic pad electrode 8p extends to the insulating film 6 provided on the n-side electrode 4n in the step portion 3a.

  In addition, the insulating film 6 includes the first insulating film 61 provided in the same manner as the insulating film 6 in the first embodiment and the side surfaces of the p-side electrode 4p and the n-side electrode 4n and the upper surface excluding the openings 6p and 6n. It consists of two layers with a second insulating film 62 provided so as to cover. For this reason, the insulating film 6 is formed thinner on the upper surfaces of the p-side electrode 4p and the n-side electrode 4n than the other regions. The first insulating film 61 and the second insulating film 62 are made of the same material and are substantially integrated films.

[Operation of semiconductor light emitting device]
The semiconductor light emitting device 1A according to the second embodiment differs from the semiconductor light emitting device 1 according to the first embodiment in that the n-side electrode 4n has a different shape and number of arrangements, and p-side eutectic pad electrodes 8p and n. Since the operation is the same except that an external current is supplied via the side eutectic pad electrode 8n, the description of the operation is omitted.

[Method for Manufacturing Semiconductor Light-Emitting Element]
Next, a method for manufacturing the semiconductor light emitting device 1A according to the second embodiment will be described with reference to FIG.
As shown in FIG. 9, the method for manufacturing the semiconductor light emitting device 1A according to the second embodiment includes a semiconductor stacked body forming step S31, a first metal film forming step S32, a second metal film forming step S33, and a metal oxide. Film forming step S34, first insulating film forming step (insulating film forming step) S35, second metal film exposing step S36, third metal film forming step S37, second insulating film forming step S38, and fourth , Fifth metal film forming step S39.

Note that the semiconductor laminate forming step S31, the first metal film forming step S32, the second metal film forming step S33, and the metal oxide film forming step S34 are the semiconductor laminate of the manufacturing method in the first embodiment shown in FIG. 3A. Since they are the same as the formation step S11, the first metal film formation step S12, the second metal film formation step S13, and the metal oxide film formation step S14, description thereof will be omitted.
The first insulating film forming step S35 and the second metal film exposing step S36 are the first insulating film 6 in the first embodiment as the insulating film 6 in the insulating film forming step S15 and the second metal film exposing step S16 in the first embodiment. Since the insulating film 61 is formed and etched, detailed description is omitted. The third metal film forming step S37 is the same as the third metal film forming step S17 in the first embodiment, and thus detailed description thereof is omitted.

Hereinafter, the subsequent steps will be described in detail with reference to FIGS. 10A to 10C (refer to FIGS. 8A to 9 as appropriate).
10B and 10C, the description of hatching of each layer of the substrate 2 and the semiconductor stacked body 3 is omitted.

  10A shows a semiconductor stacked body forming step S31, a first metal film forming step S32, a second metal film forming step S33, a metal oxide film forming step S34, a first insulating film forming step S35, a second metal film exposing step S36, and The state after performing 3rd metal film formation process S37 sequentially is shown. In the present embodiment, in addition to the region (on the left cover electrode 42 in FIG. 10A) to which the p-side eutectic pad electrode (fifth metal film) 8p formed in a later step is connected, the n-side eutectic A p-side electrode (third metal film) 4p is also formed in a region where the pad electrode (fourth metal film) 8n extends (on the right cover electrode 42 in FIG. 10A). In addition, the first insulating film 61 is covered except for the upper surfaces and upper portions of the side surfaces of the p-side electrode 4p and the n-side electrode 4n.

  In the third metal film forming step S37, Al or an alloy containing Al as a main component is used for the lowermost layer of the p-side electrode 4p, and the upper layer does not contain Al and contains no oxide or the like. It is preferable to use a material that is difficult to form a dynamic film. As a result, the passive film is not formed even by chemicals or high temperature environment used in the initial stage of the second insulating film forming step S38 and the fourth and fifth metal film forming steps S39, which are the subsequent steps, and the p-side electrode 4p The p-side eutectic pad electrode 8p can be electrically connected well. As a result, a highly reliable semiconductor light emitting device 1A can be formed.

  In the present embodiment, the p-side eutectic pad electrode 8p extending over a wide range on the insulating film 6 and the cover electrode 42 on which a passive film is easily formed on the surface because of containing Al are directly bonded. Instead, the bonding is performed through the p-side electrode 4p (third metal film) by the above-described process. Thereby, the cover electrode 42 and the p-side eutectic pad electrode 8p are electrically connected well without any passive film interposed between the cover electrode 42 and the p-side eutectic pad electrode 8p. can do.

(Second insulating film forming step)
Next, in the second insulating film forming step S38, as shown in FIG. 10B, a second insulating film 62 having openings 6p and 6n is formed on the surface of the wafer using the same material as the first insulating film 61. To do.
In this step, first, the second insulating film 62 is formed on the entire wafer by the same method as the first insulating film 61. Thereafter, using a known photolithography method, an opening 6p is formed in a region connecting the p-side electrode 4p and the p-side eutectic pad electrode 8p to the second insulating film 62, and the n-side electrode 4n and the n-side electrode are connected to each other. Openings 6n are respectively formed in regions where the crystal pad electrode 8n is connected to expose part of the upper surfaces of the p-side electrode 4p and the n-side electrode 4n.

(Fourth and fifth metal film forming step)
Next, in the fourth and fifth metal film formation step S39, as shown in FIG. 10C, the p-side eutectic pad electrode (fifth metal film) 8p and the n-side eutectic pad electrode (fourth metal film). 8n is formed. In the present embodiment, the p-side eutectic pad electrode 8p is electrically connected within the opening 6p of the second insulating film 62 to the p-side electrode 4p illustrated on the left side in FIG. The n-side electrode 4n is provided so as to extend over the second insulating film 62 covering the upper surface of the n-side electrode 4n. Further, the n-side eutectic pad electrode 8n is electrically connected to the n-side electrode 4n in the stepped portion 3a within the opening 6n of the second insulating film 62, and the p-side described on the right side in FIG. 10C. The electrode 4p is provided so as to extend over the second insulating film 62 covering the upper surface of the electrode 4p.

  The p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n are provided so as not to short-circuit each other. In addition, the region where the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n extend is an insulating layer composed of the first insulating film 61 and the second insulating film 62 except for the openings 6p and 6n. The film 6 is electrically insulated from the semiconductor stacked body 3, the p-side electrode 4p, and the n-side electrode 4n.

The p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n can be formed by a lift-off method or a photolithography method. For example, the lift-off method will be described. First, a resist pattern is formed that masks areas other than the region where the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n are arranged. Next, a metal film is formed using a metal material for forming the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n. Then, by removing (lifting off) the metal film formed on the resist pattern together with the resist pattern, it can be shaped into a p-side eutectic pad electrode 8p and an n-side eutectic pad electrode 8n having a predetermined shape. .
The semiconductor light emitting element 1A according to the second embodiment can be manufactured through the steps described above.

<Third Embodiment>
Next, the structure of the semiconductor light-emitting device according to the third embodiment of the present invention will be described with reference to FIGS. 11A to 11C. A semiconductor light emitting device 1B according to the third embodiment is a flip-chip mounted LED, and has a three-dimensional wiring structure, similar to the semiconductor light emitting device 1A according to the second embodiment shown in FIGS. 8A to 8C. It is.

As shown in FIGS. 11A to 11C, the semiconductor light emitting device 1B has a disposition range of the p-side eutectic pad electrode 8p with respect to the semiconductor light emitting device 1A according to the second embodiment shown in FIGS. 8A to 8C. The difference is that it is limited to the p-type semiconductor layer 33 and does not extend into the stepped portion 3a. Further, the shape of the n-side eutectic pad electrode 8n in plan view is also different. Other configurations and operations are the same as those of the semiconductor light emitting device 1A according to the second embodiment, and a description thereof will be omitted.
In FIG. 11A, the insulating film 6 and the metal oxide film 43 are not shown. Further, in the cross-sectional views shown in FIGS. 11B and 11C, hatching is omitted for each layer of the substrate 2 and the semiconductor stacked body 3. FIG. 11C is a cross-sectional view taken along the line AA in FIG. 11A, and shows the width and arrangement interval of each member appropriately enlarged or reduced for easy understanding of the internal structure of the semiconductor light emitting device. . Further, the regions A1 to A3 in FIG. 11C correspond to the regions A1 to A3 in FIG. 11B, respectively. That is, FIG. 11C shows the area A1 and the area A3 in an enlarged manner and the area A2 in a reduced manner in the horizontal direction with respect to FIG. 11B.

The semiconductor light emitting device 1B according to the present embodiment can be manufactured in the same manner as the semiconductor light emitting device 1A according to the second embodiment, and thus detailed description thereof is omitted.
In this embodiment, the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n are used to shape the metal film in the fourth and fifth metal film forming step S39 (see FIG. 9). The resist pattern can be formed according to the shape of the p-side eutectic pad electrode 8p and the n-side eutectic pad electrode 8n shown in FIG. 11A.

<Fourth embodiment>
[Configuration of Semiconductor Light Emitting Element]
Next, the configuration of the semiconductor light emitting device according to the fourth embodiment of the present invention will be described with reference to FIGS. 12A to 12C. A semiconductor light emitting device 1C according to the fourth embodiment is a flip-chip mounted LED, and has a three-dimensional wiring structure similar to the semiconductor light emitting device 1A according to the second embodiment shown in FIGS. 8A to 8C. It is.
In FIG. 12A, illustration of the insulating film 6 and the metal oxide film 43 is omitted. Further, in the cross-sectional views shown in FIGS. 12B and 12C, hatching is omitted for each layer of the substrate 2 and the semiconductor stacked body 3. FIG. 12C is a cross-sectional view taken along the line AA in FIG. 12A and shows the width and arrangement interval of each member appropriately enlarged or reduced in order to facilitate understanding of the internal structure of the semiconductor light emitting element. . In addition, the regions A1 to A3 in FIG. 12C correspond to the regions A1 to A3 in FIG. 12B, respectively. That is, FIG. 12C shows the area A1 and the area A3 in an enlarged manner and the area A2 in a reduced manner in the horizontal direction with respect to FIG. 12B.

As shown in FIGS. 12A to 12C, the semiconductor light emitting device 1C is different from the semiconductor light emitting device 1A according to the second embodiment shown in FIGS. 8A to 8C in that the p side electrode 4p is not provided. The crystal pad electrode (third metal film) 8 </ b> Ap is directly connected to the cover electrode 42. Further, there are three horizontally long stepped portions 3a in plan view, the n-side electrode 4n is disposed on each stepped portion 3a, the p-side eutectic pad electrode 8Ap, and the n-side eutectic pad. The shape of the electrode 8n in plan view is different. Furthermore, the insulating film 6 is different from that of a single layer.
In the fourth embodiment, the p-side eutectic pad electrode 8Ap is provided on the n-side electrode 4n in the stepped portion 3a, like the p-side eutectic pad electrode 8p in the second embodiment. It extends to the top of the insulating film 6.

As the p-side eutectic pad electrode 8Ap, similarly to the p-side eutectic pad electrode 8p in the second embodiment, for example, a multilayer film in which Ti / Ni / Au is laminated in order from the lower layer side can be used. .
Further, as described above, in this embodiment, the p-side eutectic pad electrode (third metal film) 8Ap is directly connected to the cover electrode. Therefore, the lowermost layer of the p-side eutectic pad electrode 8Ap joined to the cover electrode 42 made of Al or an alloy containing Al as a main component is preferably made of Al or an alloy containing Al as a main component. As such a metal film, for example, an Al—Cu—Si alloy (for example, Cu: 2 mass%, Si: 1 mass%, Al: balance) / Ti / Ni / Au are sequentially laminated from the lower layer side. A multilayer film can be used. Thus, the adhesiveness between the cover electrode 42 and the p-side eutectic pad electrode 8Ap can be improved by using the metal material mainly composed of Al as the lowermost layer.
Other configurations and operations of the semiconductor light emitting device 1C are the same as those of the semiconductor light emitting device 1A according to the second embodiment, and thus the description thereof is omitted.

[Method for Manufacturing Semiconductor Light-Emitting Element]
Next, a method for manufacturing the semiconductor light emitting device 1C according to the fourth embodiment will be described with reference to FIG.
As shown in FIG. 13, the manufacturing method of the semiconductor light emitting device 1C according to the fourth embodiment includes a semiconductor stacked body forming step S51, a first metal film forming step S52, a second metal film forming step S53, and a metal oxide. A film forming step S54, an n-side electrode forming step S55, an insulating film forming step S56, a second metal film exposing step S57, and a third and fourth metal film forming step S58 are configured.

  The semiconductor laminate forming step S51, the first metal film forming step S52, the second metal film forming step S53, and the metal oxide film forming step S54 are the semiconductor laminate of the manufacturing method in the first embodiment shown in FIG. 3A. Since they are the same as the formation step S11, the first metal film formation step S12, the second metal film formation step S13, and the metal oxide film formation step S14, description thereof will be omitted.

Hereinafter, the subsequent steps will be described in detail with reference to FIGS. 14A to 15B (see FIGS. 12A to 13 as appropriate).
14A to 15B, the description of hatching of each layer of the substrate 2 and the semiconductor stacked body 3 is omitted.

  FIG. 14A shows a state after the semiconductor stacked body forming step S51, the first metal film forming step S52, the second metal film forming step S53, and the metal oxide film forming step S54 are sequentially performed.

(N-side electrode forming step)
Next, in the n-side electrode forming step S55, as shown in FIG. 14B, the n-side electrode 4n is formed in the stepped portion 3a. The n-side electrode 4n can be formed by a photolithography method or a lift-off method. The metal film to be the n-side electrode 4n in this embodiment can be formed by the sputtering method or the like using the same material as that of the n-side electrode 4n in the other embodiments described above.

(Insulating film formation process)
Next, in an insulating film forming step S56, as shown in FIG. 14C, the insulating film 6 is formed on the entire wafer. The insulating film 6 can be formed in the same manner as the insulating film forming step S15 in the first embodiment, using an insulating material made of an oxide such as SiO ₂ .

(Second metal film exposure step)
Next, in the second metal film exposing step S57, as shown in FIG. 15A, openings 6p and 6n are formed in the insulating film 6 by an etching method. That is, the region for connecting the p-side eutectic pad electrode 8Ap of the cover electrode (second metal film) 42 and the region for connecting the n-side eutectic pad electrode 8n of the n-side electrode 4n are exposed. Let

  This step can be performed in the same manner as the second metal film exposure step S16 (see FIG. 3A) in the first embodiment. That is, a resist pattern having an opening is formed in a region to be exposed of the cover electrode 42 and a region to be exposed of the n-side electrode 4n, and the insulating film 6 in the opening is formed by etching using this rest pattern as a mask. In addition, the metal oxide film 43 is removed. Further, by proceeding with etching, a part of the cover electrode 42 is removed in the thickness direction to form a recess 42a (see FIG. 2). At this time, it is preferable to perform etching so that the bottom surface of the recess 42a (see FIG. 2) is roughened. This improves the adhesion between the cover electrode 42 and the p-side eutectic pad electrode 8Ap.

(Third and fourth metal film forming step)
Next, in the third and fourth metal film forming step S58, as shown in FIG. 15B, the p-side eutectic pad electrode (third metal film) 8Ap and the n-side eutectic pad electrode (fourth metal film). 8n is formed. In the present embodiment, the p-side eutectic pad electrode 8Ap is electrically connected within the opening 6p of the insulating film 6 to the cover electrode 42 illustrated on the left side in FIG. 15B, and at the n-side in the step portion 3a. The electrode 4n is provided so as to extend over the insulating film 6 covering the upper surface of the electrode 4n. The n-side eutectic pad electrode 8n is electrically connected to the n-side electrode 4n in the step portion 3a and the opening 6n of the insulating film 6, and the cover electrode 42 described on the right side in FIG. The upper surface is provided so as to extend to the insulating film 6 covering the metal oxide film 43.
The third and fourth metal film forming step S58 can be performed in the same manner as the fourth and fifth metal film forming step S39 (see FIG. 9) in the second embodiment, and thus detailed description thereof is omitted. .

  In addition, the semiconductor light emitting element 1C according to the fourth embodiment does not include the p-side electrode 4p (see FIGS. 8B and 8C), and the insulating film 6 has a single-layer configuration, and thus the semiconductor light emitting according to the second embodiment. The number of manufacturing steps can be reduced as compared with the element 1A.

<Fifth Embodiment>
Next, the configuration of the semiconductor light emitting device according to the fifth embodiment of the present invention will be described with reference to FIGS. 16A to 16C. A semiconductor light emitting device 1D according to the fifth embodiment is a flip-chip mounted LED, and has a three-dimensional wiring structure, similar to the semiconductor light emitting device 1C according to the fourth embodiment shown in FIGS. 12A to 12C. It is.

As shown in FIGS. 16A to 16C, the semiconductor light emitting element 1D has a disposition range of the p-side eutectic pad electrode 8Ap with respect to the semiconductor light emitting element 1C according to the fourth embodiment shown in FIGS. 12A to 12C. The difference is that it is limited to the p-type semiconductor layer 33 and does not extend into the stepped portion 3a. Further, the shape of the n-side eutectic pad electrode 8n in plan view is also different. Other configurations and operations are the same as those of the semiconductor light emitting device 1C according to the fourth embodiment, and thus the description thereof is omitted.
In FIG. 16A, illustration of the insulating film 6 and the metal oxide film 43 is omitted. Further, in the cross-sectional views shown in FIGS. 16B and 16C, hatching is omitted for each layer of the substrate 2 and the semiconductor stacked body 3. FIG. 16C is a cross-sectional view taken along line AA in FIG. 16A, and shows the width and arrangement interval of each member appropriately enlarged or reduced for easy understanding of the internal structure of the semiconductor light emitting device. . Further, the regions A1 to A3 in FIG. 16C correspond to the regions A1 to A3 in FIG. 16B, respectively. That is, FIG. 16C shows the region A1 and the region A3 in an enlarged manner and the region A2 in a reduced manner in the horizontal direction with respect to FIG. 16B.

Moreover, since the semiconductor light emitting element 1D according to the present embodiment can be manufactured in the same manner as the semiconductor light emitting element 1C according to the fourth embodiment, detailed description thereof is omitted.
The p-side eutectic pad electrode 8Ap and the n-side eutectic pad electrode 8n in this embodiment are for shaping the metal film in the third and fourth metal film forming step S58 (see FIG. 13). The resist pattern can be formed according to the shapes of the p-side eutectic pad electrode 8Ap and the n-side eutectic pad electrode 8n shown in FIG. 16A.

  Next, a semiconductor light emitting device was produced between the example of the present invention in which the cover electrode was formed using an Al-based alloy and the comparative example formed using a metal having a reflectance lower than that of Al. About these samples The result of measuring the light extraction efficiency from the semiconductor light emitting element to the outside will be described.

[Production conditions]
In each sample, the semiconductor light-emitting element is formed using a gallium nitride-based semiconductor material, and the emission wavelength is 450 nm (blue light).
The shape of each sample is such that in the light emitting device 1 shown in FIG. 1A, the number of steps 3a and n-side electrodes 4n is arranged from 3 × 3 = 9 to 4 × 4 = 16. .
In each sample, when the contact area between the p-type semiconductor layer and the entire surface electrode made of Ag is 100%, the contact area between the p-type semiconductor layer and the cover electrode is 5.0%.
For each sample, the metal material used for the cover electrode is as follows.
(Example 1)
Single-layer film of Al—Cu alloy (Cu: 2% by mass, Al: balance, film thickness 2000 nm) (Example 2)
Multilayer film in which Al—Cu alloy (Cu: 2% by mass, Al: balance, film thickness: 2000 nm) / Ru (film thickness: 100 nm) / Ti (film thickness: 3 nm) is laminated in order from the lower layer side (comparative example)
Multilayer film in which Ti (film thickness 2 nm) / Au (film thickness 170 nm) / W (film thickness 120 nm) / Ti (film thickness 3 nm) are laminated in order from the lower layer side.

[Measurement result of efficiency]
(Example 1) 154.5 [lm / W]
(Example 2) 155.5 [lm / W]
(Comparative example) 148.5 [lm / W]
In Example 1 and Example 2 using an Al-based alloy as the cover electrode, it was confirmed that the efficiency was improved by 4 to 5% with respect to the comparative example.

  Although the semiconductor light emitting device and the manufacturing method thereof according to the present invention have been specifically described above by the embodiments for carrying out the invention, the gist of the present invention is not limited to these descriptions, and the scope of the claims Should be interpreted broadly based on the description. Needless to say, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

1, 1A, 1B, 1C, 1D Semiconductor light emitting device 2 Substrate 3 Semiconductor laminated body 3a Stepped portion 3b Stepped portion 31 N-type semiconductor layer 32 Active layer 33 p-type semiconductor layer 4n n-side electrode 4p p-side electrode (third metal film) )
41 Full-surface electrode (first metal film)
42 Cover electrode (second metal film)
42a recess 43 metal oxide film 43a residue 6 insulating film 6n opening 6p opening 61 first insulating film 62 second insulating film 71 resist pattern 72 resist pattern 72n opening 72p opening (resist opening)
8n n-side eutectic pad electrode (fourth metal film)
8p p-side eutectic pad electrode (fifth metal film)
8 Ap p-side eutectic pad electrode (third metal film)

Claims (6)

a semiconductor stacked body forming step of forming a semiconductor stacked body by stacking an n-type semiconductor layer and a p-type semiconductor layer;
A first metal film forming step of forming a first metal film on an upper surface of the p-type semiconductor layer so that a surface in contact with the p-type semiconductor layer is Ag or an alloy containing Ag as a main component;
A second metal film forming step of forming a second metal film so as to cover an upper surface and a side surface of the first metal film using Al or an alloy containing Al as a main component;
A metal oxide film forming step of covering the surface of the second metal film and forming a metal oxide film containing at least an oxide of a metal material constituting the second metal film;
A second metal film exposing step of forming a recess in the second metal film so that a part of the surface of the second metal film is exposed from the metal oxide film by etching;
A method of manufacturing a semiconductor light emitting device, wherein a third metal film forming step of forming a third metal film on the concave portion of the second metal film is sequentially performed. After the metal oxide film forming step, an insulating film forming step of forming an insulating film covering the surface of the metal oxide film using an insulating material made of oxide is performed.
The said recessed part is formed in the said 2nd metal film so that a part of surface of the said 2nd metal film may be exposed from the said insulating film and the said metal oxide film in the said 2nd metal film exposure process. A method for manufacturing a semiconductor light emitting device. The second metal film exposing step includes
A resist pattern forming step of forming a resist pattern having a resist opening opening in a partial region on the insulating film provided on the upper surface of the second metal film;
The insulating film and the metal oxide in the resist opening are etched using the resist pattern as a mask to expose the second metal film from the insulating film and the metal oxide, and the insulating film and the metal oxide film Etching the second metal film exposed from the insulating film to form a recess; and
The method for manufacturing a semiconductor light emitting device according to claim 2, comprising:   4. The method for manufacturing a semiconductor light emitting element according to claim 1, wherein, in the second metal film exposing step, the bottom surface of the concave portion is roughened. 5.   5. The semiconductor according to claim 1, wherein, in the third metal film forming step, the third metal film is formed such that a surface in contact with the concave portion is Al or an alloy containing Al as a main component. Manufacturing method of light emitting element. In the second metal film forming step, according to any one of claims 1 to 5 to form the second metal film as the outer edge of the first metal layer in contact with the upper surface of the p-type semiconductor layer Manufacturing method of the semiconductor light-emitting device.

Images