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JP6420671B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP6420671B2
JP6420671B2 JP2015009253A JP2015009253A JP6420671B2 JP 6420671 B2 JP6420671 B2 JP 6420671B2 JP 2015009253 A JP2015009253 A JP 2015009253A JP 2015009253 A JP2015009253 A JP 2015009253A JP 6420671 B2 JP6420671 B2 JP 6420671B2
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JP
Japan
Prior art keywords
lower mold
mold cavity
cavity block
block
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015009253A
Other languages
Japanese (ja)
Other versions
JP2016134545A (en
Inventor
晴彦 原田
晴彦 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2015009253A priority Critical patent/JP6420671B2/en
Priority to TW104138110A priority patent/TWI671829B/en
Priority to CN201510959061.5A priority patent/CN105810594B/en
Priority to US14/983,143 priority patent/US9887105B2/en
Publication of JP2016134545A publication Critical patent/JP2016134545A/en
Priority to US15/857,138 priority patent/US9960055B1/en
Application granted granted Critical
Publication of JP6420671B2 publication Critical patent/JP6420671B2/en
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
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    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/02—Transfer moulding, i.e. transferring the required volume of moulding material by a plunger from a "shot" cavity into a mould cavity
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    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Description

本発明は半導体装置の製造技術に関し、例えば半導体チップをトランスファモールド方式によって樹脂封止する半導体装置の製造に好適に利用できるものである。   The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for manufacturing a semiconductor device in which a semiconductor chip is resin-sealed by a transfer mold method, for example.

例えば特開２００６−０４９６９７号公報（特許文献１）には、上型および下型を有する成形金型であって、キャビティの中に樹脂を注入し上型と下型とを離間した後、基板装着台をピンによって上方に移動させて、ベース部材に対する基板装着台の高さ位置を初期位置に復帰させる技術が記載されている。   For example, Japanese Patent Laid-Open No. 2006-049797 (Patent Document 1) discloses a molding die having an upper mold and a lower mold, in which a resin is injected into a cavity and the upper mold and the lower mold are separated, and then a substrate A technique is described in which the mounting base is moved upward by a pin to return the height position of the board mounting base to the base member to the initial position.

また、特開２００２−３４３８１９号公報（特許文献２）には、樹脂封止する際に、溶融樹脂による樹脂圧を剛性部材である可動テーパ部材に加えることにより、上型と基板との間に間隙が発生しないようにする技術が記載されている。これにより、樹脂バリが抑制され、また、圧縮ばねにより基板が適正なクランプ圧でクランプされる。   Japanese Patent Laid-Open No. 2002-343819 (Patent Document 2) discloses that when resin sealing is performed, a resin pressure by molten resin is applied to a movable taper member, which is a rigid member, so that a gap between the upper mold and the substrate is obtained. Techniques for preventing gaps are described. Thereby, resin burr | flash is suppressed and a board | substrate is clamped with a suitable clamp pressure by a compression spring.

特開２００６−０４９６９７号公報JP 2006-049797 A 特開２００２−３４３８１９号公報JP 2002-343819 A

半導体チップを樹脂封止するモールド工程において、半導体チップを搭載したパッケージ基板の側面などにモールド樹脂が付着すると、そのモールド樹脂が樹脂バリとなって、飛散し、異物となる。そして、その異物が原因となって半導体装置の信頼性および生産性が低下することが、本発明者の検討によって明らかとなった。   In a molding process for resin-sealing a semiconductor chip, if mold resin adheres to the side surface of the package substrate on which the semiconductor chip is mounted, the mold resin becomes resin burrs and scatters to become foreign matter. And it became clear by examination of this inventor that the reliability and productivity of a semiconductor device fall because of the foreign material.

その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

一実施の形態によれば、上金型、下金型およびポットブロックからなるモールド金型において、下型キャビティブロックの裏面側に設けられた押し上げピンの先端面、および下型キャビティブロックの裏面のうち押し上げピンの先端面が接触する面を、モールド樹脂が供給されるポット側に向かうに従って、下型キャビティブロックの表面との距離が長くなるように、傾斜させる。   According to one embodiment, in a mold die composed of an upper die, a lower die and a pot block, a tip surface of a push-up pin provided on the back side of the lower die cavity block, and a back surface of the lower die cavity block Of these, the surface with which the tip surface of the push-up pin comes into contact is inclined so that the distance from the surface of the lower mold cavity block becomes longer toward the pot side to which the mold resin is supplied.

一実施の形態によれば、モールド工程における樹脂バリの発生を抑制することにより、半導体装置の信頼性および生産性を向上させることができる。   According to one embodiment, the reliability and productivity of a semiconductor device can be improved by suppressing the occurrence of resin burrs in the molding process.

一実施の形態による半導体装置（ＢＧＡパッケージ）を示す要部断面図である。It is principal part sectional drawing which shows the semiconductor device (BGA package) by one Embodiment. （ａ）および（ｂ）はそれぞれ、一実施の形態によるモールディング装置の一例を示す要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing which shows an example of the molding apparatus by one Embodiment, and principal part sectional drawing which expands and shows a part of lower mold | type unit of a molding apparatus, respectively. 一実施の形態による下型キャビティブロックを搭載した下型ユニットを示す要部上面図である。It is a principal part top view which shows the lower mold | type unit carrying the lower mold | type cavity block by one Embodiment. 一実施の形態による半導体装置の製造方法のモールド工程における工程図である。It is process drawing in the mold process of the manufacturing method of the semiconductor device by one embodiment. （ａ）および（ｂ）はそれぞれ、一実施の形態によるモールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing explaining the state of the molding apparatus in the molding process by one Embodiment, respectively, and principal part sectional drawing which expands and shows a part of lower mold unit of a molding apparatus. . 一実施の形態によるモールド工程におけるモールディング装置の状態を説明する、モールド金型の上金型を透視した要部上面図である。It is the principal part top view which saw through the upper metal mold | die of the mold metal mold | die explaining the state of the molding apparatus in the molding process by one Embodiment. （ａ）および（ｂ）はそれぞれ、図５および図６に続く、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing explaining the state of the molding apparatus in a molding process following FIG. 5 and FIG. 6, respectively, and principal part cross section which expands and shows a part of lower mold unit of a molding apparatus, respectively. FIG. （ａ）および（ｂ）はそれぞれ、図７に続く、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing explaining the state of the molding apparatus in a molding process following FIG. 7, respectively, and principal part sectional drawing which expands and shows a part of lower mold unit of a molding apparatus. . 図７に続く、モールド工程におけるモールディング装置の状態を説明する、モールド金型の上金型を透視した要部上面図である。FIG. 8 is an essential part top view illustrating the state of the molding apparatus in the molding process, seeing through the upper mold of the mold, following FIG. 7. （ａ）および（ｂ）はそれぞれ、図８および図９に続く、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。FIGS. 8A and 9B are main part cross-sectional views for explaining the state of the molding apparatus in the molding process and main part cross-sections showing a part of the lower mold unit of the molding apparatus in an enlarged manner, following FIGS. FIG. 図８および図９に続く、モールド工程におけるモールディング装置の状態を説明する、モールド金型の上金型を透視した要部上面図である。FIG. 10 is a top view of the main part seen through the upper mold of the mold for explaining the state of the molding apparatus in the molding process following FIG. 8 and FIG. 9. （ａ）および（ｂ）はそれぞれ、図１０および図１１に続く、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing explaining the state of the molding apparatus in a molding process following FIG. 10 and FIG. 11, respectively, and principal part cross section which expands and shows a part of lower mold unit of a molding apparatus, respectively. FIG. 図１２に続く、モールド工程におけるモールディング装置の状態を説明する要部断面図である。It is principal part sectional drawing explaining the state of the molding apparatus in a molding process following FIG. 一実施の形態によるモールディング装置の変形例を示す要部断面図である。It is principal part sectional drawing which shows the modification of the molding apparatus by one Embodiment. 一実施の形態によるモールド工程におけるモールディング装置の変形例の状態を説明する、下型ユニットの一部を拡大して示す要部断面図である。It is principal part sectional drawing which expands and shows a part of lower mold | type unit explaining the state of the modification of the molding apparatus in the molding process by one Embodiment. （ａ）および（ｂ）はそれぞれ、本発明者が比較検討したモールディング装置の一例を示す要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。(A) And (b) is principal part sectional drawing which shows an example of the molding apparatus which this inventor compared and examined, and principal part sectional drawing which expands and shows a part of lower mold unit of a molding apparatus, respectively. （ａ）は、パッケージ基板の側面に付着する樹脂バリを説明する下型ユニットの一部を拡大して示す要部断面図、（ｂ）は、パッケージ基板の側面に付着する樹脂バリの他の例を説明する下型ユニットの一部を拡大して示す要部断面図である。(A) is a principal part sectional view which expands and shows a part of lower mold unit explaining the resin burr adhering to the side of a package substrate, (b) is other resin burr adhering to the side of a package substrate It is principal part sectional drawing which expands and shows a part of lower mold unit explaining an example. 半導体装置（ＢＧＡパッケージ）の外部端子の接合部に付着した樹脂バリを説明する裏面図である。It is a back view explaining the resin burr | flash adhering to the junction part of the external terminal of a semiconductor device (BGA package).

以下の実施の形態において、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。   In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。   Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

また、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。   Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

また、「Ａからなる」、「Ａよりなる」、「Ａを有する」、「Ａを含む」と言うときは、特にその要素のみである旨明示した場合等を除き、それ以外の要素を排除するものでないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。   In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

また、以下の実施の形態で用いる図面においては、平面図であっても図面を見易くするためにハッチングを付す場合もある。また、以下の実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。以下、本実施の形態を図面に基づいて詳細に説明する。   Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

（モールド工程における課題の詳細な説明）
本実施の形態による半導体装置の製造方法がより明確となると思われるため、本発明者によって見出された、半導体チップを樹脂封止するモールド工程における課題について詳細に説明する。 (Detailed explanation of problems in the molding process)
Since the manufacturing method of the semiconductor device according to the present embodiment is considered to be clearer, problems in the molding process for sealing the semiconductor chip, which has been found by the present inventors, will be described in detail.

例えばＢＧＡ（Ball Grid Array）パッケージのような基板品の製造においては、モールド金型（上金型、下金型およびポットブロック）を用いて半導体チップを樹脂封止するモールド工程がある。   For example, in the manufacture of a substrate product such as a BGA (Ball Grid Array) package, there is a molding process in which a semiconductor chip is resin-sealed using a molding die (upper die, lower die and pot block).

図１６（ａ）および（ｂ）はそれぞれ、本発明者が比較検討したモールディング装置の一例を示す要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。   FIGS. 16A and 16B are a cross-sectional view of a main part showing an example of a molding apparatus that the present inventors have compared and examined, and a main part cross-sectional view showing a part of a lower mold unit of the molding apparatus in an enlarged manner. .

モールド金型は、下型キャビティブロックＣＶａの下型キャビティＣＡＶａの表面上に搭載される基材ＳＴ（具体的には半導体チップＳＣを搭載するパッケージ基板（基板、配線基板）ＰＳ）の厚さにばらつきがあったとしても、その厚さのばらつきを吸収できるように、下型キャビティブロックＣＶａは摺動（上下動）が可能な状態となっている。また、先のモールド工程が終了し、次のモールド工程が行えるように下型キャビティブロックＣＶａを初期位置に戻すための押し上げピンＵＰが、下型キャビティブロックＣＶａの裏面側に設けられている。   The mold mold has a thickness of a base ST (specifically, a package substrate (substrate, wiring substrate) PS on which a semiconductor chip SC is mounted) mounted on the surface of the lower mold cavity CAVa of the lower mold cavity block CVa. Even if there is a variation, the lower mold cavity block CVa is slidable (up and down) so that the variation in thickness can be absorbed. Further, a push-up pin UP for returning the lower mold cavity block CVa to the initial position is provided on the back side of the lower mold cavity block CVa so that the previous molding process is completed and the next molding process can be performed.

ところで、下型キャビティブロックＣＶａの摺動を可能とするため、下型キャビティブロックＣＶａの側面と、モールド樹脂ＭＴＡを供給するポットブロックＰＢの側面との間に、例えば５〜１０μｍ程度の隙間が設けられている。この結果、ポットブロックＰＢから上型キャビティＣＡＶｂ内に供給されるモールド樹脂ＭＴＡの一部が、モールド樹脂ＭＴＡの流路（例えば図１１に示すランナＲＡ）にあたる部分において上記隙間に入り込んでしまう。   By the way, in order to allow the lower mold cavity block CVa to slide, a gap of, for example, about 5 to 10 μm is provided between the side surface of the lower mold cavity block CVa and the side surface of the pot block PB that supplies the mold resin MTA. It has been. As a result, a part of the mold resin MTA supplied from the pot block PB into the upper mold cavity CAVb enters the gap in a portion corresponding to the flow path (for example, the runner RA shown in FIG. 11) of the mold resin MTA.

そして、例えば図１７（ａ）に示すように、上記隙間に入り込んだモールド樹脂ＭＴＡが徐々に蓄積して、このモールド樹脂ＭＴＡが樹脂バリＭＢ１となると、下型キャビティブロックＣＶａの摺動を阻害して、下型キャビティブロックＣＶａが初期位置に戻らなくなる。下型キャビティブロックＣＶａが初期位置に戻りきらない状態で、次のモールド工程を行うと、パッケージ基板ＰＳの側面にモールド樹脂ＭＴＡの一部（樹脂バリＭＢ２）が付着し、後にパッケージ基板ＰＳの側面から離れた樹脂バリＭＢ２が異物の原因となる。   For example, as shown in FIG. 17A, when the mold resin MTA that has entered the gap gradually accumulates and the mold resin MTA becomes the resin burr MB1, the sliding of the lower mold cavity block CVa is hindered. Thus, the lower mold cavity block CVa does not return to the initial position. When the next molding process is performed in a state where the lower mold cavity block CVa does not return to the initial position, a part of the mold resin MTA (resin burr MB2) adheres to the side surface of the package substrate PS, and later the side surface of the package substrate PS. The resin burr MB2 away from the substrate causes foreign matter.

また、例えば図１７（ｂ）に示すように、ポットブロックＰＢの側面にモールド樹脂ＭＴＡの一部（樹脂バリＭＢ３）が付着した場合も、上記樹脂バリＭＢ１と同様に、ポットブロックＰＢの側面に付着した樹脂バリＭＢ３が下型キャビティブロックＣＶａの摺動を阻害して、下型キャビティブロックＣＶａが初期位置に戻らなくなる。下型キャビティブロックＣＶａが初期位置に戻りきらない状態で、次のモールド工程を行うと、パッケージ基板ＰＳの側面にモールド樹脂ＭＴＡの一部（樹脂バリＭＢ４）が付着し、後にパッケージ基板ＰＳの側面から離れた樹脂バリＭＢ４が異物の原因となる。   Further, for example, as shown in FIG. 17B, even when a part of the mold resin MTA (resin burr MB3) adheres to the side surface of the pot block PB, the side surface of the pot block PB is similar to the resin burr MB1. The attached resin burr MB3 obstructs the sliding of the lower mold cavity block CVa, and the lower mold cavity block CVa does not return to the initial position. When the next molding process is performed in a state where the lower mold cavity block CVa does not return to the initial position, a part of the mold resin MTA (resin burr MB4) adheres to the side surface of the package substrate PS, and later the side surface of the package substrate PS. Resin burr MB4 away from the substrate causes foreign matter.

さらに、例えば図１８に示すように、異物の原因となる樹脂バリＭＢ２，ＭＢ４が飛散して、半導体装置（ＢＧＡパッケージ）ＳＤの半田ボール（外部端子）ＳＢの接合部（ランド面）に樹脂バリＭＢ２，ＭＢ４が付着すると、半田ボールＳＢが接続されず、欠落不良品が製造されて、半導体装置ＳＤの信頼性および生産性が低下する。   Further, as shown in FIG. 18, for example, the resin burrs MB2 and MB4 that cause foreign matters are scattered, and the resin burrs are formed at the joints (land surfaces) of the solder balls (external terminals) SB of the semiconductor device (BGA package) SD. When MB2 and MB4 adhere, the solder balls SB are not connected, a defective defective product is manufactured, and the reliability and productivity of the semiconductor device SD are lowered.

このため、下型キャビティブロックＣＶａの側面とポットブロックＰＢの側面との間にモールド樹脂ＭＴＡが入り込まないようにする必要がある。   For this reason, it is necessary to prevent the mold resin MTA from entering between the side surface of the lower mold cavity block CVa and the side surface of the pot block PB.

（実施の形態）
１．半導体装置の構造
本実施の形態による半導体装置は、パッケージ基板上に半導体チップが搭載された樹脂封止型の半導体パッケージである。以下に、本実施の形態による半導体装置の一例としてＢＧＡパッケージを取り上げて、その構造について図１を用いて説明する。図１は、半導体装置（ＢＧＡパッケージ）を示す要部断面図である。 (Embodiment)
1. Structure of Semiconductor Device The semiconductor device according to the present embodiment is a resin-encapsulated semiconductor package in which a semiconductor chip is mounted on a package substrate. Hereinafter, a BGA package will be taken up as an example of the semiconductor device according to the present embodiment, and its structure will be described with reference to FIG. FIG. 1 is a cross-sectional view of a principal part showing a semiconductor device (BGA package).

図１に示すように、本実施の形態による半導体装置（ＢＧＡパッケージ）ＳＤのパッケージ構造は、上面（表面）ＰＳｘ、およびこの上面ＰＳｘとは反対側の下面（裏面）ＰＳｙを有するパッケージ基板（基板、配線基板）ＰＳを備えている。さらに、パッケージ基板ＰＳの上面ＰＳｘ側には、半導体素子が形成された半導体チップＳＣと、半導体チップＳＣを封止する樹脂封止体（封止体）ＲＳとを有し、パッケージ基板ＰＳの下面ＰＳｙ側には、複数のバンプ・ランド（電極パッド）ＢＬと、複数のバンプ・ランドＢＬに接続された複数の半田ボール（外部端子）ＳＢとを有している。以下、パッケージ基板ＰＳ、半導体チップＳＣおよび半田ボールＳＢについて詳細に説明する。   As shown in FIG. 1, the package structure of the semiconductor device (BGA package) SD according to the present embodiment is a package substrate (substrate) having an upper surface (front surface) PSx and a lower surface (back surface) PSy opposite to the upper surface PSx. , Wiring board) PS. Furthermore, the upper surface PSx side of the package substrate PS has a semiconductor chip SC on which semiconductor elements are formed, and a resin sealing body (sealing body) RS that seals the semiconductor chip SC, and the lower surface of the package substrate PS. On the PSy side, a plurality of bump lands (electrode pads) BL and a plurality of solder balls (external terminals) SB connected to the plurality of bump lands BL are provided. Hereinafter, the package substrate PS, the semiconductor chip SC, and the solder balls SB will be described in detail.

≪パッケージ基板ＰＳ≫
パッケージ基板ＰＳは、その厚さ方向と交差する平面形状が四角形になっている。パッケージ基板ＰＳは多層配線構造からなり、本実施の形態では４つの配線層を有している。パッケージ基板ＰＳの厚さは、例えば０．２〜０．６ｍｍ程度である。 ≪Package substrate PS≫
The package substrate PS has a quadrangular planar shape that intersects its thickness direction. The package substrate PS has a multilayer wiring structure, and has four wiring layers in the present embodiment. The thickness of the package substrate PS is, for example, about 0.2 to 0.6 mm.

詳細に説明すると、パッケージ基板ＰＳは、コア材ＣＯと、このコア材ＣＯの表面（上面ＰＳｘ側）に形成された配線層ＣＬ１と、この配線層ＣＬ１を覆うように形成された絶縁層ＩＬ１と、この絶縁層ＩＬ１の表面に形成された配線層ＣＬ２とを有している。ここで、複数のボンディング電極ＢＥは、最上層の配線層ＣＬ２の一部からなり、この最上層の配線層ＣＬ２を覆うようにして形成された保護膜ＰＦ１から露出している。   More specifically, the package substrate PS includes a core material CO, a wiring layer CL1 formed on the surface (upper surface PSx side) of the core material CO, and an insulating layer IL1 formed so as to cover the wiring layer CL1. And a wiring layer CL2 formed on the surface of the insulating layer IL1. Here, the plurality of bonding electrodes BE are part of the uppermost wiring layer CL2, and are exposed from the protective film PF1 formed so as to cover the uppermost wiring layer CL2.

また、パッケージ基板ＰＳは、コア材ＣＯの表面とは反対側に位置する裏面（下面ＰＳｙ側）に形成された配線層ＣＬ３と、この配線層ＣＬ３を覆うように形成された絶縁層ＩＬ２と、この絶縁層ＩＬ２の表面に形成された配線層ＣＬ４とを有している。ここで、複数のバンプ・ランドＢＬは、最下層の配線層ＣＬ４の一部からなり、この最下層の配線層ＣＬ４を覆うようにして形成された保護膜ＰＦ２から露出している。   The package substrate PS includes a wiring layer CL3 formed on the back surface (the lower surface PSy side) located on the opposite side of the surface of the core material CO, an insulating layer IL2 formed so as to cover the wiring layer CL3, And a wiring layer CL4 formed on the surface of the insulating layer IL2. Here, the plurality of bump lands BL are part of the lowermost wiring layer CL4 and are exposed from the protective film PF2 formed so as to cover the lowermost wiring layer CL4.

また、パッケージ基板ＰＳの上面ＰＳｘから下面ＰＳｙまたはコア材ＣＯの表面から裏面に向かって複数の貫通孔（ビア）ＴＨが形成されており、複数の貫通孔ＴＨのそれぞれの内部（内壁）には、各配線層ＣＬ１，ＣＬ２，ＣＬ３，ＣＬ４を互いに電気的に接続する導電性部材ＣＭが形成されている。また、絶縁層ＩＬ１，ＩＬ２に形成された複数の接続孔ＣＨを介して、配線層ＣＬ１と配線層ＣＬ２とは電気的に接続され、配線層ＣＬ３と配線層ＣＬ４とは電気的に接続される。   Further, a plurality of through holes (vias) TH are formed from the upper surface PSx of the package substrate PS to the lower surface PSy or from the front surface of the core material CO to the back surface, and inside each of the plurality of through holes TH (inner walls). A conductive member CM that electrically connects the wiring layers CL1, CL2, CL3, and CL4 to each other is formed. Further, the wiring layer CL1 and the wiring layer CL2 are electrically connected through the plurality of connection holes CH formed in the insulating layers IL1 and IL2, and the wiring layer CL3 and the wiring layer CL4 are electrically connected. .

コア材ＣＯおよび各絶縁層ＩＬ１，ＩＬ２は、例えばガラス繊維にエポキシ系またはポリイミド系の熱硬化性絶縁樹脂を含浸させた高弾性樹脂により形成されている。また、各配線層ＣＬ１，ＣＬ２，ＣＬ３，ＣＬ４は、例えば銅を主成分とする金属膜で形成されている。   The core material CO and the insulating layers IL1 and IL2 are made of, for example, a highly elastic resin obtained by impregnating glass fiber with an epoxy-based or polyimide-based thermosetting insulating resin. In addition, each of the wiring layers CL1, CL2, CL3, and CL4 is formed of a metal film having copper as a main component, for example.

パッケージ基板ＰＳの上面ＰＳｘ側を被覆する保護膜ＰＦ１は、主にパッケージ基板ＰＳの最上層の配線層ＣＬ２を保護する目的で形成され、パッケージ基板ＰＳの下面ＰＳｙ側を被覆する保護膜ＰＦ２は、主にパッケージ基板ＰＳの最下層の配線層ＣＬ４を保護する目的で形成されている。保護膜ＰＦ１，ＰＦ２は、例えばエポキシ系またはポリイミド系の熱硬化性絶縁樹脂を主成分とするソルダーレジストからなる。   The protective film PF1 covering the upper surface PSx side of the package substrate PS is formed mainly for the purpose of protecting the uppermost wiring layer CL2 of the package substrate PS, and the protective film PF2 covering the lower surface PSy side of the package substrate PS is It is formed mainly for the purpose of protecting the lowermost wiring layer CL4 of the package substrate PS. The protective films PF1 and PF2 are made of, for example, a solder resist whose main component is an epoxy-based or polyimide-based thermosetting insulating resin.

≪半導体チップＳＣ≫
半導体チップＳＣは、その厚さ方向と交差する平面形状が四角形になっており、例えばシリコンからなる半導体基板と、この半導体基板の主面（表面）に形成された複数の半導体素子と、絶縁層と配線層とをそれぞれ複数段積み重ねた多層配線層と、この多層配線層を覆うようにして形成された表面保護膜とを有する構成になっている。 ≪Semiconductor chip SC≫
The semiconductor chip SC has a quadrangular planar shape that intersects its thickness direction. For example, a semiconductor substrate made of silicon, a plurality of semiconductor elements formed on the main surface (front surface) of the semiconductor substrate, and an insulating layer And a multilayer wiring layer in which a plurality of wiring layers are stacked, and a surface protective film formed so as to cover the multilayer wiring layer.

半導体チップＳＣが、半導体チップＳＣの主面（表面）とは反対側の裏面と保護膜ＰＦ１とを対向させて、ダイボンド材（接着剤）ＡＢを介してパッケージ基板ＰＳの上面ＰＳｘ側に搭載されている。本実施の形態で使用するダイボンド材ＡＢは、例えばペースト状またはフィルム状の接着剤である。   The semiconductor chip SC is mounted on the upper surface PSx side of the package substrate PS via the die bond material (adhesive) AB with the back surface opposite to the main surface (front surface) of the semiconductor chip SC and the protective film PF1 facing each other. ing. The die bond material AB used in the present embodiment is, for example, a paste or film adhesive.

半導体チップＳＣの主面には、複数の半導体素子と電気的に接続された複数の電極パッドＥＰが半導体チップＳＣの各辺に沿って配置されている。これら電極パッドＥＰは、多層配線層のうちの最上層の配線からなり、半導体チップＳＣの表面保護膜にそれぞれの電極パッドＥＰに対応して形成された開口部により露出している。   On the main surface of the semiconductor chip SC, a plurality of electrode pads EP electrically connected to the plurality of semiconductor elements are arranged along each side of the semiconductor chip SC. These electrode pads EP are composed of the uppermost wiring in the multilayer wiring layer, and are exposed through openings formed in the surface protective film of the semiconductor chip SC corresponding to the respective electrode pads EP.

また、複数の電極パッドＥＰと、パッケージ基板ＰＳの上面ＰＳｘに配置された複数のボンディング電極ＢＥとが、複数の導電性部材（ボンディングワイヤ）ＢＷによってそれぞれ電気的に接続されている。導電性部材ＢＷには、例えば金線を用いる。導電性部材ＢＷは、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング（ボールボンディング）法により、半導体チップＳＣの主面に配置された電極パッドＥＰと、パッケージ基板ＰＳの上面ＰＳｘに配置されたボンディング電極ＢＥとに接続される。   Further, the plurality of electrode pads EP and the plurality of bonding electrodes BE arranged on the upper surface PSx of the package substrate PS are electrically connected to each other by a plurality of conductive members (bonding wires) BW. For example, a gold wire is used for the conductive member BW. The conductive member BW is disposed on the electrode pad EP disposed on the main surface of the semiconductor chip SC and the upper surface PSx of the package substrate PS by, for example, a nail head bonding (ball bonding) method using ultrasonic vibration in combination with thermocompression bonding. Connected to the bonding electrode BE.

半導体チップＳＣおよび導電性部材ＢＷは、パッケージ基板ＰＳの上面ＰＳｘ側を被覆する樹脂封止体ＲＳによって封止されている。樹脂封止体ＲＳは、低応力化を図る目的として、例えばフェノール系硬化剤、シリコーンゴムおよび多数のフィラー（例えばシリカ）などが添加されたエポキシ系の熱硬化性絶縁樹脂で形成されている。樹脂封止体ＲＳは、後述するようにトランスファモールド法により形成される。   The semiconductor chip SC and the conductive member BW are sealed with a resin sealing body RS that covers the upper surface PSx side of the package substrate PS. For the purpose of reducing stress, the resin sealing body RS is formed of an epoxy thermosetting insulating resin to which, for example, a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added. The resin sealing body RS is formed by a transfer mold method as will be described later.

≪半田ボールＳＢ≫
パッケージ基板ＰＳの下面ＰＳｙに形成された複数のバンプ・ランドＢＬには、複数の半田ボールＳＢが接合されている。複数のバンプ・ランドＢＬは、パッケージ基板ＰＳの下面ＰＳｙ側を被覆する保護膜ＰＦ２にそれぞれのバンプ・ランドＢＬに対応して形成された開口部により露出しており、複数の半田ボールＳＢは、複数のバンプ・ランドＢＬとそれぞれ電気的に、かつ機械的に接続されている。半田ボールＳＢとしては、鉛を実質的に含まない鉛フリー半田組成の半田バンプ、例えばＳｎ−３［ｗｔ％］Ａｇ−０．５［ｗｔ％］Ｃｕ組成の半田バンプなどが用いられる。 ≪Solder ball SB≫
A plurality of solder balls SB are joined to a plurality of bump lands BL formed on the lower surface PSy of the package substrate PS. The plurality of bump lands BL are exposed in the protective film PF2 covering the lower surface PSy side of the package substrate PS through the openings formed corresponding to the respective bump lands BL, and the plurality of solder balls SB are Each of the bump lands BL is electrically and mechanically connected. As the solder ball SB, a solder bump having a lead-free solder composition substantially free of lead, for example, a solder bump having a Sn-3 [wt%] Ag-0.5 [wt%] Cu composition, or the like is used.

２．モールディング装置（モールド装置）の構造
本実施の形態によるモールディング装置（モールド装置）の構造を図２（ａ）および（ｂ）並びに図３を用いて説明する。図２（ａ）および（ｂ）はそれぞれ、モールディング装置の一例を示す要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。図３は、下型キャビティブロックを搭載した下型ユニットを示す要部上面図である。 2. Structure of Molding Device (Molding Device) The structure of the molding device (molding device) according to this embodiment will be described with reference to FIGS. 2 (a) and 2 (b) and FIG. FIGS. 2A and 2B are a main part sectional view showing an example of the molding apparatus and a main part sectional view showing an enlarged part of the lower mold unit of the molding apparatus, respectively. FIG. 3 is a top view of the main part showing the lower mold unit on which the lower mold cavity block is mounted.

図２（ａ）および（ｂ）に示すように、本実施の形態によるモールディング装置は、トランスファモールド用の半導体製造装置である。モールディング装置のモールド金型は、半導体チップを搭載したパッケージ基板が配置される下金型ＤＭ（第１金型）と、下金型ＤＭに対向し、この下金型ＤＭと係合して半導体チップを搭載したパッケージ基板を密閉する上金型ＵＭ（第２金型）とを有している。さらに、モールディング装置のモールド金型は、モールド樹脂を供給するポットブロックＰＢを有している。以下の説明では、下金型ＤＭとポットブロックＰＢとを合わせて下型ユニットＤＭＵと言い、図２（ａ）では、下型ユニットＤＭＵの点線で囲んだ領域がポットブロックＰＢであり、その他の領域が下金型ＤＭである。   As shown in FIGS. 2A and 2B, the molding apparatus according to the present embodiment is a semiconductor manufacturing apparatus for transfer molding. The molding die of the molding device is opposed to the lower die DM (first die) on which the package substrate on which the semiconductor chip is mounted is arranged, and the lower die DM, and engages with the lower die DM to form a semiconductor. It has an upper mold UM (second mold) for sealing the package substrate on which the chip is mounted. Further, the molding die of the molding apparatus has a pot block PB for supplying mold resin. In the following description, the lower mold DM and the pot block PB are collectively referred to as a lower mold unit DMU. In FIG. 2A, the area surrounded by the dotted line of the lower mold unit DMU is the pot block PB. The area is the lower mold DM.

上金型ＵＭは、下金型ＤＭに対応した構成となっている。上金型ＵＭには、半導体チップを樹脂封止するパッケージ領域となる上型キャビティＣＡＶｂ（キャビティ部）、図２（ａ）および（ｂ）では図示は省略するが、上型キャビティＣＡＶｂ内にモールド樹脂を流入する際の入り口となるゲートＧＡ（図１１を参照）、並びにゲートＧＡを介して上型キャビティＣＡＶｂと連通し、モールド樹脂の流入経路となるランナＲＡ（図１１を参照）などが形成された上型キャビティブロックＣＶｂが備わっている。さらに、上型キャビティブロックＣＶｂには、モールド樹脂の流入源となり、上金型ＵＭと下金型ＤＭとを閉じたときに上金型ＵＭに形成されたランナＲＡと連通するカルブロックＣＢなどが形成されている。   The upper mold UM has a configuration corresponding to the lower mold DM. In the upper mold UM, an upper mold cavity CAVb (cavity portion) which becomes a package region for resin-sealing a semiconductor chip, although not shown in FIGS. 2A and 2B, is molded in the upper mold cavity CAVb. A gate GA (see FIG. 11) serving as an entrance when the resin flows in, and a runner RA (see FIG. 11) serving as a mold resin inflow path are formed through communication with the upper mold cavity CAVb via the gate GA. The upper mold cavity block CVb is provided. Further, in the upper mold cavity block CVb, there is a cull block CB that serves as an inflow source of mold resin and communicates with the runner RA formed in the upper mold UM when the upper mold UM and the lower mold DM are closed. Is formed.

下型ユニットＤＭＵを構成する下金型ＤＭは、ポットブロックＰＢ以外の領域であって、下金型ＤＭには、半導体チップを樹脂封止するパッケージ領域となる下型キャビティＣＡＶａなどが形成された下型キャビティブロックＣＶａが備わっている。本実施の形態では、ポットブロックＰＢの両側に下型キャビティブロックＣＶａが配置されている（後述の図３参照）。下型キャビティＣＡＶａの表面（成形面、主面）に、半導体チップを搭載したパッケージ基板が配置される。なお、本実施の形態では、下型キャビディＣＡＶａの表面と下型キャビティブロックＣＶａの表面とは同一平面としているので、下型キャビティブロックＣＶａの表面と言うときには、下型キャビティＣＡＶａの表面も含む。   The lower mold DM constituting the lower mold unit DMU is an area other than the pot block PB, and the lower mold DM is formed with a lower mold cavity CAVa that becomes a package area for resin-sealing a semiconductor chip. A lower die cavity block CVa is provided. In the present embodiment, lower mold cavity blocks CVa are disposed on both sides of the pot block PB (see FIG. 3 described later). A package substrate on which a semiconductor chip is mounted is disposed on the surface (molding surface, main surface) of the lower mold cavity CAVa. In the present embodiment, since the surface of the lower mold cavity CAVa and the surface of the lower mold cavity block CVa are the same plane, the surface of the lower mold cavity block CVa includes the surface of the lower mold cavity CAVa.

さらに、下金型ＤＭには、半導体チップを樹脂封止した基材を下型キャビティブロックＣＶａから押し上げるための複数のエジェクタピンＥＪＰが備わっている。また、下金型ＤＭには、下型キャビティブロックＣＶａをモールド工程後に下型キャビティブロックＣＶａを押し上げて初期位置に戻すことのできる複数の押し上げピンＵＰ、並びにクランプ圧に応じて下型キャビティブロックＣＶａを上昇または下降させることのできる複数の圧縮バネＣＳが備わっている。   Further, the lower mold DM is provided with a plurality of ejector pins EJP for pushing up a base material on which a semiconductor chip is sealed with resin from the lower mold cavity block CVa. The lower mold DM includes a plurality of push-up pins UP that can push the lower mold cavity block CVa back to the initial position after the lower mold cavity block CVa is molded, and the lower mold cavity block CVa according to the clamp pressure. Are provided with a plurality of compression springs CS that can be raised or lowered.

エジェクタピンＥＪＰの一端は、例えば下型キャビティブロックＣＶａの表面から３０〜５０μｍ程度突出するように設けられている。   One end of the ejector pin EJP is provided, for example, so as to protrude from the surface of the lower mold cavity block CVa by about 30 to 50 μm.

また、押し上げピンＵＰの先端面（下型キャビティブロックＣＶａを押し上げる面、押し上げ面）は、ポットブロックＰＢ側に向かうに従い、下型キャビティブロックＣＶａの表面（下型キャビティＣＡＶａの内、パッケージ基板を搭載する表面）との距離が長くなるように、傾斜している。言い換えると、断面視において、押し上げピンＵＰの先端面の上型キャビティＣＡＶｂ内へ樹脂を注入する側（ポットＰＯ側）と下型キャビティブロックＣＶａの表面（下型キャビティＣＡＶａの内、パッケージ基板を搭載する表面）との長さ（Ｈ１）は、押し上げピンＵＰの先端面の上型キャビティＣＡＶｂの中心側と下型キャビティブロックＣＶａの表面（下型キャビティＣＡＶａの内、パッケージ基板を搭載する表面）との長さ（Ｈ２）より、長い。また、断面視において、押し上げピンＵＰの先端面は、樹脂の流れ方向に向かって、下型キャビティブロックＣＶａの表面（下型キャビティＣＡＶａの内、パッケージ基板を搭載する表面）との距離が短くなるように、傾斜している。また、下型キャビティＣＡＶａの表面と反対側の裏面のうち、押し上げピンＵＰの先端面が接触する面も上記と同様に、押し上げピンＵＰの先端面に倣って、ポットブロックＰＢ側に向かうに従い、下型キャビティブロックＣＶａの表面（下型キャビティＣＡＶａのパッケージ基板を搭載する表面）との距離が長くなるように、傾斜している。   Further, the tip surface of the push-up pin UP (the surface that pushes up the lower mold cavity block CVa, the push-up surface) is mounted on the surface of the lower mold cavity block CVa (the package substrate of the lower mold cavity CAVa is mounted) as it goes toward the pot block PB side. The surface is inclined so that the distance to the surface becomes longer. In other words, in a cross-sectional view, the resin injection side (pot PO side) on the tip end surface of the push-up pin UP and the surface of the lower mold cavity block CVa (the package substrate among the lower mold cavities CAVa are mounted) The length (H1) of the top surface of the push-up pin UP and the center side of the upper mold cavity CAVb and the surface of the lower mold cavity block CVa (the surface of the lower mold cavity CAVa on which the package substrate is mounted) Longer than the length (H2). Also, in a cross-sectional view, the distance between the tip surface of the push-up pin UP and the surface of the lower mold cavity block CVa (the surface on which the package substrate is mounted among the lower mold cavities CAVa) decreases in the resin flow direction. So that it is inclined. Further, of the back surface opposite to the front surface of the lower mold cavity CAVa, the surface with which the tip surface of the push-up pin UP contacts is also similar to the above, following the tip surface of the push-up pin UP toward the pot block PB side. The lower mold cavity block CVa is inclined so that the distance from the surface (the surface on which the package substrate of the lower mold cavity CAVa is mounted) becomes longer.

さらに、押し上げピンＵＰの先端面は鏡面仕上げが施されており、その表面の粗さは、例えば十点平均粗さ（Ｒｚ）で３μｍ以下としている。鏡面仕上げをすることにより、押し上げピンＵＰの動きを滑らかにすることができる。また、押し上げピンＵＰの先端面には硬質クロムめっきが施されている。押し上げピンＵＰの先端面にめっき膜を形成することにより、押し上げピンＵＰの先端面が摩耗し難くなり、また、押し上げピンＵＰの動きを滑らかにすることができる。めっき膜の厚さは、例えば１μｍ程度である。   Furthermore, the tip surface of the push-up pin UP is mirror-finished, and the surface roughness is, for example, 3 μm or less in terms of 10-point average roughness (Rz). By performing the mirror finish, the movement of the push-up pin UP can be made smooth. Moreover, the hard chrome plating is given to the front end surface of the push-up pin UP. By forming a plating film on the tip surface of the push-up pin UP, the tip surface of the push-up pin UP is less likely to be worn, and the movement of the push-up pin UP can be made smooth. The thickness of the plating film is, for example, about 1 μm.

下型ユニットＤＭＵを構成するポットブロックＰＢには、タブレット（モールド樹脂を圧力で固めたもの）が投入されるポットＰＯが形成されている。このポットＰＯ内には、上下動するブランジャＰＬが設けられている。ポットＰＯに投入されたタブレットは、プランジャＰＬをサーボモータによって上昇させることにより加圧され、溶融する。タブレットが溶融し流動化したモールド樹脂は、カルブロックＣＢ、ランナＲＡおよびゲートＧＡなどを介して上型キャビティＣＡＶｂ内に注入されるようになっている。   The pot block PB constituting the lower mold unit DMU is formed with a pot PO into which a tablet (mold resin solidified by pressure) is charged. A blanker PL that moves up and down is provided in the pot PO. The tablet put into the pot PO is pressurized and melted by raising the plunger PL by a servo motor. The mold resin in which the tablet is melted and fluidized is injected into the upper mold cavity CAVb through the calblock CB, the runner RA, the gate GA, and the like.

また、図３に示すように、例えば第１方向に複数のポットＰＯを有するポットブロックＰＢの両側（第１方向と下型キャビティブロックＣＶａの表面で直交する第２方向）に、下型キャビティブロックＣＶａがそれぞれ配置されている。そして、これら下型キャビティブロックＣＶａの基材搭載エリア内、すなわち下型キャビティＣＡＶａ内に、複数の半導体チップを搭載したパッケージ基板が載置される。   Further, as shown in FIG. 3, for example, the lower die cavity block is disposed on both sides of the pot block PB having a plurality of pots PO in the first direction (the second direction orthogonal to the first direction and the surface of the lower die cavity block CVa). CVa is respectively arranged. Then, a package substrate on which a plurality of semiconductor chips are mounted is placed in the base material mounting area of these lower mold cavity blocks CVa, that is, in the lower mold cavity CAVa.

なお、モールド金型（上金型ＵＭおよび下型ユニットＤＭＵ（下金型ＤＭおよびポットブロックＰＢ））の構造は、図２（ａ）および（ｂ）並びに図３を用いて説明した構造に限定されるものではない。例えば本実施の形態では、カルブロックおよびランナなどを共に上金型ＵＭに形成したが、カルブロックを上金型ＵＭに形成し、ランナを下金型ＤＭに形成してもよく、または、カルブロックおよびランナなどを共に下金型ＤＭに形成してもよい。   The structure of the mold (upper mold UM and lower mold unit DMU (lower mold DM and pot block PB)) is limited to the structure described with reference to FIGS. 2 (a) and 2 (b) and FIG. Is not to be For example, in the present embodiment, the cull block and the runner are both formed in the upper mold UM, but the cull block may be formed in the upper mold UM and the runner may be formed in the lower mold DM. Both the block and the runner may be formed in the lower mold DM.

３．半導体装置の製造方法
本実施の形態による半導体装置の製造方法（主としてモールド工程）について図４〜図１３を用いて説明する。図４は、半導体装置の製造方法のモールド工程における工程図である。図５、図７、図８、図１０並びに図１２の各々の（ａ）および（ｂ）はそれぞれ、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。図６、図９および図１１は、モールド工程におけるモールディング装置の状態を説明する、モールド金型の上金型を透視した要部上面図である。図１３は、モールド工程におけるモールディング装置の状態を説明する要部断面図である。 3. Semiconductor Device Manufacturing Method A semiconductor device manufacturing method (mainly a molding process) according to the present embodiment will be described with reference to FIGS. FIG. 4 is a process diagram in the molding process of the semiconductor device manufacturing method. 5, FIG. 7, FIG. 8, FIG. 10 and FIG. 12 are (a) and (b), respectively, a cross-sectional view of the main part for explaining the state of the molding device in the molding process and one of the lower mold unit of the molding device. It is principal part sectional drawing which expands and shows a part. FIGS. 6, 9 and 11 are top views of the main parts seen through the upper mold of the mold, for explaining the state of the molding apparatus in the molding process. FIG. 13 is a cross-sectional view of the main part for explaining the state of the molding apparatus in the molding process.

本実施の形態においては、モールド工程において樹脂バリの発生を防止することにより、半導体装置の高信頼性および生産性の向上を図ることが主要な特徴となっており、その詳細および効果等について以降の説明で明らかにする。   In this embodiment, the main feature is to improve the reliability and productivity of the semiconductor device by preventing the occurrence of resin burrs in the molding process. It will be clarified in the explanation.

［半導体チップ準備工程］
半導体ウエハの回路形成面に集積回路を形成する。集積回路は前工程または拡散工程と呼ばれる製造工程において、所定の製造プロセスに従って半導体ウエハにチップ単位で形成される。続いて、半導体ウエハに形成された各半導体チップの良・不良を判定した後、半導体ウエハをダイシングして、各半導体チップに個片化する。 [Semiconductor chip preparation process]
An integrated circuit is formed on the circuit formation surface of the semiconductor wafer. An integrated circuit is formed on a semiconductor wafer in units of chips according to a predetermined manufacturing process in a manufacturing process called a pre-process or a diffusion process. Subsequently, after determining whether each semiconductor chip formed on the semiconductor wafer is good or defective, the semiconductor wafer is diced into individual semiconductor chips.

［パッケージ基板準備工程］
上面と、上面とは反対側の下面とを有し、多層配線構造のパッケージ基板を準備する。例えばパッケージ基板は、長手方向に半導体製品１つ分に該当するチップ搭載領域が３つ配置される構成となっている（後述の図６参照）。 [Package substrate preparation process]
A package substrate having a top surface and a bottom surface opposite to the top surface and having a multilayer wiring structure is prepared. For example, the package substrate has a configuration in which three chip mounting areas corresponding to one semiconductor product are arranged in the longitudinal direction (see FIG. 6 described later).

［ダイボンディング工程］
次に、パッケージ基板の上面（主面、表面）の各チップ搭載領域に、ダイボンド材（接着剤）を介して半導体チップを接合する。 [Die bonding process]
Next, a semiconductor chip is bonded to each chip mounting region on the upper surface (main surface, surface) of the package substrate via a die bond material (adhesive).

［ワイヤボンディング工程］
次に、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング法により、半導体チップの主面に形成された複数の電極パッドとパッケージ基板の上面に配置されたボンディング電極とを導電性部材（ボンディングワイヤ）を介してそれぞれ電気的に接続する（後述の図６参照）。ボンディングワイヤには、例えば１５〜２０μｍφの金線を用いる。 [Wire bonding process]
Next, for example, a plurality of electrode pads formed on the main surface of the semiconductor chip and a bonding electrode disposed on the upper surface of the package substrate are bonded to a conductive member (bonding) by a nail head bonding method using ultrasonic vibration combined with thermocompression bonding. Each is electrically connected via a wire (see FIG. 6 described later). As the bonding wire, for example, a gold wire of 15 to 20 μmφ is used.

［モールド工程］
≪ステップ１：基材（以下、参照。）の装着≫
まず、図５（ａ）および（ｂ）並びに図６に示すように、下型キャビティブロックＣＶａの表面上に、被封止物である複数の半導体チップＳＣが搭載されたパッケージ基板ＰＳ（以下、基材ＳＴという。）を位置決めして、載置する。次に、下金型ＤＭの温度を、例えば１７５℃程度に設定したまま、基材ＳＴに対して２０秒程度のプレヒート処置を施す。この処理は、熱による基材ＳＴの変形を落ち着かせるなどの目的のために行われる。次に、下金型ＤＭおよび上金型ＵＭの温度を、例えば１７５℃程度に設定した状態で、基材ＳＴと下型キャビティＣＡＶａの表面とを密着させる。 [Molding process]
«Step 1: Mounting of base material (refer to below)»
First, as shown in FIGS. 5 (a) and 5 (b) and FIG. 6, a package substrate PS (hereinafter, referred to as a plurality of semiconductor chips SC) to be sealed is mounted on the surface of the lower mold cavity block CVa. A base material ST) is positioned and placed. Next, preheating treatment for about 20 seconds is performed on the base material ST while the temperature of the lower mold DM is set at, for example, about 175 ° C. This process is performed for the purpose of calming the deformation of the substrate ST due to heat. Next, the base material ST and the surface of the lower mold cavity CAVa are brought into close contact with each other in a state where the temperatures of the lower mold DM and the upper mold UM are set to about 175 ° C., for example.

ここでは、下型キャビティブロックＣＶａは、下型ユニットＤＭＵに対して初期位置となっている。すなわち、初期位置において、下型キャビティブロックＣＶａの表面と、ポットブロックＰＢの上面とは同一平面にある。また、初期位置において、下型キャビティブロックＣＶａの側面とポットブロックＰＢの側面との間に、隙間が形成できないように、下型キャビティブロックＣＶａおよびポットブロックＰＢは設計されている。さらに、初期位置において、下型キャビティブロックＣＶａの側面とパッケージ基板ＰＳの側面とが上下方向（下型キャビティブロックＣＶａおよびパッケージ基板ＰＳの厚さ方向）において同一面となるように、基材ＳＴは下型キャビティブロックＣＶａの表面上に載置されている。   Here, the lower mold cavity block CVa is in an initial position with respect to the lower mold unit DMU. That is, at the initial position, the surface of the lower mold cavity block CVa and the upper surface of the pot block PB are in the same plane. Further, in the initial position, the lower mold cavity block CVa and the pot block PB are designed so that a gap cannot be formed between the side surface of the lower mold cavity block CVa and the side surface of the pot block PB. Further, at the initial position, the base material ST is arranged such that the side surface of the lower mold cavity block CVa and the side surface of the package substrate PS are flush with each other in the vertical direction (thickness direction of the lower mold cavity block CVa and the package substrate PS). It is mounted on the surface of the lower mold cavity block CVa.

≪ステップ２：型締め≫
次に、図７（ａ）および（ｂ）に示すように、下型ユニットＤＭＵ全体を型締め位置まで上方に移動（上昇）させる。そして、基材ＳＴのうち、半導体チップＳＣが搭載されておらず、かつ、導電性部材ＢＷが接続されていないパッケージ基板ＰＳの外周部の上面と、上金型ＵＭの上型キャビティブロックＣＶｂとを接触させて、上金型ＵＭと下金型ＤＭとを型締めする。これにより、上金型ＵＭと下金型ＤＭとの間にモールド樹脂が漏れることのないように隙間なくパッケージ基板ＰＳを挟み、基材ＳＴを固定する。この時、型締め力（クランプ力、クランプ圧）により圧縮バネＣＳが圧縮されて、適正な圧力を維持したまま、下型ユニットＤＭＵに対して下型キャビティブロックＣＶａおよび基材ＳＴが適切な位置まで下方に移動（下降）する。下型キャビティブロックＣＶａは、パッケージ基板ＰＳの厚さ分、下方に移動する。 ≪Step 2: Clamping≫
Next, as shown in FIGS. 7A and 7B, the entire lower mold unit DMU is moved (raised) upward to the mold clamping position. Of the substrate ST, the upper surface of the outer peripheral portion of the package substrate PS on which the semiconductor chip SC is not mounted and the conductive member BW is not connected, and the upper mold block CVb of the upper mold UM And the upper mold UM and the lower mold DM are clamped. As a result, the package substrate PS is sandwiched between the upper mold UM and the lower mold DM so that the mold resin does not leak, and the base material ST is fixed. At this time, the compression spring CS is compressed by the clamping force (clamping force, clamping pressure), and the lower die cavity block CVa and the base material ST are appropriately positioned with respect to the lower die unit DMU while maintaining an appropriate pressure. Move downward (down). The lower mold cavity block CVa moves downward by the thickness of the package substrate PS.

ここで、下型ユニットＤＭＵに対して下型キャビティブロックＣＶａおよび基材ＳＴが適切な位置まで下方に移動した場合でも、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間には隙間ができないように、下型キャビティブロックＣＶａは設計されている。   Here, even when the lower mold cavity block CVa and the base material ST move downward to an appropriate position with respect to the lower mold unit DMU, there is a gap between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa. The lower mold cavity block CVa is designed so that the

また、前述したように、初期位置において、下型キャビティブロックＣＶａの側面とパッケージ基板ＰＳの側面とが上下方向において同一面となるように、基材ＳＴは下型キャビティブロックＣＶａの表面上に載置されている。   Further, as described above, the base material ST is placed on the surface of the lower mold cavity block CVa so that the side surface of the lower mold cavity block CVa and the side surface of the package substrate PS are flush with each other at the initial position. Is placed.

≪ステップ３：下型キャビティの固定≫
次に、上型キャビティＣＡＶｂ内にモールド樹脂を注入する際の圧力または上型キャビティＣＡＶｂ内に注入されたモールド樹脂に加える圧力などによって下型キャビティブロックＣＶａが下方に移動（下降）しないように、下型キャビティブロックＣＶａを固定する。 ≪Step 3: Fixing the lower mold cavity≫
Next, the lower mold cavity block CVa is not moved downward (lowered) due to the pressure applied when the mold resin is injected into the upper mold cavity CAVb or the pressure applied to the mold resin injected into the upper mold cavity CAVb. The lower mold cavity block CVa is fixed.

次に、例えば高周波加熱機などで予備加熱され、ある程度軟化したタブレットをポットＰＯ内に投入する。タブレットは、例えばエポキシ系樹脂または低分子系樹脂を圧力で固めたものが用いられる。   Next, for example, a tablet preliminarily heated by a high-frequency heater or the like and softened to some extent is put into the pot PO. As the tablet, for example, an epoxy resin or a low molecular weight resin hardened by pressure is used.

≪ステップ４：樹脂封止≫
次に、図８（ａ）および（ｂ）並びに図９に示すように、プランジャＰＬを上昇させてタブレットを押圧し、タブレットが溶融し、液体化したモールド樹脂ＭＴＡをポットＰＯから加圧移動させる。そして、下型キャビティブロックＣＶａを固定した状態で、カルブロックＣＢからランナＲＡおよびゲートＧＡを介して上型キャビティＣＡＶｂ内へモールド樹脂ＭＴＡを注入する。 ≪Step 4: Resin sealing≫
Next, as shown in FIGS. 8A and 8B and FIG. 9, the plunger PL is raised to press the tablet, the tablet melts, and the liquefied mold resin MTA is pressurized and moved from the pot PO. . Then, with the lower mold cavity block CVa fixed, the mold resin MTA is injected from the cull block CB into the upper mold cavity CAVb through the runner RA and the gate GA.

これにより、図１０（ａ）および（ｂ）並びに図１１に示すように、パッケージ基板ＰＳの上面に搭載された複数の半導体チップＳＣおよび複数の導電性部材ＢＷなどが一括して封止されて、パッケージ基板ＰＳの上面側に複数の半導体チップを内包する一体的な立体形状の樹脂封止体ＲＳが形成される。その後、モールド樹脂ＭＴＡが硬化するまで、例えば９０秒程度のキュアを行う。   As a result, as shown in FIGS. 10A and 10B and FIG. 11, the plurality of semiconductor chips SC and the plurality of conductive members BW mounted on the upper surface of the package substrate PS are collectively sealed. An integral three-dimensional resin sealing body RS including a plurality of semiconductor chips is formed on the upper surface side of the package substrate PS. Thereafter, curing is performed for about 90 seconds until the mold resin MTA is cured.

ここで、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間には隙間ができないように、下型キャビティブロックＣＶａは設計されている。また、ポットブロックＰＢの側面とパッケージ基板ＰＳの側面との間にも隙間ができないように、基材ＳＴは下型キャビティブロックＣＶａの表面上に載置されている。これにより、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間およびポットブロックＰＢの側面とパッケージ基板ＰＳの側面との間には、モールド樹脂ＭＴＡは入り込まない。   Here, the lower mold cavity block CVa is designed so that there is no gap between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa. Further, the base material ST is placed on the surface of the lower mold cavity block CVa so that there is no gap between the side surface of the pot block PB and the side surface of the package substrate PS. Thereby, the mold resin MTA does not enter between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa and between the side surface of the pot block PB and the side surface of the package substrate PS.

≪ステップ５：型開きおよび下型キャビティブロックを初期位置に戻す動作≫
次に、図１２（ａ）および（ｂ）に示すように、所定時間経過後、モールド樹脂ＭＴＡが硬化して樹脂封止体ＲＳが形成されたところで、下型ユニットＤＭＵ全体を型締め位置から下降させることにより、上金型ＵＭと下型ユニットＤＭＵとを開く。 << Step 5: Opening the mold and returning the lower mold cavity block to the initial position >>
Next, as shown in FIGS. 12A and 12B, after a predetermined time has elapsed, when the mold resin MTA is cured and the resin sealing body RS is formed, the entire lower mold unit DMU is moved from the mold clamping position. By lowering, the upper mold UM and the lower mold unit DMU are opened.

さらに、下型キャビティブロックＣＶａを初期位置に戻す。下型キャビティブロックＣＶａを初期位置に戻す動作は、押し上げピンＵＰの先端面が下型キャビティブロックＣＶａの裏面に接触し、下型キャビティブロックＣＶａが押し上げピンＵＰによって支持されるまで、下型ユニットＤＭＵを下方に移動させる。   Further, the lower mold cavity block CVa is returned to the initial position. The operation of returning the lower mold cavity block CVa to the initial position is performed by moving the lower mold unit DMU until the tip surface of the push-up pin UP comes into contact with the back surface of the lower mold cavity block CVa and the lower mold cavity block CVa is supported by the push-up pin UP. Is moved downward.

ここで、押し上げピンＵＰの先端面、および下型キャビティブロックＣＶａの裏面のうち、押し上げピンＵＰの先端面が接触する面は、ポットブロックＰＢ側に向かうに従い、下型キャビティブロックＣＶａのパッケージ基板を搭載する表面との距離が長くなるように、傾斜している。これにより、下型キャビティブロックＣＶａは、僅かにポットブロックＰＢ側へ移動しながら上昇するので、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間には隙間は形成されない。   Here, of the front end surface of the push-up pin UP and the back surface of the lower mold cavity block CVa, the surface with which the front end surface of the push-up pin UP comes into contact with the package substrate of the lower mold cavity block CVa toward the pot block PB side. It is inclined so that the distance from the surface to be mounted becomes long. As a result, the lower mold cavity block CVa rises while slightly moving to the pot block PB side, so that no gap is formed between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa.

通常は、モールド金型の摺動性およびモールド金型の加工ばらつきなどを考慮して、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間には予め僅かに隙間ができるように、下型キャビティブロックＣＶａは設計されている。このため、例えば型締めの際（前述のステップ２）、下型キャビティブロックＣＶａが下降すると共に、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間に隙間が形成される場合がある。   Usually, considering the slidability of the mold and the processing variation of the mold, etc., a slight gap is created in advance between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa. The lower mold cavity block CVa is designed. For this reason, for example, during mold clamping (step 2 described above), the lower mold cavity block CVa is lowered, and a gap may be formed between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa. .

また、基材ＳＴを下型キャビティブロックＣＶａの表面上に載置する際のばらつきまたはパッケージ基板ＰＳの加工ばらつきなどにより、ポットブロックＰＢの側面とパッケージ基板ＰＳの側面との間に隙間が形成される場合がある。   Further, a gap is formed between the side surface of the pot block PB and the side surface of the package substrate PS due to variations in mounting the base material ST on the surface of the lower mold cavity block CVa or variations in processing of the package substrate PS. There are cases.

しかし、仮に、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間に隙間が形成される、またはポットブロックＰＢの側面とパッケージ基板ＰＳの側面との間に隙間が形成されて、モールド樹脂ＭＴＡが上記隙間に入っても、下型キャビティブロックＣＶａを初期位置に戻す際に、上記隙間からモールド樹脂ＭＴＡを掻きだすことができる。これにより、上記隙間に付着したモールド樹脂ＭＴＡを除去して、下型キャビティブロックＣＶａを初期位置に戻すことができる。   However, if a gap is formed between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa, or a gap is formed between the side surface of the pot block PB and the side surface of the package substrate PS, Even if the resin MTA enters the gap, the mold resin MTA can be scraped from the gap when returning the lower mold cavity block CVa to the initial position. Thereby, the mold resin MTA adhering to the gap can be removed, and the lower mold cavity block CVa can be returned to the initial position.

≪ステップ６：基材を引き離す動作≫
次に、図１３に示すように、複数のエジェクトピンＥＪＰを上昇させて、複数のイジェクタピンＥＪＰの一端側を下型キャビティブロックＣＶａの表面から突き出す。さらに、複数のエジェクトピンＥＪＰを上昇させて、下型キャビティブロックＣＶａに装着された被封止物である基材（複数の半導体チップＳＣを樹脂封止したパッケージ基板ＰＳ）ＳＴを上方へ押し上げて、下型キャビティブロックＣＶａから基材（複数の半導体チップＳＣを樹脂封止したパッケージ基板ＰＳ）ＳＴを引き離す。 ≪Step 6: Operation to separate the base material≫
Next, as shown in FIG. 13, the plurality of ejector pins EJP are raised, and one end sides of the plurality of ejector pins EJP are projected from the surface of the lower mold cavity block CVa. Further, the plurality of eject pins EJP are raised to push upward the base material (package substrate PS in which a plurality of semiconductor chips SC are resin-sealed) ST mounted on the lower cavity block CVa. Then, the base material (package substrate PS in which a plurality of semiconductor chips SC are sealed with resin) ST is separated from the lower mold cavity block CVa.

≪ステップ７：基材の取り出し≫
次に、下型キャビティブロックＣＶａから引き離された基材ＳＴをモールド金型から取り出す。その後、下型ユニットＤＭＵ全体を基材ＳＴの取り出し位置から上昇させることにより、モールド金型を初期の状態に戻す。 << Step 7: Removal of Substrate >>
Next, the base material ST separated from the lower mold cavity block CVa is taken out from the mold. Thereafter, the entire lower mold unit DMU is raised from the take-out position of the base material ST to return the mold to the initial state.

［切断工程］
次に、パッケージ基板ＰＳの上面側に複数の半導体チップＳＣを内包する一体的な樹脂封止体ＲＳをモールディング装置から取り出し、切断工程において個々の半導体装置（ＢＧＡパッケージ）に切り分ける。その後、仕上がった半導体装置は製品規格によって選別され、検査工程を経た後、良品と判断された半導体装置は出荷される。 [Cutting process]
Next, an integral resin sealing body RS including a plurality of semiconductor chips SC on the upper surface side of the package substrate PS is taken out from the molding device and cut into individual semiconductor devices (BGA packages) in a cutting process. Thereafter, the finished semiconductor devices are sorted according to product standards, and after undergoing an inspection process, semiconductor devices that are determined to be non-defective are shipped.

このように、本実施の形態によれば、押し上げピンＵＰの先端面、および下型キャビティブロックＣＶａの裏面のうち、押し上げピンＵＰの先端面が接触する面は、ポットブロックＰＢ側に向かうに従い、下型キャビティブロックＣＶａのパッケージ基板ＰＳを搭載する表面との距離が長くなるように、傾斜している。これにより、樹脂封止後に、下型キャビティブロックＣＶａを初期位置に戻す際、下型キャビティブロックＣＶａを僅かにポットブロックＰＢ側へ移動しながら上昇させることができる。従って、下型キャビティブロックＣＶａの側面とポットブロックＰＢの側面との間に隙間を形成することなく、下型キャビティブロックＣＶａの表面とポットブロックＰＢの上面とが同一平面にある、すなわち初期位置に、下型キャビティブロックＣＶａを戻すことができる。   Thus, according to the present embodiment, the surface of the tip surface of the push-up pin UP and the back surface of the lower mold cavity block CVa that the tip surface of the push-up pin UP comes in contact with the pot block PB side, The lower mold cavity block CVa is inclined so that the distance from the surface on which the package substrate PS is mounted becomes longer. Thus, when the lower mold cavity block CVa is returned to the initial position after resin sealing, the lower mold cavity block CVa can be raised while slightly moving to the pot block PB side. Accordingly, without forming a gap between the side surface of the lower mold cavity block CVa and the side surface of the pot block PB, the surface of the lower mold cavity block CVa and the upper surface of the pot block PB are in the same plane, that is, at the initial position. The lower mold cavity block CVa can be returned.

樹脂封止後に、下型キャビティブロックＣＶａが適正な位置に戻ることができるので、パッケージ基板ＰＳの側面に樹脂バリが発生する問題を解決することができる。また、下型キャビティブリックＣＶａの側面とポットブロックＰＢの側面との間に隙間が形成され、この隙間にモールド樹脂ＭＴＡが入り込み、ポットブロックＰＢの側面にモールド樹脂ＭＴＡが付着しても、下型キャビティブロックＣＶａが初期位置に戻る際に、上記隙間から掻きだされるので、ポットブロックＰＢの側面に樹脂バリが発生する問題を解決することができる。   After the resin sealing, the lower mold cavity block CVa can be returned to an appropriate position, so that the problem that a resin burr is generated on the side surface of the package substrate PS can be solved. Further, even if a gap is formed between the side surface of the lower mold cavity brick CVa and the side surface of the pot block PB, the mold resin MTA enters the gap, and the mold resin MTA adheres to the side surface of the pot block PB. When the cavity block CVa returns to the initial position, the cavity block CVa is scraped from the gap, so that the problem that resin burrs are generated on the side surface of the pot block PB can be solved.

さらに、異物の原因となる樹脂バリの飛散がなくなるので、例えば半導体装置ＳＤの半田ボールＳＢの接合部に樹脂バリが付着することによる欠陥不良品の製造が減り、半導体装置の信頼性および生産性の向上を図ることができる。   Further, since there is no scattering of resin burrs that cause foreign substances, for example, the production of defective products due to adhesion of resin burrs to the joints of solder balls SB of the semiconductor device SD is reduced, and the reliability and productivity of the semiconductor device are reduced. Can be improved.

（変形例）
本実施の形態の変形例を図１４および図１５を用いて説明する。図１４は、モールディング装置の変形例を示す要部断面図である。図１５は、モールド工程におけるモールディング装置の変形例の状態を説明する、下型ユニットの一部を拡大して示す要部断面図である。 (Modification)
A modification of the present embodiment will be described with reference to FIGS. FIG. 14 is a cross-sectional view of an essential part showing a modification of the molding apparatus. FIG. 15 is an essential part cross-sectional view illustrating a state of a modified example of the molding apparatus in the molding process in which a part of the lower mold unit is enlarged.

前述した実施の形態と相違する点について、以下に説明する。   Differences from the above-described embodiment will be described below.

前述した実施の形態によるモールディング装置では、図２に示したように、押し上げピンＵＰの先端面、および下型キャビティブロックＣＶａの裏面のうち、押し上げピンＵＰの先端面が接触する面が、ポットブロックＰＢ側に向かうに従い、下型キャビティブロックＣＶａのパッケージ基板ＰＳを搭載する表面との距離が長くなるように、傾斜している。   In the molding apparatus according to the above-described embodiment, as shown in FIG. 2, the surface of the tip surface of the push-up pin UP and the back surface of the lower mold cavity block CVa that is in contact with the tip surface of the push-up pin UP is the pot block. As it goes to the PB side, the lower mold cavity block CVa is inclined so that the distance from the surface on which the package substrate PS is mounted becomes longer.

これに対して、変形例によるモールディング装置では、図１４および図１５に示すように、押し上げピンＵＰの先端面、および下型キャビティブロックＣＶａの裏面のうち、押し上げピンＵＰの先端面が接触する面は、下型キャビティブロックＣＶａのパッケージ基板ＰＳを搭載する表面とほぼ平行となるように形成されている。そして、下型キャビティブロックＣＶａに形成された押し上げピンＵＰを挿入する孔（以下、押し上げピン用の孔と記す）ＵＰＨの側面の一部が傾斜している。その他の構造は、前述した実施の形態によるモールディング装置とほぼ同じである。上記押し上げピン用の孔ＵＰＨは、下型キャビティブロックＣＶａをその厚さ方向に貫通することなく、下型キャビティブロックＣＶａの裏面側に形成されている。   On the other hand, in the molding apparatus according to the modified example, as shown in FIGS. 14 and 15, the surface of the tip surface of the push-up pin UP and the surface of the bottom surface of the lower mold cavity block CVa that contacts the tip surface of the push-up pin UP. Is formed so as to be substantially parallel to the surface on which the package substrate PS of the lower mold cavity block CVa is mounted. A part of a side surface of a hole (hereinafter referred to as a hole for a push-up pin) UPH into which the push-up pin UP is formed in the lower mold cavity block CVa is inclined. Other structures are almost the same as those of the molding apparatus according to the above-described embodiment. The push-up pin hole UPH is formed on the back side of the lower mold cavity block CVa without penetrating the lower mold cavity block CVa in the thickness direction.

具体的には、図１５に示すように、樹脂封止体ＲＳが形成されたところで、下型ユニットＤＭＵ全体を型締め位置から下降させることにより、上金型ＵＭと下型ユニットＤＭＵとを開く。その後、下型キャビティブロックＣＶａを初期位置に戻し、さらに、複数のエジェクトピンＥＪＰを用いて、下型キャビティブロックＣＶａから基材（複数の半導体チップＳＣを樹脂封止したパッケージ基板ＰＳ）ＳＴを引き離す。   Specifically, as shown in FIG. 15, when the resin sealing body RS is formed, the upper mold UM and the lower mold unit DMU are opened by lowering the entire lower mold unit DMU from the mold clamping position. . Thereafter, the lower die cavity block CVa is returned to the initial position, and further, the base material (package substrate PS in which a plurality of semiconductor chips SC are sealed with resin) ST is separated from the lower die cavity block CVa using a plurality of eject pins EJP. .

下型キャビティブロックＣＶａを初期位置に戻す動作は、押し上げピンＵＰの先端面が、下型キャビティブロックＣＶａに形成された押し上げピン用の孔ＵＰＨの側面に接触し、下型キャビティブロックＣＶａが押し上げピンＵＰによって支持されるまで、下型ユニットＤＭＵを下方に移動させる。   In the operation of returning the lower mold cavity block CVa to the initial position, the tip surface of the push-up pin UP comes into contact with the side surface of the push-up pin hole UPH formed in the lower mold cavity block CVa, and the lower mold cavity block CVa is pushed up. The lower mold unit DMU is moved downward until it is supported by UP.

ここで、押し上げピン用の孔ＵＰＨの側面は、上方（下型キャビティパッケージＣＶａのパッケージ基板ＰＳを搭載する表面側）に向かうに従い、押し上げピン用の孔ＵＰＨの径が小さくなるように傾斜した部分を有している。押し上げピンＵＰが押し上げピン用の孔ＵＰＨ内を上方に移動すると、押し上げピンＵＰのポットブロックＰＢ側の側面と押し上げピン用の孔ＵＰＨのポットブロックＰＢ側の側面とが接触し、押し上げピンＵＰを基準として、下型キャビティブロックＣＶａがポットブロックＰＢ方向に移動（図１５の左図に示す寸法Ｌ）する。これにより、ポットブロックＰＢの側面と下型キャビティブロックＣＶａの側面との間に隙間が形成できないようにすることができる。   Here, the side surface of the push-up pin hole UPH is inclined so that the diameter of the push-up pin hole UPH becomes smaller toward the upper side (the surface side on which the package substrate PS of the lower mold cavity package CVa is mounted). have. When the push-up pin UP moves upward in the hole UPH for the push-up pin, the side surface on the pot block PB side of the push-up pin UP comes into contact with the side surface on the pot block PB side of the hole UPH for the push-up pin. As a reference, the lower mold cavity block CVa moves in the pot block PB direction (dimension L shown in the left diagram of FIG. 15). Accordingly, it is possible to prevent a gap from being formed between the side surface of the pot block PB and the side surface of the lower mold cavity block CVa.

また、押し上げピン用の孔ＵＰＨの側面に傾斜した部分を有することにより、押し上げピンＵＰが押し上げピン用の孔ＵＰＨに入り易くなるという効果もある。   Further, by having the inclined portion on the side surface of the push-up pin hole UPH, there is an effect that the push-up pin UP easily enters the push-up pin hole UPH.

このように、本実施の形態の変形例によれば、前述の実施の形態とほぼ同様に、下型キャビティブロックＣＶａを初期位置に戻すことができる。また、樹脂バリの発生および飛散がなくなるので、例えば半導体装置の半田ボールの接合部に樹脂バリが付着することによる欠陥不良品の製造が減り、半導体装置の信頼性および生産性の向上を図ることができる。   Thus, according to the modification of the present embodiment, the lower mold cavity block CVa can be returned to the initial position in substantially the same manner as in the previous embodiment. In addition, since the generation and scattering of resin burrs are eliminated, the production of defective products due to the resin burrs adhering to, for example, solder ball joints of semiconductor devices is reduced, and the reliability and productivity of semiconductor devices are improved. Can do.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

前記実施の形態では、ＢＧＡパッケージを例に挙げて説明したが、これに限定されるものではない。本発明の主要な特徴は、配線部材としてリードフレームを用いるＱＦＰ（Quad Flat Package）のモールド工程、ＱＦＮ（Quad Flat No lead package）のモールド工程などに適用してもよい。   In the above embodiment, the BGA package has been described as an example, but the present invention is not limited to this. The main features of the present invention may be applied to a QFP (Quad Flat Package) molding process using a lead frame as a wiring member, a QFN (Quad Flat No lead package) molding process, and the like.

ＡＢ ダイボンド材（接着剤）
ＢＥ ボンディング電極
ＢＬ バンプ・ランド（電極パッド）
ＢＷ 導電性部材（ボンディングワイヤ）
ＣＡＶａ 下型キャビティ
ＣＡＶｂ 上型キャビティ
ＣＢ カルブロック
ＣＨ 接続孔
ＣＬ１，ＣＬ２，ＣＬ３，ＣＬ４ 配線層
ＣＭ 導電性部材
ＣＯ コア材
ＣＳ 圧縮バネ
ＣＶａ 下型キャビティブロック
ＣＶｂ 上型キャビティブロック
ＤＭ 下金型（第１金型）
ＤＭＵ 下型ユニット
ＥＪＰ エジェクトピン
ＥＰ 電極パッド
ＧＡ ゲート
ＩＬ１，ＩＬ２ 絶縁層
ＭＢ１，ＭＢ２，ＭＢ３，ＭＢ４ 樹脂バリ
ＭＴＡ モールド樹脂
ＰＢ ポットブロック
ＰＦ１，ＰＦ２ 保護膜
ＰＬ プランジャ
ＰＯ ポット
ＰＳ パッケージ基板（基板、配線基板）
ＰＳｘ 上面（表面）
ＰＳｙ 下面（裏面）
ＲＡ ランナ
ＲＳ 樹脂封止体（封止体）
ＳＢ 半田ボール（外部端子）
ＳＣ 半導体チップ
ＳＤ 半導体装置（ＢＧＡパッケージ）
ＳＴ 基材
ＴＨ 貫通孔（ビア）
ＵＭ 上金型（第２金型）
ＵＰ 押し上げピン
ＵＰＨ 押し上げピン用の孔 AB Die bond material (adhesive)
BE Bonding electrode BL Bump land (electrode pad)
BW conductive member (bonding wire)
CAVa Lower mold cavity CAVb Upper mold cavity CB Calblock CH Connection hole CL1, CL2, CL3, CL4 Wiring layer CM Conductive member CO Core material CS Compression spring CVa Lower mold cavity block CVb Upper mold cavity block DM Lower mold (first mold Mold)
DMU Lower mold unit EJP Eject pin EP Electrode pad GA Gate IL1, IL2 Insulating layer MB1, MB2, MB3, MB4 Resin burr MTA Mold resin PB Pot block PF1, PF2 Protective film PL Plunger PO Pot PS Package substrate (substrate, wiring substrate)
PSx Top surface (surface)
PSy bottom (back)
RA runner RS resin sealed body (sealed body)
SB solder ball (external terminal)
SC Semiconductor chip SD Semiconductor device (BGA package)
ST Substrate TH Through hole (via)
UM Upper mold (second mold)
UP Push-up pin UPH Hole for push-up pin

Claims (10)

以下の工程を含む半導体装置の製造方法：
（ａ）上型キャビティブロックを備える上金型と、下型キャビティブロックおよび押し上げピンを備える下金型と、樹脂を供給するポットを備えるポットブロックとを有するモールド金型を準備する工程；
（ｂ）基板の上面に搭載された半導体チップを準備する工程；
（ｃ）前記基板を前記下型キャビティブロックの表面上に配置する工程；
（ｄ）前記上型キャビティブロックの上型キャビティ内に前記半導体チップが位置するように、前記上金型と前記下金型とで前記基板を挟む工程；
（ｅ）前記ポットブロックの前記ポットから前記上型キャビティ内に前記樹脂を供給して、前記半導体チップを樹脂封止する工程；
（ｆ）前記押し上げピンを前記下型キャビティブロックの前記表面とは反対側の裏面に押し当てて、前記（ｄ）工程で沈み込んだ前記下型キャビティブロックを初期位置に戻す工程；
ここで、前記押し上げピンの先端面、および前記下型キャビティブロックの前記裏面のうち前記押し上げピンの前記先端面が接触する面は、前記ポット側に向かうに従って、前記下型キャビティブロックの前記表面との距離が長くなるように、傾斜している。 A semiconductor device manufacturing method including the following steps:
(A) preparing a mold mold having an upper mold including an upper mold cavity block, a lower mold including a lower mold cavity block and a push-up pin, and a pot block including a pot for supplying resin;
(B) preparing a semiconductor chip mounted on the upper surface of the substrate;
(C) placing the substrate on a surface of the lower mold cavity block;
(D) sandwiching the substrate between the upper mold and the lower mold so that the semiconductor chip is positioned in the upper mold cavity of the upper mold cavity block;
(E) supplying the resin from the pot of the pot block into the upper mold cavity and sealing the semiconductor chip with resin;
(F) pressing the push-up pin against the back surface of the lower mold cavity block opposite to the front surface, and returning the lower mold cavity block submerged in the step (d) to an initial position;
Here, the surface of the tip surface of the push-up pin and the back surface of the lower mold cavity block that the tip surface of the push-up pin comes into contact with the surface of the lower mold cavity block as it goes toward the pot side. It is inclined so that the distance becomes longer. 請求項１記載の半導体装置の製造方法において、
前記押し上げピンの先端面は、鏡面仕上げされている、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a tip surface of the push-up pin is mirror-finished. 請求項２記載の半導体装置の製造方法において、
前記押し上げピンの先端面の表面粗さは、十点平均粗さで３μｍ以下である、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 2.
The manufacturing method of a semiconductor device, wherein the surface roughness of the tip surface of the push-up pin is 3 μm or less in terms of 10-point average roughness. 請求項１記載の半導体装置の製造方法において、
前記押し上げピンの先端面に、めっき処理が施されている、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the tip surface of the push-up pin is plated. 請求項４記載の半導体装置の製造方法において、
前記押し上げピンの先端面に、硬質クロムメッキが施されている、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4,
A method of manufacturing a semiconductor device, wherein a hard chrome plating is applied to a tip surface of the push-up pin. 請求項１記載の半導体装置の製造方法において、
２以上の前記押し上げピンを前記下型キャビティブロックの前記裏面に押し当てる、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein two or more push-up pins are pressed against the back surface of the lower mold cavity block. 請求項１記載の半導体装置の製造方法において、
前記下型キャビティブロックの初期位置では、前記下型キャビティブロックの前記表面と前記ポットブロックの上面とが同一平面となる、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the surface of the lower mold cavity block and the upper surface of the pot block are flush with each other at an initial position of the lower mold cavity block. 以下の工程を含む半導体装置の製造方法：
（ａ）上型キャビティブロックを備える上金型と、下型キャビティブロックおよび押し上げピンを備える下金型と、樹脂を供給するポットを備えるポットブロックとを有するモールド金型を準備する工程；
（ｂ）基板の上面に搭載された半導体チップを準備する工程；
（ｃ）前記基板を前記下型キャビティブロックの表面上に配置する工程；
（ｄ）前記上型キャビティブロックの上型キャビティ内に前記半導体チップが位置するように、前記上金型と前記下金型とで前記基板を挟む工程；
（ｅ）前記ポットブロックの前記ポットから前記上型キャビティ内に前記樹脂を供給して、前記半導体チップを樹脂封止する工程；
（ｆ）前記押し上げピンを前記下型キャビティブロックの前記表面とは反対側の裏面に形成された孔に挿入し、前記孔の内壁に押し当てて、前記（ｄ）工程で沈み込んだ前記下型キャビティブロックを初期位置に戻す工程；
ここで、前記押し上げピンが挿入される前記孔の側面の一部は、前記下型キャビティブロックの前記裏面側から前記表面側へ向かうに従って、前記孔の径が小さくなる方向に、傾斜している。 A semiconductor device manufacturing method including the following steps:
(A) preparing a mold mold having an upper mold including an upper mold cavity block, a lower mold including a lower mold cavity block and a push-up pin, and a pot block including a pot for supplying resin;
(B) preparing a semiconductor chip mounted on the upper surface of the substrate;
(C) placing the substrate on a surface of the lower mold cavity block;
(D) sandwiching the substrate between the upper mold and the lower mold so that the semiconductor chip is positioned in the upper mold cavity of the upper mold cavity block;
(E) supplying the resin from the pot of the pot block into the upper mold cavity and sealing the semiconductor chip with resin;
(F) The push-up pin is inserted into a hole formed on the back surface opposite to the front surface of the lower mold cavity block, pressed against the inner wall of the hole, and the lower part sunk in the step (d) Returning the mold cavity block to the initial position;
Here, a part of the side surface of the hole into which the push-up pin is inserted is inclined in a direction in which the diameter of the hole decreases from the back surface side to the front surface side of the lower mold cavity block. . 請求項８記載の半導体装置の製造方法において、
２以上の前記押し上げピンを前記下型キャビティブロックに形成された２以上の前記孔にそれぞれ挿入する、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8.
A method of manufacturing a semiconductor device, wherein two or more push-up pins are respectively inserted into two or more holes formed in the lower mold cavity block. 請求項８記載の半導体装置の製造方法において、
前記下型キャビティブロックの初期位置では、前記下型キャビティブロックの前記表面と前記ポットブロックの上面とが同一平面となる、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8.
A method of manufacturing a semiconductor device, wherein the surface of the lower mold cavity block and the upper surface of the pot block are flush with each other at an initial position of the lower mold cavity block.
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