JP6420450B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a solid-state imaging element.

  In order to capture a high-quality moving image using a digital camera, it is important to perform automatic focus detection at high speed and with high accuracy. In recent years, a digital camera has been developed that uses a solid-state imaging device having a plurality of pixels each having two photoelectric conversion means and performs automatic focus adjustment by an image plane phase difference detection method.

  Regarding providing two photodiodes in one pixel, Patent Document 1 (JP 2013-106194 A), Patent Document 2 (JP 2008-193527 A), and Patent Document 3 (JP 2013 2013). -041890). In these patent documents, the gate electrode provided between the two photodiodes does not constitute a transfer transistor used for reading the charge in the photodiode.

JP 2013-106194 A JP 2008-193527 A JP 2013-041890 A

  In order to realize moving image capturing for a long time, it is necessary to stably supply power consumption required by processing enormous data from moving images. For this purpose, it is important to reduce the power consumption of the entire camera system.

  When a plurality of photodiodes as photoelectric conversion means are formed in one pixel, when transferring the charge obtained by imaging from the photodiode, the transfer transistor adjacent to each photodiode in the pixel is turned on. It is possible to do. In this case, since it is necessary to turn on each of the plurality of transfer transistors corresponding to the plurality of photodiodes, there is a problem that power consumption in the imaging operation increases by supplying a potential to each gate electrode of the plurality of transfer transistors. Occurs.

  Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment includes a first transfer transistor that configures a solid-state imaging device and reads charge in the first photodiode to a floating diffusion capacitor in a pixel having the first and second photodiodes, And a transfer transistor that combines the respective charges of the first and second photodiodes and reads them out to the floating diffusion capacitance portion.

  According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved. In particular, power saving of the solid-state image sensor can be realized.

1 is a schematic diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram illustrating a semiconductor device according to a first embodiment of the present invention. 2 is a plan layout showing the semiconductor device according to the first embodiment of the present invention; It is sectional drawing in the AA of FIG. 4 is a plan layout showing a semiconductor device according to a second embodiment of the present invention. It is sectional drawing in the BB line of FIG. It is a circuit diagram which shows the semiconductor device which is a comparative example. It is a plane layout which shows the semiconductor device which is a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
The semiconductor device of the present embodiment will be described below with reference to FIGS. The semiconductor device according to the present embodiment relates to a solid-state image sensor, and particularly relates to a solid-state image sensor having a plurality of photodiodes in one pixel.

  FIG. 1 is a schematic diagram showing a configuration of a solid-state imaging device according to the present embodiment. The solid-state imaging device, which is a semiconductor device of the present embodiment, is a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and as shown in FIG. 1, a pixel array unit PEA, readout circuits CC1 and CC2, and an output circuit OC. A row selection circuit RC, a control circuit COC, and a memory circuit MC.

  A plurality of pixels PE are arranged in a matrix in the pixel array unit PEA. That is, a plurality of pixels PE are arranged in the X-axis direction and the Y-axis direction on the upper surface of the semiconductor substrate constituting the solid-state imaging device. The periphery of the pixel PE is surrounded by an element isolation region (element isolation structure). The X-axis direction shown in FIG. 1 is a direction along the main surface of the semiconductor substrate that constitutes the solid-state imaging device, and is along the row direction in which the pixels PE are arranged. Further, the Y-axis direction that is along the main surface of the semiconductor substrate and is orthogonal to the X-axis direction is a direction along the column direction in which the pixels PE are arranged. That is, the pixels PE are arranged in a matrix.

  Each of the plurality of pixels PE generates a signal corresponding to the intensity of the irradiated light. The row selection circuit RC selects a plurality of pixels PE in units of rows. The pixel PE selected by the row selection circuit RC outputs the generated signal to an output line OL (see FIG. 2) described later. The readout circuits CC1 and CC2 are arranged to face each other in the Y axis direction so as to sandwich the pixel array portion PEA. Each of the readout circuits CC1 and CC2 reads out a signal output from the pixel PE to the output line OL and outputs it to the output circuit OC. The memory circuit MC is a memory unit that temporarily stores the signal output from the output line OL.

  The readout circuit CC1 reads out the signal of the half pixel PE on the readout circuit CC1 side among the plurality of pixels PE, and the readout circuit CC2 reads out the signal of the remaining half pixel PE on the readout circuit CC2 side. The output circuit OC outputs the signal of the pixel PE read by the readout circuits CC1 and CC2 to the outside of the solid-state imaging device. The control circuit COC comprehensively manages the operation of the entire solid-state image sensor and controls the operation of other components of the solid-state image sensor. The memory circuit MC is used to measure the magnitude of electric charge output from each of the two photodiodes by storing a signal output from one of the two photodiodes in the pixel PE. It is done.

  Next, FIG. 2 shows a circuit diagram of one pixel. Each of the plurality of pixels PE shown in FIG. 1 has the circuit shown in FIG. As shown in FIG. 2, the pixel transfers photodiodes PD1 and PD2 that perform photoelectric conversion, a transfer transistor TX1 that transfers charges generated in the photodiode PD1, and charges generated in each of the photodiodes PD1 and PD2. A transfer transistor TX2. The pixel also includes a floating diffusion capacitor unit FD that accumulates charges transferred from the transfer transistors TX1 and TX2, and an amplification transistor AMI that amplifies the potential of the floating diffusion capacitor unit FD. The pixel further includes a selection transistor SEL for selecting whether to output the potential amplified by the amplification transistor AMI to the output line OL connected to one of the readout circuits CC1 and CC2 (see FIG. 1), and the photodiode PD1. And a reset transistor RST for initializing the potential of the cathode of PD2 and the floating diffusion capacitance portion FD to a predetermined potential. Each of the transfer transistors TX1, TX2, the reset transistor RST, the amplification transistor AMI, and the selection transistor SEL is, for example, an N-type MOS transistor.

  A ground potential GND that is a negative power supply potential is applied to the anodes of the photodiodes PD1 and PD2. The cathode of the photodiode PD2 is connected to the source of the transfer transistor TX2. The cathode of the photodiode PD1 is connected to the sources of the transfer transistors TX1 and TX2. The floating diffusion capacitance unit FD serving as a charge detection unit is connected to the drains of the transfer transistors TX1 and TX2, the source of the reset transistor RST, and the gate of the amplification transistor AMI.

  The positive power supply potential VCC is applied to the drain of the reset transistor RST and the drain of the amplification transistor AMI. The source of the amplification transistor AMI is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the output line OL connected to one of the read circuits CC1 and CC2.

  Here, the transfer transistor TX2 uses the photodiode PD1 as a source region, the transfer transistor TX3 using the floating diffusion capacitor FD as a drain region, and the transfer using the photodiode PD2 as a source region and the floating diffusion capacitor FD as a drain region. And a transistor TX4. That is, each of the transfer transistors TX3 and TX4 shares the gate electrode and the drain region.

  In other words, the photodiode PD2 is connected to the floating diffusion capacitor portion FD via the transfer transistor TX2, that is, the transfer transistor TX4. On the other hand, the photodiode PD1 is connected to the floating diffusion capacitor unit FD via the transfer transistor TX1, and is connected to the floating diffusion capacitor unit FD via the transfer transistor TX2, that is, the transfer transistor TX3. That is, the transfer transistors TX1 and TX2 are connected in parallel between the photodiode PD1 and the floating diffusion capacitor portion FD.

  In addition, the gate electrodes of the transfer transistors TX3 and TX4 are electrically connected to each other. Therefore, when a predetermined voltage is applied to the gate electrode of the transfer transistor TX2 to turn on the gate electrode, both the transfer transistors TX3 and TX4 are turned on. Therefore, when the transfer transistor TX2 is turned on, the charges generated in the photodiodes PD1 and PD2 are combined into one and transferred to the floating diffusion capacitor unit FD. That is, the transfer transistor TX2 is an element that combines the charges generated in the photodiodes PD1 and PD2 into one, that is, adds them and outputs the combined charges to the floating diffusion capacitance unit FD.

  Further, here, the charge of the photodiode PD2 cannot be transferred to the floating diffusion capacitor portion FD unless the transfer transistor TX2 is turned on, whereas the charge of the photodiode PD1 is transferred to either the transfer transistor TX1 or TX2. Can be transferred to the floating diffusion capacitor portion FD. Therefore, if the transfer transistor TX2 is turned on without turning on the transfer transistor TX1, the charges of both the photodiodes PD1 and PD2 can be read. Thereby, the respective charges of the photodiodes PD1 and PD2 are initialized, that is, reset.

  Next, FIG. 3 shows a planar layout of the pixel PE. FIG. 4 is a cross-sectional view taken along line AA in FIG. 3 is an enlarged plan view showing one pixel PE of the pixel array unit PEA shown in FIG. FIG. 3 shows a photodiode and its peripheral transistors, etc., but illustration of interlayer insulating films, wirings, microlenses, and the like provided thereon is omitted.

  As shown in FIG. 3, most of the area of one pixel PE is occupied by the light receiving portion in which the photodiodes PD1 and PD2 are formed. A plurality of peripheral transistors and substrate contact portions SC are arranged around the light receiving portion, and the peripheral edges of the active regions of the light receiving portion, the peripheral transistors, and the substrate contact portion SC are surrounded by an element isolation region EI. . The peripheral transistors here refer to the reset transistor RST, the amplification transistor AMI, and the selection transistor SEL, respectively.

  The active region AR of the light receiving unit has a shape close to a rectangle in plan view. In the active region AR, photodiodes PD1 and PD2 are arranged side by side in the X-axis direction. The photodiodes PD1 and PD2 are formed apart from each other, and the photodiodes PD1 and PD2 both have a rectangular shape in plan view.

  Each peripheral transistor is formed in the same active region, and the active region extends in the X-axis direction along one side of the active region AR of the light receiving section. Further, along the other side of the active region AR that is not adjacent to the peripheral transistor, the transfer transistor TX1 using the photodiode PD1 in the active region AR as a source region, and the photodiode in the active region AR A transfer transistor TX2 having PD2 as a source region is formed.

  Each peripheral transistor has a gate electrode GE extending in the Y-axis direction. The transfer transistor TX1 has a gate electrode GE1 extending in the X-axis direction, and the transfer transistor TX2 has a gate electrode GE2 extending in the X-axis direction. The gate electrodes GE, GE1, and GE2 are made of polysilicon, for example, and are formed on the semiconductor substrate via a gate insulating film (not shown). The gate electrodes GE1 and GE2 are separated from each other. The gate electrode GE1 is adjacent to one side of the photodiode PD1 having a rectangular planar layout, whereas the gate electrode GE2 is the one side of the photodiode PD1 and the photodiode PD2 having a rectangular planar layout. It is adjacent to one side.

  Here, it can be considered that the transfer transistor TX2 includes a transfer transistor TX3 having the photodiode PD1 as a source region and a transfer transistor TX4 having the photodiode PD2 as a source region. Since the transfer transistors TX3 and TX4 share one gate electrode GE2, both are turned on when the gate electrode GE2 is turned on. By turning on the transfer transistor TX2, the transfer transistor TX3 transfers the charge L1 generated in the photodiode PD1 to the floating diffusion capacitor unit FD, and the transfer transistor TX4 transfers the charge R1 generated in the photodiode PD2 to the floating diffusion capacitor unit. Transfer to FD.

  The floating diffusion capacitor portion FD is a semiconductor region that functions as a drain region of the transfer transistors TX1, TX2, TX3, and TX4, and is formed in the active region AR. Since the floating diffusion capacitor portion FD is in an electrically floating state, the charge accumulated in the floating diffusion capacitor portion FD is held unless the reset transistor RST is operated.

  In the active region where the peripheral transistors are formed, the reset transistor RST, the amplification transistor AMI, and the selection transistor SEL are arranged in order in the X-axis direction. The reset transistor RST and the amplification transistor AMI share the drain region of each other. The source region of the reset transistor RST is connected to the respective drain regions of the transfer transistors TX1 and TX2, that is, the floating diffusion capacitance portion FD. The source region of the amplification transistor AMI functions as the drain region of the selection transistor SEL. The source region of the selection transistor SEL is connected to the output line OL as described with reference to FIG.

The respective drain regions of the transfer transistors TX1 and TX2, the source region of the selection transistor SEL, the source region of the reset transistor RST, and the drain region of the amplification transistor AMI are N ⁺ type semiconductor regions formed on the main surface of the semiconductor substrate. The substrate contact portion SC is a P ⁺ type semiconductor region formed on the main surface of the semiconductor substrate. Contact plugs CP are respectively connected to the upper surfaces of these semiconductor regions. A contact plug CP is also connected to each upper surface of the gate electrodes GE, GE1, and GE2.

  The substrate contact portion SC is a semiconductor region to which the ground potential GND (see FIG. 2) is applied. By fixing the potential of the well on the upper surface of the semiconductor substrate to 0 V, the threshold voltage variation of the peripheral transistors is generated. It has a role to prevent.

  The photodiode (first light receiving element) PD1 and the photodiode (second light receiving element) PD2 arranged in the X-axis direction in the active region AR that is the light receiving unit are both semiconductor elements extending in the Y-axis direction. In other words, the longitudinal directions of the photodiodes PD1 and PD2 are along the Y-axis direction.

As will be described later, the photodiode PD1 includes an N ⁻ type semiconductor region N1 formed on the main surface of the semiconductor substrate and a well region WL which is a P type semiconductor region. Similarly, the photodiode PD2 includes an N ⁻ type semiconductor region N2 formed on the main surface of the semiconductor substrate and a well region WL. The photodiodes PD1 and PD2 that are the light receiving elements shown in FIG. 3 can be regarded as being formed in the formation regions of the N ⁻ type semiconductor regions N1 and N2, respectively. In the active region AR, a P ⁻ type well region WL is formed around each of the regions where the N ⁻ type semiconductor regions N1 and N2 are formed.

  The active region AR has a shape close to a rectangle in plan view, but two protrusions are formed on one side of the four sides of the rectangle, and these protrusions are extended at the tip. It is connected. That is, the active region AR has an annular planar layout composed of these protruding portions and a rectangular pattern of the light receiving portion. An element isolation region EI is formed inside the annular planar layout. The drain regions of the transfer transistors TX1 and TX2 are formed in the protruding portions. That is, each of the transfer transistors TX1 and TX2 shares the floating diffusion capacitance portion FD that is a drain region. Further, the gate electrodes GE1 and GE2 are respectively disposed so as to straddle over the two protruding portions.

  Note that when outputting a captured image, signals (charges) of two photodiodes in a pixel are output together as one signal. Thereby, an image can be obtained with an image quality equivalent to that of a solid-state imaging device including a plurality of pixels each having only one photodiode.

FIG. 4 shows a cross-sectional view along the direction in which the photodiodes PD1 and PD2 are arranged in one pixel PE (see FIG. 3). In the cross-sectional view shown in FIG. 4, illustration of boundaries between a plurality of interlayer insulating films stacked on the semiconductor substrate SB is omitted. As shown in FIG. 4, a P ⁻ type well region WL is formed in the upper surface of the semiconductor substrate SB made of N type single crystal silicon or the like. An element isolation region EI that partitions the active region AR and other active regions is formed on the well region WL. The element isolation region EI is made of, for example, a silicon oxide film and is buried in a groove formed on the upper surface of the semiconductor substrate SB.

In the upper surface of the well region WL, N ⁻ type semiconductor regions N1 and N2 are formed separately. The well region WL that forms a PN junction with the N ⁻ type semiconductor region N1 functions as an anode of the photodiode PD1. The well region WL that forms a PN junction with the N ⁻ type semiconductor region N2 functions as an anode of the photodiode PD2. The N ⁻ type semiconductor region N1 and the N ⁻ type semiconductor region N2 are provided in one active region AR sandwiched between the element isolation regions EI.

As described above, in the active region AR formed in the pixel, the photodiode PD1 including the N ⁻ type semiconductor region N1 and the well region WL and the photodiode PD2 including the N ⁻ type semiconductor region N2 and the well region WL are provided. Is formed. In the active region AR, the photodiodes PD1 and PD2 are arranged side by side so as to sandwich the region where the well region WL is exposed on the upper surface of the semiconductor substrate SB.

The formation depth of the N ⁻ type semiconductor regions N1 and N2 is shallower than the formation depth of the well region WL. Further, the depth of the groove on the upper surface of the semiconductor substrate SB in which the element isolation region EI is embedded is shallower than the formation depth of the N ⁻ type semiconductor regions N1 and N2.

  On the semiconductor substrate SB, an interlayer insulating film IF is formed so as to cover the element isolation region EI and the photodiodes PD1 and PD2. The interlayer insulating film IF is a stacked film in which a plurality of insulating films are stacked. A plurality of wiring layers are stacked in the interlayer insulating film IF, and a wiring M1 covered with the interlayer insulating film IF is formed in the lowermost wiring layer. A wiring M2 is formed on the wiring M1 via an interlayer insulating film IF, and a wiring M3 is formed on the wiring M2 via an interlayer insulating film IF. A color filter CF is formed on the interlayer insulating film IF, and a microlens ML is formed on the color filter CF. During operation of the solid-state imaging device, light is irradiated to the photodiodes PD1 and PD2 through the microlens ML and the color filter CF.

  No wiring is formed immediately above the active region AR including the photodiodes PD1 and PD2. This is to prevent light incident from the microlens ML from being blocked by the wiring and irradiating the photodiodes PD1 and PD2 which are light receiving portions of the pixels. Conversely, by arranging the wirings M1 to M3 in a region other than the active region AR, photoelectric conversion is prevented from occurring in the active region where peripheral transistors and the like are formed.

  Hereinafter, the operation of the solid-state imaging device which is the semiconductor device of the present embodiment will be described mainly using FIG. Examples of the operation of the solid-state imaging device include an imaging operation and an automatic focusing operation.

  First, the operation of the pixel when imaging is described. In this case, first, a predetermined potential is applied to the gate electrodes of the transfer transistor TX2 and the reset transistor RST to turn on both the transfer transistor TX2 and the reset transistor RST. Then, the charge remaining in the photodiodes PD1 and PD2 and the charge accumulated in the floating diffusion capacitor part FD flow toward the positive power supply potential VCC, and the charges in the photodiodes PD1 and PD2 and the floating diffusion capacitor part FD are initialized. Is done. Thereafter, the reset transistor RST is turned off.

  Next, incident light is applied to the PN junctions of the photodiodes PD1 and PD2, and photoelectric conversion occurs in each of the photodiodes PD1 and PD2. As a result, a charge L1 is generated in the photodiode PD1, and a charge R1 is generated in the photodiode PD2. As described above, the photodiodes PD1 and PD2 are light receiving elements that generate signal charges corresponding to the amount of incident light in the interior thereof by photoelectric conversion, that is, photoelectric conversion elements.

  Next, these charges are transferred to the floating diffusion capacitor portion FD. In the imaging operation, in order to operate the two photodiodes PD1 and PD2 in the pixel PE as one photoelectric conversion unit, the charges of the photodiodes PD1 and PD2 are combined and read as one signal. That is, in the imaging operation, the charge signals generated in each of the two photodiodes PD1 and PD2 are added to obtain one pixel information.

  Therefore, it is not necessary to read out the charges of the photodiodes PD1 and PD2 separately. At this time, the transfer transistor TX1 is not turned on, and the transfer transistor TX2 is turned on to transfer the charge to the floating diffusion capacitance unit FD. As a result, the floating diffusion capacitor unit FD accumulates the charges transferred from the photodiodes PD1 and PD2. As a result, the potential of the floating diffusion capacitor portion FD changes.

  Here, the process of synthesizing the charge will be described in detail. Here, first, a voltage is applied to the gate electrode GE2 in a state where the charge L1 of the photodiode PD1 and the charge R1 of the photodiode PD2 are accumulated, so that the transfer transistor TX2 is turned on. As a result, the charges L1 and R1 are synthesized in the channel induced in the main surface of the semiconductor substrate immediately below the gate electrode GE2. Thereafter, the combined charge L1 + R1 is transferred to the floating diffusion capacitor portion FD.

  Next, the selection transistor SEL is turned on, and the potential of the floating diffusion capacitor FD after the change is amplified by the amplification transistor AMI, so that an electric signal corresponding to the potential fluctuation of the floating diffusion capacitor FD is output to the output line. Output to OL. That is, by operating the selection transistor SEL, the electric signal output from the amplification transistor AMI is output to the outside. Accordingly, one of the read circuits CC1 and CC2 (see FIG. 1) reads the potential of the output line OL.

  Next, the operation of the pixel when the image plane phase difference type automatic focusing is performed will be described. A solid-state imaging element which is a semiconductor device of this embodiment is provided with a plurality of photoelectric conversion units (for example, photodiodes) in one pixel. As described above, the plurality of photodiodes are provided in the pixel because, when the solid-state imaging device is used in, for example, a digital camera having an image plane phase difference type automatic focus detection system, the accuracy of automatic focusing and This is because the speed can be improved.

  In such a digital camera, the amount of lens drive required for focusing is calculated from the amount of deviation of the signals detected by one of the photodiodes in the pixel and the other of the photodiodes, that is, the phase difference, Focusing in a short time can be realized. Therefore, by providing a plurality of photodiodes in the pixel, more fine photodiodes can be formed in the solid-state imaging device, so that the accuracy of automatic focusing can be improved. Therefore, when performing automatic focusing, unlike the above-described imaging operation, it is necessary to separately read out the charges generated in each of the plurality of photodiodes in the pixel.

  In the automatic focus detection operation, first, a predetermined potential is applied to the gate electrodes of the transfer transistor TX2 and the reset transistor RST to turn on both the transfer transistor TX2 and the reset transistor RST. As a result, the charges of the photodiodes PD1 and PD2 and the floating diffusion capacitor portion FD are initialized. Thereafter, the reset transistor RST is turned off.

  Next, incident light is applied to the PN junctions of the photodiodes PD1 and PD2, and photoelectric conversion occurs in each of the photodiodes PD1 and PD2. As a result, charges are generated in each of the photodiodes PD1 and PD2. Here, it is assumed that the charge generated in the photodiode PD1 is L1, and the charge generated in the photodiode PD2 is R1.

  Next, one of these charges is transferred to the floating diffusion capacitor portion FD. Here, first, by turning on the transfer transistor TX1, the charge L1 of the photodiode PD1 is read out to the floating diffusion capacitor portion FD, and the potential of the floating diffusion capacitor portion FD is changed. Thereafter, the selection transistor SEL is turned on, and the changed potential of the floating diffusion capacitor portion FD is amplified by the amplification transistor AMI, and then output to the output line OL. That is, the electric signal corresponding to the potential fluctuation of the floating diffusion capacitance unit FD that is the charge detection unit is amplified by the amplification transistor AMI and output. Accordingly, one of the read circuits CC1 and CC2 (see FIG. 1) reads the potential of the output line OL. The electric charge L1 read out, that is, the signal L1 is stored in the memory circuit MC (see FIG. 1).

  At this time, the charge L1 generated in the photodiode PD1 remains in the floating diffusion capacitor portion FD, and the potential of the floating diffusion capacitor portion FD remains changed. Further, the charge R1 in the photodiode PD2 has not been transferred yet.

  Next, by turning on the transfer transistor TX2, the charge R1 of the photodiode PD2 is read to the floating diffusion capacitor portion FD, and the potential of the floating diffusion capacitor portion FD is further changed. When the transfer transistor TX2 is turned on, the charges of both the photodiodes PD1 and PD2 can be combined and transferred. However, since the charge L1 in the photodiode PD1 has already been transferred, only the charge R1 of the photodiode PD2 is transferred. Transferred to the floating diffusion capacitor FD.

  As a result, in the floating diffusion capacitor portion FD, a charge obtained by combining the charge L1 of the photodiode PD1 originally stored and the charge R1 of the photodiode PD2 transferred thereafter is stored. That is, L1 + R1 charges are accumulated in the floating diffusion capacitor portion FD.

  Thereafter, the selection transistor SEL is turned on, and the changed potential of the floating diffusion capacitor portion FD is amplified by the amplification transistor AMI, and then output to the output line OL. Accordingly, one of the read circuits CC1 and CC2 (see FIG. 1) reads the potential of the output line OL. In order to calculate the charge R1 generated in the photodiode PD2 from the read charge L1 + R1 in this way, the following calculation is performed. That is, the value of the charge L1 stored in the memory circuit MC (see FIG. 1) is subtracted from the value of the charge L1 + R1. Thereby, the charge R1 of the photodiode PD2 can be read. Such calculation is performed, for example, by the control circuit COC (see FIG. 1).

  Next, the driving amount of the lens necessary for focusing is calculated from the shift amounts of the signals L1 and R1 detected by the photodiodes PD1 and PD2 in each pixel PE in the pixel array unit PEA (see FIG. 1), that is, the phase difference. Then, automatic focusing is detected.

  As described above, when the charges of the photodiodes PD1 and PD2 are sequentially read, the charge to be read first may be the charge R1 of the photodiode PD2, and then the charge L1 of the photodiode PD1 may be read.

  As another operation at the time of automatic focusing, a method of omitting the operation of calculating the charge R1 from the combined charge L1 + R1 is also conceivable. That is, after the transfer transistor TX1 is first turned on to read out and store the charge L1, the reset transistor RST is turned on to reset the floating diffusion capacitor portion FD. Thereafter, the transfer transistor TX2 is turned on to thereby turn on the photodiode. The charge R1 of PD2 can be read out alone. In this case as well, the charge L1 needs to be stored in the memory circuit MC (see FIG. 1), but the charge L1 and the charge R1 can be read out independently without performing the above calculation.

  As described above, the operations of the transfer transistors TX1 and TX2 are particularly different between the imaging operation and the automatic focusing operation. In the automatic focusing operation, a process of turning on each of the transfer transistors TX1 and TX2 is necessary, but in the imaging operation, only the transfer transistor TX2 needs to be turned on, and it is not necessary to turn on the transfer transistor TX1.

  When the solid-state image sensor of this embodiment is used in a digital camera, the above-described imaging operation is performed on each pixel for both still images and moving images. In moving image capturing, the above-described automatic focusing operation is performed on each pixel together with image capturing. In still image capturing, focusing is performed by performing the automatic focusing operation on each pixel, and other automatic focusing devices outside the solid-state imaging device are used without performing the automatic focusing operation on the pixels. There are cases.

  Next, the effects of the semiconductor device of the present embodiment will be described using comparative examples shown in FIGS. FIG. 7 is a circuit diagram illustrating a pixel included in a semiconductor device as a comparative example. FIG. 8 is a planar layout showing pixels constituting a semiconductor device as a comparative example. FIG. 8 shows only the light receiving portion and two transfer transistors adjacent to the light receiving portion in the structure constituting the pixel PE.

  As shown in FIG. 8, the configuration of the light receiving portion of the pixel PE is adjacent to each of the active region AR having a layout close to a rectangle, the photodiodes PD1 and PD2 arranged in the active region AR, and the photodiodes PD1 and PD2. It consists of transfer transistors TX5 and TX6, and is similar to the configuration of the pixel PE of this embodiment described with reference to FIG. However, the pixel PE shown in FIG. 3 has the transfer transistor TX2 that has both the photodiodes PD1 and PD2 as sources, whereas the pixel PE of the comparative example shown in FIGS. Such a transfer transistor is not formed. In the comparative example, only the transfer transistor TX5 is formed adjacent to the photodiode PD1, and only the transfer transistor TX6 is formed adjacent to the photodiode PD2.

  As shown in FIG. 8, the transfer transistors TX5 and TX6 are formed in an annular active region AR, and a gate is formed on one upper part of two protruding portions protruding in a plan view from a rectangular portion of the active region AR. An electrode GE5 is formed, and a gate electrode GE6 is formed on the other upper portion. The gate electrode GE5 constitutes a transfer transistor TX5, and the gate electrode GE6 constitutes a transfer transistor TX6. The gate electrodes GE5 and GE6 are separated from each other. Here, the transfer transistors TX5 and TX6 do not share the gate electrodes GE5 and GE6. Therefore, by turning on only one of the gate electrodes GE5 and GE6, the charges of both the photodiodes PD1 and PD2 are not simultaneously transferred.

  As shown in FIG. 7, only the transfer transistor TX6 is interposed between the photodiode PD2 and the floating diffusion capacitor portion FD. This is the same as the structure in which only the transfer transistor TX2, that is, the transfer transistor TX4 is interposed between the photodiode PD2 and the floating diffusion capacitor portion FD, as shown in FIG.

  On the other hand, as shown in FIG. 7, only the transfer transistor TX5 is connected between the photodiode PD1 and the floating diffusion capacitor portion FD, and this point is different from the configuration shown in FIG. In FIG. 2, the transfer transistor TX2, that is, the transfer transistor TX3, and the transfer transistor TX1 are connected in parallel between the photodiode PD1 and the floating diffusion capacitor FD.

  That is, in the comparative example, only one transfer transistor having the photodiode as a source region is formed for one photodiode. Therefore, when the transfer transistor TX5 is turned on, the charge L1 of the photodiode PD1 is transferred, but the charge R1 of the photodiode PD2 is not transferred. Similarly, when the transfer transistor TX6 is turned on, the charge R1 of the photodiode PD2 is transferred, but the charge L1 of the photodiode PD1 is not transferred. Therefore, when transferring the charges of both the photodiodes PD1 and PD2, it is necessary to turn on both of the transfer transistors TX5 and TX6.

  If the transfer transistor TX5 shown in FIG. 7 is a first transfer unit, it can be considered that the transfer transistor TX1 having the same role as the first transfer unit is formed in the circuit shown in FIG. If the transfer transistor TX6 shown in FIG. 7 is the second transfer unit, it can be considered that the transfer transistor TX4 having the same role as the second transfer unit is formed in the circuit shown in FIG. In this case, the configuration shown in FIG. 2 is different from the configuration shown in FIG. 7 in that the transfer transistor TX2 including the transfer transistor TX3 is provided as the third transfer unit.

  Here, the imaging operation of the solid-state imaging device of the comparative example will be described with reference to FIG. In this case, first, a predetermined potential is applied to the gate electrodes of the transfer transistors TX5 and TX6 and the reset transistor RST to turn on the transfer transistors TX5 and TX6 and the reset transistor RST. Thereby, the charges of the photodiodes PD1 and PD2 and the floating diffusion capacitor portion FD are initialized. Thereafter, the reset transistor RST is turned off. At this time, in the configuration described with reference to FIG. 2, two photodiodes PD1 and PD2 can be reset by turning on one transfer transistor TX2, but here two transfer transistors TX5 are used. , TX6 cannot be reset unless the two photodiodes PD1, PD2 are reset.

  Next, incident light is applied to the PN junctions of the photodiodes PD1 and PD2, and photoelectric conversion occurs in each of the photodiodes PD1 and PD2. As a result, charges L1 and R1 are generated in the photodiodes PD1 and PD2, respectively.

  Next, these charges are transferred to the floating diffusion capacitor portion FD. At this time, by turning on the transfer transistors TX5 and TX6, the charge L1 of the photodiode PD1 and the charge R1 of the photodiode PD2 are transferred together to the floating diffusion capacitance portion FD, and the potential of the floating diffusion capacitance portion FD is changed. In the configuration described with reference to FIG. 2, the potential of each of the two photodiodes PD1 and PD2 can be transferred by turning on one transfer transistor TX2, but here two transfer transistors Unless both TX5 and TX6 are turned on, the respective potentials of the two photodiodes PD1 and PD2 cannot be transferred.

  Next, the selection transistor SEL is turned on, and the potential of the floating diffusion capacitance part FD after the change is amplified by the amplification transistor AMI, and then output to the output line OL. Accordingly, one of the read circuits CC1 and CC2 (see FIG. 1) reads the potential of the output line OL.

  Next, with reference to FIG. 7, an explanation will be given on the operation of the pixel when the image plane phase difference type automatic focusing is performed. Here, first, a predetermined potential is applied to the gate electrodes of the transfer transistors TX5 and TX6 and the reset transistor RST, and both the transfer transistors TX5 and TX6 and the reset transistor RST are turned on. As a result, the charges of the photodiodes PD1 and PD2 and the floating diffusion capacitor portion FD are initialized. Thereafter, the reset transistor RST is turned off. Again, in order to reset the two photodiodes PD1 and PD2, it is necessary to turn on the two transfer transistors TX5 and TX6.

  Next, incident light is applied to the PN junctions of the photodiodes PD1 and PD2, and photoelectric conversion occurs in each of the photodiodes PD1 and PD2. As a result, charges L1 and R1 are generated in the photodiodes PD1 and PD2, respectively.

  Next, one of these charges is transferred to the floating diffusion capacitor portion FD. Here, by first turning on the transfer transistor TX5, the charge L1 of the photodiode PD1 is read out to the floating diffusion capacitor portion FD. Thereafter, the amplified potential is output to the output line OL using the selection transistor SEL and the amplification transistor AMI. Accordingly, one of the read circuits CC1 and CC2 (see FIG. 1) reads the potential of the output line OL. The electric charge L1 read out, that is, the signal L1 is stored in the memory circuit MC (see FIG. 1).

  Next, by turning on the transfer transistor TX6, the charge R1 of the photodiode PD2 is read to the floating diffusion capacitor portion FD, and the potential of the floating diffusion capacitor portion FD is further changed. As a result, in the floating diffusion capacitor portion FD, a charge obtained by combining the charge L1 of the photodiode PD1 originally stored and the charge R1 of the photodiode PD2 transferred thereafter is stored. That is, L1 + R1 charges are accumulated in the floating diffusion capacitor portion FD. Subsequent calculation of the charge R1 is performed by subtraction similar to the step using FIG. Thereby, the charge L1 of the photodiode PD1 and the charge R1 of the photodiode PD2 can be read separately.

  Next, the driving amount of the lens necessary for focusing is calculated from the shift amounts of the signals L1 and R1 detected by the photodiodes PD1 and PD2 in each pixel PE in the pixel array unit PEA (see FIG. 1), that is, the phase difference. Then, automatic focusing is detected.

  As described above, in the imaging operation and the automatic focusing operation of the comparative example, both the two transfer transistors TX5 and TX6 are first used to reset and initialize the charges of the photodiodes PD1 and PD2. Must turn on. Further, in the imaging operation of the comparative example, the potentials of the two photodiodes PD1 and PD2 cannot be transferred unless both of the two transfer transistors TX5 and TX6 are turned on.

  For this reason, in the solid-state imaging device of the comparative example, the potential is supplied to the two gate electrodes GE5 and GE6 by 2 in the operation for resetting and the operation of transferring charges from the photodiode for imaging. The transfer transistors TX5 and TX6 need to be turned on. Operating the two transfer transistors for reset and transfer in this manner increases the power consumption for operating the solid-state imaging device. In particular, moving images that are continuously imaged are subject to reduction in power consumption. However, if potentials are supplied to a plurality of transfer transistors in a pixel as in the comparative example, an increase in power consumption is a major problem. Become.

  Further, since the increase in the capacitance of the floating diffusion capacitance portion FD causes an increase in the noise of the signal obtained from the pixel, it is important to reduce the capacitance of the floating diffusion capacitance portion FD from the viewpoint of reducing the noise. . In the semiconductor device of the comparative example, since the distance between the transfer transistors TX5 and TX6 is large, the area of the floating diffusion capacitance portion FD is large. For this reason, in the comparative example, there is a problem that noise in the pixel PE increases due to an increase in the capacitance of the floating diffusion capacitance portion FD.

  On the other hand, in the semiconductor device of the present embodiment shown in FIG. 2, in the imaging operation and the automatic focusing operation, each photo transistor can be obtained by turning on the transfer transistor TX2 and the reset transistor RST without turning on the transfer transistor TX1. The charge of the diodes PD1 and PD2 can be reset and initialized.

  In the imaging operation, even if the transfer transistor TX1 is not turned on, the charges L1 and R1 of the photodiodes PD1 and PD2 can be transferred together if the transfer transistor TX2 is turned on. Those charges L1 and R1 can be synthesized. Therefore, in these operations, it is not necessary to operate a plurality of transfer transistors in each pixel, so that power consumption for operating the semiconductor device can be reduced. Thus, the performance of the semiconductor device can be improved.

  Further, as shown in FIG. 3, since the transfer transistor TX2 is formed so as to straddle one side of the photodiode PD1 and one side of the photodiode PD2 in plan view, the transfer transistor TX1 and the transfer transistor The distance to TX2 can be reduced. Therefore, the area in plan view of the semiconductor region shared by the transfer transistors TX1 and TX2 as the drain region can be reduced as compared with the comparative example. Since the floating diffusion capacitor portion FD is a portion that holds charges accumulated in the semiconductor region, the capacitance of the charges accumulated in the floating diffusion capacitor portion FD is reduced by reducing the area of the semiconductor region. Can do. Thereby, noise generated in the pixel PE can be reduced. Thus, the performance of the semiconductor device can be improved.

In the present embodiment, a case where a P-type well region as an anode is used as a photodiode and a diffusion layer which is an N ⁻ -type semiconductor region is used as a cathode is described. However, the present invention is not limited to this, and a photodiode comprising an N-type well and a P ⁻ -type diffusion layer in the N-type well, or a photodiode having a diffusion layer of the same conductivity type as the pixel well on the surface The same effect can be obtained even in a solid-state imaging device having the above.

(Embodiment 2)
In this embodiment, a structure in which a gate electrode of a transfer transistor is formed between two photodiodes arranged in a pixel will be described with reference to FIGS. FIG. 5 is a plan layout showing the semiconductor device of the present embodiment. 6 is a cross-sectional view taken along line BB in FIG. FIG. 5 shows only the light receiving portion and two transfer transistors adjacent to the light receiving portion in the structure constituting the pixel PE.

  The pixel PE of the present embodiment shown in FIG. 5 has substantially the same configuration as the pixel PE of the first embodiment shown in FIG. However, FIG. 5 is different from the first embodiment in that a part of the gate electrode GE3 constituting the transfer transistor TX2 extends in the Y-axis direction between the photodiodes PD1 and PD2.

  As shown in FIG. 5, photodiodes PD1 and PD2 are arranged side by side in the X-axis direction in the active region AR of the pixel PE. Here, the photodiodes PD1 and PD2 are separated from each other with the well region WL interposed therebetween, and the gate electrode GE3 is disposed on the semiconductor substrate between the photodiodes PD1 and PD2 via a gate insulating film (not shown). Part of is formed. That is, the gate electrode GE3 is formed so as to divide the photodiodes PD1 and PD2 in plan view.

  The gate electrode GE3 of the transfer transistor TX2 in a plan view includes a pattern extending in the X-axis direction, that is, the direction in which the photodiodes PD1 and PD2 are aligned, and the Y-axis direction, that is, the photodiode from the center of the pattern in the X-axis direction. It has a shape in which the patterns extending in the extending direction of PD1 and PD2 are integrated. The pattern extending in the X-axis direction constituting the gate electrode GE3 extends adjacent to one side of the photodiode PD1 and one side of the photodiode PD2, similarly to the gate electrode GE2 shown in FIG. Further, the pattern extending in the Y-axis direction constituting the gate electrode GE3 is disposed between the photodiodes PD1 and PD2 in plan view. That is, the gate electrode GE3 has a T shape in plan view.

Note that the N ⁻ type semiconductor region N1 constituting the photodiode PD1 and the gate electrode GE3 partially overlap in plan view. Similarly, the N ⁻ type semiconductor region N2 constituting the photodiode PD2 and the gate electrode GE3 partially overlap in plan view. In FIG. 5, the boundaries between the N ⁻ type semiconductor regions N1 and N2 and the well region WL immediately below the gate electrode GE3 are indicated by broken lines. The outline of the photodiode PD1 at a position overlapping the gate electrode GE1 in plan view is indicated by a broken line.

  Further, as shown in FIG. 6, the cross-sectional structure in the direction in which the photodiodes PD1 and PD2 are arranged in the pixel is substantially the same as the structure of the first embodiment shown in FIG. However, as shown in FIG. 6, the gate electrode GE3 is formed on the semiconductor substrate between the photodiodes PD1 and PD2 via the gate insulating film GF, which is different from the first embodiment.

  Here, as shown in FIGS. 5 and 6, the distance between the adjacent photodiodes PD1 and PD2 in the pixel PE is assumed to be X1. Further, as shown in FIG. 5, the semiconductor region which is a part of the active region AR and forms the floating diffusion capacitance portion FD in the X-axis direction in the vicinity of the width of the drain region of the transfer transistor TX2, that is, the gate electrode GE3. Is X2.

The distance X1 is smaller than the distance (refer to FIG. 3) between the photodiodes PD1 and PD2 of the first embodiment corresponding to the location. This is because the gate electrode GE3 extending in the Y-axis direction when impurity ions are implanted from the semiconductor substrate into the main surface of the semiconductor substrate by ion implantation to form the N ⁻ type semiconductor regions N1 and N2. This is because the N ⁻ type semiconductor regions N1 and N2 are formed in a self-aligning manner using the mask as a mask.

  That is, since the gate electrode is not formed between the photodiodes PD1 and PD2 in the configuration shown in FIG. 3, the formation positions of the opposing sides of the photodiodes PD1 and PD2 are defined by ion implantation using the photoresist film as a mask. Is done. Since a photoresist film used as a mask for this ion implantation is difficult to form as a narrow pattern, the distance between the photodiodes PD1 and PD2 is relatively large.

On the other hand, since the photoresist film used for patterning the gate electrode GE3 shown in FIG. 5 can be easily formed with a width smaller than the photoresist film used as a mask for ion implantation, the gate electrode GE3 is formed by ion implantation. It can be formed narrower with a smaller width than the photoresist film used as the mask. Therefore, by forming the N ⁻ type semiconductor regions N1 and N2 in a self-aligning manner using the gate electrode GE3 as a mask, the distance X1 between the photodiodes PD1 and PD2 facing each other in the pixel PE can be reduced. In addition, the photodiodes PD1 and PD2 can be formed while maintaining the distance X1 with high accuracy. Therefore, by reducing the distance X1, the area occupied by the photodiodes PD1 and PD2 in the active region AR can be increased.

When the areas of the photodiodes PD1 and PD2 are small, when the photodiodes PD1 and PD2 receive light during the operation of the solid-state imaging device, electrons easily saturate inside the N ⁻ type semiconductor regions N1 and N2, respectively. There is a problem that the obtained image is likely to be whiteout. However, in this embodiment, since the areas of the photodiodes PD1 and PD2 can be enlarged as described above, it is possible to prevent the above-described whiteout from occurring. That is, the amount of electrons that can be accumulated in the photodiodes PD1 and PD2 can be increased in the solid-state imaging device of the present embodiment.

  Since such a solid-state imaging device can be sensitive to brighter light, the sensitivity of the device is increased. For this reason, in a digital camera using the solid-state imaging device, the dynamic range can be increased. Therefore, in this embodiment, since the image quality of an image captured using a solid-state imaging element can be improved, the performance of the semiconductor device can be improved.

Further, N constituting the photodiode PD1, PD2 ^- -type semiconductor regions N1, N2 by a self-aligned manner, irrespective like exposure precision in photolithography, N with high precision ^- -type semiconductor regions N1, N2 Can be formed at predetermined intervals at desired positions. As a result, the yield of the semiconductor device can be improved, and the reliability of the semiconductor device can be improved.

  Here, in the readout operation at the time of capturing a still image, the potential of the channel region below the gate electrode GE3 provided between the two photodiodes PD1 and PD2 is raised by turning on or turning on the transfer transistor TX2. Go down. As a result, the electrons accumulated in the two photodiodes PD1 and PD2 are collected and synthesized in the channel region having a low potential, which is induced directly below the gate electrode GE3, and then the floating diffusion capacitance portion having a lower potential. Induced to FD.

  In the present embodiment, the gate electrode GE3 extends along the whole of the opposing sides of the photodiodes PD1 and PD2. For this reason, compared with the solid-state imaging device of the first embodiment, the photodiode PD1, PD2 is wider in the width of the gate electrode GE3 in contact with the photodiode PD1, PD2 and can induce charges to a wider gate. There is a feature that charges generated in PD1 and PD2 are easily induced to a channel generated immediately below the gate electrode GE3. As a result, since the width of the transfer section is widened, charge transfer at the time of imaging or automatic focus detection can be performed efficiently. Therefore, the charge reading operation can be performed at high speed, so that the performance of the semiconductor device can be improved.

  In this embodiment, the distance X2, which is the width of the drain region of the transfer transistor TX2, is smaller than the width of the drain region of the corresponding transfer transistor TX2 (see FIG. 3) of the solid-state imaging device of the first embodiment. can do. This is because the pixels in the photodiodes PD1 and PD2 shown in FIG. 5 are guided to the channel region immediately below the gate electrode GE3 extending in the Y-axis direction between the photodiodes so as to be in the floating diffusion capacitance portion FD. This is because it is not necessary to overlap the photodiodes PD1 and PD2 with the gate electrode GE3 extending in the X-axis direction because the transfer is possible.

  Therefore, even if the distance X2, which is the width of the drain region of the transfer transistor TX2 adjacent to the gate electrode GE3 in the portion extending in the X-axis direction, is reduced, the efficiency of transferring charges from the photodiodes PD1 and PD2 decreases. Can be prevented. Therefore, the distance X2 can be reduced, thereby reducing the area of the semiconductor region constituting the floating diffusion capacitance portion FD. For this reason, since the capacity | capacitance of the floating diffusion capacity | capacitance part FD can be reduced, the noise which arises in the pixel PE can be reduced. Therefore, the performance of the semiconductor device can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, the structure in which two photodiodes are provided in the pixel has been described. However, even if the number of photodiodes provided in one pixel is an even number greater than two, Good. For example, when four photodiodes are provided in a pixel, it is assumed that there are two sets of light receiving units each including two photodiodes, and two photodiodes in each set of light receiving units are connected to each other in the present embodiment. The semiconductor device has the same structure as that of the semiconductor device of mode 1 or 2.

  In the first and second embodiments, one floating diffusion capacitor portion FD is formed by connecting two protruding portions protruding from the rectangular portion of the active region AR shown in FIG. One of the protruding portions constituting the drain may not be connected to the other protruding portion constituting the drain of the transfer transistor TX2. In this case, each protruding portion is electrically connected by the contact plug CP and the wiring, and the semiconductor region of each protruding portion is used as the floating diffusion capacitance portion FD.

AMI amplification transistor AR active region CP contact plug EI element isolation region FD floating diffusion capacitance portion GE, GE1, GE2 gate electrode N1, N2 N ^- type semiconductor region PD1, PD2 photodiode PE pixel RST reset transistor SC substrate contact portion SEL selection transistor TX1-TX4 transfer transistor WL well region

Claims (8)

A semiconductor substrate;
A first light receiving element formed in the semiconductor substrate;
The first light receiving element and the second light receiving element formed in the semiconductor substrate apart from each other without an element isolation region formed in the semiconductor substrate;
A floating diffusion capacitor formed in the semiconductor substrate; and in plan view, a first transfer transistor formed adjacent to the first light receiving element;
A second transfer transistor formed adjacent to the second light receiving element in plan view;
A solid-state imaging device provided with pixels having
The floating diffusion capacitor is connected to the drain of the first transfer transistor and the drain of the second transfer transistor;
The first light receiving element is connected to a source of the first transfer transistor and a source of the second transfer transistor;
The semiconductor device, wherein the second light receiving element is connected to the source of the second transfer transistor. The semiconductor device according to claim 1,
The second transfer transistor is a semiconductor device in which charges in the first light receiving element and the second light receiving element are combined and transferred to the floating diffusion capacitor unit. The semiconductor device according to claim 1,
The first light receiving element is formed along a first side surface of the second transfer transistor;
The second light receiving element is formed along a second side surface opposite to the first side surface of the second transfer transistor;
The semiconductor device, wherein each of the shape of the first light receiving element and the shape of the second light receiving element is rectangular in plan view. The semiconductor device according to claim 3.
The semiconductor device, wherein the first light receiving element and the second light receiving element are formed in a self-aligned manner with respect to a gate electrode of the second transfer transistor. The semiconductor device according to claim 4.
The width of the gate electrode of the second transfer transistor is longer than the width in the longitudinal direction of the first light receiving element and the width in the longitudinal direction of the second light receiving element. The semiconductor device according to claim 5.
The semiconductor device, wherein a distance between the first light receiving element and the second light receiving element is shorter than a gate length of the gate electrode of the second transfer transistor. The semiconductor device according to claim 1,
The semiconductor device, wherein the drain of the first transfer transistor, the drain of the second transfer transistor, and the floating diffusion capacitance portion are formed of a semiconductor region of the same conductivity type. The semiconductor device according to claim 1,
The first light receiving element is formed by a PN junction of a first conductive type first semiconductor region and a second conductive type second semiconductor region,
The second light receiving element is formed by a PN junction of the first conductive type third semiconductor region and the second conductive type fourth semiconductor region,
Each conductivity type of the first semiconductor region of the first light receiving element, the third semiconductor region of the second light receiving element, the source of the first transfer transistor, and the source of the second transfer transistor. Are the same, semiconductor devices.

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