JP6420209B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device capable of controlling the transfer of charges that are always moving randomly by thermal energy.

  The electric charge in the semiconductor moves at random by heat energy, but in order to generate current using this, a temperature difference may be provided in the semiconductor. The temperature difference is converted into a potential difference by the Seebeck effect, thereby generating a current.

K. Nishiguchi, C. Koechlin, Y. Ono, A. Fujiwara, H. Inokawa, and H. Yamaguchi, "Single-electron-resolution electrometer based on field-effect transistor", Jpn. J. Appl. Phys., Vol .47, pp.8305-8310, 2008. L. Fricke, M. Wulf, B. Kaestner, F. Hohls, P. Mirovsky, B. Mackrodt, and HW Schumacher, "Self-referenced single-electron quantized current source", Phys. Rev. Lett., Vol.112 , 226803, 2014.

  By the way, even in a state where there is no temperature difference, the electric charge in the semiconductor always moves randomly by the heat energy. Such random movement of electric charge is regarded as noise in the semiconductor device and has not been used as a resource for generating current.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to make it possible to use a charge in a semiconductor that is constantly moving randomly by heat energy as a resource for generating current. To do.

  A semiconductor device according to the present invention includes a thin line structure made of a semiconductor formed on a substrate, a charge storage portion provided in the thin line structure, a source and a drain provided in the thin line structure with the charge storage portion interposed therebetween, A gate electrode provided between the source and the charge storage unit and between the charge storage unit and the drain; and charge detection means for detecting the number of charges stored in the charge storage unit.

  In the semiconductor device, a plurality of charge storage units arranged in series between a source and a drain, a gate electrode provided between adjacent charge storage units, and a plurality of charge storage units are provided. A plurality of charge detection means may be provided.

  In the semiconductor device, the charge detection means may be composed of a field effect transistor having a charge storage portion as a gate electrode.

The semiconductor device includes a control unit that controls a voltage applied to each gate electrode based on a charge number detection result of the charge storage unit by the charge detection unit. the gate electrode on the drain side is turned off is turned on to the gate electrode of the source side by the small not charge number of the detection, the gate electrode of the source side by the multi have the number of charges detected from the reference value in the charge accumulating portion by charge detecting means The applied voltage is turned off and the gate electrode on the drain side is turned on.

  As described above, according to the present invention, it is possible to obtain an excellent effect that charges in a semiconductor that is constantly moving randomly by thermal energy can be used as a resource for current generation.

FIG. 1A is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a partial configuration of the semiconductor device according to Embodiment 1 of the present invention. FIG. 1C is an explanatory diagram showing a change in potential energy on the thin wire structure 102 of the semiconductor device in the first embodiment of the present invention. FIG. 2A is an explanatory diagram for explaining charge transfer in the semiconductor device according to the first embodiment of the present invention. FIG. 2B is an explanatory diagram for explaining charge transfer in the semiconductor device according to the first embodiment of the present invention. FIG. 2C is an explanatory diagram for explaining charge transfer in the semiconductor device according to the first embodiment of the present invention. FIG. 3A is a plan view showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 3B is an explanatory diagram showing a change in potential energy on the thin wire structure 202 of the semiconductor device according to the second embodiment of the present invention. FIG. 4A is an explanatory diagram for explaining charge transfer in the semiconductor device according to the second embodiment of the present invention. FIG. 4B is an explanatory diagram for explaining charge transfer in the semiconductor device according to the second embodiment of the present invention. FIG. 4C is an explanatory diagram for explaining charge transfer in the semiconductor device according to the second embodiment of the present invention. FIG. 4D is an explanatory diagram for explaining charge transfer in the semiconductor device according to the second embodiment of the present invention. FIG. 5 is an explanatory diagram for explaining charge transfer in another semiconductor device according to the second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a partial configuration of the semiconductor device according to Embodiment 1 of the present invention. FIG. 1B shows a cross section taken along line bb ′ of FIG. 1A.

  This semiconductor device is first provided in a thin line structure 102 formed of a semiconductor formed on a substrate 101, a charge storage unit 103 provided in the thin line structure 102, and the charge storage unit 103. A source 104 and a drain 105 are provided. In addition, a first gate electrode (source-side gate electrode) 106 provided between the source 104 and the charge storage unit 103 and a second gate electrode (drain) provided between the charge storage unit 103 and the drain 105 are provided. Side gate electrode) 107.

  As shown in FIG. 1C, the charge storage unit 103 is formed in the thin line structure 102 by turning off the first gate electrode 106 and the second gate electrode 107 (applying a negative potential when the charge is an electron). This is a region formed in the thin wire structure 102 by an energy barrier.

  Note that the first gate electrode 106 and the second gate electrode 107 are insulated from the thin line structure 102. For example, as shown in FIG. 1B, an insulating layer 109 is formed between the thin line structure 102 and the first gate electrode 106. The insulating layer 109 may have a thickness within a range where the electric field effect by the first gate electrode 106 is expressed with respect to the thin wire structure 102 in the region where the first gate electrode 106 is formed. The same applies between the fine wire structure 102 and the second gate electrode 107.

  The semiconductor device also includes a charge detection unit 120 that detects the number of charges accumulated in the charge accumulation unit 103. The charge detection unit 120 is, for example, a field effect transistor having the charge storage unit 103 as a gate electrode and having a channel 121, a source 122, and a drain 123. As a matter of course, the channel 121, the source 122, and the drain 123 are insulated and separated from the charge storage unit 103. In the field-effect transistor, the channel 121 having a thin wire structure is preferably small in cross-sectional size and length so that single charge detection is possible (see Non-Patent Document 1).

  For example, the substrate 101 is a well-known SOI (silicon-on-insulator) substrate, and by patterning the surface silicon layer, the thin wire structure 102 (charge storage portion 103, source 104, drain 105), channel 121, A source 122 and a drain 123 may be formed. In this case, these are formed on the buried insulating layer 101a. For example, the above-described portions can be formed by patterning the surface silicon layer by a well-known lithography technique and dry etching technique.

  In addition, the charge storage unit 103 may be in an undoped intrinsic semiconductor state, and the source 104 and the drain 105 may be an n-type semiconductor into which an n-type impurity is introduced, for example. In this case, the charge is an electron. The source 104 and the drain 105 may be a p-type semiconductor into which a p-type impurity is introduced, for example. In this case, the charges are holes. In the case where the charge is a hole, a positive potential is applied to the first gate electrode 106 and the second gate electrode 107 so that the transistor is turned off.

  For example, the thin line structure 102 has a thickness of 20 to 30 nm and a width of about 50 nm, and the thin line structure channel 121 has a thickness of 20 to 30 nm and a width of about 50 nm. The distance between the fine line structure 102 and the channel 121 is about 50 nm. At this distance, the charge storage unit 103 and the channel 121 can be electrostatically coupled, the charge storage unit 103 functions as a gate electrode of a field effect transistor by the channel 121, and the number of charges in the charge storage unit 103 is room temperature. It can be detected at (about 25 ° C.).

  The thin wire structure 102 and the channel 121 can be electrostatically coupled at room temperature, the charge storage unit 103 functions as a gate electrode of a field effect transistor by the channel 121, and the number of charges in the charge storage unit 103 is detected at room temperature. It is sufficient that the distance is possible. Similarly, the cross-sectional dimension of the channel 121 may be such that the number of charges in the charge storage portion 103 can be detected by the field effect transistor using the channel 121.

  In addition, the semiconductor device in Embodiment 1 includes a control unit (non-control unit) that controls the voltage applied to the first gate electrode 106 and the second gate electrode 107 based on the charge number detection result of the charge storage unit 103 by the charge detection unit 120. As shown).

  Hereinafter, an operation example of the semiconductor device in Embodiment 1 will be described. First, when it is detected that the number of charges (electrons) in the charge storage unit 103 is smaller than the reference value, the voltage applied to the first gate electrode 106 is shifted to the positive state to turn on, and the potential energy on the source 104 side As shown in FIG. 2A, the barrier is lowered so that heat (energy) indicated by a black circle can pass (transfer) between the source 104 and the charge storage portion 103 by thermal energy. At the same time, the voltage applied to the second gate electrode 107 is negatively shifted to an off state, the potential energy barrier on the drain 105 side is increased, and the movement of charges between the charge storage portion 103 and the drain 105 is suppressed.

  Further, when it is detected that the number of charges in the charge storage unit 103 is larger than the reference value, the voltage applied to the second gate electrode 107 is positively shifted to the on state, and the potential energy barrier on the drain 105 side is lowered. As shown in FIG. 2B, the heat can be passed between the charge storage portion 103 and the drain 105 by heat energy. At the same time, the voltage applied to the first gate electrode 106 is negatively shifted to an off state, the potential energy barrier on the source 104 side is increased, and the movement of charges between the charge storage portion 103 and the source 104 is suppressed. When the charge is a hole, the polarity of the voltage described above is reversed.

  When the charge is transferred from the source 104 to the charge storage unit 103 by the feedback control based on the charge number detection result of the charge detection unit 120 described above, the state illustrated in FIG. 2A is changed to the state illustrated in FIG. By repeatedly changing the state shown in FIG. 2B to the state shown in FIG. 2A when the drain 105 moves, the charge is rectified from the source 104 side to the drain 105 side by rectifying the charge fluctuation without directly applying energy to the charge. (Transfer) to generate a current. As described above, when the semiconductor device in Embodiment 1 is used, current can be generated by rectifying the fluctuation of charge.

  The energy that can be transferred from the source 104 side to the drain 105 side by one cycle as described above is usually about the magnitude of thermal energy as shown in FIG. 2C. In order to detect the number of charges in the charge storage unit 103, it is necessary to reduce the size of the charge storage unit 103 (the diameter of the charge storage unit 103 of the thin wire structure 102 and the length between the source 104 and the drain 105). . However, if the size of the charge storage unit 103 is reduced to the extent that the energy (charging energy) required to add one charge is larger than the thermal energy, the fluctuation of the charge is suppressed due to the effect of the charging effect, and the charge can be extracted. The energy that can be reduced. Therefore, it is desirable to design the size of the charge storage unit 103 so that the charge energy of one charge is smaller than the thermal energy so that the fluctuation of the charge is not suppressed.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIG. 3A. FIG. 3A is a plan view showing the configuration of the semiconductor device according to the second embodiment of the present invention.

  In this semiconductor device, first, a fine line structure 202 made of a semiconductor formed on a substrate 201, and a first charge accumulation unit 203a, a second charge accumulation unit 203b, and a third charge accumulation unit 203c provided in the fine line structure 202. Is provided. The first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c are arranged in this order. In addition, a source 204 and a drain 205 provided in the thin line structure 202 are provided with the first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c interposed therebetween.

  The first gate electrode 206 provided between the source 204 and the first charge storage unit 203a, and the second gate electrode 207 provided between the first charge storage unit 203a and the second charge storage unit 203b. A third gate electrode 208 provided between the second charge storage unit 203b and the third charge storage unit 203c, and a fourth gate electrode 209 provided between the third charge storage unit 203c and the drain 205. With.

  As shown in FIG. 3B, the first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c include a first gate electrode 206, a second gate electrode 207, a third gate electrode 208, and a fourth gate. This is a region formed in the fine line structure 202 by an energy barrier formed in the fine line structure 202 by turning off the electrode 209 (a negative potential is applied when the charge is an electron).

  Note that the first gate electrode 206, the second gate electrode 207, the third gate electrode 208, and the fourth gate electrode 209 are insulated and separated from the thin line structure 202. For example, an insulating layer (not shown) is formed between the thin line structure 202 and the first gate electrode 206. The insulating layer may have a thickness within a range in which the electric field effect by the first gate electrode 206 is expressed with respect to the thin line structure 202 in the first gate electrode 206 formation region. The same applies to the thin wire structure 202 and the second gate electrode 207, the third gate electrode 208, and the fourth gate electrode 209.

  The semiconductor device also includes a first charge detection unit 220a and a second charge detection unit 220b that detect the number of charges stored in the first charge storage unit 203a, the second charge storage unit 203b, and the third charge storage unit 203c. , A third charge detector 220c.

  The first charge detection unit 220a is a field effect transistor having the first charge accumulation unit 203a as a gate electrode, a first channel 221a, a readout unit 222 serving as a source, and a readout unit 223 serving as a drain.

  The second charge detection unit 220b is a field effect transistor having the second charge storage unit 203b as a gate electrode, a second channel 221b, a reading unit 223 serving as a source, and a reading unit 224 serving as a drain.

  The third charge detection unit 220c is a field effect transistor having the third charge storage unit 203c as a gate electrode, a third channel 221c, a reading unit 224 serving as a source, and a reading unit 225 serving as a drain.

  In each of these field effect transistors, the first channel 221a, the second channel 221b, and the third channel 221c having a thin wire structure are preferably small in cross-sectional dimension and length so that single charge detection is possible (non- Patent Document 1).

  For example, the substrate 201 is a well-known SOI substrate, and by patterning the surface silicon layer, the thin wire structure 202 (first charge storage unit 203a, second charge storage unit 203b, third charge storage unit 203c, source 204, drain 205), first charge detector 220a, second charge detector 220b, and third charge detector 220c may be formed. In this case, these are formed on the buried insulating layer 201a. For example, the above-described portions can be formed by patterning the surface silicon layer by a well-known lithography technique and dry etching technique.

  The first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c are in an undoped intrinsic semiconductor state, and the source 204 and the drain 205 are n-type semiconductors into which an n-type impurity is introduced, for example. What should I do? In this case, the charge is an electron. The source 204 and the drain 205 may be a p-type semiconductor into which a p-type impurity is introduced, for example. In this case, the charges are holes. When the charge is a hole, a positive potential is applied to the first gate electrode 206, the second gate electrode 207, the third gate electrode 208, and the fourth gate electrode 209, thereby turning off.

  For example, the thin line structure 202 has a thickness of about 20 to 30 nm and a width of about 50 nm, and the first channel 221a, the second channel 221b, and the third channel 221c of the thin line structure have a thickness of about 20 to 30 nm and a width of about 50 nm. Yes. The distance between the thin line structure 202 and the first channel 221a, the second channel 221b, and the third channel 221c is about 50 nm.

  The thin wire structure 202, the first channel 221a, the second channel 221b, and the third channel 221c are the first charge storage unit 203a, the second charge storage unit 203b, and the third charge storage unit 203c, and the first channel 221a, The distance that functions as the gate electrode of the field effect transistor by the two channels 221b and the third channel 221c may be used.

  In addition, the cross-sectional dimensions of the first channel 221a, the second channel 221b, and the third channel 221c are the same as the first charge accumulation unit 203a, the first channel 221a, the second channel 221b, and the third channel 221c. It is only necessary that the number of charges in the two-charge storage unit 203b and the third charge storage unit 203c be detected.

  Further, the semiconductor device according to the second embodiment includes a first charge accumulation unit 203a, a second charge accumulation unit 203b, and a third charge that are formed by the first charge detection unit 220a, the second charge detection unit 220b, and the third charge detection unit 220c. A control unit (not shown) that controls voltages applied to the first gate electrode 206, the second gate electrode 207, the third gate electrode 208, and the fourth gate electrode 209 is provided according to the charge number detection result of the storage unit 203c.

  Hereinafter, an operation example of the semiconductor device in Embodiment 2 will be described. First, when it is detected that the number of charges in the first charge storage unit 203a, the second charge storage unit 203b, and the third charge storage unit 203c is smaller than the reference value, the voltage applied to the first gate electrode 206 is positively set. The potential energy barrier on the source 204 side is lowered by shifting and the potential energy barrier on the source 204 side is lowered, and as shown in FIG. Let it pass. At the same time, the voltages applied to the second gate electrode 207, the third gate electrode 208, and the fourth gate electrode 209 are negatively shifted to an off state, and the potential energy barrier in these regions is increased. This suppresses the movement of charges between the first charge accumulation unit 203a and the second charge accumulation unit 203b, the second charge accumulation unit 203b and the third charge accumulation unit 203c, and between the third charge accumulation unit 203c and the drain 205. .

  As described above, when the charge is stored in the first charge storage unit 203a and it is detected that the number of charges in the first charge storage unit 203a is larger than the reference value, the charge is applied to the second gate electrode 207. The voltage is positively shifted to the on state, the potential energy barrier in the region of the second gate electrode 207 is lowered, and as shown in FIG. 4B, the first charge accumulation unit 203a and the second charge accumulation unit 203b are caused by thermal energy. It is in a state where charges can pass between them. At the same time, the voltages applied to the first gate electrode 206, the third gate electrode 208, and the fourth gate electrode 209 are shifted to the negative state to increase the potential energy barrier in these regions. This suppresses the movement of charges between the source 204 and the first charge accumulation unit 203a, the second charge accumulation unit 203b and the third charge accumulation unit 203c, and between the third charge accumulation unit 203c and the drain 205.

  As described above, when the charge is stored in the second charge storage unit 203b and it is detected that the number of charges in the second charge storage unit 203b is larger than the reference value, the charge is applied to the third gate electrode 208. The voltage is positively shifted to the on state, the potential energy barrier in the region of the third gate electrode 208 is lowered, and as shown in FIG. 4C, the second charge accumulation unit 203b and the third charge accumulation unit 203c are caused by thermal energy. It is in a state where charges can pass between them. At the same time, the voltage applied to the first gate electrode 206, the second gate electrode 207, and the fourth gate electrode 209 is negatively shifted to the off state, and the potential energy barrier in these regions is increased. This suppresses the movement of charges between the source 204 and the first charge storage unit 203a, the first charge storage unit 203a and the second charge storage unit 203b, and the third charge storage unit 203c and the drain 205.

  As described above, when the charge is stored in the third charge storage unit 203c and it is detected that the number of charges in the third charge storage unit 203c is larger than the reference value, the charge is applied to the fourth gate electrode 209. The voltage is positively shifted to the on state, the potential energy barrier in the region of the fourth gate electrode 209 is lowered, and as shown in FIG. 4D, a charge is generated between the third charge accumulation unit 203c and the drain 205 by the thermal energy. Let it pass. At the same time, the voltages applied to the first gate electrode 206, the second gate electrode 207, and the third gate electrode 208 are negatively shifted to the off state, and the potential energy barrier in these regions is increased. This suppresses the movement of charges between the source 204 and the first charge storage unit 203a, the first charge storage unit 203a and the second charge storage unit 203b, and between the second charge storage unit 203b and the third charge storage unit 203c. .

  As described above with reference to FIGS. 4A, 4B, 4C, and 4D by the feedback control based on the charge number detection results of the first charge detection unit 220a, the second charge detection unit 220b, and the third charge detection unit 220c. In addition, the charge is sequentially transferred from the source 204 to the drain 205 via the first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c, thereby rectifying the charge fluctuations and current. Can be taken out as.

  In addition, since the number of charges at the three locations of the first charge accumulation unit 203a, the second charge accumulation unit 203b, and the third charge accumulation unit 203c can be simultaneously observed in real time, the charge accumulated in the second charge accumulation unit 203b is Whether it has moved to the first charge storage unit 203a, the third charge storage unit 203c, or has leaked to another location can be accurately detected.

  Further, according to the second embodiment, a self-reference type single electron pump can be realized. At ultra-low temperatures, self-referenced single-electron pumps using compound semiconductors have already been realized to improve the accuracy of current standard elements (see Non-Patent Document 2). On the other hand, according to the second embodiment, single charge detection is possible at room temperature, and a self-reference type single electron pump can be realized at room temperature.

  In the above description, the case where three charge storage units are arranged in series has been described as an example. However, the present invention is not limited to this. As shown in FIG. 5, four or more n charge storage units 303- 1 to 303-n may be arranged in series between the source 304 and the drain 305. In this way, by arranging a plurality of charge storage units in series, each charge storage unit can acquire energy corresponding to the charging energy with respect to the charge. As a result, a large amount of energy that cannot be realized in the case of a single charge storage unit can be acquired by the charge.

  As described above, according to the present invention, since the number of charges in the charge storage unit is detected, the gate electrode can be controlled based on the detection result of the number of charges in the charge storage unit, and the heat energy and the like can be controlled. It is possible to rectify the fluctuation of the electric charge due to the disturbance and use the electric charge in the semiconductor that is always moving randomly by the thermal energy as a resource for generating current. Further, by using the three charge storage units, it is possible to accurately determine the moving direction of electrons. Furthermore, by using four or more charge storage units, a large amount of energy corresponding to the number of charge storage units can be imparted to the charge.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, the semiconductor used is not limited to silicon, and other semiconductors such as germanium and III-V compound semiconductors may be used.

  DESCRIPTION OF SYMBOLS 101 ... Board | substrate, 101a ... Embedded insulating layer, 102 ... Fine wire structure, 103 ... Charge storage part, 104 ... Source, 105 ... Drain, 106 ... 1st gate electrode, 107 ... 2nd gate electrode, 120 ... Charge detection part, 121 ... channel, 122 ... source, 123 ... drain.

Claims (3)

A fine wire structure made of a semiconductor formed on a substrate;
A charge storage portion provided in the fine wire structure;
A source and a drain provided in the thin line structure sandwiching the charge storage portion;
A gate electrode provided between each of the source and the charge storage unit and between the charge storage unit and the drain;
Charge detection means for detecting the number of charges stored in the charge storage section ;
Control means for controlling the voltage applied to each of the gate electrodes according to the charge number detection result of the charge storage section by the charge detection means;
With
The control means includes
The source-side gate electrode is turned on by detecting the number of charges smaller than a reference value in the charge storage unit by the charge detection means, and the drain-side gate electrode is turned off,
A voltage applied to the gate electrode on the source side is turned off by turning off the voltage applied to the gate electrode on the source side by detecting the number of charges larger than a reference value in the charge storage unit by the charge detecting means, and the gate electrode on the drain side is turned on. A semiconductor device. The semiconductor device according to claim 1,
A plurality of the charge storage units arranged in series between the source and the drain;
A gate electrode provided between the charge storage units adjacent to each other;
And a plurality of the charge detection means provided corresponding to the plurality of charge storage units. The semiconductor device according to claim 1 or 2,
2. The semiconductor device according to claim 1, wherein the charge detection means comprises a field effect transistor having the charge storage portion as a gate electrode.

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