JP6414702B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus.

  An image processing apparatus discards the line when the clock count number during the assertion period of the valid section signal of the image is not a predetermined value due to noise mixing in the image transfer clock on the image data transmission side and the image reception side. Instead, the previous line is output (see, for example, Patent Document 1).

  Also, in a certain image interface circuit, the transmission side circuit generates parity information for noise detection of the image data signal for each pixel and transmits it to the reception side circuit by a line synchronization signal, and the reception side circuit receives the received image data. If the parity of the signal does not match the received parity information, an image one pixel before is used (see, for example, Patent Document 2).

JP 2012-56161 A JP 2003-122649 A

  However, as described above, when outputting a line one line before an error detected line, for example, due to an error for one pixel, an image of many valid pixels in which no error has occurred is discarded. .

  In addition, when an image one pixel before is used for a pixel in which an error is detected, noise is continuously mixed on the communication path, and if an error is detected in a plurality of consecutive pixels, a single image is continuous. As a result, the image quality deterioration becomes conspicuous.

  The present invention has been made in view of the above problems, and an object of the present invention is to obtain an image processing apparatus that corrects a location where an error has occurred without discarding a large number of valid pixel images in which no error has occurred. To do.

An image processing apparatus according to the present invention includes a transmission-side apparatus that transmits an image data signal and a reception-side apparatus that receives the image data signal. The transmission side device generates error detection data of image data in each of a plurality of sections obtained by dividing a transfer period of image data for one line by a predetermined number, and the image data and the error detection data are converted into an image. Transmit as a data signal. The receiving side device receives the image data signal, and in the line where the error is detected by the error detection data in the image data signal, the error is detected in a section before the section where the error is detected. The image data of the detected line is used, and at least for the section where the error is detected, the image data of the line one line before the line where the error is detected is used. Further, (A) the receiving side device includes a double buffer including a first line memory and a second line memory, and a line memory control unit, and the line memory control unit includes the line memory control unit in the received image data signal. Image data is alternately written to the first line memory and the second line memory line by line, the image data is alternately read line by line from the first line memory and the second line memory, and the line memory control unit In the line in which an error is detected by the error detection data, (a) image data of the line in which the error is detected in the section before the section in which the error is detected is stored in the first line memory and the first line memory. Read from one of the two line memories, (b) at least the error For the detected section, image data one line before the line where the error is detected is read from the other of the first line memory and the second line memory, and the first line memory and the second line memory are read out. In parallel with reading from the other of the second line memory, the image data of the line next to the line where the error is detected is written to the other of the first line memory and the second line memory, or (B) The transmission side device asserts an image valid signal in the transfer period of the image data and the transfer period of the error detection data in the image data signal, and transfers the transfer period of the image data and the transfer of the error detection data. In an interval between periods, the image valid signal is negated and the receiving device Based on the assertion period of the image valid signal, the image data signal is separated into said image data and said error detection data.

  According to the present invention, it is possible to obtain an image processing apparatus that corrects a location where an error has occurred without discarding a large number of valid pixel images in which no error has occurred.

  These and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a timing chart showing signals transmitted from the transmission side apparatus 1 in FIG. FIG. 3 is a timing chart for explaining the operation of the reception-side device 2 in the first embodiment. FIG. 4 is a timing chart illustrating details of the operation of the reception-side device 2 in the first embodiment. FIG. 5 is a timing chart for explaining the operation of the reception-side device 2 in the second embodiment. FIG. 6 is a timing chart for explaining details of the operation of the reception-side device 2 in the third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.

  The image processing apparatus shown in FIG. 1 includes a transmission side apparatus 1 that transmits an image data signal DATA line by line in synchronization with a horizontal synchronization signal HSYNC, and a reception side apparatus 2 that receives the image data signal DATA. For example, the transmission-side apparatus 1 is an apparatus that acquires an image data of an original image by controlling an image reading unit that optically reads an original image from an original. The reception-side apparatus 2 receives from the transmission-side apparatus 1. It is a device that executes various image processing on the processed image data.

  The transmission-side apparatus 1 has an image data signal DATA (that is, image data to be transmitted) in each of a plurality of sections obtained by dividing a transfer period of image data for one line by a predetermined number (here, equally). Error detection data is generated, and the image data and the error detection data are transmitted as an image data signal DATA.

  The receiving side apparatus 2 receives the image data signal DATA, and an error is detected in a section before the section in which the error is detected in the line in which the error is detected by the error detection data in the image data signal DATA. Image processing is executed using the image data of the line one line before the line where the error is detected at least for the section where the error is detected using the image data of the line.

  The transmission side device 1 includes an image processing unit 11, a line memory control unit 12, line memories 13-1 and 13-2, an integration circuit 14, a multiplexer 15, and an MRE signal output unit 16.

  The image processing unit 11 performs predetermined image processing (for example, resolution conversion) on the image data.

  The line memory control unit 12 writes the image data after image processing alternately line by line to the line memories 13-1 and 13-2, and alternately writes the image data line by line to the line memories 13-1 and 13-. Read from 2.

  The line memory control unit 12 outputs the image data line by line to the integrating circuit 14 and the multiplexer 15 in synchronization with the horizontal synchronization signal HSYNC, and asserts the image valid signal MRE during the transfer period of the image data signal DATA.

  The line memories 13-1 and 13-2 constitute a double buffer.

  For a plurality of sections obtained by dividing the transfer period of the image data for one line into a predetermined number (here, 4), the integration circuit 14 sets the image data signal DATA pixel by pixel from the beginning of each section. Then, the integrated value of the image data signal DATA in the section (that is, the integrated value of the image data to be transmitted in the section) is calculated as error detection data. Here, the integration circuit 14 calculates the integration value of the image data signal DATA of the section for each section having a predetermined length during the period in which the image valid signal MRE output by the line memory control unit 12 is asserted.

  The multiplexer 15 first selects the image data from the line memory control unit 12 during the period when the image valid signal MRE is asserted, selects the error detection data from the integrating circuit 14 after the image data, Output as image data signal DATA. Thereby, error detection data is added to the image data to be transmitted in the image data signal DATA.

  Here, the image data signal DATA is an 8-bit signal, the image data is 8-bit data per pixel, and image data of one pixel is transferred in one clock. The error detection data in each section is 24-bit data. Therefore, the error detection data in each section is divided into three data of each of the lower, middle, and upper 8 bits and is included in the image data signal DATA as three data.

  That is, the error detection data is transmitted from the transmission side apparatus 1 to the reception side apparatus 2 as the image data signal DATA through the same signal line as the image data.

  The MRE signal output unit 16 extends the assertion period of the image valid signal MRE output from the line memory control unit 12 and outputs the image valid signal MRE after the assertion period extension. That is, the MRE signal output unit 16 asserts the image valid signal MRE in the error detection data transfer period in addition to the assertion period of the image valid signal MRE output from the line memory control unit 12 (that is, the image data transfer period). To do.

  The reception side device 2 includes a demultiplexer 21, an integration circuit 22, a comparison circuit 23, a line memory control unit 24, line memories 25-1 and 25-2, and an image processing unit 26.

  The demultiplexer 21 outputs the received image data signal DATA by separating the image data and the error detection data from each other. Specifically, the demultiplexer 21 outputs image data for one line having a predetermined data length to the integration circuit 22 and the line memory control unit 24 from the assertion start timing of the image valid signal MRE, and detects subsequent errors. The data is output to the comparison circuit 23.

  The integration circuit 22 integrates the value of the image data signal DATA pixel by pixel from the beginning of the interval for each interval, and calculates the integrated value of the image data signal DATA (that is, image data) for the interval. Specifically, the integration circuit 22 identifies each section with reference to the assertion start timing of the image valid signal MRE, and calculates the checksum of the image data of each identified section.

  The comparison circuit 23 compares the received error detection data with the integrated value of the image data signal DATA calculated by the integrating circuit 22, and determines whether or not they match (or the difference between the two exceeds a predetermined threshold value). A comparison result indicating whether or not) is output.

  When no error is detected based on the comparison result, the line memory control unit 24 alternately writes the image data in the received image data signal DATA to the line memories 25-1 and 25-2 line by line, and the image data Are alternately read from the line memories 25-1 and 25-2 line by line.

  When an error is detected based on the comparison result, the line memory control unit 24, as the image data of the line where the error is detected, for the section before the section where the error is detected, Image data is read from one of the line memories 25-1 and 25-2, and at least for the section in which an error is detected, the image data of the line one line before the line in which the error is detected is stored in the line memories 25-1, 25-1. Read from the other of 25-2.

  The line memories 25-1 and 25-2 constitute a double buffer.

  The image processing unit 26 performs predetermined image processing on the image data read from the line memories 25-1 and 25-2.

  Next, the operation of the image processing apparatus will be described.

  FIG. 2 is a timing chart showing signals (horizontal synchronization signal HSYNC, image valid signal MRE, and image data signal DATA) transmitted from the transmission-side device 1 in FIG. FIG. 3 is a timing chart for explaining the operation of the reception-side device 2 in the first embodiment. FIG. 4 is a timing chart illustrating details of the operation of the reception-side device 2 in the first embodiment.

  As described above, the transmission-side device 1 transmits the horizontal synchronization signal HSYNC, the image valid signal MRE, and the image data signal DATA.

  As shown in FIG. 2, error detection data that is an integrated value for each of a plurality of sections # 1 to # 4 of the image data in the image data signal DATA is output following the image data signal DATA.

  Then, the image valid signal MRE is asserted in the transfer period of the image data signal DATA and the error detection data.

  On the other hand, the receiving side device 2 receives the horizontal synchronization signal HSYNC, the image valid signal MRE, and the image data signal DATA, and further receives error detection data of each section in the image data signal DATA, and each section of each line. , Whether or not an error has occurred is determined based on the received error detection data and the integrated value of the received image data signal DATA in that interval.

  As shown in FIG. 3, if no error is detected, the image data based on the received image data signal DATA is alternately written to the line memories 25-1 and 25-2 line by line, line by line. The data is alternately read from the line memories 25-1 and 25-2.

  Then, when an error is detected in a certain section #j (for example, section # 3 in FIG. 3) for a certain line (i), as shown in FIGS. 3 and 4, the section before the section #j (FIG. 3). 4 and FIG. 4, the image data of the section # 1, # 2) is read from the image data in the line memory 25-2 (that is, the image data of the line (i)). In FIG. 3 and FIG. 4, the image data of the line memory 25-1 (that is, the image data of the line (i-1)) is read and used as the image data of the sections # 3 and # 4).

  The line memories 25-1 and 25-2 use dual accessible memories, and the image data of the line (i + 1) is overwritten sequentially from the portion where the reading of the image data of the line memory 25-1 is completed. Go.

  As described above, in the first embodiment, the line memory control unit 24, in the line (i) where the error is detected by the error detection data, (a) the section before the section where the error is detected (FIG. 3 and FIG. 4, the image data of the line in which the error is detected is read from one of the line memories 25-1 and 25-2 (in FIG. 3 and FIG. 4, the line memory 25-2) for the section # 1 and # 2). b) At least for the section in which an error is detected, the line memory 25-1, 25-2 (line memory 25-1 in FIGS. 3 and 4) from the other of the line memories 25-1, 25-2 Reads the image data of the line (i-1) and is parallel to the reading from the other of the line memories 25-1 and 25-2 (the line memory 25-1 in FIGS. 3 and 4). The image data of the line (i + 1) next to the line (i) where the error is detected is transferred to the other of the line memories 25-1 and 25-2 (line memory 25-1 in FIGS. 3 and 4). Perform writing.

  In the first embodiment, the line memory control unit 24, in the line (i) where the error is detected by the error detection data, the section in which the error is detected and the section after the section in which the error is detected (FIG. 3). In FIG. 4 and FIG. 4, the section # 3, # 4) is read from the other of the line memories 25-1, 25-2 (the line memory 25-1 in FIGS. 3 and 4), and the line memories 25-1, 25 are read. -2 (in FIG. 3 and FIG. 4, the line memory 25-1) is read in parallel with the other of the line memories 25-1 and 25-2 (in FIG. 3 and FIG. 4, in the line memory 25-1). ), The image data of the line (i + 1) following the line (i) where the error is detected is written.

  As described above, according to the first embodiment, the transmission-side apparatus 1 detects error detection data of image data in each of a plurality of sections obtained by dividing a transfer period of image data for one line by a predetermined number. And the image data and error detection data are transmitted as an image data signal DATA. The receiving side apparatus 2 receives the image data signal DATA, and an error is detected in a section before the section in which the error is detected in the line in which the error is detected by the error detection data in the image data signal DATA. The image data of the line is used, and at least for the section where the error is detected, the image data of the line one line before the line where the error is detected is used.

  Thereby, the location where the error has occurred is corrected without discarding many images of valid pixels in which no error has occurred.

  In the first embodiment, for the line in which the error is detected, the image of the line in which the error is detected is used as it is as the image in the section before the section in which the error is detected. As the image of the section, the image of the line immediately before the line where the error is detected is used. Therefore, the image in the section before the section in which the error is detected is used without being discarded. In addition, since the image one line before is used for the section in which the error is detected, even if errors occur continuously, the image where the error occurs does not have to be a single value.

Embodiment 2. FIG.

  FIG. 5 is a timing chart for explaining the operation of the reception-side device 2 in the second embodiment. In the second embodiment, as shown in FIG. 5, the line memory control unit 24 starts from the section where the error is detected (section # 3 in FIG. 5) in the line (i) where the error is detected by the error detection data. For the subsequent section (section # 4 in FIG. 5), the image of the line (i) in which an error is detected from one of the line memories 25-1 and 25-2 (line memory 25-2 in FIG. 5). Read data. That is, in the second embodiment, the image data of the previous line (i-1) is used for the section in which the error is detected as the image data of the line (i) in which the error is detected. The image data of the line (i) is used for the section.

  Note that other configurations and operations of the image processing apparatus according to the second embodiment are the same as those of the first embodiment, and thus description thereof is omitted.

Embodiment 3 FIG.

  FIG. 6 is a timing chart for explaining details of the operation of the reception-side device 2 in the third embodiment. In the third embodiment, as shown in FIG. 6, in the image data signal DATA, a predetermined interval is provided between the image data and the error detection data, and the image valid signal MRE output from the transmission side apparatus 1 is Asserted in the transfer period of the image data, negated in the interval, and asserted again in the transfer period of the error detection data.

  Thereby, the image data and the error detection data are accurately separated from each other based on the assertion period of the image valid signal MRE. That is, even if the data length of the image data changes due to errors such as noise, the error detection data is accurately extracted because it is synchronized with the second assertion period of the image valid signal MRE.

  Note that other configurations and operations of the image processing apparatus according to the third embodiment are the same as those in the first or second embodiment, and thus description thereof is omitted.

  Various changes and modifications to the above-described embodiment will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the subject matter and without diminishing its intended advantages. That is, such changes and modifications are intended to be included within the scope of the claims.

  For example, in the above embodiment, the integrated value (that is, checksum) of the image data signal DATA of each section is used as error detection data of each section. Instead, the image data signal DATA of each section is used. A known error detection code (parity or the like) obtained from the above may be used.

  The present invention is applicable to an image forming apparatus such as a multifunction machine.

1 Transmitting device 2 Receiving device

Claims (4)

A transmitting side device for transmitting an image data signal;
A receiving side device for receiving the image data signal,
The transmission side device generates error detection data of image data in each of a plurality of sections obtained by dividing a transfer period of image data for one line by a predetermined number, and the image data and the error detection data are converted into an image. Send as data signal,
The receiving side device receives the image data signal, and in the line where the error is detected by the error detection data in the image data signal, the error is detected in a section before the section where the error is detected. Using the image data of the detected line, at least for the section where the error is detected, use the image data of the line one line before the line where the error is detected ,
The receiving side device includes a double buffer including a first line memory and a second line memory, and a line memory control unit,
The line memory control unit writes the image data in the received image data signal alternately to the first line memory and the second line memory line by line, and writes the image data line by line to the first line memory. Read from the line memory and the second line memory;
The line memory control unit includes: (a) image data of the line in which the error is detected in a section before the section in which the error is detected in the line in which the error is detected by the error detection data; Read from one of the line memory and the second line memory. (B) At least for the section in which the error is detected, from the other of the first line memory and the second line memory, In parallel with reading from the other one of the first line memory and the second line memory, the error to the other of the first line memory and the second line memory is read out. Executing writing of the image data of the line next to the detected line;
An image processing apparatus. The line memory control unit, in a line in which an error is detected by the error detection data, for a section after the section in which the error is detected, from the other of the first line memory and the second line memory, The first line memory and the second line memory are read in parallel with the reading from the other of the first line memory and the second line memory, reading image data one line before the line where the error is detected. the image processing apparatus according to claim 1, wherein the said error to the other and executes the writing of the image data of the next line of the detected line. The line memory control unit, in a line in which an error is detected by the error detection data, for a section after the section in which the error is detected, from the one of the first line memory and the second line memory, the image processing apparatus according to claim 1, wherein the read out image data of a line in which the error is detected. A transmitting side device for transmitting an image data signal;
A receiving side device for receiving the image data signal,
The transmission side device generates error detection data of image data in each of a plurality of sections obtained by dividing a transfer period of image data for one line by a predetermined number, and the image data and the error detection data are converted into an image. Send as data signal,
The receiving side device receives the image data signal, and in the line where the error is detected by the error detection data in the image data signal, the error is detected in a section before the section where the error is detected. Using the image data of the detected line, at least for the section where the error is detected, use the image data of the line one line before the line where the error is detected,
The transmission-side device asserts an image valid signal in the image data transfer period and the error detection data transfer period in the image data signal, and between the image data transfer period and the error detection data transfer period In the interval, the image valid signal is negated,
The receiving side device separates the image data signal into the image data and the error detection data based on an assertion period of the image valid signal;
Images processor said.

Images