JP6413777B2 - Electronic circuit device and test device - Google Patents

Description

  The present case relates to an electronic circuit device and a test device.

  The boundary scan test defined by IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 1149.1 is, for example, a connection between terminals (Large Scale Integration) mounted on a circuit board. Confirmation is possible (see, for example, Patent Documents 1 and 2). According to the boundary scan test, it is possible to detect a solder failure of a terminal, a short circuit and an open of a wiring even in an LSI such as a BGA (Ball Grid Array) type in which the terminal state is not directly visible.

JP 2004-325124 A JP 7-152595 A

  However, when the boundary scan test function of the LSI itself is in a failure state or an unstable state, normal confirmation is impossible. For example, if there is an LSI with an error in the boundary scan register on the JTAG (Joint Test Action Group) chain, the location that is determined to be defective changes each time a boundary scan test is performed, so the defective LSI is identified. Can not do it. In this case, the LSI must be discarded along with the circuit board, and the loss is greater than when only the abnormal LSI is discarded. Furthermore, even if an abnormal LSI can be identified by analysis using a measuring instrument, there is a problem that much time is consumed.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide an electronic circuit device and a test device that detect an abnormal boundary scan register.

  An electronic circuit device described in the present specification includes a plurality of register circuits that sequentially hold and output values input by executing a boundary scan test, and input values and output values of the register circuits of the plurality of stages. The output value of the register circuit in which the input value and the output value do not coincide with each other as a result of the comparison by the comparison circuit among the plurality of register circuits, and the fixed value is And a control circuit that switches the fixed value to another value after being output.

  The test apparatus described in the present specification is a test apparatus that performs a boundary scan test of an electronic circuit device provided with a plurality of register circuits that sequentially hold and output input values. An output unit that sequentially outputs a value according to a predetermined pattern; and an output value of a register circuit in which the input value and the output value do not match among the plurality of register circuits for the electronic circuit device. By fixing the fixed value and outputting the fixed value, the instruction unit for instructing to switch the fixed value to another value, and detecting the boundary at which the values sequentially output from the plurality of register circuits are switched And a specifying unit for specifying a register circuit in which an input value and an output value do not match among the plurality of register circuits.

  An abnormal boundary scan register can be detected.

It is a block diagram which shows an example of the test system of a boundary scan test. It is a block diagram which shows an example of the device of a test object. It is a figure which shows an example of operation | movement when the connection between the terminals of devices is normal, and an input value of serial data, an output value, and an expected value. It is a figure which shows an example when the connection between the terminals of devices is abnormal, and an example of the input value of serial data, an output value, and an expected value. It is a figure which shows an example of the operation | movement when a boundary scan register is abnormal, and the input value of serial data, an output value, and an expected value. It is a figure which shows the other example of operation | movement when a boundary scan register is abnormal, and the input value of serial data, an output value, and an expected value. It is a block diagram which shows the comparative example of a boundary scan cancellation. It is a block diagram which shows an example of the comparison means of the input value of a boundary scan register, and an output value. It is a table | surface which shows the shift operation at the time of normal and abnormal. It is a block diagram which shows an example of the structure which added the comparison circuit to the boundary scan cell. It is a block diagram which shows the other example of the comparison means of the input value of a boundary scan register, and an output value. It is a block diagram which shows the other example of the structure which added the comparison circuit to the boundary scan cell. It is a block diagram which shows the other example of the comparison means of the input value of a boundary scan register, and an output value. It is a block diagram which shows the other example of the structure which added the comparison circuit to the boundary scan cell. It is a table | surface which shows the shift operation at the time of normal and abnormal. It is a block diagram which shows an example of the structure which added the control circuit to the boundary scan cell. It is a flowchart which shows the process of a test device. It is a figure which shows the set value of the boundary scan register at the time of initialization, abnormality reproduction, and output control. It is a flowchart which shows the process of a device. It is a block diagram which shows an example of a test apparatus.

  FIG. 1 is a configuration diagram illustrating an example of a test system for a boundary scan test. The test system includes a terminal device 90 such as a personal computer, a test device 91 for a boundary scan test, and a circuit board 92 to be tested.

  The terminal device 90 acquires various test pattern data generated based on information about devices and wirings mounted on the circuit board 92 from, for example, a server via a network. The terminal device 90 transmits the test pattern data to the test device 91, receives test result data from the test device 91, and displays the result on a display device such as a display.

  The test apparatus 91 generates a data signal TDI (Test Data In) and a clock signal TCK (Test Clock) based on the test pattern data input from the terminal apparatus 90, and outputs the data signal TDI (Test Clock In) to the circuit board 92. Further, the test apparatus 91 generates a TAP (Test Access Port) controller state control signal TMS (Test Mode Select) and a reset signal TRST (Test Reset) based on the test pattern data, and outputs them to the circuit board 92. The test apparatus 91 receives a data signal TDO (Test Data Out) output from the circuit board 92, generates test result data based on the data signal TDO, and outputs it to the terminal apparatus 90.

  The circuit board 92 shifts to the test mode in accordance with each signal TDI, TCK, TMS, TRST input from the test apparatus 91, and executes data shift of the boundary scan register. The circuit board 92 outputs a data signal TDO to the test apparatus 91 as a test result. A plurality of devices including a TAP controller whose state transitions according to the state control signal TMS are mounted on the circuit board 92.

  FIG. 2 is a configuration diagram illustrating an example of a device to be tested. FIG. 2 shows two devices 1a and 1b connected to each other as an example, but the number of connected devices and the connection form are not limited.

  The devices 1a and 1b are an example of an electronic circuit device such as an LSI corresponding to a boundary scan test. The devices 1a and 1b include a plurality of external terminals T, a plurality of stages of boundary scan cells BC connected to the plurality of external terminals T, an internal logic circuit 10 connected to each of the boundary scan cells BC, and a TAP controller 11. And have.

  In addition to the external terminal T, the devices 1a and 1b are provided with terminals corresponding to the signals TDI, TCK, TMS, TRST, and TDO of the boundary scan test. In the following description, the terminals of the data signals TDI and TDO are denoted as TDI and TDO, respectively.

  The internal logic circuit 10 is a logic circuit that realizes the functions of the devices 1a and 1b. Signals are input to and output from the internal logic circuit 10 via a plurality of external terminals T. Some of the external terminals T of the devices 1 a and 1 b are connected to each other via a wiring W on the circuit board 92.

  The TAP controller 11 receives a state control signal TMS, a reset signal TRST, and a clock signal TCK. The TAP controller 11 is connected to a plurality of boundary scan cells BC, and executes a boundary scan test sequence by making a state transition in accordance with the state control signal TMS. Note that the TAP controller 11 transitions to the initial state in response to the input of the reset signal TRST.

  The multi-stage boundary scan cell BC is an example of a multi-stage register circuit that sequentially holds and outputs values input by executing the boundary scan test. The boundary scan cells BC in a plurality of stages are connected in series between the input terminal TDI and the output terminal TDO, and hold the input value as a boundary scan register by latching the input value using the edge of the clock signal TCK as a trigger.

  The devices 1a and 1b are connected to each other on the JTAG chain. That is, the output terminal TDO of one device 1a is connected to the input terminal TDI of the other device 1b. For this reason, the multi-stage boundary scan cell BC of each device 1a, 1b functions as a shift register across both devices 1a, 1b.

  More specifically, the boundary scan cell BC holds serial data input from the input terminal TDI or the previous boundary scan cell BC as a boundary scan register in synchronization with the clock signal TCK, and the subsequent boundary scan cell BC. Or output to the subsequent boundary scan cell BC and the output terminal TDO. That is, the plurality of boundary scan cells BC sequentially shift the value of the boundary scan register from the front stage to the rear stage. The serial data output from the output terminal TDO of the device 1b is input to the test apparatus 91.

  In the boundary scan test of this embodiment, the connection between the terminals T of the devices 1a and 1b is inspected. Hereinafter, the operation of the boundary scan cell BC will be described.

  FIG. 3A shows an example of the operation when the connection between the terminals T of the devices 1a and 1b is normal. FIG. 3A shows a part of the terminal T of the devices 1a and 1b in FIG. FIG. 3B shows an example of the input value, output value, and expected value of serial data for each boundary scan cell BC.

  The device 1a is provided with boundary scan cells BC # 1 to # 5 connected in series, and the device 1b is provided with boundary scan cells BC # 6 to # 10 connected in series. The boundary scan cells BC # 1 to # 5 of the device 1a are connected to the boundary scan cells BC # 6 to # 10 of the other device 1b via the wiring W, respectively. The boundary scan cells BC # 5 and # 6 are connected to each other via terminals TDI and TDO.

  “1”, “0”, “1”, “0”, “1” (binary numbers) are input to the boundary scan cells BC # 1 to # 5 as examples of input values of serial data. The input values of the device 1a boundary scan cells BC # 1 to # 5 are held as boundary scan registers, and then output to the boundary scan cells BC # 6 to # 10 of the device 1b via the wiring W between the terminals T. . For example, the input value “1” is output as a high level voltage ‘H’, and the input value “0” is output as a low level voltage ‘L’.

  Thereby, the boundary scan cells BC # 6 to # 10 hold “1”, “0”, “1”, “0”, “1”. The values of the boundary scan registers held in the boundary scan cells BC # 1 to BC # 10 are output from the output terminal TDO of the device 1b by the shift operation, and collated with a predetermined expected value in the test apparatus 91. Note that the expected value is held in the test apparatus 91 in advance.

  The test apparatus 91 has serial data output values “1”, “0”, “1”, “0”... With expected values “1”, “0”, “1”, “0”. Since they match, it is determined that the connection between the terminals T of the devices 1a and 1b is normal.

  On the other hand, FIG. 4A shows an example of the operation when the connection between the terminals T of the devices 1a and 1b is abnormal. In FIG. 4 (a), the same components as those in FIG. 3 (a) are denoted by the same reference numerals, and the description thereof is omitted. FIG. 4B shows an example of the input value, output value, and expected value of serial data for each boundary scan cell BC.

  In this example, the connection between the terminals T of the boundary scan cells BC # 1 and # 10 is in an open state due to a defect in the wiring W (see the x mark). For this reason, the value “1” of the boundary scan register held in the boundary scan cell BC # 1 is output to the boundary scan cell BC # 10 as the high level voltage “H”, but the boundary scan cell BC # 10 Holds “0”.

  Therefore, the output value from the boundary scan cell BC # 10 to the test apparatus 91 is “0”. Since the output value “0” of the boundary scan cell BC # 10 does not match the expected value “1” (see reference numeral E1), the test apparatus 91 determines the connection between the terminals T of the boundary scan cells BC # 1 and # 10. Detect anomalies. Thereby, as a test result, it is determined that there is a solder defect, a cut, or a ground short in each terminal T of the boundary scan cells BC # 1 and # 10 or the wiring W between the terminals T.

  However, when the boundary scan test function itself of the devices 1a and 1b is in a failure state or an unstable state, normal confirmation is impossible. For example, even when there is an abnormality in the boundary scan register of the device 1a, the location determined to be defective changes every time the boundary scan test is performed, and thus the defective device 1a cannot be specified. The operation when the boundary scan register is abnormal will be described below with an example.

  FIG. 5A shows an example of the operation when the boundary scan register is abnormal. In FIG. 5 (a), the same reference numerals are given to components common to FIG. 3 (a), and description thereof is omitted. FIG. 5B shows an example of the input value, output value, and expected value of serial data for each boundary scan cell BC.

  When the boundary scan cell BC # 3 is in an unstable state, each time a shift operation is performed, a case where a normal value is held and a case where an abnormal value is held randomly occur. In this example, the boundary scan cell BC # 3 has normal values “0” and “0” in the shift operation that holds the input values “0” and “1” of the subsequent boundary scan cancels BC # 4 and BC # 5. 1 ”is held. However, the boundary scan cell BC # 3 holds an abnormal value “0” in the shift operation that holds its own input value “1”.

  That is, the boundary scan cell BC # 3 succeeds in the shift operation that holds the input values of the boundary scan cells BC # 4 and BC # 5, but the shift operation that holds its own input value "1" Failed due to latch failure. As a result, the boundary scan cancel BC # 3 holds the erroneous boundary scan register value “0” (the correct value is “1”). Since the value “0” of the boundary scan register is output to the boundary scan cell BC # 8 as the low level voltage “L”, the boundary scan cell BC # 8 holds “0”.

  Therefore, the output value from the boundary scan cell BC # 8 to the test apparatus 91 is “0”. Since the output value “0” of the boundary scan cell BC # 8 does not match the expected value “1” (see symbol E2), the test apparatus 91 is normal, but the boundary scan cell BC # 3, ## An abnormality in connection between the eight terminals T is detected.

  FIG. 6A shows another example of the operation when the value held in the boundary scan register is abnormal. In FIG. 6 (a), the same reference numerals are given to components common to FIG. 3 (a), and description thereof is omitted. FIG. 6B shows other examples of input values, output values, and expected values of serial data for each boundary scan cell BC.

  In this example, the boundary scan cell BC # 3 is different from the case of FIG. 5A and FIG. 5B, and the input values “1” and “0” of the boundary scan cell BC # 4 of the self and the subsequent stage. In the shift operation that holds “”, normal values “1” and “0” are held. However, the boundary scan cancel BC # 3 holds an abnormal value “0” in the shift operation that holds the input value “1” of the subsequent boundary scan cancel BC # 5. That is, since the value “1” to be set to the boundary scan cell BC # 5 passes the unstable boundary scan cell BC # 3, the shift operation has failed due to a latch failure. "0" is shifted to the subsequent boundary scan cell BC # 4.

  As a result, the boundary scan cancel BC # 5 holds the wrong boundary scan register value “0” (the correct value is “1”). Therefore, the value “0” of the boundary scan register is output to the boundary scan cell BC # 6 as the low-level voltage “L”, and thus the boundary scan cell BC # 6 holds “0”.

  Therefore, the output value from the boundary scan cell BC # 6 to the test apparatus 91 is “0”. Since the output value “0” of the boundary scan cell BC # 6 does not match the expected value “1” (see symbol E3), the test apparatus 91 is normal, but the boundary scan cell BC # 5, ## An abnormality in connection between the six terminals T is detected.

  Next, the configuration of the boundary scan cell BC will be described. FIG. 7 is a configuration diagram illustrating a comparative example of the boundary scan cell BC. In FIG. 7, BC_1 is raised as an example of the boundary scan cell BC, but is not limited to this, and BC_2 to BC_10 may be used.

  The boundary scan cell BC has selectors 20 and 23 and flip-flops 21 and 22. In accordance with a control signal ShiftDR (Shift Data Register) from the TAP controller 11, the selector 20 selects one of the input value from the external terminal T and the input value from the previous boundary scan cell BC (or input terminal TDI) and flip-flops Output to the group 21. When the flip-flop 21 detects the rising edge of the clock signal ClockDR (Clock Data Register) from the TAP controller 11, it latches the input value from the selector 20 and holds it as a boundary scan register.

  The value held by the flip-flop 21 is output to the subsequent boundary scan cell BC (or the output terminal TDO) and the other flip-flops 22. When the flip-flop 22 detects the rising edge of the control signal UpdateDR (Update Data Register) from the TAP controller 11, the flip-flop 22 holds the input value from the flip-flop 21 and outputs it to the selector 23.

  The selector 23 selects one of the input value from the internal logic circuit 10 and the input value from the flip-flop 22 according to the control signal Mode from the TAP controller 11 and outputs the selected value to the external terminal T. The control signals ShiftDR, UpdateDR, and Mode are output according to the state transition of the TAP controller 11, and the clock signal ClockDR is generated based on the clock signal TCK.

  When the boundary scan cell BC performs a serial data shift operation, the selector 20 selects an input value from the previous boundary scan cell BC (or input terminal TDI) and outputs it to the flip-flop 21 as shown by the solid line. To do. The flip-flop 21 holds the input value and outputs it to the subsequent boundary scan cell BC (or the output terminal TDO).

  In the above example, when the boundary scan cell BC of one device 1a outputs a value to the boundary scan cell BC of the other device 1b via the wiring W, the flip-flop 22 is indicated by a dotted line. The input value from the other flip-flop 21 is held and output to the selector 23. The selector 23 selects the input value from the flip-flop 22 and outputs it to the external terminal T. As a result, the value held in the flip-flop 21 is input to the boundary scan cell BC of the other device 1b via the wiring W.

  Further, when one device 1b holds the input value from the other device 1a in the boundary scan cell BC, the selector 20 selects the input value from the external terminal T as shown by the alternate long and short dash line, and the flip-flop To 21. The flip-flop 21 holds the input value.

  Thus, the boundary scan cell BC holds the input value of the shift data in the flip-flop 21 as a boundary scan register. For this reason, when the flip-flop 21 is defective, the boundary scan register becomes abnormal as described above.

  Therefore, in order to detect an abnormal boundary scan register, the devices 1a and 1b of the present embodiment are provided with a comparison circuit that compares the input value and the output value of each boundary scan register and outputs the comparison result. Yes.

  FIG. 8 is a block diagram showing an example of a means for comparing the input value and the output value of the boundary scan register. FIG. 8 shows the flip-flops 21 of the multiple stages of boundary scan cells BC connected in series. The plurality of flip-flops 21 perform a shift operation of the serial data input from the input terminal TDI and output from the output terminal TDO.

  The comparison circuit 3a includes flip-flops 30 (# 1, #) provided corresponding to the flip-flops 21 (# 1, # 2,..., #N (N: positive integer)) of each boundary scan cell BC. 2,..., #N) and an XOR (exclusive OR) circuit 31. Each flip-flop 30 holds the input value of the flip-flop 21 and outputs it to the XOR circuit 31 when detecting the rising edge of the clock signal ClockDR.

  The XOR circuit 31 calculates the exclusive OR of the input value from the flip-flop 30 and the input value from the flip-flop 21 of the boundary scan cell BC, and outputs the operation values EX1, EX2,. Is output. That is, the XOR circuit 31 calculates the exclusive OR of the input value and the output value (holding value) of the flip-flop 21 in synchronization with the clock signal ClockDR. Thereby, the comparison circuit 3a compares the input value and the output value of each of the plurality of stages of the boundary scan cell BC.

  FIG. 9A and FIG. 9B show the shift operations at normal time and abnormal time, respectively. 9A and 9B show the input values a, b,..., F (binary number) of serial data input from the input terminal TDI, and the flip-flops 21 and 30 (# 1, #). 2, #N) and the operation values EX1, EX2, and EXn of the XOR circuit 31 are shown. In this example, the number of flip-flops 21 and 30 is three (that is, N = 3).

  In this example, serial data a, b,..., F are sequentially input to the input terminal TDI in synchronization with the clock signal ClockDR. When the shift operation is normal, as shown in FIG. 9A, each of the flip-flops 21 and 30 (# 1, # 2, and #N) is synchronized with the clock signal ClockDR so that the serial data a, b, .., F are sequentially held and output. The operation values EX1, EX2, and EXn of the XOR circuit 31 are all “0” because the input values from the flip-flops 21 and 30 (# 1, # 2, and #N) always match.

  On the other hand, when the shift operation is abnormal, as shown in FIG. 9B, for example, when the input value b is input from the input terminal TDI, the flip-flop 21 (# 1) A different input value x is held (see symbol E4). As a result, the operation value EX1 of the XOR circuit 31 becomes “1” because the input values from the flip-flops 21 and 30 (# 1) do not match (see reference numeral E5).

  FIG. 10 is a configuration diagram illustrating an example of a configuration in which a comparison circuit 3a is added to the boundary scan cell BC. FIG. 10 shows the configuration of the comparison circuit 3a corresponding to one boundary scan cell BC. The comparison circuit 3 a includes a flip-flop 32 in addition to the flip-flop 30 and the XOR circuit 31 described above.

  The flip-flop 30 holds the input value from the selector 20 and outputs it to the XOR circuit 31 in synchronization with the clock signal ClockDR. The XOR circuit 31 calculates an exclusive OR of the input values of the flip-flops 21 and 30 and outputs an operation value EXn to the flip-flop 32. When the flip-flop 32 detects the rising edge of the clock signal ClockDR, the flip-flop 32 holds and outputs the operation value EXn.

  In this way, during the shift operation, the comparison circuit 3a compares the input value and the output value of the flip-flop 21 by the XOR circuit 31, and outputs the comparison results (EX1, EX2,..., EXn).

  FIG. 11 is a block diagram showing another example of the comparison means for the input value and the output value of the boundary scan register. In FIG. 11, the flip-flops 21 of the multi-stage boundary scan cell BC are shown in a form connected in series. The plurality of flip-flops 21 perform a shift operation of the serial data input from the input terminal TDI and output from the output terminal TDO.

  The comparison circuit 3b includes flip-flops 30 (# 1, # 2,..., #N) provided corresponding to the flip-flops 21 (# 1, # 2,..., #N) of each boundary scan cell BC. And an XOR circuit 31. Unlike the example of FIG. 8, the flip-flops 30 (# 1, # 2,..., #N) are connected in series with each other. Therefore, the flip-flops 30 (# 1, # 2,..., #N) perform a serial data shift operation in synchronization with the flip-flops 21 (# 1, # 2,..., #N).

  When the flip-flop 30 (# 1) detects the rising edge of the clock signal ClockDR, the flip-flop 30 (# 1) holds the input value of the flip-flop 21 (# 1) and sends it to the XOR circuit 31 and the subsequent flip-flop 30 (# 2). Output. The XOR circuit 31 calculates the exclusive OR of the input value from the flip-flop 30 (# 1) and the input value from the flip-flop 21 (# 1), and outputs an operation value EX1.

  When the rising edge of the clock signal ClockDR is detected, the flip-flop 30 (# 2) holds the input value from the preceding flip-flop 30 (# 1), and the XOR circuit 31 and the subsequent flip-flop 30 (# 3) ). The XOR circuit 31 calculates an exclusive OR of the input value from the flip-flop 30 (# 2) and the input value from the flip-flop 21 (# 2), and outputs an operation value EX2. The flip-flops 30 (# 2,..., #N) subsequent to the flip-flop 30 (# 1) also operate in the same manner as described above.

  As described above, the XOR circuit 31 calculates the exclusive OR of the output values (holding values) of the flip-flops 21 and 30 in synchronization with the clock signal ClockDR. Thereby, the comparison circuit 3a compares the input value and the output value of each of the plurality of stages of the boundary scan cell BC. Note that the shift operation in this example is the same as in FIGS. 9A and 9B.

  FIG. 12 is a configuration diagram illustrating an example of a configuration in which a comparison circuit 3b is added to the boundary scan cell BC. FIG. 12 shows the configuration of the comparison circuit 3b corresponding to the first and second boundary scan cells BC as an example. The comparison circuit 3b includes a flip-flop 32 in addition to the flip-flop 30 and the XOR circuit 31 described above.

  The first-stage flip-flop 30 (# 1) holds the input value from the selector 20 in synchronization with the clock signal ClockDR, and outputs it to the XOR circuit 31 and the subsequent-stage flip-flop 30 (# 2). The XOR circuit 31 calculates the exclusive OR of the input values of the flip-flops 21 and 30 (# 1), and outputs the operation value EX1 to the flip-flop 32 (# 1). When the flip-flop 32 (# 1) detects the rising edge of the clock signal ClockDR, the flip-flop 32 (# 1) holds and outputs the operation value EX1.

  The second-stage flip-flop 30 (# 2) holds the input value from the previous-stage flip-flop 30 (# 1) in synchronization with the clock signal ClockDR, and the XOR circuit 31 and the subsequent-stage flip-flop 30 (#) Output to 3). The XOR circuit 31 calculates an exclusive OR of the input values of the flip-flops 21 and 30 (# 2), and outputs an operation value EX2 to the flip-flop 32 (# 2). When the flip-flop 32 (# 2) detects the rising edge of the clock signal ClockDR, it holds and outputs the operation value EX2.

  FIG. 13 is a block diagram showing another example of the comparison means for the input value and the output value of the boundary scan register. In FIG. 13, the flip-flops 21 and 21a of the boundary scan cells BC of a plurality of stages are shown in a form connected in series. The plurality of flip-flops 21 and 21a perform a shift operation of serial data input from the input terminal TDI and output from the output terminal TDO.

  In this example, even-numbered boundary scan cells BC # 2, # 4,... Are provided with a first flip-flop 21, and odd-numbered boundary scan cells BC # 1, # 3,. A second flip-flop 21 a having a trigger different from that of the first flip-flop 21 is provided. That is, the first flip-flops 21 and the second flip-flops 21a are alternately provided in the multi-stage boundary scan cell BC.

  When detecting the rising edge of the clock signal ClockDR, the first flip-flop 21 holds and outputs the input value. On the other hand, when the second flip-flop 21a detects the falling edge of the clock signal ClockDR, the second flip-flop 21a holds and outputs the input value.

  The comparison circuit 3c includes an XOR circuit 31 connected to each first flip-flop 21 and each second flip-flop 21a. The XOR circuit 31 is an example of an arithmetic circuit that calculates an exclusive OR of an input value and an output value for each of the first flip-flop 21 and the second flip-flop 21a.

  The XOR circuit 31 calculates the exclusive OR of the input value and the output value of the first flip-flop 21 and the second flip-flop 21a, and outputs the calculated values EX1, EX2, EX3, EX4,. Thereby, the comparison circuit 3c compares the input value and the output value of each of the plural stages of the boundary scan cell BC.

  FIG. 14 is a configuration diagram showing another example of the configuration in which the comparison circuit 3c is added to the boundary scan cell BC. FIG. 14 shows the configuration of the comparison circuit 3c corresponding to a set of odd-numbered and even-numbered boundary scan cells BC # i and # i + 1 (i: odd) connected to each other. The comparison circuit 3c includes flip-flops 32a and 32b in addition to the XOR circuit 31 described above.

  The odd-numbered XOR circuit 31 has an input value from the second flip-flop 21a (#i) and an input value from the first flip-flop 21 (# i-1) of the previous (even-numbered) boundary scan cell BC. And the operation value EXi is output to the flip-flop 32a. When the flip-flop 32a detects the rising edge of the clock signal ClockDR, the flip-flop 32a holds and outputs the operation value EXi.

  The even-numbered XOR circuit 31 includes an input value from the first flip-flop 21 (# i + 1) and an input value from the first flip-flop 21a (#i) of the previous stage (odd-numbered) boundary scan cell BC. The exclusive OR is calculated and the calculated value EXi + 1 is output to the flip-flop 32b. When detecting the falling edge of the clock signal ClockDR, the flip-flop 32b holds and outputs the operation value EXi + 1.

  FIGS. 15 (a) and 15 (b) show the shift operations during normal operation and abnormal operation, respectively, in this example. 15A and 15B show the clock signal ClockDR, the input values a, b,..., F of the serial data input from the input terminal TDI, and the first flip-flops 21 (# 2, #). 4) and output values of the second flip-flops 21a (# 1, # 3). 15A and 15B show the output values of the flip-flops 32a (# 1, # 3) and 32b (# 2 and # 4) of the comparison circuit 3c and the operations of the XOR circuits 31. FIG. The values EX1 to EX4 are indicated.

  In this example, serial data a, b,..., F are sequentially input to the input terminal TDI in synchronization with the clock signal ClockDR. When the shift operation is normal, as shown in FIG. 15A, each of the flip-flops 21 and 21a (# 1 to # 4) has serial data a, b,... In synchronization with the clock signal ClockDR. , F are sequentially held and output. As a result, the serial data a, b,..., F are shifted every half cycle of the clock signal ClockDR.

  Accordingly, the first flip-flop 21 (# 2, # 4) and the second flip-flop 21a (# 1, # 3) have the same input value and output value (holding value) for each half cycle of the clock signal ClockDR. For this reason, the operation values EX1 to EX4 of each XOR circuit 31 repeat “1” (mismatch state) and “0” (match state) every half cycle of the clock signal ClockDR.

  However, since the odd-numbered flip-flops 32a (# 1, # 3) perform a latch operation using the rising edge of the clock signal ClockDR as a trigger, the correct state “0” is held and output as the operation values EX1, EX3. To do. Similarly, even-numbered flip-flops 32b (# 2, # 4) perform a latch operation with the falling edge of the clock signal ClockDR as a trigger, and thus hold “0”, which is the correct state, as the operation values EX2, EX4. Output.

  When the shift operation is abnormal, for example, when the input value a is input from the input terminal TDI, the flip-flop 21a (# 1) holds the input value x different from the input value a (see symbol E6). As a result, the operation value EX1 of the XOR circuit 31 becomes “1” because the input value and the output value of the flip-flop 21a (# 1) do not match (see reference numeral E7). When the flip-flop 32a (# 1) detects the rising edge of the clock signal ClockDR, the flip-flop 32a (# 1) holds and outputs the calculated value EX1 (= “1”).

  In this manner, during the shift operation, the comparison circuit 3c compares the input values and output values of the flip-flops 21 and 21a by the XOR circuit 31, and outputs the comparison results (EX1 to EX4).

  Further, in this example, the first flip-flop 21 and the second flip-flop 21a having different triggers for holding the input value are alternately provided, which is different from the examples shown in FIGS. The flip-flop 30 can be omitted from the comparison circuit 3c.

  The calculation values EX1 to EXn obtained by the above-described configuration are output to the test apparatus 91 from a dedicated terminal, for example. For example, the devices 1a and 1b may perform an AND operation on all the operation values EX1 to EXn, and retiming the operation values with the clock signal ClockDR to output them to a dedicated terminal or latching and holding them. Thereby, an abnormal boundary scan register is specified in units of devices 1a and 1b.

  On the other hand, when an abnormal boundary scan register is specified in the unit of the boundary scan cell BC, the longer the number of devices, the longer it takes to specify the device. Therefore, the devices 1a and 1b have the boundary scan cell number (# 1, # 2,...) May be encoded and notified to the test apparatus 91. In this case, for example, dedicated terminals for the number of bits corresponding to the number of boundary scan cells are provided for each of the devices 1a and 1b. For example, in the case of 256 boundary scan cells BC, a dedicated terminal of 8 bits (8) necessary for displaying 256 binary numbers is provided, and in the case of 1024 boundary scan cells BC, 1024 binary numbers Dedicated terminals for 10 bits (10) necessary for display are provided.

  However, in the above-described method, a logic circuit that executes the AND operation and encoding and a plurality of dedicated terminals are added to the devices 1a and 1b. In order to avoid the addition of such large-scale hardware, for example, by adding a simple control circuit described below, the test apparatus 91 can detect an abnormal boundary based on the serial data output from the output terminal TDO. A scan register may be specified.

  FIG. 16 is a configuration diagram illustrating an example of a configuration in which a control circuit is added to the boundary scan cell BC. FIG. 16 illustrates the comparison circuit 3a illustrated in FIG. 10, but the comparison circuits 3b and 3c illustrated in FIG. 12 or 14 may be used. In FIG. 16, the same components as those in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted. FIG. 16 shows the configuration of the control circuit 4 corresponding to one boundary scan cell BC. The control circuit 4 has the same configuration for each boundary scan cell BC.

  The control circuit 4 includes a latch circuit 40, AND circuits 41 and 42, and a switching control unit 43. The control circuit 4 is connected to the comparison circuit 3a and controls the output value of the boundary scan cell BC according to the operation value EXn output from the comparison circuit 3a. Therefore, in the boundary scan cell BC, a selector 24 is added between the flip-flop 21 and the output terminal to the subsequent boundary scan cell BC (or the output terminal TDO).

  The latch circuit 40 holds the operation value EXn output from the flip-flop 32 of the comparison circuit 3a. The operation value EXn held in the latch circuit 40 is input to one of the input terminals of the AND circuits 41 and 42, respectively. The switching control unit 43 is a logic circuit that generates and outputs control values C0 and C1 according to the control of the TAP controller 11.

  The switching control unit 43 outputs the control values C0 and C1 to the other input terminals of the AND circuits 41 and 42, respectively. The AND circuits 41 and 42 perform AND operations on the control values C0 and C1 and the operation value EXn, respectively, and output selection signals SEL_0 and SEL_1 indicating the operation results to the selector 24 in the boundary scan cell BC. The selection signals SEL_0 and SEL_1 are examples of a plurality of control signals that respectively control a plurality of stages of boundary scan cells BC.

  The selector 24 selects an output value corresponding to the level (“0” or “1”) of the selection signals SEL_0 and SEL_1, and outputs it to the boundary scan cell BC (or output terminal TDO) at the subsequent stage. More specifically, the selector 24 selects and outputs the input value from the flip-flop 21 when the selection values SEL_0 and SEL_1 are both “0”.

  Further, when the selection value SEL_0 is “1” and SEL_1 is “0”, the selector 24 selects and outputs the fixed value “0”. On the other hand, when the selection value SEL_0 is “0” and SEL_1 is “1”, the selector 24 selects and outputs the fixed value “1”.

  With the above configuration, the control circuit 4 controls the output value of the boundary scan cell BC according to the control of the TAP controller 11. As a result, when the calculated value EXn is “0”, the boundary scan cell BC outputs the retained serial data to the subsequent boundary scan cell BC (or the output terminal TDO). On the other hand, when the calculated value EXn is “1”, the boundary scan cell BC outputs a fixed value “0” or “1” to the subsequent boundary scan cell BC (or the output terminal TDO).

  As a result of the comparison by the comparison circuits 3a to 3c, the control circuit 4 fixes the output value of the boundary scan cell BC whose input value and output value do not match among the multiple stages of the boundary scan cell BC to “0”. After the fixed value is output, the fixed value is switched to “1”. Accordingly, the test apparatus 91 identifies an abnormal boundary scan register by detecting the boundary between the fixed values “0” and “1” from the serial data output from the output terminal TDO. Below, the process of the test apparatus 91 is described.

  FIG. 17 is a flowchart showing the processing of the test apparatus 91. This process is executed when an abnormality occurs in the shift operation of the boundary scan register as illustrated in FIGS. 5 and 6. 18 (a) to 18 (c) show initialization, abnormality reproduction, and output control when this processing is performed on the devices 1a and 1b illustrated in FIGS. The value of the boundary scan register at the time is shown.

  The test apparatus 91 outputs serial data of All “0” (binary number) to the input terminal TDI of the device 1a (step St1). As a result, the boundary scan registers of the boundary scan cells BC # 1 to # 10 are initialized to “0” as shown in FIG.

  Next, the test apparatus 91 outputs the toggle pattern serial data to the input terminal TDI of the device 1a (step St2). Examples of the toggle pattern serial data include “010101...”, “101010...”, “00110011...”, “110001100. This makes it easy to reproduce an abnormal shift operation of the boundary scan register.

  When the abnormal shift operation is reproduced, for example, as shown in FIG. 18B, the boundary scan registers of all the boundary scan cells BC # 5 to # 10 subsequent to the abnormal boundary scan cell BC # 4 are abnormal values “ x ". The abnormal boundary scan cell BC # 4 latches the abnormal state as the operation value EX4 = “1”.

  Next, the test apparatus 91 instructs the TAP controller 11 to fix the output of the abnormal boundary scan register to “0” using the “Instruction OPCODE” command (step St3). At this time, the TAP controller 11 sets the control value C0 of the switching control unit 43 to “1” and the control value C1 to “0”. For this reason, the output value of the abnormal boundary scan cell BC whose calculated value EXn is “1” is fixed to “0”. On the other hand, the output value of the normal boundary scan cell BC with the operation value EXn of “0” is not fixed and becomes the value of the serial data held in the flip-flop 21.

  Next, the test apparatus 91 outputs serial data of All “1” (binary number) to the input terminal TDI of the device 1a (step St4). As a result, as shown in FIG. 18C, the values of the boundary scan registers of the abnormal boundary scan cancel BC # 4 and the boundary scan cancel BC # 1- # 3 preceding the boundary scan cancel BC # 4 are “1”. On the other hand, the values of the boundary scan registers of the boundary scan cells BC # 5 to # 10 subsequent to the abnormal boundary scan cell BC # 4 are set to “0” by the output value fixing control in step St3.

  Next, the test apparatus 91 instructs the TAP controller 11 to fix the output of the abnormal boundary scan register to “1” using the “Instruction OPCODE” command (step St5). At this time, the TAP controller 11 sets the control value C0 of the switching control unit 43 to “0” and the control value C1 to “1”. For this reason, the output value of the abnormal boundary scan cell BC whose calculated value EXn is “1” is fixed to “1”. On the other hand, the output value of the normal boundary scan cell BC with the operation value EXn of “0” is not fixed and becomes the value of the serial data held in the flip-flop 21.

  As described above, the control circuit 4 generates the plurality of selection signals SEL_0 and SEL_1 based on the comparison results of the comparison circuits 3a to 3c, and outputs them to the plurality of stages of boundary scan cells BC. The multi-stage boundary scan cell BC controls the output value according to the plurality of selection signals SEL_0 and SEL_1. For this reason, the control circuit 4 can save time and effort to select and control the boundary scan cell BC whose input value and output value do not match from the boundary scan cell BC of a plurality of stages.

  Next, the test apparatus 91 reads all the boundary scan registers from the boundary scan cells BC # 1 to # 10 (step St6). As a result, serial data is input to the test apparatus 91 from the output terminal TDO. At this time, even if the boundary scan cancel BC # 4 performs an abnormal shift operation, the output value is fixed to “1”, so that the abnormal value “x” is output to the subsequent boundary scan cancel BC. There is no.

  Next, the test apparatus 91 determines success / failure of reproduction of the abnormal shift operation from the value of the read boundary scan register (see symbol H in FIG. 18C) (step St7). When all the values of the boundary scan register are “1”, the test apparatus 91 determines that the reproduction has failed (No in Step St7), changes the toggle pattern (Step St10), and performs the process of Step St1 again. Do.

  On the other hand, when all the values of the boundary scan register are not “1”, the test apparatus 91 determines that the reproduction is successful (Yes in step St7). In this case, the test apparatus 91 detects the boundary between “0” and “1” of the read boundary scan register (step St8), and identifies the abnormal devices 1a and 1b and the abnormal boundary scan register (step St9). ).

  In the example indicated by the symbol H in FIG. 18C, the boundary between “0” and “1” exists between the boundary scan cells BC # 4 and # 5 of the device 1a. Therefore, the test apparatus 91 detects that the boundary scan register of the boundary scan cell BC # 4 of the device 1a is abnormal. In this way, the test apparatus 91 performs processing.

  FIG. 19 is a flowchart showing processing of the devices 1a and 1b. More specifically, FIG. 19 shows processing on the device 1a, 1b side corresponding to the processing shown in FIG.

  Each boundary scan cell BC shifts the serial data of All “0” in accordance with the processing in step St1 (step St21). Next, each boundary scan cell BC shifts the serial data of the toggle pattern in accordance with the processing in step St2 (step St22). At this time, if the abnormal shift operation is reproduced, as illustrated in FIG. 8B, the boundary scan cells BC # 5 to # 10 subsequent to the abnormal boundary scan cell BC # 4 have an abnormal value “x”. Hold.

  The operation of the devices 1a and 1b according to the processing after step St3 is divided into a case where the boundary scan register is normal and a case where it is abnormal for each boundary scan cell BC. When the boundary scan register is normal (No in step St23), the boundary scan cells BC # 1 to # 3 and # 5 to # 10 are inputted serially because the selector 24 selects the holding value of the flip-flop 21. The data is shifted (step St27).

  If the boundary scan register is abnormal (Yes in step St23), the boundary scan cancel BC # 4 is output when the selector 24 selects the fixed value “0” in accordance with the processing in step St3. The value is fixed to “0” (step St24). Next, the boundary scan cell BC # 4 performs a shift operation in accordance with the processing in step St4 (step St25). Accordingly, the boundary scan cell BC # 4 outputs “0” to the subsequent boundary scan cell BC # 5. Therefore, as illustrated in FIG. 18C, the boundary scan cell BC # 5 to # 10 Holds “0”.

  Next, the boundary scan cell BC # 4 fixes the output value to “1” when the selector 24 selects the fixed value “1” in accordance with the processing of step St5 (step St26). For this reason, the value of the boundary scan register read out by the process of step St6 is “1” in the boundary scan cells BC # 1 to # 4, as indicated by the symbol H in FIG. The boundary scan cells BC # 5 to # 10 are “0”. In this way, the devices 1a and 1b perform processing.

  As described above, the values of the boundary scan registers read from the plurality of stages of boundary scan cells BC # 1 to # 10 have a boundary of “1” that is continuous and “0” that is continuous. The boundary between “0” and “1” indicates the boundary scan cancel BC # 4 in which the boundary scan register is abnormal.

  Accordingly, the test apparatus 91 can identify the abnormal boundary scan cell BC # 4 by detecting the boundary between “0” and “1” from the serial data output from the output terminal TDO. No change is required. On the other hand, the devices 1a and 1b also do not require the addition of large-scale hardware like the method described above. Therefore, according to the above method, an abnormal boundary scan register can be detected while suppressing an increase in cost.

  In this embodiment, the control circuit 4 fixes the output value of the abnormal boundary scan cell BC # 4 to “0”, and after the shift operation, fixes the output value to “1”. It is not limited. On the contrary, the control circuit 4 may fix the output value of the abnormal boundary scan cell BC # 4 to “1” and fix the output value to “0” after the shift operation.

  Next, the configuration of the test apparatus 91 will be described. FIG. 20 is a configuration diagram illustrating an example of the test apparatus 91. As described above, the test apparatus 91 performs the boundary scan test of the devices 1a and 1b provided with the multiple stages of boundary scan cells BC # 1 to # 10.

  The test apparatus 91 includes an output unit 910, a control unit 911, a specifying unit 912, a comparison unit 913, and an expected value storage unit 914. The control unit 911 receives a command from the terminal device 90 and controls the output unit 910, the specifying unit 912, and the comparison unit 913 according to the command. For example, the control unit 911 activates the comparison unit 913 when performing the boundary scan test, and activates the identification unit 912 when performing the process of identifying an abnormal boundary scan register as illustrated in FIG.

  The output unit 910 sequentially outputs values to the boundary scan cells BC # 1 to # 10 according to a predetermined pattern. The output value is input to the devices 1a and 1b as the data signal TDI. In the processing shown in FIG. 17, the output unit 910 outputs serial data of All “0” (binary number) (step St1), outputs serial data of toggle pattern (step St2), and further all “1”. (Binary number) serial data is output (step St4).

  The control unit 911 generates a clock signal TCK, a state control signal TMS, and a reset signal TRST according to the received command, and outputs them to the TAP controller 11 of the devices 1a and 1b. In the processing shown in FIG. 17, the control unit 911 instructs the devices 1a and 1b to fix the output of the abnormal boundary scan register to “0” (step St3). An instruction is given to fix (step St5). At this time, the control unit 911 generates a state control signal TMS corresponding to the above “Instruction OPCODE” command, and outputs it to the TAP controller 11 of the devices 1a and 1b.

  In this way, the control unit 911 functions as an instruction unit, and for the devices 1a and 1b, among the boundary scan cells BC # 1 to # 10, the input value and the output value do not coincide with each other. The output value is fixed to “0”, and after the fixed value is output, an instruction is given to switch the fixed value to another value “1”.

  In the process shown in FIG. 17, the identifying unit 912 reads all the boundary scan registers from the boundary scan cells BC # 1 to # 10 (step St6), and determines whether or not the abnormal shift operation has been reproduced (step). St7). If the identifying unit 912 determines that the reproduction has succeeded (Yes in Step St7), the boundary of the read boundary scan register “0” and “1” is detected (Step St8), and the abnormal devices 1a and 1b are detected. Then, an abnormal boundary scan register is specified (step St9).

  That is, the identifying unit 912 identifies a boundary scan cell where the input value and the output value do not match by detecting a boundary where the values sequentially output from the boundary scan cells BC # 1 to # 10 are switched. . The identifying unit 912 notifies the terminal device 90 of the identified abnormal devices 1a and 1b and the abnormal boundary scan register as a specified result.

  Also, if the specifying unit 912 determines that the reproduction has failed (No in Step St7), that is, if the boundary between the read boundary scan registers “0” and “1” cannot be detected, the identifying unit 912 notifies the control unit 911 of that fact. Notice. Upon receiving the notification, the control unit 911 instructs the output unit 910 to change the toggle pattern (step St10).

  The output unit 910 outputs serial data again with the changed toggle pattern. That is, the output unit 910 changes a predetermined pattern when the boundary is not detected by the specifying unit 912, and outputs a value according to the changed pattern. As a result, the abnormal shift operation of the boundary scan register is reproduced.

  As described with reference to FIGS. 3 to 6, the comparison unit 913 reads the boundary scan registers held in the boundary scan cells BC # 1 to # 10 from the devices 1 a and 1 b, and the expected value storage unit 914. Compare with the expected value read from. The expected value storage unit 914 is information storage means such as a memory, and stores the expected values of the output values of the boundary scan cells BC # 1 to # 10. The comparison unit 913 outputs the test result obtained by the comparison to the terminal device 90.

  Note that the output unit 910, the control unit 911, the specifying unit 912, and the comparison unit 913 may be configured by hardware such as LSI, or may be configured by software. When configured by software, the output unit 910, the control unit 911, the specifying unit 912, and the comparison unit 913 are each formed as a part of a function of a program read by a processor such as a CPU (Central Processing Unit).

  As described above, the electronic circuit devices 1a and 1b according to the embodiments include the multi-stage register circuit BC, the comparison circuits 3a to 3c, and the control circuit 4. The multi-stage register circuit BC sequentially holds and outputs the values input by executing the boundary scan test.

  The comparison circuits 3a to 3c compare input values and output values of the register circuits BC in a plurality of stages. The control circuit 4 fixes the output value of the register circuit BC whose input value and output value do not match as a result of the comparison by the comparison circuits 3a to 3c among the plurality of register circuits BC, and outputs the fixed value. After that, switch the fixed value to another value.

  According to the above configuration, the comparison circuits 3a to 3c compare the input value and the output value of each of the plurality of stages of register circuits BC, so that it is possible to detect the register circuit BC whose input value and output value do not match. The control circuit 4 fixes the output value of the register circuit BC, and after the fixed value is output, switches the fixed value to another value.

  Therefore, an abnormal boundary scan register can be detected by detecting a place where values sequentially output from the register circuits BC in a plurality of stages are switched.

  Further, the test apparatus 91 according to the embodiment performs a boundary scan test of the electronic circuit apparatuses 1a and 1b provided with a plurality of stages of register circuits BC that sequentially hold and output input values. The test apparatus 91 includes an output unit 910, a control unit 911, and a specifying unit 912.

  The output unit 910 sequentially outputs values to a plurality of register circuits BC according to a predetermined pattern. The control unit 911 fixes the output value of the register circuit in which the input value and the output value do not match among the plurality of register circuits BC to the electronic circuit devices 1a and 1b, and the fixed value is output. After that, the fixed value is instructed to switch to another value. The identifying unit 912 detects a boundary at which values sequentially output from a plurality of register circuits BC are switched, thereby causing a register circuit in which the input value and the output value of the register circuits BC are inconsistent. Is identified.

  Therefore, the test apparatus 91 can detect an abnormal boundary scan register.

  The above-described embodiment is an example of a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

1a, 1b Device 3a-3c Comparison circuit 4 Control circuit 11 TAP controller 91 Test device 910 Output unit 911 Control unit 912 Specific unit BC Boundary cancel

Claims (5)

A multi-stage register circuit for sequentially holding and outputting the values input by executing the boundary scan test;
A comparison circuit for comparing an input value and an output value of each of the plurality of register circuits;
As a result of comparison by the comparison circuit among the plurality of register circuits, the output value of the register circuit in which the input value and the output value do not match is fixed, and after the fixed value is output, the fixed value is output. An electronic circuit device comprising a control circuit for switching a value to another value. The control circuit generates a plurality of control signals based on the comparison result of the comparison circuit and outputs the control signals to the plurality of register circuits,
The electronic circuit device according to claim 1, wherein the plurality of register circuits control the output value according to the plurality of control signals. The plurality of register circuits are provided with first flip-flops and second flip-flops alternately,
When the first flip-flop detects a rising edge of a clock signal, the first flip-flop holds and outputs the input value;
When the second flip-flop detects a falling edge of the clock signal, the second flip-flop holds and outputs the input value;
The said comparison circuit has an arithmetic circuit which calculates the exclusive OR of the said input value and the said output value for every said 1st flip-flop and said 2nd flip-flop. Electronic circuit device. In a test apparatus that performs a boundary scan test of an electronic circuit device provided with a plurality of register circuits that sequentially hold and output input values,
An output unit for sequentially outputting values to the plurality of register circuits according to a predetermined pattern;
For the electronic circuit device, the output value of the register circuit in which the input value and the output value do not match among the plurality of register circuits is fixed, and after the fixed value is output, the fixed value is An instruction unit for instructing to switch to another value;
A specifying unit that identifies a register circuit in which an input value and an output value do not match among the plurality of register circuits by detecting a boundary where values sequentially output from the register circuits in the plurality of stages are switched. And a test apparatus.   The test apparatus according to claim 4, wherein the output unit changes the predetermined pattern and outputs a value according to the changed pattern when the boundary is not detected in the specifying unit.

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