JP6400924B2 - Electronic component mounting structure - Google Patents

Description

  The present invention relates to an electronic component mounting structure.

  In an electronic component, in particular, a multilayer electronic component in which a dielectric layer and an internal electrode layer are stacked, when a DC voltage and an AC voltage are simultaneously applied to the electronic component, the dielectric layer is distorted due to the electrostrictive effect of the voltage. Occurs and the electronic component itself vibrates. Due to the vibration of the electronic component, the substrate on which the electronic component is mounted by solder or the like vibrates, and when the substrate resonates at the audible resonance frequency, a vibration sound called “sounding” is generated.

  In order to reduce such “sounding”, a method of suppressing the distortion of the electronic component itself and reducing the vibration (for example, using a low dielectric constant material having a small electrostrictive effect or suppressing the electrostrictive effect by an internal electrode pattern). In addition, a method of absorbing vibration of an electronic component and suppressing transmission to a substrate (for example, absorbing vibration by a metal terminal or lead, defining a height of a solder fillet, etc.) has been proposed. For example, Patent Document 1 discloses that a conductive material, which is a propagation medium of capacitor vibration, has a mounting structure that is farthest from the most vibrating portion of the capacitor, so that vibration is less likely to propagate to the circuit board. Yes.

JP2013-065820A

  However, when the distortion of the electronic component itself is suppressed, there is a problem that a capacitor cannot be secured, for example, in the case of a capacitor or the like because the dielectric constant of the material is low and the capacity development region is small. Further, when vibration is absorbed by metal terminals and leads, or even a mounting structure as described in Patent Document 1, a sufficient vibration damping effect cannot be obtained even though the manufacturing process and the mounting process are complicated. was there.

  The present invention has been made in view of the above problems, and an object thereof is to provide an electronic component mounting structure that can reduce noise.

The electronic component mounting structure of the present invention is an electronic component mounting structure in which a pair of external terminal electrodes of an electronic component and a pair of lands provided on a mounting surface of a substrate are joined via a conductive material. In the first main surface of the electronic component facing the substrate, the pair of external terminal electrodes is in a region including the vicinity of any one of the pair of first sides. It is provided so that it does not overlap and includes a part of the bisector of the first side, the length of the first side is E1, and the direction of the first side of the land When L1 is L1, L1 <E1, and when the electronic component is projected onto the mounting surface of the substrate, the bisector of the first side is located on the land. It is characterized by that.

  ADVANTAGE OF THE INVENTION According to this invention, the mounting structure of the electronic component which can reduce sound noise can be provided.

1 shows a first embodiment of a mounting structure for an electronic component according to the present invention, (a) is a plan view showing the arrangement of electronic components and lands as viewed from the mounting surface side of the substrate, and (b) is a side surface as viewed from the y-axis direction of the coordinate axis. FIG. 4C is a side view of the coordinate axis viewed from the x-axis direction. (A) is a top view which shows the dimension of each part of Fig.1 (a), (b) and (c) are top views which show the other aspect of 1st Embodiment. It is sectional drawing which shows the internal structure of an electronic component. It is A1-A1 sectional view taken on the line of Fig.1 (a). It is a graph which shows the impedance measurement result at the time of applying a DC bias of 4V to a monolithic ceramic capacitor. It is a schematic diagram of the model of the finite element method used for the impedance analysis of a multilayer ceramic capacitor. It is a perspective view which shows the calculation result of the vibration mode in 10kHz of a monolithic ceramic capacitor, Comprising: (a) is the figure seen from the symmetrical plane side, (b) is the figure seen from the surface side. It is a perspective view which shows typically the node part of the vibration mode in a multilayer ceramic capacitor. The 2nd Embodiment of the mounting structure of the electronic component of this invention is shown, (a) is a top view which shows arrangement | positioning of the electronic component and land seen from the mounting surface side of a board | substrate, (b) is the side surface seen from the y-axis direction of the coordinate axis FIG. 4C is a side view of the coordinate axis viewed from the x-axis direction. (A) is a top view which shows the dimension of each part of Fig.9 (a), (b) and (c) are top views which show the other aspect of 2nd Embodiment. It is A2-A2 sectional view taken on the line of Fig.9 (a). It is the schematic of the measuring apparatus of a sound pressure level. It is a graph which shows the sound pressure level of the sound sound measured in the Example, (a) is a graph which shows the measurement data using the board | substrate A, (b) is a graph which shows the measurement data using the board | substrate B. A conventional electronic component mounting structure is shown; (a) is a plan view showing the arrangement of electronic components and lands; (b) is a side view as seen from the y-axis direction of the coordinate axis; and (c) is seen from the x-axis direction of the coordinate axis. FIG.

  The electronic component mounting structure of the present invention will be described in detail with reference to the drawings. In addition, in each drawing, the same code | symbol is used about the same member and part, and the overlapping description is abbreviate | omitted. In addition, each drawing is provided with xyz coordinate axes for easy explanation. Further, each figure is schematic, and in particular, the dimensions of the substrate, the thickness of the conductor, etc. do not reflect the actual dimensional relationship.

(First embodiment)
In the electronic component mounting structure according to the first embodiment of the present invention, as shown in FIGS. 1A to 1C, the electronic component 1 includes a pair of external terminals provided at both ends of the laminate 2. The electrode 3 and a pair of lands 6 provided on the mounting surface 5 of the substrate 4 are joined to each other via a conductive material 7. The conductive material 7 plays a role of electrically connecting the external terminal electrode 3 of the electronic component 1 and a circuit (not shown) of the substrate 4 together with the role of bonding the electronic component 1 to the substrate 4.

  The land 6 is an exposed portion of the conductor on the mounting surface 5, and in FIGS. 1B and 1C, the surface of the land 6 protrudes from the mounting surface 5 of the substrate 4 (on the mounting surface 5 of the substrate 4). However, a part or all of the mounting surface 5 of the substrate 4 except the land 6 is covered with a solder resist, and the surface of the land 6 and the surface of the solder resist are on the same plane. Alternatively, the land 6 may be recessed with respect to the surface of the solder resist. Further, when the solder resist is present at a portion facing the electronic component 1 of the substrate 4, the surface of the solder resist is regarded as the mounting surface 5.

  On the first main surface 8 of the electronic component 1 facing the mounting surface 5, the pair of external terminal electrodes 3 is a first bisector 9 c that is a bisector of the pair of first sides 9. It is provided so that a part of may be included. In other words, of the side portions constituting the first main surface 8, the side portion where the external terminal electrode 3 exists on the bisector of the side portion is referred to as the first side portion 9.

  The first bisector 9c that bisects the first side portion 9 bisects the length of the first side portion 9 on the first main surface 8 side and the first bisector 9c. A straight line perpendicular to the side 9.

  Note that, of the side portions constituting the first main surface 8, a side portion where the external terminal electrode 3 does not exist on the bisector of the side portion is referred to as a second side portion 10.

  In the present embodiment, as shown in FIG. 2A, the length E1 of the first side portion 9 is shorter than the length E2 of the second side portion 10, that is, E1 <E2. E1 and E2 are both the lengths of the electronic component 1 including the external terminal electrodes 3. D is the distance between the pair of lands 6, that is, the distance between the pair of lands 6 in the direction perpendicular to the first side portion 9 of the electronic component 1 on the mounting surface 5 of the substrate 4. 1B and 1C, H0 is the height of the electronic component 1 in the z-axis direction, and C is the distance between the mounting surface 5 of the substrate 4 and the electronic component 1.

  In the present embodiment, as shown in FIG. 2A, the length L1 of the pair of lands 6 in the first side portion 9 direction is longer than the length E1 of the pair of first side portions 9. It is important that it is small, ie L1 <E1.

  On the other hand, in a conventional electronic component mounting structure (hereinafter sometimes simply referred to as a conventional structure), the external terminal electrode 3 and the land 106 on the substrate are made of a conductive material (solder) 107 as shown in FIG. It is fixed in a state where it is electrically connected via. The solder 107 fills the gap between the external terminal electrode 3 and the land 106, and further covers the external terminal electrode 3 that covers the end surface of the multilayer body 2 and the side surface and part of the upper and lower surfaces. The length L1 in the first side portion direction is equal to or larger than the length E1 of the first side portion 9, that is, L1 ≧ E1. In FIG. 14, the components of the electronic component 1 are shown as visible through the lands 106 for convenience.

  Here, as shown in FIG. 3, the multilayer body 2 of the electronic component 1 is formed by alternately laminating dielectric layers 11 and internal electrode layers 12, and the internal electrode layer 12 is composed of the multilayer body 2. Either one of both end portions is electrically connected to the external terminal electrode 3.

  The structure of the dielectric layer 11 and the internal electrode layer 12 shown in FIG. 3 is a schematic structure, and actually several to several hundreds of dielectric layers 11 and the internal electrode layer 12 are laminated. Many things are used. The same applies to the electronic component 1 having another structure as described later.

  For example, a multilayer ceramic capacitor which is one of electronic components uses a ferroelectric material such as barium titanate as the dielectric layer 11 and a metal material such as Ni as the internal electrode layer 12. In addition, the external terminal electrode 3 is usually made by baking a Cu paste as a base electrode and applying Ni and Sn plating on the surface thereof.

  When an AC voltage is applied to a multilayer ceramic capacitor mounted on a substrate together with a DC voltage (DC bias), a piezoelectric property is generated in the dielectric layer due to an electrostrictive effect due to the DC voltage, and piezoelectric vibration is generated by the AC voltage. Occur. Furthermore, in the conventional structure, the piezoelectric vibration of the multilayer ceramic capacitor is transmitted to the substrate 104 via the solder 107 and the substrate 104 vibrates, and when the substrate 104 resonates at an audible resonance frequency, a vibration sound called “sounding” is generated. Will occur.

  Therefore, a simulation was performed on the piezoelectric vibration of the multilayer ceramic capacitor body. First, a 1005 type monolithic ceramic capacitor (capacitance 10 μF, rated voltage 4 V, hereinafter simply referred to as an evaluation component) was used as the monolithic ceramic capacitor, and impedance was measured in a state where a DC voltage (DC bias) of 4 V was applied. The measurement results are shown in FIG.

  In addition, impedance simulation is performed using a model (dielectric material: barium titanate material, internal electrode: Ni, external electrode: Cu, laminate size: 1100 × 620 × 620 μm, external electrode thickness 20 μm) based on the evaluation part. went. The material parameters of the evaluation parts were fitted so that the piezoelectric resonance peak existing in the frequency region of 2 GHz or more matched the measured actual value. FIG. 6 schematically shows a finite element method model used for impedance simulation. This is a 1/8 model considering symmetry, and the two cross sections appearing on the front surface of FIG. 6 and the lower cross section are symmetrical planes.

Table 1 shows the parameters (elastic stiffness c _ij and piezoelectric constant e _ij ) of the dielectric layer 11 obtained by the fitting. From Table 1, it can be seen that the material properties of the dielectric layer 11 of the evaluation part have anisotropy (c ₁₁ > c ₃₃ , c ₂₂ > c ₃₃ ). This is considered due to the compressive stress caused by the internal electrode layer 12.

Using the obtained parameters, the vibration mode in the audible frequency region (20 Hz to 20 kHz) of the evaluation component was calculated using the above-mentioned 1/8 model. FIG. 7 shows the calculation result at 10 kHz. 7A is a view from the inside (symmetric plane side) of the 1/8 model, and FIG. 7B is the opposite side of FIG. 7A, that is, the outside of the 1/8 model. Viewed from the side (surface side). Here, the broken line indicates the shape of the evaluation component in a state where no AC voltage is applied, and the solid line indicates the shape of the evaluation component that is displaced to the maximum by the AC voltage. From this result, as shown in FIG. 8 schematically showing the entire evaluation component, the vibration amplitude is small at the center of each side on the two main surfaces located in the stacking direction of the evaluation component, that is, the vibration node. It can be seen that there can be a region 15 (hereinafter referred to as a nodal portion). By fixing the electronic component 1 to the substrate 4 at or near the node-like portion 15, it is considered that the propagation of piezoelectric vibration of the electronic component 1 to the substrate 4 is suppressed, and sound generation can be reduced.

  In the present invention, the electronic component 1 only needs to be fixed to the substrate 4 at or near the node-like portion 15, and as shown in FIG. 4, any one of the two main surfaces positioned in the stacking direction of the electronic component 1. These may be fixed to the substrate 4 as the first main surface 8, or other main surfaces may be fixed to the substrate 4 as the first main surface 8.

  In the present embodiment, since the length L1 of the land 6 of the substrate 4 is smaller than the length E1 of the first side portion 9 of the electronic component 1 joined to the land 6, the external terminal electrode of the electronic component 1 is used. It is possible to fix the electronic component 1 to the substrate 4 in such a node-like portion 15 existing on the substrate 3.

  In particular, when L1 / E1 ≦ 0.6, that is, L1 has a length not more than 0.6 times E1, and the electronic component 1 is projected onto the mounting surface 5 of the substrate 4, the bisector of the first side 9 Is located on the land 6, the electronic component 1 can be bonded to the substrate 4 in a region where the vibration amplitude of the node-like portion 15 is smaller, and the noise is further reduced. The bisector of the first side 9 is more preferably located on a bisector in the direction of the first side 9 of the land 6.

  Note that L1 / E1 is preferably 0.4 or more in terms of mountability, that is, L1 is 0.4 or more times E1.

  In addition, in the present embodiment, the entire first side portion 9 is constituted by the external terminal electrode 3. However, as another aspect, the first side portion 9 is laminated with the external terminal electrode 3 as shown in FIG. It may be composed of the body 2. Further, as shown in FIG. 2C, the entire first side portion 9 is configured by the laminated body 2, and the external terminal electrode 3 is positioned in the vicinity of the first side portion 9 of the first main surface 8. You may do it. That is, when the length of the external terminal electrode 3 in the first side portion direction is M1, M1 <E1 may be satisfied. In this case, when the electronic component 1 is bonded to the substrate 4, the protrusion of the conductive material 7 on the substrate 4 is reduced, and the mounting density of the electronic component 1 can be improved. In the present embodiment, the vicinity of the first side 9 on the first main surface 8 side is a region whose distance from the first side 9 is not more than 0.25 times E2. Further, it is preferable that the external terminal electrode 3 is not provided at the apex of the electronic component 1 having a relatively large vibration amplitude.

  Furthermore, by setting M1 / E1 to 0.4 to 0.6, the accuracy of joining the electronic component 1 to the substrate 4 in the region where the vibration amplitude of the node-like portion 15 is small is improved.

  As described above, when the length M1 of the external terminal electrode 3 is smaller than the length E1 of the first side portion 9, the pair of external terminal electrodes 3 are located at portions facing each other via the first main surface 8. It is preferable to be positioned, and further, from the viewpoint of mountability, it is preferable to be positioned at a point symmetrical with respect to the center of gravity of the first main surface 8.

As a method of forming such external terminal electrodes 3 on the laminate 2, the external terminal electrodes 3 having a desired shape are formed on the surface where the internal electrode layer 12 of the laminate 2 is exposed using a conductive material such as metal. In addition to the direct formation, for example, an internal electrode connection layer that electrically connects the internal electrode layers 12 is formed on the surface of the laminate 2 where the internal electrode layers 12 are exposed, and the first side portion 9 or the vicinity thereof is formed. The external terminal electrode 3 having a desired shape may be formed, and the corresponding internal electrode connection layer and the external terminal electrode 3 may be electrically connected directly or via a conductor. Further, the internal electrode connection layer described above is covered with an insulating material, leaving a part of the first side portion 9 or its vicinity, and a portion of the internal electrode connection layer not covered with the insulating material is externally provided. The terminal electrode 3 may be used.

  Further, according to the result of the vibration mode analysis of the evaluation part, the vibration amplitude is large near the center of each surface constituting the evaluation part. Therefore, the distance between the pair of lands 6 in the direction perpendicular to the first side portion 9, that is, the distance between the pair of lands 6 is 0 as a ratio (D / E2) to the length E2 of the second side portion 10. .5 or more is preferable.

  In the present embodiment, the electronic component 1 is not in direct contact with the mounting surface 5 of the substrate 4. In particular, the ratio of C to H0 (C / H0), which is the distance between the electronic component 1 and the mounting surface 5 of the substrate 4, is preferably 0.1 or more.

  As the conductive material 7, for example, a brazing material such as eutectic solder or lead-free solder (Sn—Ag—Cu), a conductive adhesive, or the like can be used.

  In the present invention, a multilayer ceramic capacitor using a ferroelectric material such as barium titanate for the dielectric layer 11 and a metal material such as Ni, Cu, Ag, Ag-Pd for the internal electrode layer 12 is used as an electronic component. 1 is particularly preferably used, but it can also be applied to other electronic components when it is necessary to suppress excitation of a substrate or the like on which the electronic component is mounted due to piezoelectric vibration of the electronic component itself. . The present invention can exert a remarkable effect particularly in a multilayer electronic component of a 1005 type or more type.

  Further, for example, in many multilayer ceramic capacitors, an external terminal electrode 3 in which a base electrode made of Cu is plated with Ni and Sn is used, but it is composed of only a plated electrode without using the base electrode. The present invention can also be suitably applied to those having the external terminal electrode 3.

(Second Embodiment)
Also in the second embodiment of the present invention, as in the first embodiment, the electronic component 1 is provided on the pair of external terminal electrodes 3 provided at both ends of the multilayer body 2 and the mounting surface 5 of the substrate 4. A pair of lands 6 are joined to each other via a conductive material 7, and L1 is smaller than E1, that is, L1 <E1 (FIGS. 9 and 10).

  The difference from the first embodiment is that the length E1 of the first side 9 is longer than the length E2 of the second side 10, as shown in FIG. 10A, that is, E1> E2. That is the point.

  Also in this embodiment, L1 is L1 / E1 ≦ 0.6, that is, L1 is 0.6 times shorter than E1 as in the first embodiment, and the electronic component 1 is mounted on the mounting surface 5 of the substrate 4. When projected, the bisection point of the first side portion 9 is located on the land 6, so that the electronic component 1 can be bonded to the substrate 4 in a region where the vibration amplitude of the node-like portion 15 is smaller, The noise is further reduced. Since L1 / E1 is more likely to be inclined with respect to the substrate 4 of the electronic component 1 during mounting as L1 / E1 is smaller, it is preferable that L1 / E1 is 0.1 to 0.5 from the viewpoint of mountability. Further, the length M1 of the external terminal electrode 3 in the direction of the first side portion 9 is preferably M1 <E1 as shown in FIGS. 10B and 10C, and further M1 / E1 is 0.1. It is preferable to set it to -0.5. In addition, about C and D, it is preferable to set it as the same range as 1st Embodiment.

  11 is a cross-sectional view taken along line A2-A2 of FIG. 9A, and the internal electrode 12 is electrically connected to the external terminal electrode 3 at either one of both end portions of the multilayer body 2. FIG.

  As the conductive material 7, for example, a brazing material such as eutectic solder or lead-free solder (Sn—Ag—Cu), a conductive adhesive, or the like can be used as in the first embodiment.

  Since the configuration and material of the electronic component to which this embodiment can be applied are the same as those in the first embodiment, further description is omitted.

  The sound produced when a multilayer ceramic capacitor was mounted on a substrate was measured. For the measurement, a 1005 type monolithic ceramic capacitor (capacitance 10 μF, rated voltage 4 V, hereinafter simply referred to as a capacitor) and a substrate made of an FR material of 100 × 40 mm and a thickness of 0.8 mm were used. The capacitor was mounted on the center of the substrate using Sn-Ag-Cu (SAC) solder.

  Two types of substrates (substrate A and substrate B) having different land shapes were used as substrates to which the capacitors were bonded. The substrate A had L1 of 0.5 mm and D of 0.5 mm, and the substrate B had L1 of 0.3 mm and D of 0.3 mm.

  After mounting the capacitors on substrates A and B (hereinafter sometimes simply referred to as substrates), the mounting state is observed with a microscope. Both have a solder fillet height of 460 μm, and the mounting surface of the substrate and the capacitor It was confirmed that the interval C was 45 μm.

  The measurement was performed using a sound pressure level measuring apparatus as shown in FIG. A mounting board 21 (hereinafter also referred to simply as a mounting board) on which a capacitor is mounted is placed in an anechoic box 22 (inner dimensions 600 × 700 mm, height 600 mm), and 3 mm in the direction perpendicular to the board from the center of the board. Sounds were collected by the sound collecting microphone 23 installed at a separated position, and the sound pressure level of the collected sound was measured by the amplifier 24 and the FET analyzer 25 (DS2100 manufactured by Ono Sokki). FIGS. 13A and 13B show the sounding measurement results when a DC voltage of 4 V (DC bias) and an AC voltage of 20 Hz to 20 kHz and 1 Vp-p are applied to the capacitor.

  In FIGS. 13A and 13B, the sound pressure level is indicated by an A characteristic sound pressure level (dBA), and 0 dBA corresponds to the lowest sound pressure level that a human can hear as a sound. This is a sound pressure level weighted for each frequency so as to be close to human hearing, and is described in the standard of a sound level meter (sound level meter) (JISC1509-1: 2005).

  FIG. 13A is a graph showing a measurement result when the substrate A is used, and FIG. 13B is a graph showing a measurement result when the substrate B is used. It can be seen that the sound pressure level is reduced over the entire measurement frequency in the substrate B in which L1 is reduced. In addition, when the obtained results are averaged over the frequency range of 5 Hz to 20 kHz, the average value of the sound pressure level in the board B is a result of being reduced by 5.6 dBA in the case of the board A, that is, the conventional mounting structure. It was.

DESCRIPTION OF SYMBOLS 1 Electronic component 2 Laminate body 3 External electrode 4, 104 Substrate 5, 105 Board mounting surface 6, 106 Land 7, 107 Conductive material 8 First main surface 9 First side portion 9c First side portion 2 Equal line 10 Second side 10c Second side bisector 11 Dielectric layer 12 Internal electrode layer 15 Node 21 Mounting board 22 Anechoic box 23 Sound collecting microphone 24 Amplifier 25 FET analyzer

Claims (10)

In the mounting structure of the electronic component formed by bonding a pair of external terminal electrodes of the electronic component and a pair of lands provided on the mounting surface of the substrate via a conductive material,
The pair of external terminal electrodes overlaps the first side portion in a region including the vicinity of one of the pair of first side portions on the first main surface of the electronic component facing the substrate. And is provided so as to include a part of the bisector of the first side,
When the length of the first side portion is E1, and the length of the land in the first side portion direction is L1, L1 <E1 and
An electronic component mounting structure, wherein when the electronic component is projected onto the mounting surface of the substrate, a bisection point of the first side portion is located on the land .   2. The electronic component mounting structure according to claim 1, wherein the L1 is 0.6 or less in a ratio (L1 / E1) to the E1. The conductive material, mounting structure for an electronic component according to claim 1 or 2, characterized in that at least either of the brazing material and the conductive adhesive. Wherein when the length of the first side portion direction of the external terminal electrodes and the M1, mounting structure for an electronic component according to any of claims 1 to 3, characterized in that the M1 <E1. The electronic component mounting structure according to claim 4 , wherein the external terminal electrode is not provided at an apex of the electronic component. When the distance between the pair of lands is D and the length of the other pair of sides on the first main surface of the electronic component is E2, the ratio of D to E2 (D / E2) is: mounting structure for an electronic component according to any of claims 1 to 5, characterized in that not less than 0.5. Wherein the length of the other pair of side portions when the E2 in the first major surface, the mounting structure of the electronic component according to any one of claims 1 to 6, characterized in that the E1 <E2. The electronic component mounting structure according to claim 7, wherein the L1 is 0.4 or more in a ratio (L1 / E1) to the E1. Wherein the length of the other pair of side portions when the E2 in the first major surface, the mounting structure of the electronic component according to any one of claims 1 to 6, characterized in that the E1> E2. 10. The electronic component mounting structure according to claim 9 , wherein the L1 is a ratio (L1 / E1) to the E1, and is not less than 0.1 and not more than 0.5.

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