JP6485158B2 - Imaging circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an imaging circuit device, an electronic device, and the like.

  In FIG. 1 of Patent Document 1, a horizontal transfer unit 5 is arranged below a pixel unit 3 in which pixels of a light receiving element (photodiode) are arranged in a matrix of N rows × M columns, and the right side of the horizontal transfer unit 5 is arranged. Further, a solid-state imaging device in which a pixel signal output unit 6 is arranged is disclosed.

  FIG. 1 of Patent Document 2 includes a pixel unit 10 (pixel array) in which a large number of pixels are arranged in the horizontal direction, and shift registers 12 and 16 (CCD registers) arranged above and below the pixel unit 10. A solid-state imaging device is disclosed.

JP 2013-17241 A JP 2010-41077 A

  When the pixels are arranged in a matrix of N rows × M columns as in Patent Document 1, it is difficult to make the solid-state imaging device into an elongated chip. For this reason, for example, an imaging circuit device suitable for a contact image sensor or the like that arranges an imaging element in the main scanning direction and is moved and operated in the sub scanning direction to scan a document cannot be realized.

  Further, Patent Document 2 does not have a correlated double sampling circuit, and the layout arrangement of the correlated double sampling circuit and the layout of the correlated double sampling circuit and other circuits (output circuit, readout circuit unit). There is no mention of the placement relationship.

  Some embodiments of the present invention provide an imaging circuit device and an electronic device that can efficiently arrange a pixel portion, a readout circuit portion, and a control circuit portion to realize a layout arrangement suitable for an elongated chip.

(1) One aspect of the present invention is
A pixel portion in which a light receiving element is disposed in each of a plurality of pixels;
A readout circuit unit that converts the electric charge from the pixel unit into a voltage and reads the voltage;
A control circuit unit that performs control for outputting a pixel signal based on an output voltage from the readout circuit unit;
An imaging circuit device comprising:
The control circuit unit is
A correlated double sampling circuit that performs correlated double sampling processing on the output voltage from the readout circuit unit;
An output circuit that outputs the pixel signal based on an output voltage from the correlated double sampling circuit;
Have
A region along the first side that is the long side of the imaging circuit device that is rectangular is defined as a first region, and a region along the second side that faces the first side of the imaging circuit device is defined as a second region. If it is an area,
In the first region, the pixel portion and the readout circuit portion are disposed,
The present invention relates to an imaging circuit device in which the correlated double sampling circuit and the output circuit are arranged in a first direction parallel to the second side in the second region.

  According to one aspect of the present invention, since the pixel portion and the readout circuit portion have a length that covers substantially the entire length of the imaging circuit device, the first region along the first side that is the long side of the rectangular imaging circuit device. Placed in. Since the readout circuit unit converts the charges from each pixel of the pixel unit into a voltage and reads out the voltage, the pixel unit and the readout circuit are arranged side by side in the first region. On the other hand, the correlated double sampling circuit and the output circuit are arranged along the first direction parallel to the second side in the second region. In this manner, a compact and efficient layout arrangement of the pixel unit, the readout circuit unit, and the control circuit unit (correlated double sampling circuit and output circuit) is possible, and a layout arrangement suitable for an elongated imaging circuit device can be realized. In addition, it is possible to reduce adverse effects of noise from the control circuit unit arranged in the second region on the pixel unit and the readout circuit unit arranged in the first region. Further, according to this configuration, correlated double sampling is performed at one location in a time division manner for each pixel in the subsequent stage of the readout circuit section. Therefore, compared with the case where the correlated double sampling is simultaneously performed for each pixel in the previous stage of the readout circuit, this configuration is slower, but the variation for each pixel can be reduced and the circuit scale can be reduced.

(2) In one aspect of the present invention,
The control circuit unit further includes a logic circuit that performs control processing of the imaging circuit device, and the logic circuit, the correlated double sampling circuit, and the output circuit are provided in the second region. It can be arranged along the direction. By arranging a logic circuit that generates a control signal (logic signal) and the like to be supplied to the readout circuit unit, the correlated double sampling circuit, and the output circuit together with the correlated double sampling circuit and the output circuit in a second row, A compact and efficient layout arrangement becomes possible.

  (3) In one aspect of the present invention, the correlated double sampling circuit can be disposed between the logic circuit and the output circuit. In this way, the correlated double sampling circuit can be disposed near the center of the elongated imaging circuit device, and variations in the wiring length from each pixel of the elongated pixel portion to the correlated double sampling circuit are reduced. Thereby, it is possible to suppress the pixel signal of each pixel from being varied due to the difference in wiring load.

  (4) In one aspect of the present invention, the correlated double sampling circuit can be arranged at a position that intersects a center line that bisects the second side of the imaging circuit device in plan view. In this way, the correlated double sampling circuit can be arranged at the center position of the elongated imaging circuit device, and the variation in the wiring length from each pixel of the elongated pixel portion to the correlated double sampling circuit is further reduced. Thereby, it is possible to suppress the pixel signal of each pixel from being varied due to the difference in wiring load.

  (5) In one aspect of the present invention, a chip start signal input terminal and a chip that are disposed at both ends of the terminal group arrangement region in the first direction in a terminal group arrangement region that overlaps the control circuit unit in plan view A terminal group including a start signal output terminal is provided, and the correlated double sampling circuit can be disposed between the chip start signal input terminal and the chip start signal output terminal in plan view. In this way, the correlated double sampling circuit can be disposed near the center of the elongated imaging circuit device, and variations in the wiring length from each pixel of the elongated pixel portion to the correlated double sampling circuit are reduced. Thereby, it is possible to suppress the pixel signal of each pixel from being varied due to the difference in wiring load. Note that a plurality of imaging circuit devices (chips) can be used in series, and therefore, the terminal group includes a chip start signal input terminal and a chip start signal output terminal. In this case, the chip start signal input terminal and the chip start signal output terminal are provided at both ends in the long side direction (first direction) in the terminal group, thereby facilitating connection between the chips.

  (6) In one aspect of the present invention, the readout circuit unit includes a plurality of readout units that are arranged along the first direction and perform readout operations in a time-sharing manner, and the plurality of readout units have a common wiring. And can be connected to the correlated double sampling circuit. Outputs of a plurality of readout units read out in a time division manner are sequentially processed by a correlated double sampling circuit via a common connection line. In this way, correlated double sampling can be performed at one location in a time division manner for each pixel in the subsequent stage of the readout circuit section.

  (7) In one embodiment of the present invention, the readout circuit unit includes a plurality of readout units that are arranged along the first direction and perform readout operation in a time-sharing manner, and a part of the plurality of readout units is a first one. One of the plurality of readout units is connected to a second common line, and the correlated double sampling circuit is switched between the first common line and the second common line by a selector. Can be connected. This reduces the wiring load of the first and second common wirings. Note that the connection to the first common wiring / second common wiring can be odd-numbered / even-numbered of the plurality of readout units, or the right half / left half of the plurality of readout units. Further, the common wiring may be divided into three or more.

  (8) Another aspect of the present invention defines an electronic apparatus having the imaging circuit device described in (1) to (7) above. Examples of this type of electronic device include a scanner device using an imaging circuit device as an image sensor, and a multifunction device in which a printer and / or a copier coexist in the scanner device.

It is a figure which shows the CIS module used for the scanner apparatus of the contact image sensor (CIS) system which is one Embodiment of the electronic device which concerns on this invention. It is a figure which shows the main board | substrate connected via the flexible wiring with the CIS module shown in FIG. It is a timing chart which shows the example of control of a color scan. It is a schematic block diagram of an imaging circuit device (image sensor chip). It is a figure which shows an example of the planar layout of the circuit part and element of an imaging circuit device (image sensor chip). It is a figure which shows the modification which has arrange | positioned the correlation double sampling circuit in the center position of the 2nd area | region. It is a figure which shows the layout of the comparative example with respect to FIG. FIG. 8 is a characteristic diagram showing the position dependency of the output voltage of the image sensor chip of FIGS. 6 and 7. FIG. 8 is a characteristic diagram showing position dependency of output voltage when three image sensor chips of FIG. 6 and FIG. 7 are connected in series. It is a figure which shows an example of the layout of the power supply wiring and bypass capacitor (1st-4th capacitor) of an imaging circuit device (image sensor chip). It is a figure which shows the planar layout of the terminal group of an imaging circuit device (image sensor chip). It is a circuit diagram which shows one pixel and its reading part. It is a figure which shows the output voltage from a read-out circuit part. It is a figure which shows the unit block comprised by the pixel part of 4 pixels, and the reading circuit connected to it, and the control signal supplied to a unit block. It is a figure which shows the circuit which produces | generates the control signal of a front | former stage side transfer gate. 16 is an operation timing chart of the control signal generation circuit shown in FIG. It is an operation | movement timing chart of the unit block shown in FIG. It is a timing chart which shows the production | generation operation | movement of the 1st-4th control signal. It is a figure which shows the comparative example with respect to embodiment of FIG. It is a timing chart which shows the production | generation of the control signal in the main scanning period over 2 lines. It is a figure which shows the layout of a unit block typically. 22A and 22B are diagrams illustrating an example in which the readout circuit unit and the correlated double sampling circuit are connected to each other through a plurality of common wirings and a selector.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not always.

1. FIG. 1 is a diagram showing a CIS module 10 used in, for example, a contact image sensor (CIS) type scanner device which is an embodiment of an electronic apparatus according to the present invention. In FIG. 1, a CIS module 10 includes a light guide 11 that irradiates light on a document 1, a lens array 12 that forms an image of reflected light from the document 1, and an optical element such as a photodiode at a pixel at the image formation position. And an image sensor 13.

  The light guide 11 includes, for example, a light source 14 that makes light incident from the end of the light guide 11 (see FIG. 2). The light guide 11 guides light so that light from a light source, for example, the LED 14 irradiates the entire area of the document 1 in the main scanning direction. The lens array 12 is formed by, for example, a rod lens array. The image sensor 13 has a large number of pixels in the main scanning direction A, and is moved in the sub-scanning direction B together with the light guide 11 and the lens array 12. The CIS scanner device is superior to the optical reduction scanner device in that it has a short optical path, is suitable for thinning, has a small number of parts, consumes less power, and is inexpensive.

  As shown in FIG. 2, the image sensor 13 may be configured by connecting a plurality of image sensor chips 20 in series. In this embodiment, for example, twelve image sensor chips 20 are connected in series. The image sensor chip 20 has, for example, 864 pixels, and the twelve image sensor chips have a total of 864 × 12 = 10368 pixels. One image sensor chip 20 has an elongated shape with a long side of a rectangle of, for example, 18 to 20 mm, and a short side of, for example, 0.5 mm or less.

  As shown in FIG. 2, the CIS module 10 moved in the sub-scanning direction is connected to a main substrate 16 fixed to the scanner device via a flexible wiring 15. A system-on-chip (SoC) 17 and an analog front end (AFE) 18 are mounted on the main board 16. The system on chip (SoC) 17 supplies a clock signal, a control signal, and the like to the CIS module 10. The main board 16 supplies a power supply voltage, a reference voltage, and the like to the CIS module 10. Pixel signals (analog data) from the CIS module 10 are supplied to an analog front end (AFE) 18. The analog front end (AFE) 18 performs analog / digital conversion on the pixel signal and outputs digital pixel data to the system on chip (SoC) 17. The CIS module 10 may be equipped with a power supply IC, an analog front end (AFE) 18, a light source driver, or the like.

  In the case of a color scanner, the R, G, and B LEDs are pulsed in a time-sharing manner as shown in FIG. The image sensor 13 samples and holds the R, G, B light reflected from the document 1 based on the sample hold signal SH shown in FIG.

2. Imaging circuit device (image sensor chip)
2.1. Circuit Layout FIG. 4 shows a schematic block diagram of the image sensor chip 20. The image sensor chip 20 includes a pixel unit 30 in which a light receiving element (e.g., a photodiode) is disposed in each of a plurality of pixels (e.g., 864 pixels), a read circuit unit 40 that converts charges from the pixel unit 30 and reads out the voltages, And a control circuit unit 50 that performs control for outputting a pixel signal based on an output voltage from the readout circuit unit 40. 4 shows an example in which the control circuit unit 50 includes an output unit 60 and a logic unit (logic circuit) 70.

  FIG. 5 shows a more specific block diagram of the image sensor chip 20. In FIG. 5, a rectangular image sensor chip 20 has a first side 20A and a second side 20B that are long sides, and a third side 20C and a fourth side 20D that are short sides. A direction along the long side is defined as a first direction D1, and a direction along the short side is defined as a second direction D2.

  A region in the image sensor chip 20 is divided into two in the second direction D2, and a region along the first side 20A is a first region AR1, and a region along the second side 20B is a second region AR2. In the first area AR1, the pixel unit 30 and the readout circuit unit 40 are arranged. The pixel unit 30 and the readout circuit unit 40 are arranged over substantially the entire region in the first direction D1 in the first region AR1. In other words, the lengths of the long sides 20A and 20B of the image sensor chip 20 are determined by the length of the pixel unit 30 and the readout circuit unit 40 along the first direction D1 + the margin part. That is, no circuit is arranged between the pixel unit 30 and the readout circuit unit 40 and the third side 20C, and between the pixel unit 30 and the readout circuit unit 40 and the fourth side 20D.

  Since the readout circuit unit 40 converts the charges from the respective pixels of the pixel unit 30 into voltage and reads out, the pixel unit 30 and the readout circuit unit 40 are arranged side by side in the second direction D2 in the first area AR. The pixel unit 30 is arranged along the first side 20A, and the readout circuit unit 4 is shifted to the second side 20B side in the second direction D2 relative to the pixel unit 30 (the direction of reading charge from the pixel unit 30). ).

  In the second area AR <b> 2 of the image sensor chip 20, a control circuit unit 50 is disposed as a circuit unit other than the pixel unit 30 and the readout circuit unit 40.

  Here, the output unit 60 of the control circuit unit 50 can include an output circuit 60 </ b> A that outputs a pixel signal based on the output voltage from the readout circuit unit 40. The output unit 60 of the control circuit unit 50 may further include a correlated double sampling circuit (CDS) 60B that performs correlated double sampling processing on the output voltage of the readout circuit unit 40. The correlated double sampling circuit 60B samples the voltage immediately after the reset and after the exposure, and performs a difference process between these to cancel the reset noise and output a voltage corresponding to the light intensity. The output circuit 60A and the correlated double sampling circuit 60B are arranged along the first direction D1 in the second region AR2. In this case, the correlated double sampling circuit 60B performs correlated double sampling processing on the output voltage from the readout circuit unit 40, and is then amplified by the output circuit 60A to output a pixel signal.

  In this manner, a compact and efficient layout arrangement of the pixel unit 30, the readout circuit unit 40, and the control circuit unit 50 (the output circuit 60A and the correlated double sampling circuit 60B) is possible, and a layout suitable for the elongated image sensor chip 20 is achieved. Arrangement can be realized. In addition, it is possible to reduce adverse effects of noise of the control circuit unit 50 arranged in the second area AR2 on the pixel unit 30 and the readout circuit unit 40 arranged in the first area AR1. Further, according to this configuration, correlated double sampling is performed at one location in a time division manner for each pixel in the subsequent stage of the readout circuit unit 40. Therefore, compared with the case where the correlated double sampling is simultaneously performed for each pixel in the previous stage of the readout circuit unit 40, the present configuration is slow, but the variation for each pixel can be reduced and the circuit scale can be reduced.

  As illustrated in FIG. 5, the control circuit unit 50 may further include a logic unit (logic circuit) 70 that performs control processing of the imaging circuit device. In this case, in the second region AR2, the logic unit 70, the correlated double sampling circuit 60B, and the output circuit 60A can be arranged along the first direction D1. A logic unit 70 that generates a control signal (logic signal) and the like supplied to the readout circuit unit 40, the correlated double sampling circuit 60B, and the output circuit 60A is placed in the second area AR2 together with the correlated double sampling circuit 60B and the output circuit 60A. Arranging in a single row enables a compact and efficient layout arrangement.

  The correlated double sampling circuit 60B can be disposed between the logic circuit 70 and the output circuit 60A. More preferably, as shown in FIG. 6, the correlated double sampling circuit 60 </ b> B is disposed at a position that intersects the center line L <b> 1 that bisects the second side 20 </ b> B of the image sensor chip 20 in plan view. it can. Here, the output from the readout circuit section 40 is supplied to the correlated double sampling circuit 60B via the common wiring 120. In any of the cases described above, the correlated double sampling circuit 60B can be disposed near the center of the elongated image sensor chip 20 in the longitudinal direction, and the correlated double sampling circuit 60B can be arranged from each pixel of the pixel portion 30 of the elongated image sensor chip 20. Variations in wiring length up to are reduced. Thereby, it is possible to suppress the pixel signal of each pixel from being varied due to the difference in wiring load.

  This will be described with reference to FIGS. FIG. 7 is a layout of a comparative example for the embodiment and the embodiment of FIG. In the image sensor chip 21 shown in FIG. 7, the control circuit unit 50 is arranged at the end of the image sensor chip 21 in the first direction D <b> 1 rather than the embodiment of FIG. 6. FIG. 8 shows the position dependency characteristic E1 of the pixel signal in the main scanning direction A according to the embodiment of FIG. 6 and the position dependency characteristic E2 of the pixel signal in the main scanning direction A according to the comparative example of FIG. The reason why the output voltage variation is small in the position-dependent characteristic E1 of the embodiment is that, as described above, the variation in the wiring length from each pixel of the pixel unit 30 of the elongated image sensor chip 20 to the correlated double sampling circuit 60B is reduced. Because it is done. In the position dependency characteristic E2 of the comparative example, the variation in the output voltage increases from upstream to downstream in the main scanning direction A. FIG. 9 shows characteristics in which three image sensor chips 20 in FIG. 6 and three image sensor chips 21 in FIG. 7 are connected in series. The difference in output voltage is maximized at the joint between the image sensor chips 21 of the comparative example having the position-dependent characteristic E2. For this reason, a difference in pixel values appears in the form of vertical stripes along the sub-scanning direction B, leading to a reduction in image quality. At the joint between the image sensor chips 20 of the embodiment having the position-dependent characteristic E1, the difference in output voltage is suppressed.

  FIG. 10 is a diagram showing an example of the layout of the power supply wiring and coupling capacitors (first to fourth capacitors 80 to 83) of the image sensor chip 20. As shown in FIG. In FIG. 10, a first high potential side power supply line 100 connected to one end of the first capacitor 80 and a first low potential side power supply line 101 connected to the other end of the first capacitor 80 are: The first region AR1 is wired in parallel with the first direction D1. The second high-potential side power supply line 102 connected to one end of the second capacitor 81 and the second low-potential side power supply line 103 connected to the other end of the second capacitor 81 are in the second region AR2. It is wired in parallel with the first direction D1. The first high potential side power supply line 100 and the second high potential side power supply line 102 are connected by a wiring 105. The first low potential side power supply line 101 and the second low potential side power supply line 103 are connected by a wiring 106. Thus, power can be supplied to the pixel unit 30 and the readout circuit unit 40 from the first high-potential side power supply line 100 and the first low-potential side power supply line 101 arranged in the first area AR1 at the shortest distance. Similarly, power can be supplied to the control circuit unit 50 from the second high potential side power supply line 102 and the second low potential side power supply line 103 arranged in the second region ASR2 in the shortest distance.

  FIG. 11 is a diagram illustrating a planar layout of a terminal group provided in the image sensor chip 20. In FIG. 11, a terminal group including power supply terminals 110 to 112, a chip start signal input terminal 113, and a chip start signal output terminal 114 can be provided in a region overlapping the control circuit unit 50 in plan view. Here, the high potential side power supply (VDD) terminal 110 is connected to the first and second high potential side power supply lines 100 and 102. The low potential side power supply (VSS) terminal 112 is connected to the first and second low potential side power supply lines 101 and 103. A reference power supply (Vref) terminal 111 is supplied with a reference voltage Vref that is connected to a signal output terminal 117 (to be described later) and applied to an output circuit that outputs a pixel signal.

  The chip start signal input terminal 113 and the chip start signal output terminal 114 are used when a plurality of image sensor chips 20 are connected in series as assumed in the description of the characteristics shown in FIG. When a plurality of image sensor chips 20 are connected in series, scanning in the main scanning direction A is started in accordance with reception of a chip start signal from the preceding image sensor chip 20, and after the main scanning is completed, the next stage is scanned. A chip start signal can be output to the image sensor chip 20.

  Here, as is clear from comparison with FIGS. 5, 6, and 11, the correlated double sampling circuit 60 </ b> B is provided between the chip start signal input terminal 113 and the chip start signal output terminal 114 in plan view. Can be arranged. In this way, the correlated double sampling circuit 60B can be arranged near the center of the elongated image sensor chip 20 (FIG. 6). Thereby, as described above, variations in the wiring length from each pixel of the pixel unit 30 of the elongated image sensor chip 20 to the correlated double sampling circuit 60B are reduced. As a result, the pixel signal of each pixel can be prevented from varying due to the difference in wiring load (see the position dependent characteristic E1 in FIG. 8). Further, the chip start signal input terminal 113 and the chip start signal output terminal 114 are easily connected between the chips by providing them at both ends in the first direction D1 in the terminal group.

  Of the terminal group, other terminals such as a clock terminal 115, a reset terminal (also serving as a resolution mode input terminal) 116, a signal output terminal 117, and the like are a power supply terminal 110 to 112 and a chip start signal input terminal 113 or a chip. It can be arranged between the start signal output terminal 114. As will be described later, the control signal Tx1 (see FIG. 14) supplied to the control terminal of the pre-stage transfer gate 200 provided in the readout circuit section 40 can be generated with a boosted voltage. In this case, when the boosted voltage is supplied from the outside of the image sensor chip 20, a boosted voltage input terminal can be provided in the terminal group.

  In the second area AR2 of the image sensor chip 20, in addition to the control circuit unit 50, elements (for example, first to fourth capacitors 80 to 83 to be described later) can be arranged as necessary. Here, in the elongated image sensor chip 20, it is necessary to stabilize the power supplied to each unit arranged in the image sensor chip 20. For this purpose, the first capacitor 80 for stabilizing the power supply of the pixel unit 30 and the readout circuit unit 40 and the second capacitor 81 for stabilizing the power supply of the control circuit unit 50 are provided in the second region AR2. it can. Accordingly, the first capacitor 80 for stabilizing the power supply of the pixel unit 30 and the readout circuit unit 40 is disposed in the second region AR2, and the first capacitor 80 is not disposed in the first region AR1, thereby the image sensor chip. The length of 20 long sides 20A and 20B can be shortened. The first capacitors 80 are disposed in the second region AR2 of the image sensor chip 20 on both outer sides of the control circuit unit 50 in a plan view, preferably at both ends of the image sensor chip 20 in the first direction D1. Can do. Meanwhile, the second capacitor 81 can be disposed between the control circuit unit 50 and the two first capacitors 80 in the first direction D1 in the second region AR2 of the image sensor chip 20.

  Thus, a compact and efficient layout arrangement of the pixel unit 30, the readout circuit unit 40, the control circuit unit 50, and the first and second capacitors 80 and 81 is possible, and a layout arrangement suitable for the elongated image sensor chip 20 is achieved. Can be realized. In addition, it is possible to reduce adverse effects of noise of the control circuit unit 50 arranged in the second area AR2 on the pixel unit 30 and the readout circuit unit 40 arranged in the first area AR1.

  Further, the third capacitor 82 for stabilizing the power supply of the output circuit 60A can be disposed in the second area AR2 of the image sensor chip 20. By providing the third capacitor 82 in addition to the second capacitor 81 for stabilizing the power supply of the control circuit unit 50, the power supply stabilization of the output circuit 60A can be enhanced.

  Further, the fourth capacitor 83 for stabilizing the power supply of the correlated double sampling circuit 60B can be disposed in the second area AR2 of the image sensor chip 20. By providing the fourth capacitor 83 in addition to the second capacitor 81 for stabilizing the power supply of the control circuit unit 50, the power supply stabilization of the correlated double sampling circuit 60B can be enhanced.

2.2. Pixel unit and readout circuit unit 2.2.1. Operation Principle of Pixel Unit and Readout Circuit Unit FIG. 12 is a circuit diagram showing one pixel and its readout unit. In FIG. 12, a light receiving element having a photoelectric conversion function, for example, a photodiode PD is disposed in one pixel of the pixel portion 30. The photodiode PD accumulates charges according to the received light intensity at the cathode.

  In order to read out signal charges from the photodiode PD of one pixel, the readout circuit unit 40 includes a first transfer gate (previous-stage transfer gate) 200, an intermediate storage capacitor C1, a second transfer gate (rear-stage transfer gate) 210, charges A voltage conversion capacitor C2, a reset transistor 220, a pixel output transistor 230, and a selection transistor 310; The charge-voltage conversion capacitor C2 is provided in the floating diffusion region FD (floating diffusion). The photodiode PD, the first transfer gate 200, and the second transfer gate 210 are connected in series between the fixed voltage VSS and the floating diffusion FD. Further, in the case where an analog shift register is provided in the final stage of the reading circuit unit 40 illustrated in FIG. 5, the selection transistor 310 can be included in the analog shift register.

  The first transfer gate 200 transfers the charge stored in the photodiode PD to the intermediate storage capacitor C1. The second transfer gate 210 transfers the charge stored in the intermediate storage capacitor C1 to the charge-voltage conversion capacitor C2 (floating diffusion FD). The charge-voltage conversion capacitor C2 performs charge-voltage conversion. The reset transistor 220 resets the potential of the charge-voltage conversion capacitor C2 (floating diffusion FD) to the initial potential. The pixel output transistor 230 outputs a voltage corresponding to the voltage converted by the charge-voltage conversion capacitor C2 (floating diffusion FD). The selection transistor 310 selects the output of the pixel output transistor 230 in the order according to the main scanning direction. The output of the selection transistor 310 becomes the output voltage Vs of the readout circuit unit 40.

  FIG. 13 shows the reset control signal Vrst and the output voltage Vs of the readout circuit unit 40. The output Vs of the read circuit section 40 is lowered according to the signal charge amount stored in the photodiode PD after being reset to the initial voltage Vdd. That is, the signal component is Vdd−Vs, and this signal component is acquired by the correlated double sampling circuit 60B described above.

2.2.2. Unit Block of Pixel Unit and Readout Circuit In this embodiment, the mode can be switched to a plurality of levels, for example, three levels (for example, 1200 dpi, 600 dpi, and 300 dpi). Therefore, as shown in FIG. 14, four photodiodes (first to fourth photodiodes) PDa to PDd that are continuous in the main scanning direction A, and a read circuit unit 40 that converts signal charges from them into voltage and reads them. This constitutes the unit block 40A. The number N of unit blocks 40A provided in one image sensor chip 20 is N = 216.

  The unit block 40A includes first to fourth front-stage transfer gates 200a to 200d, first to fourth rear-stage transfer gates 210a to 210d, one reset transistor 220, and one pixel output transistor 230. That is, one reset transistor 220 and one pixel output transistor 230 are shared by the first to fourth photodiodes PDa to PDd.

  Here, regardless of the resolution mode, the first to fourth pre-stage transfer gates 200a to 200d are simultaneously turned on. On the other hand, the timings at which the first to fourth rear transfer gates 210a to 210d are turned on differ depending on the resolution mode.

  In the high resolution mode (1200 dpi), the first to fourth rear transfer gates 210a to 210d are turned on at different timings. Accordingly, voltages Vs1 to Vs4 corresponding to the signal charges of the first to fourth photodiodes PDa to PDd are output from the unit block 40A in a time division manner.

  In the low resolution mode (300 dpi), the first to fourth rear transfer gates 210a to 210d are simultaneously turned on. Thereby, a voltage Vs corresponding to the total signal charge of the first to fourth photodiodes PDa to PDd is output from the unit block 40A (the first to fourth photodiodes PDa to PDd are one pixel).

  In the medium resolution mode (600 dpi), the first and second rear-stage transfer gates 210a and 210b are simultaneously turned on, and then the third and fourth rear-stage transfer gates 210c and 210d are simultaneously turned on. As a result, the voltage Vs1 corresponding to the total signal charge of the first and second photodiodes PDa and PDb and the voltage Vs2 corresponding to the total signal charge of the third and fourth photodiodes PDc and PDd are unit blocks. 40A is output in a time-sharing manner (the first and second photodiodes PDa and PDb are one pixel, and the third and fourth photodiodes PDc and PDd are one other pixel).

  Note that the time for exposing the document 1 of FIG. 1 is also changed according to the resolution mode. The exposure time is the longest in the high resolution mode and the shortest in the low resolution mode. Therefore, high speed scanning is possible as an advantage of the low resolution mode.

2.2.3. FIG. 14 shows control signals Tx1 supplied to the first to fourth front-stage transfer gates 200a to 200d and the first to fourth rear-stage transfer gates 210a. The first to fourth control signals Tx2a to Tx2d supplied to ˜210d are shown. As described above, the first to fourth pre-stage transfer gates 200a to 200d are simultaneously turned on regardless of the resolution mode, so that the common control signal Tx1 is supplied to each control terminal.

  Here, the control signal Tx1 supplied to the first to fourth pre-stage transfer gates 200a to 200d and the first to fourth control signals supplied to the first to fourth post-stage transfer gates 210a to 210d. The voltage level is different from Tx2a to Tx2d. The control signal Tx1 supplied to the first to fourth pre-stage transfer gates 200a to 200d is at a voltage level higher than the power supply voltage. For example, when the control signal Tx1 supplied to the first to fourth pre-stage transfer gates 200a to 200d is an NMOS gate, the control signal Tx1 having a voltage level higher than the power supply voltage is supplied to the gate. As a result, the first to fourth pre-stage transfer gates 200a to 200d when turned on do not saturate the charge transfer capability at the exposure intensity equal to or lower than the specified value, or can improve the saturation level. Therefore, the signal charges stored in the first to fourth photodiodes PDa to PDd can be transferred with high transfer capability via the first to fourth pre-stage transfer gates 200a to 200d. Thereby, an image with high contrast can be formed.

  On the other hand, the first to fourth control signals Tx2a to Tx2d supplied to the first to fourth rear transfer gates 210a to 210d are generated via CMOS logic circuits 500a to 500d, respectively, as shown in FIG. Is done. As a comparative example, a control signal generated via an NMOS that is not a CMOS logic circuit drops in voltage by a threshold value, so that the charge transfer capability of the rear transfer gate is inferior. Since the CMOS logic circuits 500a to 500d can generate the first to fourth control signals Tx2a to Tx2d without voltage drop, the transfer capability of the first to fourth rear-stage transfer gates 210a to 210d can also be enhanced.

  According to the experiment of the present inventor, a sensor for output at dark time and output at 50% light saturation using a plurality of types of CMOS logic circuits and a plurality of types of NMOS manufactured under different process conditions (threshold value Vth). The output level was compared. In the case of dark output, the difference in sensor output level using various NMOSs was about 0.6 mV, but the difference in sensor output level using various CMOS logic circuits was drastically reduced to about 0.03 mV. did. Even in the case of output at 50% saturation, the difference in sensor output level using various NMOS was about 0.4 mV, but the difference in sensor output level using various CMOS logic circuits was up to about 0.2 mV. Declined. From this, it was found that the influence on the sensor output level due to the process variation is reduced by using the CMOS logic circuit. Thereby, the process margin can be expanded.

  In FIG. 14, the CMOS logic circuits 500a to 500d are formed of transfer gates composed of PMOS and NMOS, but the invention is not limited to this. As the CMOS logic circuits 500a to 500d, other CMOS logic circuits, for example, a clocked CMOS logic circuit, an AND gate circuit, or the like having no voltage drop can be used.

  FIG. 15 shows an example of the control signal generation circuit 510 that generates the control signal Tx1. The control signal generation circuit 510 may be built in the logic unit 70 of the image sensor chip 20 or may be mounted on the main board 16 in FIG. The control signal generation circuit 510 illustrated in FIG. 15 performs a boost operation in accordance with a period during which the first to fourth pre-stage transfer gates 200a to 200d are turned on, and performs an intermittent operation so that the operation is stopped in other periods.

  A control signal generation circuit 510 illustrated in FIG. 15 includes an AND gate 511, a booster circuit 512, and a reset transistor 513. The AND gate 511 outputs a logical product signal 523 of the clock signal 521 and the boost period signal 522 shown in FIG. The booster circuit 512 outputs the control signal Tx1 stepped up in accordance with the clock signal 523 input during the boosting period defined by the boosting period signal 522, and the boosting operation is stopped in other periods. Therefore, the booster circuit 512 performs a boost operation in accordance with a period during which the first to fourth pre-stage transfer gates 200a to 200d are turned on, and performs an intermittent operation so that the operation is stopped in other periods. An inverted signal 524 of the boost period signal 522 is input to the gate of the reset transistor 513. When the reset transistor 513 is turned on outside the boost period, the control signal Tx1 becomes LOW outside the boost period.

  The operation of the unit block 40A will be described with reference to the timing chart shown in FIG. First, light (LED or the like) is applied to the photodiodes PDa to PDd, charges are generated by the photodiodes PDa to PDd, and the charges are accumulated. A control signal generation circuit 510 shown in FIG. 15 outputs a boosted control signal Tx1. The first to fourth pre-stage transfer gates 200a to 200d are turned on by the boosted control signal Tx1, and the signal charges stored in the first to fourth photodiodes PDa to PDd are transferred to the first to fourth pre-stage transfer gates 200a to 200d. Transfer is performed below the side transfer gates 200a to 200d. At this time, since the areas of the photodiodes PDa to PDd are large, it is necessary to collect charges from a wide range under the gates of the first to fourth front-side transfer gates 200a to 200d. Therefore, charges are easily collected by boosting the voltage of the control signal Tx1 supplied to the gates of the first to fourth pre-stage transfer gates 200a to 200d and increasing the potential gradient. Next, when the control signal Tx1 becomes LOW, the charges stored under the gates of the first to fourth front transfer gates 200a to 200d are transferred to the intermediate accumulation region C1.

  On the other hand, when the boosting is stopped and the control signal Tx1 becomes LOW by the reset transistor 513 in FIG. 15, the reset signal RST becomes HIGH next, and the reset transistor 220 in FIG. 14 is turned on. As a result, the floating diffusion FD (charge-voltage conversion capacitor C2) is reset to the initial voltage Vdd.

  Thereafter, in the high resolution mode (1200 dpi), the first to fourth control signals Tx2a to Tx2d sequentially become HIGH as shown in FIG. The first to fourth rear transfer gates 210a to 210d are sequentially turned on by the first to fourth control signals Tx2a to Tx2d. As a result, the charges respectively stored in the intermediate storage region C1 are transferred below the first to fourth rear transfer gates 210a to 210d. At this time, since the first to fourth rear-stage transfer gates 210a to 210d have a small transfer source area, charges are transferred even if there is no boosted voltage like the first to fourth front-stage transfer gates 200a to 200d. it can. Thereafter, when the first to fourth control signals Tx2a to Tx2d become LOW, the charges stored under the gates of the first to fourth rear-stage transfer gates 210a to 210d are changed to the first to fourth rear-stage transfer gates. The data is transferred to one floating diffusion FD (charge-voltage conversion capacitor C2) connected to each of 210a to 210d. The voltage of the floating diffusion FD changes in the same manner as in FIG. 13 according to the signal charge. The four floating diffusions FD are connected to the gate of the pixel output transistor 230 through a common wiring. Accordingly, the pixel output transistor 230 is driven according to the voltages of the four floating diffusions FD. Output voltages Vs (see FIG. 13) of the four pixels are selected and output by the selection transistor 310 shown in FIG.

  Next, generation of the first to fourth control signals Tx2a to Tx2d will be described with reference to the timing chart of FIG. The logic unit 70 generates timing signals Tx2a1 to Tx2d1 shown in FIG. 18 and supplies them to all the unit blocks 40A. The logic unit 70 further generates post-transfer period timing signals Tx2 and Tx2r shown in FIG. 18 that are specific to one unit block 40A. The first to fourth CMOS logic circuits 500a to 500d shown in FIG. 14 maintain the voltages of the timing signals Tx2a1 to Tx2d1, which are input signals, based on the subsequent transfer period timing signals Tx2 and Tx2r inputted to the control terminals. Transfer as is. The high level of the first to fourth control signals Tx2a to Tx2d generated thereby is Vdd. Note that the timing signals Tx2a1 to Tx2d1 are changed to HIGH timing by the resolution mode signal, and FIG. 18 shows an example of the high resolution mode (1200 dpi).

  FIG. 19 shows a comparative example for the embodiment of FIG. In FIG. 19, first to fourth NMOS gates 501 a to 501 d are provided instead of the first to fourth CMOS logic circuits 500 a to 500 d of FIG. 14. When a high level signal is input to the NMOS gates 501a to 501d, a voltage drop corresponding to the threshold voltage Vth occurs in the output signal. Accordingly, in the comparative example of FIG. 19, the control signal Tx2a (Tx2b to Tx2d is the same) having a voltage drop as shown by the broken line is generated in the control signal Tx2a of FIG. The transfer capability at 210d is reduced.

  FIG. 20 is a timing chart showing generation of control signals in the main scanning period over two lines. In FIG. 20, a control signal MR is a start timing signal for starting main scanning of each line, and the resolution mode (1200 dpi, 600 dpi, 300 dpi) can be specified by the pulse width of the control signal MR. When the control signal MR becomes active, the booster circuit 512 of FIG. 15 starts the boosting operation according to the timing chart shown in FIG. As a result, a boosted control signal Tx1 is generated, and after a predetermined boosting period, the boosting operation is stopped and the control signal Tx1 becomes LOW. Thereby, the signal charges of the photodiodes PD of all the pixels of the twelve image sensor chips 20 (1) to 20 (12) are simultaneously transferred to the intermediate storage capacitor C1 by the front-side transfer gate 200 (200a to 200d). .

  Thereafter, as shown in FIG. 20, the reset signal RST and the first to fourth units of the twelve image sensor chips 20 (1) to 20 (12) for each unit block 40 </ b> A in order from the upstream side in the main scanning direction A. Control signals Tx2a to Tx2d are generated. As a result, the charges are transferred to the floating diffusion FD by the procedure according to the resolution mode by the first to fourth rear-stage transfer transistors 210a to 210d and subjected to charge-voltage conversion. Thereafter, the operation is repeated for all the unit blocks 40A of one image sensor chip 20. When the operation of the most upstream image sensor chip 20 (1) in the main scanning direction A is completed, the remaining 11 image sensor chips 20 (2) to 20 (12) are sequentially started from the upstream in the main scanning direction A. The operation is repeated. Thereby, the main-scanned pixel signal for the first line can be output. The same operation as the first line is repeated for the second and subsequent lines.

  Here, the period during which the boosted control signal Tx1 is generated, that is, the period during which the booster circuit 512 of FIG. 15 performs the boosting operation is only the slight head period of the main scanning period (between two active MR signals) of each line. It is. As described above, the booster circuit 512 becomes an intermittent operation that operates only for a slight boosting period, and power saving is achieved. However, in order to transfer charges from the light receiving elements PDa to PDd having a relatively large area during the boosting period, the boosting period (the HIGH period of the control signal Tx1) is set longer than the HIGH period of the control signals Tx2a to Tx2d. .

2.2.4. Unit Block Layout of Pixel Unit and Reading Circuit FIG. 21 schematically shows the layout of the unit block 40A. In FIG. 21, the first front-stage transfer gate 200a and the second front-stage transfer gate 200b have a first common gate 201A. Similarly, the third front-stage transfer gate 200c and the fourth front-stage transfer gate 200d have a second common gate 201B. These first and second common gates 201A and 201B are connected to a control signal line 250 extending along the first direction D1 of the image sensor chip 20, and supplied with a control signal Tx1.

  The gate 211a of the first rear transfer transistor 210a is connected to a CMOS logic circuit 500a (not shown in FIG. 21, see FIG. 14) connected between the gate wiring 211a1 and the first control signal line 251. The first control signal Tx2a is supplied. The gate 211b of the second rear transfer transistor 210b is connected to a CMOS logic circuit 500b (not shown in FIG. 21, see FIG. 14) connected between the gate wiring and the second control signal line 252. Control signal Tx2b is supplied. The gate 211c of the third rear transfer transistor 210c is connected to a CMOS logic circuit 500c (not shown in FIG. 21, see FIG. 14) connected between the gate wiring and the third control signal line 253. 3 The control signal Tx2c is supplied. The gate 211d of the fourth rear transfer transistor 210d is connected to a CMOS logic circuit 500d (not shown in FIG. 21, see FIG. 14) connected between the gate wiring 211d1 and the fourth control signal line 254. A fourth control signal Tx2d is supplied.

  In FIG. 21, a common wiring 256 electrically connected to the floating diffusion FD is connected to the drain of the reset transistor 220 and the gate 231 of the pixel output transistor 230.

  The first front-stage transfer gate 200a and the second front-stage transfer gate 200b are arranged to be biased toward the first extension line L1 that extends the boundary line between the first photodiode PDa and the second photodiode PDb. The first common gate 201A intersects the first extension line L1 in plan view. In addition, the first rear-stage transfer gate 210a and the second rear-stage transfer gate 210b are located at positions closer to the second direction D2 than the first front-stage transfer gate 200a and the second front-stage transfer gate 200b. For example, the first front-side transfer gate 200a and the second front-side transfer gate 200b are arranged so as to be opposed to the first extension line side L1 so as to face each other.

  In the present embodiment, the center line of the first common gate 201A of the first front-stage transfer gate 200a and the second front-stage transfer gate 200b substantially matches the first extension line L1. The gates 211a and 211b of the first rear transfer gate 210a and the second rear transfer gate 210b are arranged at positions where the center lines of the respective gate widths are symmetrical with respect to the first extension line L1. .

  As a result, the length of the charge transfer path from the first photodiode PDa (pixel) through the first front-stage transfer gate 200a to the other end (floating diffusion FD) of the first rear-stage transfer gate 210a, the second The difference in the length of the charge transfer path from the photodiode PDb (pixel) to the other end (floating diffusion FD) of the second rear-stage transfer gate 210b through the second front-stage transfer gate 200b can be reduced. Therefore, variations in pixel signals due to the difference between the lengths of the charge transfer paths from the two pixels PDa and PDb are reduced. Therefore, even in the low resolution mode in which the first and second rear transfer gates 210a and 210b are simultaneously turned on, and in the high resolution mode in which the first and second rear transfer gates 210a and 210b are turned on in a time division manner, the pixels Variations between signals are reduced.

  In addition, an empty space is secured on both sides of the first and second front-stage and rear-stage transfer gates 200a, 200b, 210a, and 210b in the area of the pixel width. Therefore, it can be used as a wiring space in the same layer as the gates 201A, 211a, 211b. In the present embodiment, in FIG. 21, the gate wiring 211a1 and the like are formed in the empty space on the right side of the first front-stage and rear-stage transfer gates 200a and 210a.

  The layout described above for the first and second front-stage and rear-stage transfer gates 200a, 200b, 210a, and 210b is also applied to the third and fourth front-stage and rear-stage transfer gates 200c, 200d, 210c, and 210d. Has been. For this reason, even in the low resolution mode in which the first to fourth rear-stage transfer gates 210a to 210d are simultaneously turned on and in the high resolution mode in which the first to fourth rear-stage transfer gates 210a to 210d are turned on in four divisions, the first Even in the medium resolution mode in which the first to fourth rear-stage transfer gates 210a to 210d are turned on in two, variations between pixel signals are reduced.

  Next, prevention of deterioration in signal voltage due to capacitive coupling between wirings will be described. According to the earnest study of the present inventor, when the common output line 256 electrically connected to the floating diffusion FD and the gate wiring 211a1 of the first rear transfer transistor 210a are close to each other, the capacitance between the wirings It has been found that the signal voltage of the common output line 256 varies due to the coupling. Similarly, when the common output line 256 and the gate wiring 211d1 of the fourth rear transfer transistor 210d are close to each other, the signal voltage of the common output line 256 varies due to capacitive coupling between the wirings.

  When the voltages of the gate wirings 211a1 and 211d1 are HIGH, signal charges are supplied to the floating diffusion FD via the second rear transfer gates 210a and 210d, and signal-voltage conversion is performed to generate signal voltages. This signal voltage is supplied to the gate 231 of the pixel output transistor 230 via the common wiring 256. When the voltage of the gate wirings 211a1 and 211d1 is HIGH, the common wiring 256 is adversely affected.

  In this embodiment, the first control signal Tx2a is supplied to the common wiring 256 connected to the floating diffusion FD on the other end side of the first second-stage transfer gate 210a and the first second-stage transfer gate 210a in plan view. A shield line is provided between the gate wiring 211a1 to be supplied. As this shield line, a reset control signal line 221a for supplying a reset signal to the gate 221 of the reset transistor 220 was used. In this case, the gate wiring 211a1 and the common wiring 256 are not capacitively coupled by the reset control signal line 221a. Therefore, even if the potential of the gate wiring 211a1 changes, the potential of the common wiring 256 can be suppressed from changing. Note that at the timing when the signal voltage is output from the common wiring 256, the reset control signal line 211a1 is at a fixed potential.

  In the present embodiment, the fourth control signal Tx2d is further supplied to the common wiring 256 connected to the floating diffusion FD on the other end side of the fourth rear-stage transfer gate 210d and the fourth rear-stage transfer gate 210d in plan view. A shield line is provided between the gate wiring 211d1 and the gate wiring 211d1. As this shield line, a dummy wiring 257 that is electrically connected to the reset control signal line 221a and the control signal wiring 255 is used. Accordingly, the gate wiring 211d1 and the common wiring 256 are not capacitively coupled by the dummy wiring 257, so that the potential of the common wiring 256 can be prevented from changing even if the potential of the gate wiring 211d1 changes. Note that at the timing when the signal voltage is output from the common wiring 256, the dummy wiring 257 that is electrically connected to the reset control signal line 221a and the control signal wiring 255 has a fixed potential.

2.2.6. Connection form of readout circuit unit and correlated double sampling circuit In FIG. 6, it has been described that the readout circuit unit 40 and the correlated double sampling circuit 60B are connected by the common wiring 120. The wiring load of 120 cannot be ignored. Therefore, as shown in FIGS. 22A and 22B, a plurality of, for example, two common wires 120A and 120B can be divided to reduce the wiring load. In FIGS. 22A and 22B, the read circuit unit 40 includes a plurality of read units 301. In the case of FIG. 22A, the readout unit 301 on the upstream side of the readout circuit unit 40 in the main scanning direction A, for example, is connected to the first common wiring 120A, and the readout unit 301 on the downstream side is connected to the second common wiring 120B. The In the case of FIG. 22B, for example, odd-numbered read units 301 of the read circuit section 40 are connected to the first common wiring 120A, and even-numbered read units 301 are connected to the second common wiring 120B. In either case, the first common line 120A and the second common line 120B are switched by the selector 130 and connected to the correlated double sampling circuit 60B.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

20 imaging circuit device (image sensor chip), 20A first side, 20B second side, 30 pixel unit, 40 reading circuit unit, 40A unit block, 50 control circuit unit, 60 output unit, 60A output circuit, 60B correlation Double sampling circuit (CDS), 70 logic part (logic circuit), 110 high potential side power supply terminal, 111 reference power supply terminal, 112 low potential side power supply terminal, 113 start signal input terminal, 114 start signal output terminal, 120 common wiring , 120A, 120B, first and second common wiring, 130 selector, 301 reading unit (register unit), A main scanning direction, B sub-scanning direction, AR1 first area, AR2 second area, D1 first direction, D2 first 2-way, FD floating diffusion, PDa to PDd

Claims (8)

A pixel portion in which a light receiving element is disposed in each of a plurality of pixels;
A readout circuit unit that converts the electric charge from the pixel unit into a voltage and reads the voltage;
A control circuit unit that performs control for outputting a pixel signal based on an output voltage from the readout circuit unit;
An imaging circuit device comprising:
The control circuit unit is
A correlated double sampling circuit that performs correlated double sampling processing on the output voltage from the readout circuit unit;
An output circuit that outputs the pixel signal based on an output voltage from the correlated double sampling circuit;
Have
A region along the first side that is the long side of the imaging circuit device that is rectangular is defined as a first region, and a region along the second side that faces the first side of the imaging circuit device is defined as a second region. If it is an area,
In the first region, the pixel portion and the readout circuit portion are disposed,
The imaging circuit device, wherein the correlated double sampling circuit and the output circuit are arranged in the second region along a first direction parallel to the second side. The imaging circuit device according to claim 1,
The control circuit unit further includes a logic circuit that performs control processing of the imaging circuit device,
The imaging circuit device, wherein the logic circuit, the correlated double sampling circuit, and the output circuit are arranged along the first direction in the second region. The imaging circuit device according to claim 2,
2. The imaging circuit device according to claim 1, wherein the correlated double sampling circuit is arranged between the logic circuit and the output circuit. In the imaging circuit device according to claim 1 or 2,
The correlated double sampling circuit is arranged at a position that intersects a center line that bisects the second side of the imaging circuit device in plan view. In the imaging circuit device according to claim 1 or 2,
A terminal group including a chip start signal input terminal and a chip start signal output terminal arranged at both ends of the terminal group arrangement area in the first direction in a terminal group arrangement area overlapping the control circuit unit in plan view. Provided,
The correlated double sampling circuit is disposed between the chip start signal input terminal and the chip start signal output terminal in plan view, and is an imaging circuit device. The imaging circuit device according to any one of claims 1 to 5,
The readout circuit unit includes a plurality of readout units that are arranged along the first direction and that perform readout operations in a time-sharing manner.
The imaging circuit device, wherein the plurality of readout units are connected to the correlated double sampling circuit via a common wiring. The imaging circuit device according to any one of claims 1 to 5,
The readout circuit unit includes a plurality of readout units that are arranged along the first direction and that perform readout operations in a time-sharing manner.
A part of the plurality of readout units is connected to a first common wiring, another part of the plurality of readout units is connected to a second common wiring, and the first common wiring and the second common wiring are selected by a selector. The imaging circuit device is connected to the correlated double sampling circuit by switching between the two.   An electronic apparatus comprising one imaging circuit device according to claim 1, or a plurality of imaging circuit devices connected in series.