JP6475093B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having an element isolation region.

  Patent Document 1 below discloses a semiconductor integrated circuit having an element isolation region (element isolation structure). The semiconductor integrated circuit is formed of a p-type semiconductor substrate, and an n-type well region and a p-type well region are formed on the main surface portion of the semiconductor substrate. A p-type MOS transistor having a pair of p-type semiconductor regions is formed in the n-type well region, and an n-type MOS transistor having a pair of n-type semiconductor regions is formed in the p-type well region. The element isolation region is disposed between the n-type well region and the p-type well region on the main surface portion of the semiconductor substrate. The element isolation region is formed by a p-type isolation well region having the same depth and the same impurity density as the p-type well region, and the p-type isolation well region is connected to the ground terminal.

  In the semiconductor integrated circuit, for example, when a surge is applied to the p-type semiconductor region of the p-type MOS transistor, the surge causes breakdown at the pn junction between the p-type semiconductor region and the n-type well region. Carrier flows into the area. For this reason, in a parasitic pnp bipolar transistor in which the p-type semiconductor region is the collector region, the n-type well region is the base region, and the p-type semiconductor substrate is the emitter region, the base potential rises, and the base region increases from the emitter region to the emitter region. Directional current flows. As a result, the parasitic pnp bipolar transistor operates and a surge flows to the semiconductor substrate.

  Here, since the impurity density of the p-type isolation well region is generally set lower than that of the p-type semiconductor region, the resistance of the p-type isolation well region is high, and the surge hardly flows to the ground terminal. Therefore, the base potential rises in a parasitic npn bipolar transistor in which the n-type well region is the collector region, the p-type isolation well region is the base region, and the n-type semiconductor region of the MOS transistor is the emitter region. As a result, a forward current flows from the base region to the emitter region, the parasitic npn-type bipolar transistor operates, and a surge flows from the collector region (n-type well region) to the emitter region (n-type semiconductor region). For this reason, when a surge is applied, the p-type MOS transistor and the n-type MOS transistor cannot be electrically isolated from each other in the element isolation region, so there is room for improvement.

JP 11-135645 A

  In view of the above-described facts, an object of the present invention is to obtain a semiconductor integrated circuit having an element isolation region capable of improving the isolation performance against surge between complementary insulated gate field effect transistors.

  A semiconductor integrated circuit according to a first aspect of the present invention is provided in a first conductivity type first semiconductor region connected to a fixed potential and a first region of a main surface portion of the first semiconductor region, and the first conductivity type A first well region of a second conductivity type opposite to the mold; a first insulated gate field effect transistor provided on a main surface portion of the first well region and having a pair of first main electrode regions of the first conductivity type; A first conductivity type second well region provided in a second region different from the first region of the main surface portion of the first semiconductor region, and a second conductivity type pair provided in the main surface portion of the second well region. A second insulated gate field effect transistor having the second main electrode region, and a third semiconductor electrode region in the third region between the first region and the second region of the main surface portion of the first semiconductor region. And a second surface provided on the main surface of the third main electrode region and connected to a fixed potential. A first bipolar structure including a first control electrode region of electric type and a fourth main electrode region of a first conductivity type provided on a main surface portion of the first control electrode region and connected to a fixed potential. And an element isolation region having a transistor.

  In the semiconductor integrated circuit according to claim 1, a first well region of the second conductivity type is provided in the first region of the main surface portion of the first semiconductor region of the first conductivity type connected to the fixed potential, and the first semiconductor region A second well region of the first conductivity type is provided in the second region of the main surface portion. A main surface portion of the first well region is provided with a first insulated gate field effect transistor having a pair of first main electrode regions of the first conductivity type. A second insulating gate field effect transistor having a pair of second main electrode regions of the second conductivity type is provided on the main surface portion of the second well region. An element isolation region is provided in a third region between the first region and the second region of the main surface portion of the first semiconductor region.

  Here, the element isolation region has a first bipolar transistor. The first bipolar transistor includes a first conductivity type third main electrode region, a second conductivity type first control electrode region, and a first conductivity type fourth main electrode region. The third main electrode region is formed by the first semiconductor region. The first control electrode region is provided on the main surface portion of the third main electrode region and is connected to a fixed potential. The fourth main electrode region is provided on the main surface portion of the first control electrode region and is connected to a fixed potential. For this reason, when a surge flows in the first semiconductor region in the element isolation region, the surge is absorbed to a fixed potential by the operation of the first bipolar transistor before the operation of the parasitic bipolar transistor. The parasitic bipolar transistor is formed with the first well region as one main electrode region and the second main electrode region of the second insulated gate field effect transistor as the other main electrode region.

  In a semiconductor integrated circuit according to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the element isolation region includes the fourth main electrode region and the first control electrode region of the first bipolar transistor. A contact region that is formed in the depth direction of the first semiconductor region and electrically connects the first semiconductor region and the fixed potential is provided.

  According to the semiconductor integrated circuit of the second aspect, the contact region is provided in the element isolation region. The contact region is formed in the depth direction of the first semiconductor region along the fourth main electrode region and the first control electrode region of the first bipolar transistor, and the contact region electrically connects the first semiconductor region and the fixed potential. Connected to. For this reason, the potential of the first semiconductor region can be stabilized in the element isolation region.

  In a semiconductor integrated circuit according to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the first control electrode region has the same junction depth as the first well region and the same impurity. It is formed by density.

  According to the semiconductor integrated circuit of the third aspect, the first control electrode region of the first bipolar transistor is formed with the same junction depth and the same impurity density as the first well region. Easy to use.

  A semiconductor integrated circuit according to a fourth aspect of the present invention is the semiconductor integrated circuit according to any one of the first to third aspects, wherein the first region, the second region, and the main region of the first semiconductor region A fifth main electrode region of a second conductivity type provided in a fourth region different from the third region and formed with the same junction depth and the same impurity density as the first well region; and a fifth main electrode region A second conductivity type second control electrode region provided on the main surface portion of the second control electrode region, and a second conductivity type sixth main electrode region provided on the main surface portion of the second control electrode region. A bipolar transistor is further provided, and the fourth main electrode region is formed with the same junction depth and the same impurity density as the second control electrode region.

  According to the semiconductor integrated circuit of the fourth aspect, the second bipolar transistor is provided in the fourth region different from the first region, the second region, and the third region of the main surface portion of the first semiconductor region. The second bipolar transistor includes a second conductivity type fifth main electrode region, a first conductivity type second control electrode region, and a second conductivity type sixth main electrode region. The fifth main electrode region is formed with the same junction depth and the same impurity density as the first well region. The second control electrode region is provided on the main surface portion of the fifth main electrode region. The sixth main electrode region is provided on the main surface portion of the second control electrode region.

  Here, since the fourth main electrode region of the first bipolar transistor is formed with the same junction depth and the same impurity density as the second control electrode region of the second bipolar transistor, the second control electrode region is used. And easy to form.

A semiconductor integrated circuit according to a fifth aspect of the present invention is the semiconductor integrated circuit according to the fourth aspect, wherein the fourth main electrode region and the first control electrode region of the first bipolar transistor are provided in the element isolation region. The contact region formed in the depth direction of the first semiconductor region along the line and electrically connecting the first semiconductor region and the fixed potential has the same depth as the second well region and the same impurity density. A first well-type third well region, a first-conductivity-type fourth well region formed with the same junction depth and the same impurity density as the second control electrode region, and a first main electrode region; And a first conductivity type second semiconductor region formed with the same impurity density as the first main electrode region.

  According to another aspect of the semiconductor integrated circuit of the present invention, the contact region includes a first conductivity type third well region, a first conductivity type fourth well region, and a first conductivity type second semiconductor region. Consists of. The third well region is formed with the same depth and the same impurity density as the second well region. The fourth well region is formed with the same junction depth and the same impurity density as the second control electrode region. The second semiconductor region is formed with the same depth as the junction depth of the first main electrode region and the same impurity density as the first main electrode region. Therefore, the contact region is easily formed using the second well region, the second control electrode region, and the first main electrode region.

  ADVANTAGE OF THE INVENTION According to this invention, it has the outstanding effect that the semiconductor integrated circuit provided with the element isolation region which can improve the isolation performance with respect to the surge between complementary insulated gate field effect transistors can be obtained.

It is principal part sectional drawing of the semiconductor integrated circuit provided with the element isolation region which concerns on one embodiment of this invention. FIG. 6 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor integrated circuit shown in FIG. 1. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is 4th process sectional drawing. It is 5th process sectional drawing.

  Hereinafter, a semiconductor integrated circuit including an element isolation region according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a cross-sectional structure of a semiconductor integrated circuit in which the wiring and interlayer insulating film on the main surface of the semiconductor substrate are omitted and the structure is easily understood.

(Vertical cross-sectional structure of a semiconductor integrated circuit)
As shown in FIG. 1, the semiconductor integrated circuit 10 according to the present embodiment includes a semiconductor substrate 12. The semiconductor substrate 12 is used as a first semiconductor region that is electrically isolated from other regions. In the present embodiment, it is formed of a silicon (Si) substrate set to p-type as the first conductivity type. The semiconductor substrate 12 is connected to a ground terminal GND to which a fixed potential for circuit operation is supplied. The impurity density of the semiconductor substrate 12 is set to 10 ¹⁵ atoms / cm ³ , for example, and the specific resistance value of the semiconductor substrate 12 is set to 8 Ω · cm to 12 Ω · cm, for example.

  A first region A1, a second region A2, a third region A3, and a fourth region A4 are set in the main surface portion including the main surface 12A of the semiconductor substrate 12. In the first region A1, a p-channel IGFET 14 serving as one first IGFET of a complementary insulated gate field effect transistor (hereinafter referred to as “IGFET”) is disposed. The second region A2 is set at a different position from the first region A1, and the n-channel IGFET 16 as the other second IGFET of the complementary IGFET is disposed in the second region A2. Here, the n-type is the second conductivity type opposite to the first conductivity type. The third region A3 is set between the first region A1 and the second region A2, and an element isolation region 18 that electrically isolates the IGFET 14 and the IGFET 16 is disposed in the third region A3. The fourth region A4 is set at a position different from the first region A1, the second region A2, and the third region A3, and the fourth region A4 has an npn-type bipolar transistor 20 as a second bipolar transistor in the present embodiment. Is arranged.

In the first region A1, the main surface portion of the semiconductor substrate 12 is provided with an n-type well region 22A as a first well region. The n-type well region 22A has, for example, a junction depth of 3 μm or more, is set to an impurity density of 10 ¹⁶ atoms / cm ³ to 10 ¹⁷ atoms / cm ³ , and is 0.07 Ω · cm to 0.5 Ω · cm. The specific resistance value is set.

The IGFET 14 is provided on the main surface portion of the n-type well region 22 </ b> A in a region surrounded by the field insulating film 36. The IGFET 14 includes a channel formation region, a pair of p-type semiconductor regions 30A as a first main electrode region used as a source region and a drain region, a gate insulating film 40, and a gate electrode 42. . The channel formation region is formed using the n-type well region 22A. The p-type semiconductor region 30A has, for example, a junction depth shallower than the n-type well region 22A and 1 μm or less, and is higher than the n-type well region 22A, for example, by 10 ¹⁹ atoms / cm ³ to 10 ²⁰ atoms / cm ³ . The impurity density is set, for example, a specific resistance value of 7.0 × 10 ⁻³ Ω · cm to 5.0 × 10 ⁻² Ω · cm. The gate insulating film 40 is provided on the main surface of the n-type well region 22A (on the main surface 12A of the semiconductor substrate 12), and is formed of, for example, a silicon oxide film. The gate insulating film 40 may be an oxynitride film or a composite film in which a silicon oxide film and a silicon nitride film are stacked. The gate electrode 42 is provided on the gate insulating film 40 and is formed of, for example, a silicon polycrystalline film. The gate electrode 42 may be a composite film in which a refractory metal film or a refractory silicide film is stacked on a silicon polycrystalline film. The gate electrode 42 is connected to the input terminal IN via a wiring (not shown), and a signal for controlling the ON / OFF operation of the IGFET 14 is input from the input terminal IN to the gate electrode 42.

  Here, the pair of p-type semiconductor regions 30 </ b> A is formed by self-alignment with respect to the side wall in the gate length direction of the gate electrode 42. The pair of p-type semiconductor regions 30A may have an LDD (lightly doped drain) structure in which the impurity density on the channel formation region side is set low.

  One p-type semiconductor region 30A used as the source region of the IGFET 14 is connected to a power supply terminal Vcc to which a fixed potential necessary for circuit operation is supplied via a wiring (not shown). The wiring is made of, for example, an aluminum alloy film or a composite film mainly composed of the aluminum alloy film. The semiconductor integrated circuit 10 according to the present embodiment is incorporated as an electronic component in a vehicle such as an automobile, and power is supplied from a battery (for example, DC 12V or DC 24V) to the power supply terminal Vcc. The other p-type semiconductor region 30A used as the drain region of the IGFET 14 is connected to the output terminal OUT via a wiring (not shown), and a signal from the IGFET 14 is output from the p-type semiconductor region 30A to the output terminal OUT.

  Further, at a position different from the IGFET 14, an n-type semiconductor region 32B used as a contact region is provided in the main surface portion of the n-type well region 22A. The n-type semiconductor region 32B is connected to the power supply terminal Vcc via a wiring (not shown), and is configured to supply a fixed potential to the n-type well region 22A. Although the n-type semiconductor region 32B has a different conductivity type, the n-type semiconductor region 32B has substantially the same depth as the junction depth of the p-type semiconductor region 30A and is set to an impurity density substantially the same as that of the p-type semiconductor region 30A.

  In the second region A2, the main surface portion of the semiconductor substrate 12 is provided with a p-type well region 24A as a second well region. In the present embodiment, the p-type well region 24A has substantially the same depth as the n-type well region 22A, is set to have substantially the same impurity density, and is set to have substantially the same specific resistance value. Yes.

  The IGFET 16 is provided in the main surface portion of the p-type well region 24A in a region surrounded by the field insulating film 36. The IGFET 16 includes a channel formation region, a pair of n-type semiconductor regions 32A as a second main electrode region used as a source region and a drain region, a gate insulating film 40, and a gate electrode 44. . The channel formation region is formed using the p-type well region 24A. In this embodiment, n-type semiconductor region 32A has substantially the same junction depth as p-type semiconductor region 30A, is set to substantially the same impurity density, and is set to substantially the same specific resistance value. ing. The gate insulating film 40 and the gate electrode 44 are formed of the same material and the same structure as the gate insulating film 40 and the gate electrode 42 of the IGFET 14. The gate electrode 44 is connected to the input terminal IN via a wiring (not shown).

  One n-type semiconductor region 32A used as the source region of the IGFET 16 is connected to a ground terminal GND to which a fixed potential serving as a reference for circuit operation is supplied via a wiring (not shown). In the present embodiment, the ground terminal GND is connected to the ground terminal (for example, 0 V) of the battery or the vehicle body ground. The other n-type semiconductor region 32A used as the drain region of the IGFET 16 is connected to the output terminal OUT via a wiring (not shown).

  Further, at a position different from the IGFET 16, a p-type semiconductor region 30B used as a contact region is provided in the main surface portion of the p-type well region 24A. The p-type semiconductor region 30B is connected to the ground terminal GND via a wiring (not shown), and is configured to supply a fixed potential to the p-type well region 24A. The p-type semiconductor region 30B has the same depth as the junction depth of the p-type semiconductor region 30A of the IGFET 14, and is set to the same impurity density as the p-type semiconductor region 30A.

  On the other hand, the bipolar transistor 20 is provided in the main surface portion of the semiconductor substrate 12 in the fourth region A4. The bipolar transistor 20 includes an n-type collector region 22C as a fifth main electrode region, a p-type base region 26B as a second control electrode region, and an n-type emitter region 32E as a sixth main electrode region. Has been.

The n-type collector region 22C is provided in the main surface portion of the semiconductor substrate 12, and has the same junction depth, the same impurity density, and the same specific resistance value as the n-type well region 22A. Has been. The p-type base region 26B is provided on the main surface portion of the n-type collector region 22C. The p-type base region 26B is set to a junction depth shallower than the n-type collector region 22C and deeper than the n-type emitter region 32E, for example, about 3 μm. The p-type base region 26B has an impurity density of, for example, 10 ¹⁷ atoms / cm ³ to 10 ¹⁸ atoms / cm ³ , which is higher than the p-type well region 24A provided with the IGFET 16 and lower than the p-type semiconductor region 30A of the IGFET 14. Is set to The specific resistance value of the p-type base region 26B is set to 0.02 Ω · cm to 0.1 Ω · cm, for example. The n-type emitter region 32E is provided on the main surface portion of the p-type base region 26B in the region surrounded by the field insulating film 36. The n-type emitter region 32E has the same junction depth with respect to the n-type semiconductor region 32A of the IGFET 16, is set to the same impurity density, and is set to the same specific resistance value.

At a position different from the p-type base region 26B, an n-type semiconductor region 32D used as a contact region is provided in the main surface portion of the n-type collector region 22C. The n-type semiconductor region 32D is connected to the collector signal terminal V _C via a wiring (not shown). The collector signal terminal V _C is configured to supply a collector signal to the n-type collector region 22C. The n-type semiconductor region 32D has the same depth as the n-type semiconductor region 32B and is set to the same impurity density as the n-type semiconductor region 32B. At a position different from the n-type emitter region 32E, a p-type semiconductor region 30D used as a contact region is provided on the main surface portion of the p-type base region 26B. The p-type semiconductor region 30D is connected to the base signal terminal V _B via a wiring (not shown). The base signal terminal V _B is configured to supply a base signal to the p-type base region 26B. The n-type emitter region 32E is connected to the emitter signal terminal V _E via a wiring (not shown). The emitter signal terminal V _E is configured to supply an emitter signal to the n-type emitter region 32E.

(Vertical cross-sectional structure of element isolation region)
The third region A3 is located between the n-type well region 22A and the p-well region 24A, and the element isolation region 18 is provided in the main surface portion of the semiconductor substrate 12 in the third region A3. The element isolation region 18 includes a field insulating film 36, a pnp bipolar transistor 54 as a first bipolar transistor, and a contact region 56. The bipolar transistor 54 includes a p-type emitter region as a third main electrode region, an n-type base region as a first control electrode region, and a p-type collector region as a fourth main electrode region. .

  The p-type emitter region is formed by the semiconductor substrate 12. The n-type base region is formed by the n-type well region 22B. The n-type well region 22B has the same junction depth, the same impurity density, and the same specific resistance as the n-type well region 22A or the n-type collector region 22C. An n-type semiconductor region 32C as a contact region is provided on the main surface portion of the n-type well region 22B, and the n-type semiconductor region 32C is connected to the ground terminal GND through a wiring (not shown). The n-type semiconductor region 32C has the same depth as the n-type semiconductor region 32D of the bipolar transistor 20, is set to the same impurity density, and is set to the same specific resistance value. The p-type collector region is formed by the p-type well region 26A. The p-type well region 26A has the same junction depth as the p-type base region 26B of the bipolar transistor 20, is set to the same impurity density, and is set to the same specific resistance value. A p-type semiconductor region 30C as a contact region is provided on the main surface portion of the p-type well region 26A, and the p-type semiconductor region 30C is connected to the ground terminal GND via a wiring (not shown). The p-type semiconductor region 30C has the same depth as the p-type semiconductor region 30D of the bipolar transistor 20, is set to the same impurity density, and is set to the same specific resistance value.

  The bipolar transistor 54 is disposed in the whole area along the periphery of the n-type well region 22A and the p-type well region 24A in plan view. In addition, the bipolar transistors 54 may be disposed at a plurality of locations along the periphery of the n-type well region 22A and the p-type well region 24A, for example, at regular intervals.

  In the present embodiment, a pair of contact regions 56 are disposed between bipolar transistor 54 and n-type well region 22A and between bipolar transistor 54 and p-type well region 24A. The contact region 56 includes a p-type well region 24B as a third well region, a p-type well region 26A as a fourth well region, and a p-type semiconductor region 30C as a second semiconductor region. Yes. The p-type well region 24B is provided in the main surface portion of the semiconductor substrate 12, has the same depth as the p-type well region 24A, is set to the same impurity density, and is set to the same specific resistance value. The p-type well region 26A and the p-type semiconductor region 30C are formed using the p-type well region 26A as a p-type collector region of the bipolar transistor 54 and the p-type semiconductor region 30C as a contact region. A parasitic resistance R is added to the contact region 56 over the p-type well region 24B, the p-type well region 26A, and the p-type semiconductor region 30C.

(Method for manufacturing semiconductor integrated circuit)
A method for manufacturing the semiconductor integrated circuit 10 according to the present embodiment is as follows. First, a p-type semiconductor substrate 12 is prepared (see FIG. 2). In the main surface portion of the semiconductor substrate 12, an n-type well region 22A is formed in the first region A1 (see FIG. 2). By the same manufacturing process as this n-type well region 22A, an n-type well region 22B is formed in the third region A3, and an n-type collector region 22C is formed in the fourth region A4. The n-type well region 22A, n-type well region 22B, and n-type collector region 22C are formed by implanting n-type impurities into the semiconductor substrate 12 by ion implantation using a mask formed by photolithography. . In general, the impurities implanted by the ion implantation method are activated by the drive-in diffusion process of the final stage of the pretreatment process. Therefore, the same manufacturing process means that the impurity implantation process is the same process. means.

  As shown in FIG. 2, a p-type well region 24 </ b> A is formed in the second region A <b> 2 of the main surface portion of the semiconductor substrate 12. A p-type well region 24B is formed in the third region A3 by the same manufacturing process as the p-type well region 24A. The p-type well region 24A and the p-type well region 24B are formed by implanting p-type impurities into the semiconductor substrate 12 by ion implantation using a mask formed by photolithography.

  As shown in FIG. 3, a p-type base region 26B is formed in the main surface portion of the n-type collector region 22C in the fourth region A4. By the same manufacturing process as this p-type base region 26B, the p-type well region 26A is formed across the main surface portion of the n-type well region 22B and the main surface portion of the p-type well region 24B in the third region A3. The p-type base region 26B and the p-type well region 26A are similarly formed using an ion implantation method.

  As shown in FIG. 4, a field insulating film 36 is formed on a part of the main surface 12 </ b> A of the semiconductor substrate 12 in each of the first region A <b> 1 to the fourth region A <b> 4. The field insulating film 36 is formed in the inactive region and electrically isolates the active regions. In the present embodiment, the field insulating film 36 is formed using a selective thermal oxidation method for the main surface 12A of the semiconductor substrate 12. A gate insulating film 40 is formed on the main surface of the n-type well region 22A in the first region A1 and on the main surface of the p-type well region 24A in the second region A2. Here, the gate insulating film 40 is formed using a thermal oxidation method.

  As shown in FIG. 5, the gate electrode 42 is formed on the gate insulating film 40 in the first region A1, and the gate electrode 44 is formed on the gate insulating film 40 in the second region A2 by the same manufacturing process as the gate electrode 42. Is formed. The gate electrode 42 and the gate electrode 44 are formed, for example, by forming a silicon polycrystalline film by chemical vapor deposition (CVD) and patterning the silicon polycrystalline film using a photolithography technique. An n-type impurity is added to the silicon polycrystalline film during or after the film formation to reduce the resistance value.

  Next, a pair of p-type semiconductor regions 30A are formed in the main surface portion of the n-type well region 22A in the first region A1 (see FIG. 6). Thereby, the p-channel IGFET 14 is substantially formed. By the same manufacturing process as p-type semiconductor region 30A, p-type semiconductor region 30B is formed in the main surface portion of p-type well region 24A in second region A2, and p-type is formed in the main surface portion of p-type well region 26A in third region A3. A semiconductor region 30C is formed. In the third region A3, the contact region 56 of the element isolation region 18 is substantially completed. Also in the fourth region A4, the p-type semiconductor region 30D is formed in the main surface portion of the p-type base region 26B by the same manufacturing process.

  As shown in FIG. 6, in the second region A2, a pair of n-type semiconductor regions 32A are formed in the main surface portion of the p-type well region 24A. Thereby, the n-channel IGFET 16 is substantially completed. By the same manufacturing process as the n-type semiconductor region 32A, an n-type semiconductor region 32B is formed in the main surface portion of the n-type well region 22A in the first region A1, and an n-type semiconductor region is formed in the main surface portion of the n-type well region 22B in the third region A3. A semiconductor region 32C is formed. In the third region A3, the bipolar transistor 54 in the element isolation region 18 is substantially completed. Also in the fourth region A4, the n-type semiconductor region 32D is formed in the main surface portion of the n-type collector region 22C, and the n-type emitter region 30E is formed in the main surface portion of the p-type base region 26B by the same manufacturing process. Thereby, the bipolar transistor 20 is substantially completed in the fourth region A4.

  Next, although not shown, an interlayer insulating film is formed on the main surface of the semiconductor substrate 12, and a connection hole is formed in the interlayer insulating film. A wiring electrically connected to each region through the connection hole is formed on the interlayer insulating film. When these series of manufacturing steps are completed, the semiconductor integrated circuit 10 according to the present embodiment is completed.

(Operation and effect of the present embodiment)
In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 1, the n-type well region 22A is provided in the first region A1 of the main surface portion of the p-type semiconductor substrate 12 connected to the ground terminal GND. A p-type well region 24 </ b> A is provided in the second region A <b> 2 of the main surface portion of the semiconductor substrate 12. A p-channel IGFET 14 having a pair of p-type semiconductor regions 30A is provided on the main surface portion of the n-type well region 22A. An n-channel IGFET 16 having a pair of n-type semiconductor regions 32A is provided on the main surface portion of the p-type well region 24A. An element isolation region 18 is provided in the third region A3 between the first region A1 and the second region A2 on the main surface portion of the semiconductor substrate 12.

  Here, the element isolation region 18 includes a pnp bipolar transistor 54. The bipolar transistor 54 includes a p-type emitter region, an n-type base region, and a p-type collector region. The p-type emitter region is formed by the semiconductor substrate 12. The n-type base region is formed by an n-type well region 22B provided in the main surface portion of the p-type emitter region, and is connected to the ground terminal GND. The p-type collector region is formed by a p-type well region 26A provided in the main surface portion of the n-type base region, and is connected to the ground terminal GND. The ON resistance of the bipolar transistor 54 is configured to be smaller than the resistance R of the base region of the parasitic bipolar transistor 52. In the parasitic bipolar transistor 52, the n-type well region 22A is an n-type collector region, the n-type semiconductor region 32A of the n-channel IGFET 16 is an n-type emitter region, and the p-type well region 24B of the contact region 56 of the element isolation region 18 is a p-type. It is an npn type used as a base region.

  For example, assume that a surge is input to the p-type semiconductor region 30 </ b> A as the source region of the p-channel IGFET 14. When a surge is input, breakdown occurs at the pn junction between the p-type semiconductor region 30A and the n-type well region 22A, and surge carriers flow into the n-type well region 22A. As a result, in the pnp parasitic bipolar transistor 50 in which the p-type semiconductor region 30A is used as the collector region, the n-type well region 22A is used as the base region, and the semiconductor substrate 12 is used as the emitter region, the base potential rises. A forward current flows through. Then, the parasitic bipolar transistor 50 operates and a surge flows to the semiconductor substrate 12. In the present embodiment, since the bipolar transistor 54 is provided, when a surge flows through the semiconductor substrate 12 in the element isolation region 18, the surge is grounded by the operation of the bipolar transistor 54 before the operation of the parasitic bipolar transistor 52. Absorbed by GND. Therefore, in the element isolation region 18 of the semiconductor integrated circuit 10 according to the present embodiment, it is possible to improve the insulation isolation performance against the surge between the complementary IGFETs.

  In the semiconductor integrated circuit 10 according to the present embodiment, a contact region 56 is provided in the element isolation region 18. The contact region 56 is formed in the depth direction of the semiconductor substrate 12 along the p-type well region 26A as the p-type collector region of the bipolar transistor 54 and the n-type well region 22B as the n-type base region. A contact region 56 is electrically connected to the terminal GND. Therefore, the potential of the semiconductor substrate 12 can be stabilized in the element isolation region 18.

  Furthermore, in the semiconductor integrated circuit 10 according to the present embodiment, the n-type well region 22B as the n-type base region of the bipolar transistor 54 in the element isolation region 18 has the same junction depth as the n-type well region 22A of the IGFET 14 and , With the same impurity density. Therefore, the n-type well region 22B is easily formed using the n-type well region 22A. In the method of manufacturing the semiconductor integrated circuit 10, since the n-type well region 22B is formed by the same manufacturing process as the n-type well region 22A, the n-type well region 22B is formed by a separate process from the n-type well region 22A. In comparison, the number of manufacturing steps can be reduced.

  In the semiconductor integrated circuit 10 according to the present embodiment, the bipolar transistor 20 is provided in the fourth region A4 different from the first region A1, the second region A2, and the third region A3 of the main surface portion of the semiconductor substrate 12. . The bipolar transistor 20 includes an n-type collector region 22C, a p-type base region 26B, and an n-type emitter region 32E. The n-type collector region 22C is formed with the same junction depth and the same impurity density as the n-type well region 22A of the IGFET 14. The p-type base region 26B is provided on the main surface portion of the n-type collector region 22C. The n-type emitter region 32E is provided on the main surface portion of the p-type base region 26B.

  Here, the p-type well region 26A as the p-type collector region of the bipolar transistor 54 in the element isolation region 18 is formed with the same junction depth and the same impurity density as the p-type base region 26B of the bipolar transistor 20. Therefore, the p-type well region 26A is easily formed using the p-type base region 26B. In the method of manufacturing the semiconductor integrated circuit 10, the p-type well region 26A is formed by the same manufacturing process as the p-type base region 26B. Therefore, when the p-type well region 26A is formed by a separate process from the p-type base region 26B. In comparison, the number of manufacturing steps can be reduced.

  Further, in the semiconductor integrated circuit 10 according to the present embodiment, the contact region 56 of the element isolation region 18 includes the p-type well region 24B, the p-type well region 26A, and the p-type semiconductor region 30C. . The p-type well region 24B is formed with the same depth and the same impurity density as the p-type well region 24A of the IGFET 16. The p-type well region 26A is formed with the same junction depth and the same impurity density as the p-type base region 26B of the bipolar transistor 20. The p-type semiconductor region 30C is formed with the same depth as the junction depth of the p-type semiconductor region 30A of the IGFET 14 and the same impurity density as the p-type semiconductor region 30A. Therefore, the contact region 56 is easily formed using the p-type well region 24A, the p-type base region 26B, and the p-type semiconductor region 30A. In the method of manufacturing the semiconductor integrated circuit 10, the contact region 56 is formed by the same manufacturing process as each of the p-type well region 24A, the p-type base region 26B, and the p-type semiconductor region 30A. it can.

[Supplementary explanation of the above embodiment]
The present invention is not limited to the above-described embodiment, and can be modified as follows, for example, without departing from the gist thereof. For example, the present invention may be applied to an element isolation region between an IGFET and a bipolar transistor. In the present invention, the conductivity type of the semiconductor substrate may be n-type, and the bipolar transistor in the element isolation region may be npn-type. According to the present invention, a well region (first semiconductor region) of the same conductivity type or opposite conductivity type as that of the semiconductor substrate is provided in the entire region or a partial region of the main surface portion of the semiconductor substrate, and complementary to the main surface portion of the well region. An n-type well region and a p-type well region constituting each of the type IGFET and the element isolation region may be provided.

  Furthermore, the present invention is not limited to a silicon substrate as a semiconductor substrate, and a compound semiconductor substrate other than a silicon substrate may be used. The present invention is not limited to a semiconductor integrated circuit mounted on a vehicle, but may be applied to a semiconductor integrated circuit incorporated in a general personal computer, portable terminal, cellular phone, or the like.

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 12 Semiconductor substrate 14, 16 IGFET
18 Element isolation region 20, 54 Bipolar transistor 22A, 22B, 24A, 24B, 26A Well region 22C Collector region 26B Base region 30A, 30B, 30C, 32A, 32B, 32C, 32D Semiconductor region 32E Emitter region 50, 52 Parasitic bipolar transistor 56 Contact area

Claims (5)

A first semiconductor region of a first conductivity type connected to a fixed potential;
A first well region of a second conductivity type provided in a first region of the main surface portion of the first semiconductor region and opposite to the first conductivity type;
A first insulated gate field effect transistor provided on a main surface portion of the first well region and having a pair of first main electrode regions of a first conductivity type;
A second well region of a first conductivity type provided in a second region different from the first region of the main surface portion of the first semiconductor region;
A second insulated gate field effect transistor provided on a main surface of the second well region and having a pair of second main electrode regions of the second conductivity type;
The first semiconductor region of the third region between the first region and the second region of the main surface portion of the first semiconductor region is defined as a third main electrode region, and is provided on the main surface portion of the third main electrode region. A first control electrode region of the second conductivity type connected to the fixed potential, and a first conductivity type of the first conductivity type provided on the main surface of the first control electrode region and connected to the fixed potential. An element isolation region having a first bipolar transistor configured to include a fourth main electrode region;
A semiconductor integrated circuit.   The element isolation region is formed in the depth direction of the first semiconductor region along the fourth main electrode region and the first control electrode region of the first bipolar transistor, and the first semiconductor region and the fixed region are formed. The semiconductor integrated circuit according to claim 1, wherein a contact region for electrically connecting the potential is provided.   The semiconductor integrated circuit according to claim 1, wherein the first control electrode region is formed with the same junction depth and the same impurity density as the first well region. The first semiconductor region is provided in a fourth region different from the first region, the second region, and the third region, and has the same junction depth and the same impurity density as the first well region. A second conductive type fifth main electrode region, a first conductive type second control electrode region provided on a main surface portion of the fifth main electrode region, and a main surface portion of the second control electrode region And a second bipolar transistor configured to include a sixth main electrode region of the second conductivity type provided in
4. The semiconductor integrated circuit according to claim 1, wherein the fourth main electrode region is formed with the same junction depth and the same impurity density as the second control electrode region. 5. The first semiconductor region is provided in the element isolation region and formed in the depth direction of the first semiconductor region along the fourth main electrode region and the first control electrode region of the first bipolar transistor. A contact region electrically connecting between the first well type and the fixed potential is a third well region of the first conductivity type formed with the same depth and the same impurity density as the second well region, and the second well region. The first well type fourth well region formed with the same junction depth and the same impurity density as the control electrode region, and the same depth as the junction depth of the first main electrode region, and the first main electrode 5. The semiconductor integrated circuit according to claim 4, comprising a second semiconductor region of the first conductivity type formed with the same impurity density as that of the region.

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