JP6467539B2 - Comparison circuit, power supply control IC, switching power supply - Google Patents

Description

  The present invention relates to a comparison circuit having an automatic offset correction technique between a plurality of comparators, and a power supply control IC and a switching power supply device using the comparison circuit.

  Conventionally, a comparison circuit is known in which a plurality of comparators having different characteristics can be used properly according to the situation.

JP 2010-35140 A

  However, in the conventional comparison circuit, when the input offset for each comparator is deviated, even if the same input signal is compared with the same reference voltage, the logic switching timing of the comparison signal differs. There was a problem that the output accuracy as a whole deteriorated.

  In order to solve the above problem, a calibration process that eliminates the deviation of the input offset for each comparator is effective. However, if the configuration is such that only the calibration process is performed when the comparison circuit is activated, the input offset for each comparator may deviate due to a change in the external environment (for example, power supply voltage, temperature, etc.) after the calibration process. The problem arises. In addition, when the configuration is such that only the calibration process is performed at the time of starting the comparison circuit, there is a problem that the input offset for each comparator remains deviated if an incorrect calibration is performed in the calibration process at the time of startup. Arise.

  The offset adjustment method disclosed in Patent Document 1 compares the output of the first comparator and the output of the second comparator, and sets an offset amount of reverse polarity in each comparator according to the comparison result. The essential structure of the present invention is different.

  In view of the above-described problems and problems found by the inventors of the present application, the present invention returns to a setting in which the output accuracy does not decrease even if the output accuracy is not reduced and uses a plurality of comparators having different characteristics. It is an object of the present invention to provide a comparison circuit that can be used, and a power supply control IC and a switching power supply device using the same.

  The comparison circuit disclosed in the present specification is provided in a non-linear control switching power supply device that generates a desired output voltage from an input voltage, and receives the output voltage or a feedback voltage corresponding to the output voltage as an input signal. A first comparator that compares the input signal with a reference voltage to generate a first comparison signal; a second comparator that compares the input signal with a variable reference voltage to generate a second comparison signal; A variable reference voltage generation unit that generates a variable reference voltage; and a logic unit that outputs one of the first comparison signal and the second comparison signal as a comparison signal. The logic unit includes the first comparison signal. Is output as the comparison signal, and the coil provided in the switching power supply device is turned on while the first comparator and the second comparator are in operation. A period from when the backflow of the detected current is detected to when the first predetermined time elapses in a state where the switching operation of the switching power supply is stopped (however, shorter than the first predetermined time from the time when the backflow is detected) The variable reference voltage is adjusted so as to approach the reference voltage (a first configuration) except for a period until the second predetermined time elapses).

  In the comparison circuit having the first configuration, the logic unit outputs the first comparison signal as the comparison signal while operating the first comparator and the second comparator. A configuration in which the magnitude relationship between the reference voltage and the variable reference voltage is confirmed based on the level of the second comparison signal at the time when the level of the comparison signal is switched, and the variable reference voltage is adjusted according to the magnitude relationship ( The second configuration may be adopted.

  Another comparison circuit disclosed in this specification is provided in a nonlinear control switching power supply device that generates a desired output voltage from an input voltage, and receives the output voltage or a feedback voltage corresponding to the output voltage as an input signal. A first comparator for comparing the input signal and a reference voltage to generate a first comparison signal; and a second comparator for comparing the input signal and a variable reference voltage to generate a second comparison signal; A variable reference voltage generation unit that generates the variable reference voltage; and a logic unit that outputs one of the first comparison signal and the second comparison signal as a comparison signal. From the state where the first comparator is stopped and the second comparator is operated while outputting the comparison signal as the comparison signal, the first comparison signal is used as the comparison signal. While output and shifts to a state in which by operating the first comparator and the second comparator, and is configured to adjust said variable reference voltage closer to the reference voltage (third configuration).

  In the comparison circuit having the third configuration, the logic unit outputs the second comparison signal as the comparison signal, stops the first comparator, and operates the second comparator. The magnitude relationship between the reference voltage and the variable reference voltage is confirmed based on the level of the first comparison signal when a predetermined delay time has elapsed from the time when the level of the second comparison signal is switched. Accordingly, the variable reference voltage may be adjusted (fourth configuration).

  The comparison circuit having the fourth configuration may have a configuration (fifth configuration) in which the switching operation of the switching power supply device is resumed after the adjustment of the variable reference voltage is completed.

  In the comparison circuit having any one of the first to fifth configurations, the response speed of the first comparator is faster than the response speed of the second comparator, and the power consumption of the second comparator is the same as that of the first comparator. It is good also as a structure (6th structure) smaller than power consumption.

  In the comparison circuit having any one of the first to sixth configurations, the variable reference voltage generation unit includes an up / down counter, and a DAC (digital to analog converter) that converts the counter value of the up / down counter into an analog voltage. The analog voltage or a voltage corresponding to the analog voltage may be output as the variable reference voltage (seventh configuration).

  In the comparison circuit having the seventh configuration, the variable reference voltage generation unit further includes an addition unit that generates the variable reference voltage by adding the analog voltage to the reference voltage (eighth). Configuration).

  The power supply control IC disclosed in this specification includes a ripple injection circuit that generates a feedback voltage by superimposing a ripple voltage simulating a coil current on an output voltage or a divided voltage thereof, and a predetermined reference voltage. A reference voltage generation circuit for generating, a main comparator for generating a comparison signal by comparing the feedback voltage and the reference voltage, and a one-shot pulse generation circuit for generating a one-shot pulse for a set signal in accordance with the comparison signal; An RS flip-flop that sets the output signal to a first logic level in response to the set signal and resets the output signal to a second logic level in response to a reset signal; and the output signal is set to the first logic level. ON time setting circuit for generating a one-shot pulse for the reset signal when a predetermined ON time has elapsed since A gate driver circuit that generates a drive signal for the output transistor and the synchronous rectification transistor according to the output signal, and a reverse current detection circuit that detects the reverse current of the coil current and forcibly turns off the synchronous rectification transistor. The main comparator is configured to include a comparison circuit having any one of the first to eighth configurations (the ninth configuration).

  The switching power supply disclosed in this specification generates a power supply control IC having the ninth configuration and an output voltage from an input voltage by attaching a part or all of the power supply control IC to the power supply control IC. And a switch output stage (tenth configuration).

  According to the invention disclosed in the present specification, a comparison circuit capable of properly using a plurality of comparators having different characteristics without causing a decrease in output accuracy, and a power supply control IC and a switching power supply device using the same are provided. It becomes possible to provide.

Block diagram showing the overall configuration of the switching power supply Timing chart showing switching operation under heavy load Timing chart showing reverse flow cut-off operation at light load Block diagram showing a configuration example of the main comparator 13 Timing chart showing relationship between feedback voltage, reference voltage and variable reference voltage, and output of first and second comparators Timing chart showing relationship between feedback voltage, reference voltage and variable reference voltage, and output of first and second comparators Timing chart during count-up operation Timing chart during countdown operation Timing chart showing relationship between feedback voltage, reference voltage and variable reference voltage, and output of first and second comparators Timing chart showing relationship between feedback voltage, reference voltage and variable reference voltage, and output of first and second comparators Block diagram showing another configuration example of the main comparator 13 Block diagram showing a configuration example of a television equipped with a switching power supply device Front view of a TV equipped with a switching power supply Side view of a TV equipped with a switching power supply Rear view of a TV with a switching power supply

<Switching power supply>
FIG. 1 is a block diagram showing the overall configuration of the switching power supply apparatus. The switching power supply device 1 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). The switching power supply device 1 includes a semiconductor device 10 and various discrete components externally attached to the semiconductor device 10 (N-channel MOS [metal oxide semiconductor] field effect transistors N1 and N2, a coil L1, a capacitor C1, and a resistor R1. And a switch output stage 20 formed by R2).

  The semiconductor device 10 is a main body (so-called power supply control IC) that comprehensively controls the entire operation of the switching power supply device 1. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5 as means for establishing electrical connection with the outside of the device. , Output voltage terminal T6 and ground terminal T7).

  The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to the application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application end (a connection node between the resistor R1 and the resistor R2) of the divided voltage Vdiv. The external terminal T5 is connected to the application terminal for the input voltage Vin. The external terminal T6 is connected to the application terminal for the output voltage Vout. The external terminal T7 is connected to the ground terminal.

  Next, the connection relationship of discrete components attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal for the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application terminal for the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to the gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled in accordance with the gate signal G2 input from the external terminal T2. As the rectifying element, a diode may be used instead of the transistor N2. The transistors N1 and N2 can also be built in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying / smoothing unit that rectifies and smoothes the rectangular-wave switch voltage Vsw appearing at the external terminal T3 to generate the output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv. However, when the output voltage Vout is within the input dynamic range of the ripple injection circuit 11 (or the main comparator 13), the divided voltage generation unit may be omitted.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip-flop 15, an on time setting circuit 16, and a gate driver circuit 17. The backflow detection circuit 18 is integrated.

  The ripple injection circuit 11 adds a ripple voltage Vrpl (a pseudo ripple component simulating a coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and thus the divided voltage Vdiv) is not so large. A ceramic capacitor or the like can be used. However, when the ripple component of the output voltage Vout is sufficiently large, the ripple injection circuit 11 can be omitted.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the non-inverting input terminal (+) with the reference voltage Vref input to the inverting input terminal (−) to generate a comparison signal S1. The comparison signal S1 is at a high level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a low level when the feedback voltage Vfb is lower than the reference voltage Vref.

  The one-shot pulse generation circuit 14 generates a one-shot pulse (eg, a falling pulse) in the set signal S2 using the falling edge of the comparison signal S1 as a trigger.

  The RS flip-flop 15 sets the output signal S4 to a high level at the pulse edge (eg, falling edge) of the set signal S2 input to the set end (S), and the reset signal input to the reset end (R). The output signal S4 is reset to a low level at the pulse edge (eg, falling edge) of S3.

  The on-time setting circuit 16 outputs a reset signal S3 after a predetermined on-time Ton has elapsed after the inverted output signal S4B of the RS flip-flop 15 (= the logic inverted signal of the output signal S4) has fallen to a low level. A one-shot pulse (eg, falling pulse) is generated.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4 of the RS flip-flop 15, and switches the transistors N1 and N2 in a complementary manner. Note that the term “complementary” used in this specification includes the case where the transistors N1 and N2 are turned on / off completely, as well as the transistors N1 and N2 from the viewpoint of preventing through current. This includes a case where a delay is given to the on / off transition timing (a case where a so-called simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors the backflow of the coil current IL (coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) and generates a backflow detection signal S5. The backflow detection signal S5 is latched at a high level (a logic level when a backflow is detected) when a backflow of the coil current IL is detected, and a low level (a logic when no backflow is detected) at the rising edge of the gate signal G1 in the next cycle. Level). As a method for monitoring the backflow of the coil current IL, for example, a zero cross point at which the switch voltage Vsw switches from negative to positive during the ON period of the transistor N2 may be detected. When the backflow detection signal S5 is at a high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The ripple injection circuit 11, the reference voltage generation circuit 12, the main comparator 13, the one-shot pulse generation circuit 14, the RS flip-flop 15, the on-time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 described above are: A non-linear control method for generating the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result of the feedback voltage Vfb and the reference voltage Vref (in this configuration example, bottom detection on-time) Functions as a switching control circuit.

<Switching operation>
FIG. 2 is a timing chart showing the switching operation at the time of heavy load (current continuous mode), in which the feedback voltage Vfb, the set signal S2, the reset signal S3, and the output signal S4 are depicted in order from the top.

  When the feedback voltage Vfb decreases to the reference voltage Vref at time t11, the set signal S2 falls to the low level, and the output signal S4 changes to the high level. Accordingly, the transistor N1 is turned on, and the feedback voltage Vfb starts to rise.

  Thereafter, when the reset signal S3 falls to the low level at the time t12 due to the elapse of the on time Ton, the output signal S4 transitions to the low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb starts to fall again.

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4, and performs on / off control of the transistors N1 and N2 using this. Specifically, when the output signal S4 is at a high level, basically, the gate signal G1 is set to a high level to turn on the transistor N1, and the gate signal G2 is set to a low level to turn off the transistor N2. Is done. Conversely, when the output signal S4 is at a low level, basically, the gate signal G1 is set to a low level to turn off the transistor N1, and the gate signal G2 is set to a high level to turn on the transistor N2.

  Due to the on / off control of the transistors N1 and N2, the switch voltage Vsw having a rectangular waveform appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1, and the output voltage Vout is generated. The output voltage Vout is divided by the resistors R1 and R2, and the divided voltage Vdiv (and thus the feedback voltage Vfb) is generated. With such output feedback control, the switching power supply device 1 generates the desired output voltage Vout from the input voltage Vin with a very simple configuration.

<Backflow blocking operation>
FIG. 3 is a timing chart showing the reverse current cut-off operation at the time of light load (in the current discontinuous mode). It is depicted.

  At times t21 to t22, since the gate signal G1 is at a high level and the gate signal G2 is at a low level, the transistor N1 is turned on and the transistor N2 is turned off. Accordingly, at times t21 to t22, the switch voltage Vsw rises to substantially the input voltage Vin, and the coil current IL increases.

  At time t22, when the gate signal G1 falls to the low level and the gate signal G2 rises to the high level, the transistor N1 is turned off and the transistor N2 is turned on. Therefore, the switch voltage Vsw decreases to a negative voltage (= GND−IL × RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing through the load is sufficiently heavy, the energy stored in the coil L1 is large, so that the coil current IL has a zero value until time t24 when the gate signal G1 is raised to the high level again. The switch voltage Vsw is maintained at a negative voltage while continuing to flow toward the load without falling below. On the other hand, at the time of light load when the output current Iout flowing through the load is small, the energy stored in the coil L1 is small. Therefore, at time t23, the coil current IL falls below the zero value, and a reverse flow of the coil current IL occurs. The polarity of the voltage Vsw switches from negative to positive. In such a state, since the electric charge stored in the capacitor C1 is returned to the input side via the coil L1, the efficiency at a light load is lowered.

  Therefore, the switching power supply device 1 uses the backflow detection circuit 18 to detect backflow of the coil current IL (polarity inversion of the switch voltage Vsw), and during the high level period (time t23 to t24) of the backflow detection signal S5, the transistor N2 Is forcibly turned off. By adopting such a configuration, the reverse flow of the coil current IL can be promptly interrupted, so that it is possible to eliminate a decrease in efficiency at a light load.

<Main comparator>
FIG. 4 is a block diagram illustrating a configuration example of the main comparator 13. The main comparator 13 of this configuration example is a comparison circuit that compares the feedback voltage Vfb (corresponding to an input signal) and the reference voltage Vref to generate a comparison signal S1, and includes a first comparator 131, a second comparator 132, A variable reference voltage generation unit 133 and a logic unit 134 are included.

  The first comparator 131 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the reference voltage Vref input to the inverting input terminal (−) to generate the first comparison signal S131. The first comparison signal S131 is at a high level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a low level when the feedback voltage Vfb is lower than the reference voltage Vref.

  Further, whether or not the first comparator 131 operates is controlled according to an enable signal EN131 input from the logic unit 134. More specifically, the first comparator 131 is activated when the enable signal EN131 is at the first logic level (= the logic level when enabled), and the enable signal EN131 is at the second logic level (= when disabled). When it is (logical level), it becomes a stop state. Note that the power consumption can be reduced to almost zero by setting the first comparator 131 to the stop state.

  The second comparator 132 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the variable reference voltage Vref2 input to the inverting input terminal (−) to generate a second comparison signal S132. The second comparison signal S132 is at a high level when the feedback voltage Vfb is higher than the variable reference voltage Vref2, and is at a low level when the feedback voltage Vfb is lower than the variable reference voltage Vref2. Note that, unlike the first comparator 131, the second comparator 132 always continues to operate after the semiconductor device 10 is activated.

  Note that the response speed of the first comparator 131 is faster than the response speed of the second comparator 132. Further, the power consumption of the second comparator 132 is extremely smaller than the power consumption of the first comparator 131. That is, the first comparator 131 is a high-speed response type that prioritizes the improvement of the response speed over the reduction of power consumption, and the second comparator 132 is an ultra-low speed that prioritizes the reduction of the power consumption over improvement of the response speed. It is a power consumption type.

  The variable reference voltage generation unit 133 is a circuit unit that generates the variable reference voltage Vref2, and includes an up / down counter 133a and a DAC 133b.

  The up / down counter 133a is any of a count-up operation for incrementing the counter value Scnt, a count-down operation for decrementing the counter value Scnt, and a count stop operation for holding the counter value Scnt according to the control signal S6 input from the logic unit 134 I do. Then, the up / down counter 133a outputs the counter value Scnt to the DAC 133b.

  The DAC 133b converts the digital counter value Scnt into an analog voltage Vdac and outputs it as a variable reference voltage Vref2. Therefore, the variable reference voltage Vref2 increases stepwise with the increment of the counter value Scnt and decreases stepwise with the decrement of the counter value Scnt.

  The logic unit 134 outputs one of the first comparison signal S131 and the second comparison signal S132 as the comparison signal S1. The logic unit 134 operates the first comparator 131 by setting the enable signal EN131 to the first logic level (= the logic level when enabled) while the first comparison signal S131 is output as the comparison signal S1. Let On the other hand, the logic unit 134 sets the enable signal EN131 to the second logic level (= the logic level when disabled) while the second comparison signal S132 is output as the comparison signal S1, thereby causing the first comparator 131 to change. Stop.

  More specifically, the logic unit 134 operates the first comparator 131 while the backflow detection signal S5 is at a low level, and outputs the first comparison signal S131 as the comparison signal S1. In addition, the logic unit 134 operates the first comparator 131 until the first predetermined time (for example, 8 μs) elapses after the backflow detection signal S5 is switched from the low level to the high level, and the first comparison signal S131. Is output as the comparison signal S1. On the other hand, if the reverse flow detection signal S5 continues from the low level to the high level and the high level of the reverse flow detection signal S5 continues for a first predetermined time (for example, 8 μs) after the reverse flow detection signal S5 switches from the low level to the high level, the reverse flow detection signal S5 The first comparator 131 is stopped and the second comparison signal S132 is output as the comparison signal S1 until is switched from the high level to the low level. That is, if the period during which the output voltage Vout is sufficient and both the transistors N1 and N2 are off exceeds a first predetermined time (for example, 8 μs), the first comparator 131 is stopped only for the period exceeding the first predetermined time. Thus, power saving of the main comparator 13 is achieved. As described above, the logic unit 134 has a function of selectively using the first comparator 131 for high-speed response and the second comparator 132 for ultra-low power consumption according to the situation (load state).

  However, when the input offsets of the first comparator 131 and the second comparator 132 are different, the logic switching timing of the comparison signal S1 differs depending on which of the first comparator 131 and the second comparator 132 is used. As a result, the output accuracy of the main comparator 13 as a whole (and hence the accuracy of the output voltage Vout) decreases.

  Therefore, it is necessary to eliminate the input offset mismatch between the comparators by the calibration process. Therefore, the startup correction process is executed in the following procedure when the switching power supply device 1 is started.

  The trigger signal AOC_trig illustrated in FIG. 7 and FIG. 8 is a logic signal indicating the magnitude relationship between the reference voltage Vref and the variable reference voltage Vref2.

  When the first comparator 131 reacts before the second comparator 132 when the switching power supply device 1 is activated, a count-up operation as shown in FIG. 7 is performed by the activation correction process. As shown in FIG. 7, the trigger signal AOC_trig is maintained at a low level while the first comparator 131 is reacting before the second comparator 132 as shown before the time t31. On the other hand, as shown at time t31, the variable reference voltage Vref2 becomes higher than the reference voltage Vref, and as a result of the second comparator 132 reacting before the first comparator 131, the first comparison signal S131 falls to a low level. If the second comparison signal S132 falls to the low level before the trigger signal AOC_trig rises to the high level.

  Although the increment of the counter value Scnt can be completed at this time, in the example of this figure, after the trigger signal AOC_trig rises to the high level, n pulses of the output signal S4 (n is an integer of 2 or more). The counter value Scnt continues to be incremented over a period of time. At time t32, when the (n + 1) -th pulse rises in the output signal S4, the adjustment completion signal AOC_end rises to a high level.

  When the second comparator 132 reacts before the first comparator 131 when the switching power supply device 1 is activated, a countdown operation as shown in FIG. 8 is performed by the activation correction process. As shown in FIG. 8, the trigger signal AOC_trig is maintained at a high level while the second comparator 132 is reacting before the first comparator 131 as shown before the time t30. On the other hand, as shown at time t30, the variable reference voltage Vref2 becomes lower than the reference voltage Vref, and as a result of the first comparator 131 reacting before the second comparator 132, the second comparison signal S132 falls to a low level. If the first comparison signal S131 falls to the low level before the trigger signal AOC_trig falls to the low level. Since the processing after time t30 is the same as that in FIG. 7, the description thereof is omitted.

  If only the above-described start-up calibration process is performed, there is a possibility that the input offset for each of the first and second comparators 131 and 132 may deviate due to a change in the external environment (for example, power supply voltage, temperature, etc.) after the start-up calibration process. is there. In addition, if incorrect calibration is performed in the startup calibration process, the input offset for each of the first and second comparators 131 and 132 remains deviated. Therefore, in the switching power supply device 1, the first calibration process and the second calibration process are executed after the start-up correction process is completed, that is, after the adjustment completion signal AOC_end becomes high level. Hereinafter, the first calibration process and the second calibration process will be described in order.

<First calibration process>
The first calibration process is executed before the period in which only the second comparator 132 is operating and when both the first comparator 131 and the second comparator 132 are still operating. That is, when the logic unit 134 sets the enable signal EN131 to the first logic level (= the logic level when enabled), the first calibration process is executed. Rather than operating the first comparator 131 only for the first calibration process, the period during which the first comparator 131 is operating based on the original operation of the switching power supply apparatus unrelated to the first calibration process is set. The first calibration process is executed using this. Thereby, it is possible to prevent an increase in current consumption due to the execution of the first calibration process.

  The logic unit 134 outputs from the second comparator 132 when the feedback voltage Vfb decreases to the same value as the reference voltage Vref, that is, when the first comparison signal S131 output from the first comparator 131 switches from high level to low level. The level of the second comparison signal S132 is confirmed.

  If the confirmed second comparison signal S132 is at a high level, the variable reference voltage Vref2 is smaller than the reference voltage Vref as shown in FIG. On the other hand, if the confirmed second comparison signal S132 is at a low level, the variable reference voltage Vref2 is larger than the reference voltage Vref as shown in FIG. Therefore, the logic unit 134 confirms the magnitude relationship between the reference voltage and the variable reference voltage based on the level of the second comparison signal S132 by confirming the level of the second comparison signal S132. In FIGS. 5 and 6, even if the feedback voltage Vfb becomes larger than the reference voltage Vref, the first comparison signal S131 does not immediately return from the low level to the high level because of the effect of the response speed of the first comparator 131. It is. Similarly, in FIG. 6, even if the feedback voltage Vfb becomes larger than the variable reference voltage Vref2, the second comparison signal S132 does not immediately return from the low level to the high level because of the effect of the response speed of the second comparator 132. is there.

  Then, the logic unit 134 determines that the high level of the backflow detection signal S5 continues for a second predetermined time (a time shorter than the first predetermined time, eg, 4 μs) after the backflow detection signal S5 is switched from the low level to the high level. The first calibration process is started, and the first calibration process is completed until a first predetermined time (for example, 8 μs) elapses after the backflow detection signal S5 is switched from the low level to the high level.

  In the first calibration process, the logic unit 134 causes the up / down counter 133a to increment the counter value Scnt by the control signal S6 if the most recently confirmed second comparison signal S132 is at a high level.

  On the other hand, in the first calibration process, the logic unit 134 causes the up / down counter 133a to decrement the counter value Scnt by the control signal S6 if the most recently confirmed second comparison signal S132 is at a low level.

<Second calibration process>
The second calibration process is executed when shifting from a state where only the second comparator 132 is operating to a state where both the first comparator 131 and the second comparator 132 are operating. That is, when the logic unit 134 switches the enable signal EN131 from the second logic level (= the logic level when disabled) to the first logic level (= the logic level when enabled), the second calibration process is executed. Rather than operating the first comparator 131 only for the second calibration process, the period during which the first comparator 131 is operating based on the original operation of the switching power supply device that is unrelated to the second calibration process. The second calibration process is executed using this. Thereby, it is possible to prevent an increase in current consumption due to the execution of the second calibration process.

  The logic unit 134 determines that the feedback voltage Vfb has decreased to the same value as the variable reference voltage Vref2 when only the second comparator 132 is operating, that is, when only the second comparator 132 is operating. It is detected that the second comparison signal S132 output from is switched from the high level to the low level. When the detection is performed, the logic unit 134 checks the level of the first comparison signal S131 output from the first comparator 131 when a predetermined delay time D has elapsed from the detection timing.

  When the second comparison signal S132 output from the second comparator 132 is switched from the high level to the low level, the first comparator 131 is stopped. Since the logic unit 134 activates the first comparator 131 triggered by the switching of the second comparison signal S132 output from the second comparator 132 from the high level to the low level, the activation of the first comparator 131 is completed. The predetermined delay time D is set to be longer than the time required for.

  If the confirmed first comparison signal S131 is at a low level, the variable reference voltage Vref2 is smaller than the reference voltage Vref as shown in FIG. On the other hand, if the confirmed first comparison signal S131 is at a high level, the variable reference voltage Vref2 is larger than the reference voltage Vref as shown in FIG. Therefore, the logic unit 134 confirms the magnitude relationship between the reference voltage and the variable reference voltage based on the level of the first comparison signal S131 by confirming the level of the first comparison signal S131. 9 and 10, even if the feedback voltage Vfb becomes larger than the variable reference voltage Vref2, the second comparison signal S132 does not immediately return from the low level to the high level because of the effect of the response speed of the second comparator 132. Is.

  And the logic part 134 performs a 2nd calibration process, after the level confirmation of 1st comparison signal S131 mentioned above is complete | finished.

  In the second calibration process, the logic unit 134 causes the up / down counter 133a to increment the counter value Scnt by the control signal S6 if the most recently confirmed first comparison signal S131 is at a low level.

  On the other hand, in the second calibration process, the logic unit 134 causes the up / down counter 133a to decrement the counter value Scnt by the control signal S6 if the most recently confirmed first comparison signal S131 is at a high level.

  9 and 10, the feedback voltage Vfb is at the timing when the second comparison signal S132 output from the second comparator 132 is switched from the high level to the low level when only the second comparator 132 is operating. It is rising. That is, the switching of the transistors N1 and N2 is resumed at the timing when the second comparison signal S132 output from the second comparator 132 is switched from the high level to the low level in a state where only the second comparator 132 is operating. .

  On the other hand, the transistors N1 and N2 are kept off after the timing when the second comparison signal S132 output from the second comparator 132 is switched from the high level to the low level in a state where only the second comparator 132 is operating. And switching of transistors N1 and N2 may resume after the second calibration process is complete. Thereby, it can be avoided that the second calibration process is adversely affected by the switching of the transistors N1 and N2.

<Modification of main comparator>
FIG. 11 is a circuit diagram showing a modification of the main comparator 13. The main comparator 13 of the present modification is based on the previous configuration example (FIG. 4), and further has an addition unit 133c added thereto. Therefore, the same circuit elements as those in the previous configuration example are denoted by the same reference numerals as those in FIG. 4, and redundant description is omitted. Hereinafter, characteristic portions of the modification example will be described mainly.

  The adding unit 133c generates the variable reference voltage Vref2 (= Vref + Vdac) by adding the analog voltage Vdac to the reference voltage Vref, and outputs this to the inverting input terminal (−) of the second comparator 132.

  That is, the analog voltage Vdac is used not as the variable reference voltage Vref2 itself but as an offset voltage added to the reference voltage Vref. The analog voltage Vdac is set to an analog output value with respect to the counter value Scnt so that the variable reference voltage Vref2 can take both positive and negative voltage values with respect to the reference voltage Vref.

  With such a configuration, the offset adjustment of the second comparator 132 can be performed with the reference voltage Vref input to the first comparator 131 as the center value.

<Application to TV>
FIG. 12 is a block diagram illustrating a configuration example of a television equipped with the above switching power supply device. 13A to 13C are a front view, a side view, and a rear view, respectively, of a television on which the above switching power supply device is mounted. The TV A in this configuration example includes a tuner unit A1, a decoder unit A2, a display unit A3, a speaker unit A4, an operation unit A5, an interface unit A6, a control unit A7, and a power supply unit A8. Have.

  The tuner unit A1 selects a broadcast signal of a desired channel from a reception signal received by an antenna A0 externally connected to the television A.

  The decoder unit A2 generates a video signal and an audio signal from the broadcast signal selected by the tuner A1. The decoder unit A2 also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit A6.

  The display unit A3 outputs the video signal generated by the decoder unit A2 as a video.

  The speaker unit A4 outputs the audio signal generated by the decoder unit A2 as audio.

  The operation unit A5 is one of human interfaces that accept user operations. As the operation unit A5, a button, a switch, a remote controller, or the like can be used.

  The interface unit A6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  The control unit A7 comprehensively controls the operations of the units A1 to A6. As the control unit A7, a CPU [central processing unit] or the like can be used.

  The power supply unit A8 supplies power to the units A1 to A7. As the power supply unit A8, the above-described switching power supply device 1 can be suitably used.

<Other variations>
In the above embodiment, the configuration in which the present invention is applied to the step-down switching power supply apparatus has been described as an example. However, the application target of the present invention is not limited to this, and for example, the switching power supply apparatus The output stage may be a step-up type, a step-up / step-down type, or an inversion type.

  In the above embodiment, the fixed on-time switching power supply (on-time setting circuit) has been described as an example. However, the application target of the present invention is not limited to this, and the same as described above. By changing the behavior of the variable reference voltage Vref2 based on the technical idea, it can be applied to a switching power supply device of a fixed off time type.

  In the above embodiment, the switching power supply device that performs both the first calibration process and the second calibration process has been described as an example. However, although the frequency of performing the calibration process is slightly inferior, It may be a switching power supply apparatus that performs only one of the first calibration process and the second calibration process.

  As described above, the configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The switching power supply according to the present invention is a power supply (for example, SOC [system-on-chip]) mounted on various electronic devices such as a liquid crystal display, a plasma display, a BD recorder / player, a set top box, and a personal computer. Or power supply for peripheral devices).

1 Switching power supply device 10 Semiconductor device (power supply control IC)
11 Ripple injection circuit 12 Reference voltage generation circuit 13 Main comparator (comparison circuit)
131 First Comparator 132 Second Comparator 133 Variable Reference Voltage Generation Unit 133a Up / Down Counter 133b DAC
133c Adding unit 134 Logic unit 14 One-shot pulse generation circuit 15 RS flip-flop 16 On-time setting circuit 17 Gate driver circuit 18 Backflow detection circuit 20 Switch output stage N1 N-channel MOS field effect transistor (output transistor)
N2 N-channel MOS field effect transistor (synchronous rectification transistor)
L1 Coil R1, R2 Resistor C1 Capacitor T1-T8 External terminal A TV A0 Antenna A1 Tuner A2 Decoder A3 Display A4 Speaker A5 Operation A6 A6 Interface A7 Control A8 Power supply

Claims (10)

A comparison circuit that is provided in a switching power supply device of a non-linear control system that generates a desired output voltage from an input voltage, and that receives the output voltage or a feedback voltage corresponding thereto as an input signal,
A first comparator that compares the input signal with a reference voltage to generate a first comparison signal;
A second comparator that compares the input signal with a variable reference voltage to generate a second comparison signal;
A variable reference voltage generator for generating the variable reference voltage;
A logic unit that outputs one of the first comparison signal and the second comparison signal as a comparison signal;
Have
While the logic unit outputs the first comparison signal as the comparison signal and operates the first comparator and the second comparator, a reverse current of a current flowing through a coil provided in the switching power supply device is generated. A period from when the switching power supply apparatus is detected to when the first predetermined time elapses in a state where the switching operation of the switching power supply is stopped (however, a second predetermined time shorter than the first predetermined time from the time when the backflow is detected In the comparison circuit, the variable reference voltage is adjusted to bring the logic switching timing of the second comparison signal closer to the logic switching timing of the first comparison signal in a period excluding a period until the time elapses). The logic part is
The level of the second comparison signal at the time when the level of the first comparison signal is switched while the first comparator and the second comparator are operated while outputting the first comparison signal as the comparison signal. Confirming the magnitude relationship between the reference voltage and the variable reference voltage based on
The comparison circuit according to claim 1, wherein the variable reference voltage is adjusted according to the magnitude relationship. A comparison circuit that is provided in a switching power supply device of a non-linear control system that generates a desired output voltage from an input voltage, and that receives the output voltage or a feedback voltage corresponding thereto as an input signal,
A first comparator that compares the input signal with a reference voltage to generate a first comparison signal;
A second comparator that compares the input signal with a variable reference voltage to generate a second comparison signal;
A variable reference voltage generator for generating the variable reference voltage;
A logic unit that outputs one of the first comparison signal and the second comparison signal as a comparison signal;
Have
The logic unit outputs the first comparison signal as the comparison signal from a state in which the first comparator is stopped and the second comparator is operated while outputting the second comparison signal as the comparison signal. However, when the first comparator and the second comparator are operated, the variable reference voltage is adjusted so that the logic switching timing of the second comparison signal approaches the logic switching timing of the first comparison signal. A comparison circuit characterized by that. The logic part is
While outputting the second comparison signal as the comparison signal, a predetermined delay time from when the level of the second comparison signal is switched while the first comparator is stopped and the second comparator is operated. Check the magnitude relationship between the reference voltage and the variable reference voltage based on the level of the first comparison signal when it has passed,
The comparison circuit according to claim 3, wherein the variable reference voltage is adjusted according to the magnitude relationship.   The comparison circuit according to claim 4, wherein the switching operation of the switching power supply device restarts after the adjustment of the variable reference voltage is completed. The response speed of the first comparator is faster than the response speed of the second comparator,
The power consumption of the second comparator is smaller than the power consumption of the first comparator.
The comparison circuit according to any one of claims 1 to 5, wherein the comparison circuit is characterized in that The variable reference voltage generator is
Up-down counter,
DAC (digital to analog converter) that converts the counter value of the up / down counter into an analog voltage;
Including
The comparison circuit according to any one of claims 1 to 6, wherein the analog voltage or a voltage corresponding to the analog voltage is output as the variable reference voltage.   The comparison circuit according to claim 7, wherein the variable reference voltage generation unit further includes an addition unit that generates the variable reference voltage by adding the analog voltage to the reference voltage. A ripple injection circuit that generates a feedback voltage by superimposing a ripple voltage simulating a coil current on the output voltage or its divided voltage; and
A reference voltage generation circuit for generating a predetermined reference voltage;
A main comparator that compares the feedback voltage with the reference voltage to generate a comparison signal;
A one-shot pulse generating circuit for generating a one-shot pulse in the set signal in accordance with the comparison signal;
An RS flip-flop that sets an output signal to a first logic level in response to the set signal and resets the output signal to a second logic level in response to a reset signal;
An on-time setting circuit for generating a one-shot pulse for the reset signal when a predetermined on-time has elapsed since the output signal was set to the first logic level;
A gate driver circuit that generates a drive signal for the output transistor and the synchronous rectification transistor according to the output signal;
A reverse current detection circuit for detecting the reverse current of the coil current and forcibly turning off the synchronous rectification transistor;
It is formed by integrating
A power supply control IC comprising the comparison circuit according to claim 1 as the main comparator. A power supply control IC according to claim 9,
A switch output stage that is externally or partially attached to the power supply control IC and generates an output voltage from an input voltage;
A switching power supply device comprising:

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