JP6318115B2 - Power system - Google Patents

Description

  The present invention relates to a power supply system, and more particularly, performs pulse-width modulation (PWM) control to perform DC power conversion between two DC power supplies and a load via current passing through two reactors. It relates to a power supply system.

  A hybrid power supply system that uses a power converter connected between a plurality of power supplies and a load to supply power to the load by combining the plurality of power supplies is used.

  For example, Japanese Patent Laying-Open No. 2013-13234 (Patent Document 1) describes a configuration of a power converter that can switch an operation mode by switching switching patterns of a plurality of switching elements. The operation mode includes a mode (parallel connection mode) in which DC power conversion is performed in a state where two DC power supplies are used in parallel. In the parallel connection mode, on / off of a plurality of switching elements is controlled by PWM control based on a comparison between a duty ratio for output control and a carrier wave for each of the two DC power supplies.

  Patent Document 2 describes the structure of a magnetic component for integrally configuring two reactors used in the power converter and the like described in Patent Document 1.

JP2013-13234A JP 2013-198246 A

  Patent Document 1 describes that power loss in a plurality of switching elements is reduced by controlling the phases of currents flowing through two reactors. Specifically, it is described that the current phase is controlled so that the rise timing or the fall timing (that is, the inflection point) is the same between the reactor currents.

  However, in Patent Document 1, the above-described current phase is realized by carrier phase control that controls a phase difference between carrier signals used for PWM control of two DC power supplies. For this reason, it is necessary to change the phase difference every time the duty ratio in the PWM control changes. As a result, the calculation load for carrier phase control becomes large, and the reactor current may fluctuate because the carrier phase difference becomes inappropriate due to the influence of calculation delay.

  Further, Patent Document 1 discloses an operation state of a power converter, specifically whether an inflection point to be matched between reactor currents is an ascending timing (minimum point) or a descending timing (maximum point). Describes that each DC power supply changes depending on whether it is operating in regeneration or powering. For this reason, there is a concern that the reactor current may fluctuate transiently due to an increase in the change amount of the carrier phase.

  The present invention has been made to solve such problems, and an object of the present invention is to convert DC power conversion between two DC power sources and a load via currents passing through two reactors. In the power supply system to be executed, the performance of the power supply system is improved by simply executing the current phase control for matching the timing of the inflection point between the reactor currents without increasing the calculation load of the PWM control. .

  In one aspect of the present invention, the power supply system controls a DC voltage between the first power line on the high voltage side and the second power line on the low voltage side connected to the load. The power supply system includes a first DC power supply, a second DC power supply, a power conversion for executing DC power conversion in parallel between the first and second DC power supplies, and the first and second power lines. And a control device for controlling DC power conversion in the power converter. The power converter includes a first reactor, a second reactor, and a plurality of switching elements. The plurality of switching elements are arranged so as to switch a current path passing through each of the first and second reactors by on / off control in response to a control signal from the control device. The current path passing through the first reactor includes first and second current paths. The first current path is formed between the first DC power source and the first reactor without including both the first and second power lines. The second current path connects the first DC power source and the first reactor in series between the first and second power lines. The current path passing through the second reactor includes third and fourth current paths. The third current path is formed between the second DC power source and the second reactor without including both the first and second power lines. The fourth current path connects the second DC power source and the second reactor in series between the first and second power lines. According to the comparison between the first output duty ratio for controlling the output from the first DC power supply and the first carrier wave having a voltage width corresponding to the maximum value of the first output duty ratio, A second carrier having a voltage width corresponding to the maximum value of the second output duty ratio and a second output duty ratio for selectively forming a current path and controlling the output from the second DC power supply Control signals for the plurality of switching elements are generated so as to selectively form the third and fourth current paths according to the comparison with the wave. For each of the first and second carrier waves, one of the first sawtooth wave having a straight line portion rising right and the second sawtooth wave having a straight line portion falling right is selected at the same frequency and synchronized in edge timing. It is composed by doing. During operation of the power converter, the control device switches the selection of the first and second sawtooth waves for each of the first and second carrier waves according to the operating state of the power converter.

  Preferably, when switching the selection of the first and second sawtooth waves in the first carrier wave, the control device provides a transition period having the same length as that of the first and second sawtooth waves, In the transition period, the first carrier wave is set to a triangular wave having the same frequency as that of the first and second sawtooth waves, or a reverse-phase triangular wave of the triangular wave, and the average current of the first reactor in the transition period However, the first output duty ratio is converted so as to be equal to the period immediately before the transition period. Further, the control measure provides a transition period when switching the selection of the first and second sawtooth waves in the second carrier wave, and changes the second carrier wave to a triangular wave or a reverse-phase triangular wave in the transition period. Further, the second output duty ratio is converted so that the average current of the second reactor in the transition period becomes equal to the period immediately before the transition period.

  More preferably, when the control device switches from the first sawtooth wave to the second sawtooth wave for each of the first or second carrier waves, the control device sets an antiphase triangular wave in the transition period. When switching from the second sawtooth wave to the first sawtooth wave, a triangular wave is set in the transition period. Alternatively, when switching from the first sawtooth wave to the second sawtooth wave for each of the first or second carrier waves, the control device sets the triangular wave in the transition period while When switching from the sawtooth wave to the first sawtooth wave, an antiphase triangular wave is set in the transition period.

  Preferably, the plurality of switching elements include first to fourth switching elements. The first switching element is electrically connected between the first node and the first power line. The second switching element is electrically connected between the second node and the first node. The third switching element is electrically connected between the third node and the second node. The fourth switching element is electrically connected between the second power line electrically connected to the negative terminal of the second DC power supply and the third node. The first reactor is electrically connected in series with the first DC power source between the second node and the first or second power line. The second reactor is electrically connected in series with the second DC power source between the first and third nodes. In the configuration in which the first reactor is connected between the second node and the second power line, the third and fourth switching elements are turned on when the first current path is formed, and the second current path The first and second switching elements are turned on during formation, the second and third switching elements are turned on during formation of the third current path, and the first and fourth switching elements are formed during formation of the fourth current path. Is turned on. In the configuration in which the first reactor is connected between the first node and the second power line, the first and second switching elements are turned on when the first current path is formed, and the second current path The third and fourth switching elements are turned on during formation, the second and third switching elements are turned on during formation of the third current path, and the first and fourth switching elements are formed during formation of the fourth current path. Is turned on.

  Preferably, the power converter includes first to fifth semiconductor elements. The first semiconductor element is electrically connected between the first power line and the first node. The second semiconductor element is electrically connected between the second power line and the first node. The third semiconductor element is electrically connected between the second node and the second power line. The fourth semiconductor element is electrically connected between the first power line and the second node. The fifth semiconductor element is electrically connected between the first node and the second node. At least the second, fourth, and fifth semiconductor elements have switching elements. At least the first and third semiconductor elements have diodes arranged with the direction from the second power line toward the first power line as the forward direction. The first reactor is electrically connected in series with the first DC power source between the first node and the second power line. The second reactor is electrically connected in series with the second DC power source between the second node and the first power line. When the first current path is formed, a current path is formed by the second semiconductor element, and when the second current path is formed, a current path is formed by the first semiconductor element. When the third current path is formed, a current path is formed by the fourth semiconductor element, and when the fourth current path is formed, a current path is formed by the third semiconductor element. The fifth semiconductor element forms a current path in a period in which the first and fourth current paths are formed simultaneously and in a period in which the second and third current paths are formed simultaneously.

  More preferably, in at least one of the first and third semiconductor elements, a switching element for forming a current path in a direction opposite to that of the diode is further provided in parallel with the diode. Responsive to the signal, it is controlled to turn on when the second or fourth current path is formed.

  Alternatively, more preferably, the fifth semiconductor element has first and second sub-switching elements. The first sub-switching element has an ON state that forms a current path from the first node to the second node between the first and second nodes and an OFF state that blocks the current path from the control device. The second sub-switching element is configured to selectively form in response to a signal. The second sub-switching element is turned on to form a current path from the second node to the first node between the first and second nodes. A state and an off state that interrupts the current path are selectively formed in response to a signal from the control device.

  Preferably, the first and second reactors are integrally configured by a single composite magnetic component. The composite magnetic component includes first to third windings and a core. The first and second windings are electrically connected in series, and the first current passes therethrough. The first and second windings are electrically connected in series to form a first reactor. The third winding constitutes a second reactor. The core is made of a non-linear magnetic material. The core includes a first magnetic leg portion around which the first winding is wound, a second magnetic leg portion around which the second winding is wound, and a third winding around which the third winding is wound. 3 magnetic leg portions and a fourth magnetic leg portion for forming a magnetic path between the first to third magnetic leg portions.

  More preferably, the operating states of the first reactor and the second reactor are the first and second reactors from the non-magnetic coupling mode in which the first and second reactors operate in a magnetically non-interfering state in response to an increase in current. It changes into the magnetic coupling mode which operate | moves in the state which the 2nd reactor interfered magnetically. In the nonmagnetic coupling mode, the magnetic permeability in the first and second magnetic leg portions is equal, while in the magnetic coupling mode, the magnetic permeability in one of the first and second magnetic leg portions is The permeability of the other of the first and second magnetic leg portions is lower.

  Alternatively, more preferably, when each of the first and second DC power supplies performs a power running operation, the first generated from the first winding and the second winding by the current passing through the first reactor, respectively. Of the first and second magnetic leg portions, and the third magnetic field generated from the third winding by the current passing through the second reactor. The first to third windings from the first so that the first and second magnetic fields weaken each other at the third magnetic leg, while the other magnetic leg weakens at the other and the first and second magnetic fields weaken each other at the third magnetic leg. Each is wound around the third magnetic leg portion.

  According to the present invention, in a power supply system that executes DC power conversion between two DC power supplies and a load through currents that pass through two reactors, the current between reactor currents is increased without increasing the calculation load of PWM control. Thus, the performance of the power supply system can be improved by simply executing the current phase control for matching the timing of the inflection points.

1 is a circuit diagram showing a configuration of a power supply system according to a first embodiment. It is the schematic which shows the structural example of the load shown by FIG. FIG. 2 is a first circuit diagram illustrating a current path of the power converter illustrated in FIG. 1. FIG. 3 is a second circuit diagram for explaining a current path of the power converter shown in FIG. 1. It is a functional block diagram explaining the control structure of the power converter shown by FIG. It is a wave form diagram explaining the operation example in the parallel control mode to which the carrier phase control shown as a comparative example was applied. It is a current waveform diagram for demonstrating the operation example of the carrier phase control in parallel connection mode. FIG. 8 is a circuit diagram illustrating a current path in a predetermined period of FIG. It is a chart for demonstrating the example of control of the electric current phase according to the direction of a reactor current. It is a 1st waveform diagram for demonstrating the carrier wave mode of the PWM control applied with the power supply system according to this Embodiment. It is a 2nd waveform diagram for demonstrating the carrier wave mode of the PWM control applied with the power supply system according to this Embodiment. It is a 3rd waveform diagram for demonstrating the carrier wave mode of the PWM control applied with the power supply system according to this Embodiment. It is a 4th waveform diagram for demonstrating the carrier wave mode of the PWM control applied with the power supply system according to this Embodiment. It is a table | surface explaining the response | compatibility with the waveform of the sawtooth wave in 4 carrier wave modes, and the phase pattern of a reactor current. FIG. 11 is an operation waveform diagram for illustrating a problem at the time of switching of a carrier wave mode in PWM control according to the first embodiment. It is a wave form diagram explaining the 1st control example at the time of the carrier wave mode switching in the PWM control according to the modification of this Embodiment 1. FIG. It is a wave form diagram for explaining duty ratio conversion in a transition period in PWM control according to a modification of the first embodiment. FIG. 17 is a chart for explaining a list of carrier wave settings in a transition period according to the first control example shown in FIG. 16. It is a wave form diagram explaining the 2nd control example at the time of the carrier wave mode switching in the PWM control according to the modification of this Embodiment 1. FIG. FIG. 20 is a chart for explaining a list of carrier wave settings in a transition period according to the first control example shown in FIG. 19. FIG. 2 is a chart showing a list of a plurality of operation modes included in the power converter shown in FIG. 1. It is a circuit diagram which shows the modification of the circuit structure of the power converter shown by FIG. FIG. 11 is a circuit diagram illustrating a configuration of a power supply system according to a second embodiment. FIG. 24 is a first equivalent circuit diagram of the power converter shown in FIG. 23 in a parallel boost mode. FIG. 25 is a circuit diagram showing a current path when the lower arm of each DC power supply in the equivalent circuit diagram shown in FIG. 24 is turned on. FIG. 25 is a circuit diagram showing a current path when the upper arm of each DC power supply is on in the equivalent circuit diagram shown in FIG. 24. FIG. 25 is a second equivalent circuit diagram in the parallel boost mode of the power converter shown in FIG. 24. FIG. 28 is a circuit diagram showing a current path when the lower arm of each DC power supply in the equivalent circuit diagram shown in FIG. 27 is turned on. FIG. 28 is a circuit diagram showing a current path when the upper arm of each DC power supply is on in the equivalent circuit diagram shown in FIG. 27. The correspondence relationship between each arm on / off of the boost chopper circuit using the first arm and the second arm and the on / off of the switching element is shown. FIG. 24 is a chart showing a list of gate logical expressions for on / off control of each switching element in the parallel boost mode of the power converter shown in FIG. 23. A waveform diagram for explaining a comparative example of the control operation in the parallel connection mode of the power converter shown in FIG. 23 is shown. FIG. 24 is a chart showing a list of switching patterns in the parallel boost mode of the power converter shown in FIG. 23. FIG. 24 is an equivalent circuit diagram of a boost chopper circuit using a first arm in the power converter shown in FIG. 23. It is an enlarged view of the part enclosed with the dotted line in FIG. FIG. 24 is an equivalent circuit diagram of a boost chopper circuit using a second arm in the power converter shown in FIG. 23. FIG. 37 is an enlarged view of a portion surrounded by a dotted line in FIG. 36. It is a conceptual diagram explaining the combination of the direction of the reactor current in the power converter shown by FIG. It is a wave form diagram which shows the example of an electric current behavior in case both DC power supplies carry out a power running operation. FIG. 38 is a circuit diagram for explaining three types of current paths that can be formed by the equivalent circuit shown in FIG. 37. It is a wave form diagram which shows transition of the conduction | electrical_connection loss in each of the three electric current paths shown by FIG. FIG. 42 is a circuit diagram for explaining a current path formed in the first period in FIGS. 39 and 41 in the power converter shown in FIG. 23. FIG. 42 is a circuit diagram for explaining a current path formed in a second period in FIGS. 39 and 41 in the power converter shown in FIG. 23. FIG. 37 is a circuit diagram for illustrating a current path when the power converter according to the first embodiment is operated in the same manner as in FIG. 36. FIG. 24 is a waveform diagram illustrating an example of current behavior when one DC power supply performs a power running operation and the other DC power supply performs a regenerative operation in the power converter illustrated in FIG. 23. FIG. 46 is a circuit diagram for describing three current paths that can be formed in the period shown in FIG. 45. It is a wave form diagram which shows transition of the conduction | electrical_connection loss in each of the three electric current paths shown by FIG. FIG. 12 is a waveform diagram for explaining application of PWM control similar to that in the first embodiment to the power converter according to the second embodiment. FIG. 11 is a circuit diagram for illustrating a configuration of a modification of the power converter according to the second embodiment. FIG. 50 is a chart showing a list of gate logical expressions for on / off control of each switching element in the parallel boost mode of the power converter shown in FIG. 49. FIG. 24 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 23 when the first DC power supply is not regeneratively charged. FIG. 24 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 23 when the second DC power supply is not regeneratively charged. FIG. 24 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 23 when the first and second DC power supplies are not regeneratively charged. FIG. 50 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 49 when the first DC power supply is not regeneratively charged. FIG. 50 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 49 when the second DC power supply is not regeneratively charged. FIG. 50 is a circuit diagram showing a modification of the configuration of the power converter shown in FIG. 49 when the first and second DC power supplies are not regeneratively charged. FIG. 11 is a circuit diagram showing a configuration example of a power supply system according to a third embodiment. FIG. 58 is an example of a schematic external view of a magnetically coupled reactor for integrally configuring the two reactors shown in FIG. 57. FIG. 59 is a conceptual cross-sectional view for further explaining the structure of the magnetically coupled reactor shown in FIG. 58. FIG. 60 is a conceptual diagram for explaining an example of a winding mode of each winding shown in FIG. 59. FIG. 60 is a conceptual diagram for explaining another example of the winding mode of each winding shown in FIG. 59. FIG. 60 is an electrical equivalent circuit diagram of the magnetically coupled reactor shown in FIG. 59. It is a conceptual 1st sectional view for explaining relation of magnetic flux generated from each winding in a core. It is a conceptual 2nd sectional view for explaining relation of magnetic flux generated from each coil in a core. It is a conceptual diagram which shows the general magnetization curve (BH curve) of a ferromagnetic. FIG. 66 is a conceptual diagram showing a change characteristic of magnetic permeability with respect to a change in magnetic flux density in the magnetization curve shown in FIG. 65. It is a conceptual diagram explaining the magnetic operating point of each magnetic leg part of the core in the area | region where a reactor current is small. It is a conceptual diagram explaining the magnetic operating point of each magnetic leg part of the core in the area | region where a reactor current is large. It is a conceptual waveform diagram for explaining the relationship between the phase of the reactor current and the magnetic flux density. FIG. 58 is a waveform diagram for explaining an example of current phase control in the power supply system shown in FIG. 57. FIG. 12 is a waveform diagram illustrating another example of current phase control in the power supply system according to the third embodiment. FIG. 12 is a waveform diagram illustrating still another example of current phase control in the power supply system according to the third embodiment. It is a wave form diagram which shows the 1st operation example when the phase of the reactor current in the power supply system according to Embodiment 3 is controlled. It is a wave form diagram which shows the 2nd example of operation when the phase of the reactor current in the power supply system according to Embodiment 3 is controlled. It is a schematic external view of the magnetic coupling reactor according to a modification. FIG. 76 is an external view of a core of the magnetically coupled reactor shown in FIG. 75. FIG. 76 is a schematic plan view for explaining a winding mode of each winding in the magnetic coupling reactor shown in FIG. 75.

  Embodiments of the present invention will be described below in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[Embodiment 1]
(Circuit configuration)
FIG. 1 is a circuit diagram showing a configuration example of a power supply system according to the first embodiment of the present invention. Power supply system 5A according to the first embodiment has the same circuit configuration as that of the power supply system disclosed in Patent Document 1.

  Referring to FIG. 1, power supply system 5 </ b> A includes DC power supply B <b> 1, DC power supply B <b> 2, load 30, control device 40, and power converter 50.

  In the first embodiment, DC power supplies B1 and B2 are configured by a power storage device such as a secondary battery or an electric double layer capacitor. For example, DC power supply B1 is comprised with secondary batteries, such as a lithium ion secondary battery and a nickel metal hydride battery. The DC power source B2 is constituted by a DC voltage source element having excellent output characteristics such as an electric double layer capacitor and a lithium ion capacitor.

  Note that the DC power supplies B1 and B2 can be configured by the same type of power storage device. Further, the capacities of the DC power supplies B1 and B2 are not particularly limited, and each of the DC power supplies B1 and B2 may be configured with an equivalent capacity, and the capacity of one DC power supply may be the same as that of the other DC power supply. It may be larger than the capacity.

  The power converter 50 is configured to control a DC voltage VH (hereinafter also referred to as an output voltage VH) between the high voltage side power line PL and the low voltage side power line GL. The power line GL is typically constituted by a ground wiring. Power lines PL and GL are connected to load 30.

  Load 30 operates by receiving output voltage VH of power converter 50 via power lines PL and GL. Voltage command value VH * of output voltage VH is set to a voltage suitable for the operation of load 30. Voltage command value VH * may be variably set according to the state of load 30. Furthermore, the load 30 may be configured to be able to generate charging power for the DC power sources B1 and / or B2 by regenerative power generation or the like.

FIG. 2 is a schematic diagram illustrating a configuration example of the load 30.
Referring to FIG. 2, load 30 is configured to include, for example, a traveling motor for an electric vehicle. Load 30 includes a smoothing capacitor CH, an inverter 32, a motor generator 35, a power transmission gear 36, and drive wheels 37.

  The motor generator 35 is a traveling motor for generating vehicle driving force, and is constituted by, for example, a multi-phase permanent magnet type synchronous motor. The output torque of the motor generator 35 is transmitted to the drive wheels 37 via a power transmission gear 36 constituted by a speed reducer and a power split mechanism. The electric vehicle travels with the torque transmitted to the drive wheels 37. Further, the motor generator 35 generates power by the rotational force of the drive wheels 37 during regenerative braking of the electric vehicle. This generated power is AC / DC converted by the inverter 32. This DC power can be used as charging power for DC power supplies B1 and B2 included in the power supply system 5A. In the configuration example of FIG. 2, the output voltage VH needs to be controlled to a voltage higher than the induced voltage generated in the motor generator 35.

  In a hybrid vehicle in which an engine (not shown) is mounted in addition to the motor generator, vehicle driving force required for the electric vehicle is generated by cooperatively operating the engine and the motor generator 35. At this time, it is also possible to charge the DC power sources B1 and B2 using the power generated by the rotation of the engine.

  As described above, the electric vehicle comprehensively represents a vehicle equipped with the electric motor for traveling, and includes a hybrid vehicle that generates vehicle driving force by the engine and the electric motor, and an electric vehicle and a fuel cell vehicle not equipped with the engine. It includes both.

  Referring to FIG. 1 again, power converter 50 includes power semiconductor switching elements S1 to S4 and reactors L1 and L2. In the present embodiment, an IGBT (Insulated Gate Bipolar Transistor), a power MOS (Metal Oxide Semiconductor) transistor, a power bipolar transistor, or the like is used as a power semiconductor switching element (hereinafter also simply referred to as “switching element”). be able to. Anti-parallel diodes D1 to D4 are arranged for switching elements S1 to S4.

  The switching elements S1 to S4 can be turned on and off in response to control signals SG1 to SG4 from the control device 40. That is, the switching elements S1 to S4 are turned on when the control signals SG1 to SG4 are at a logic high level (hereinafter, “H level”), and are turned off when the control signals SG1 to SG4 are at a logic low level (hereinafter, “L level”). .

  Switching element S1 is electrically connected between power line PL and node N1. Reactor L2 and DC power supply B2 are electrically connected in series between nodes N1 and N3. For example, reactor L2 is electrically connected between node N1 and the positive terminal of DC power supply B2, and the negative terminal of DC power supply B2 is electrically connected to node N3.

  Switching element S2 is electrically connected between nodes N1 and N2. Reactor L1 and DC power supply B1 are electrically connected in series between node N2 and power line GL. For example, reactor L1 is electrically connected between the positive terminal of DC power supply B1 and node N1, and the negative terminal of DC power supply B1 is electrically connected to power line GL.

  Switching element S3 is electrically connected between nodes N2 and N3. Switching element S4 is electrically connected between node N3 and power line GL. Power line GL is electrically connected to load 30 and the negative terminal of DC power supply B1.

  The control device 40 is configured by, for example, an electronic control unit (ECU) having a CPU (Central Processing Unit) and a memory (not shown). The control device 40 is configured to perform arithmetic processing using the detection values of each sensor based on the map and program stored in the memory. Alternatively, at least a part of the control device 40 may be configured to execute predetermined numerical / logical operation processing by hardware such as an electronic circuit.

  The control device 40 generates control signals SG1 to SG4 for controlling on / off of the switching elements S1 to S4 in order to control the output voltage VH.

  Although not shown in FIG. 1, the voltage (hereinafter referred to as V [1]) and current (hereinafter referred to as I [1]) of the DC power supply B1, and the voltage (hereinafter referred to as I [1]) of the DC power supply B1. , V [2]) and current (hereinafter referred to as I [2]) and an output voltage VH detector (voltage sensor, current sensor). The outputs of these detectors are provided to the controller 40.

  In the configuration of FIG. 1, the power line PL corresponds to a “first power line”, and the power line GL corresponds to a “second power line”. Further, switching elements S1 to S4 correspond to “first switching element” to “fourth switching element”, respectively, and reactors L1 and L2 respectively correspond to “first reactor” and “second reactor”. Correspond.

(Circuit operation in parallel boost mode)
Next, the control operation of the power converter 50 in the parallel boost mode will be described. The parallel boost mode is equivalent to the “parallel connection mode” in Patent Document 1.

  Referring to FIG. 1, power converter 50 is configured to include a boost chopper circuit corresponding to each of DC power supply B1 and DC power supply B2. That is, for DC power supply B1, a current bidirectional first step-up chopper circuit is configured with switching elements S1 and S2 as upper arms and switching elements S3 and S4 as lower arms. For DC power supply B2, a current bidirectional second step-up chopper circuit is configured with switching elements S1 and S4 as upper arms and switching elements S2 and S3 as lower arms.

  3 and 4 show a current conversion circuit of the power converter 50. FIG. FIG. 3 shows a current path in the first boost chopper circuit for DC power supply B1 and reactor L1, and FIG. 4 shows a current path in the second boost chopper circuit for DC power supply B2 and reactor L2. It is.

  Referring to FIG. 3A, when switching elements S3 and S4 constituting the lower arm of the first step-up chopper circuit are turned on, a current path 120 for storing energy in reactor L1 is formed by the current from DC power supply B1. Is done. That is, for DC power supply B1, loop-shaped current path 120 including DC power supply B1 and reactor L1 is formed without including power lines PL and GL. The current path 120 corresponds to the “first current path”.

  Referring to FIG. 3 (b), when switching elements S3 and S4 are turned off and switching elements S1 and S2 are turned on, accumulation is performed in reactor L1 via diodes D1 and D2 (or switching elements S1 and S2). It is possible to form a current path 121 for supplying the generated energy and the energy from the DC power supply B1 from the power converter 50 to the load 30. That is, for DC power supply B1, a current path 121 is formed in which DC power supply B1 and reactor L1 are connected in series between power lines PL and GL. The current path 121 corresponds to a “second current path”.

  In the circuit state of FIG. 3B, by turning on the switching elements S1 and S2 constituting the upper arm of the first step-up chopper circuit, the path for the regenerative current (reverse current of the current path 121) is also passed. Can be secured. That is, by turning on the switching elements S1 and S2, it is possible to cope with both the powering current (B1 discharging) and the regenerative current (B1 charging) without switching the switching pattern.

  The output from the DC power supply B1 is such that the period during which the current path 120 is formed when the lower arm is turned on (lower arm on period) and the period during which the current path 121 is formed when the upper arm is turned on (upper arm on period). It is controlled by being repeated. Hereinafter, the time ratio of the lower arm on period to the sum of the lower arm on period and the upper arm on period (that is, the switching cycle) is also referred to as “duty ratio”.

  Referring to FIG. 4A, when switching elements S2 and S3 constituting the lower arm of the second step-up chopper circuit are turned on, a current path 130 for storing energy in reactor L2 is formed by the current from DC power supply B2. Is done. That is, for DC power supply B2, a loop-shaped current path 130 including DC power supply B1 and reactor L1 is formed without including power lines PL and GL. The current path 130 corresponds to a “third current path”.

  Referring to FIG. 4B, when switching elements S2 and S3 are turned off and switching elements S1 and S4 are turned on, accumulation is performed in reactor L2 via diodes D1 and D4 (or switching elements S1 and S4). A current path 131 for supplying the generated energy and the energy from the DC power source B2 from the power converter 50 to the load 30 can be formed. That is, for DC power supply B2, a current path 131 is formed in which DC power supply B2 and reactor L2 are connected in series between power lines PL and GL. The current path 131 corresponds to the “fourth current path”.

  In the circuit state of FIG. 4B, by turning on the switching elements S1 and S4 constituting the upper arm of the second step-up chopper circuit, the path for the regenerative current (reverse current of the current path 131) is also passed. Can be secured. That is, by turning on the switching elements S1 and S4, it is possible to cope with both the powering current (discharge of B2) and the regenerative current (charge of B2) without switching the switching pattern.

  The output from the DC power supply B2 is also controlled by alternately repeating the lower arm on period in which the current path 130 is formed and the upper arm on period in which the current path 131 is formed.

  Thus, when the first and second boost chopper circuits are operated in parallel (parallel boost mode), the first boost chopper circuit formed between the DC power supply B1 and the power lines PL and GL is the first. Each of switching elements S1 to S4 is included in both the power conversion path and the second power conversion path formed between DC power supply B2 and power lines PL and GL by the second boost chopper circuit. Here, the first power conversion path corresponds to the path of the reactor current IL1 flowing through the reactor L1, and the second power conversion path corresponds to the path of the reactor current IL2 flowing through the reactor L2. Reactor current IL1 corresponds to current I [1] of DC power supply B1, and reactor current IL2 corresponds to current I [2] of DC power supply B2.

(Control operation in parallel boost mode)
FIG. 5 is a functional block diagram for controlling the power converter in the power supply system according to the present embodiment. In addition, the function of each block shown in the following functional block diagrams including FIG. 5 is realized in the control device 40 by software processing by execution of a predetermined program and / or hardware processing by a dedicated electronic circuit or the like. Shall be.

  Referring to FIG. 5, control device 40 includes an output control unit 500 for controlling the output of DC power supply B1 and an output control unit 510 for controlling the output of DC power supply B2. The output control unit 500 generates the duty ratio DT1 of the DC power supply B1. Output control unit 510 outputs duty ratio DT2 of DC power supply B2.

  For example, the output control unit 500 controls the output of the DC power supply B1 so that the output voltage VH is set to the voltage command value VH *. The output control unit 500 includes a deviation calculation unit 502, a PI control unit 505, and an addition unit 507.

  Deviation calculation unit 502 calculates a voltage deviation ΔVH (ΔVH = VH * −VH) of output voltage VH with respect to voltage command value VH *. The PI control unit 505 sets a feedback control amount by PI (proportional integration) control with respect to the voltage deviation ΔVH. The adding unit 507 calculates the duty ratio DT1 by adding the feedback control amount from the PI control unit 505 and the feedforward control amount Dff1.

  The feedforward control amount Dff1 is set according to the equation (1) according to the voltage ratio between the output voltage VH and the voltage V [1] of the DC power supply B1. That is, Dff1 represents a duty ratio set according to the theoretical boost ratio of the boost chopper circuit.

Dff1 = 1− (V [1] / VH *) (1)
Thus, it is understood that the duty ratio DT1 for controlling the output from the DC power supply B1 is set larger as the ratio of the voltage V [1] of the DC power supply B1 to the DC voltage VH becomes lower.

  For example, output control unit 510 controls the output of DC power supply B2 according to current command value Io *. The output control unit 510 includes a deviation calculation unit 512, a PI control unit 515, and an addition unit 517.

  As described in Patent Document 1, in the parallel boost mode, the power distribution between the DC power sources B1 and B2 can be controlled. Therefore, the power command value P2 * for the DC power source B2 controlled by the output control unit 510 is controlled. Can be set. This makes it possible to control the distribution between the DC power supplies B1 and B2 with respect to the total power input / output from the power converter 50 to the load 30. At this time, in the configuration example of FIG. 5, the current command value Io * = P2 * / V [2] can be set.

  The deviation calculator 512 calculates a current deviation ΔIo (ΔIo = Io * −Io) of the current Io with respect to the current command value Io *. For example, as shown in FIG. 5, in the configuration in which the direct current power source B2 is current-controlled, the current Io = I [2].

  The PI control unit 515 sets a feedback control amount by PI (proportional integration) control with respect to the current deviation ΔIo. The adding unit 517 calculates the duty ratio DT2 by adding the feedback control amount from the PI control unit 515 and the feedforward control amount Dff2.

  The feedforward control amount Dff2 is set according to the equation (2) according to the voltage ratio between the output voltage VH and the voltage V [2] of the DC power supply B2. That is, Dff2 indicates a duty ratio set according to the theoretical boost ratio of the boost chopper circuit.

Dff2 = 1− (V [2] / VH *) (2)
As described above, the duty ratio DT2 for controlling the output from the DC power supply B2 is qualitatively set larger as the ratio of the voltage V [2] of the DC power supply B2 to the DC voltage VH is lower. Is understood.

  Note that the output control of the DC power supplies B1 and B2 is not limited to the example in FIG. 5, and the calculation of the duty ratios DT1 and DT2 is arbitrary as long as it has a function of controlling the output voltage VH to the voltage command value VH *. Can be implemented in a manner.

  As an example of the arrangement, the output of the DC power sources B1 and B2 is controlled by power control (current control) based on the calculation of the required power Pr input / output from the power converter 50 in order to control the output voltage VH to the voltage command value VH *. ) Is also possible. Specifically, it is possible to control the output power of the DC power supplies B1 and B2 according to the power command values P1 * and P2 * in which the required power Pr is distributed between the DC power supplies B1 and B2 (Pr = P1). * + P2 *). In the parallel boost mode, the distribution between the power command values P1 * and P2 * can be made free.

  In this case, in the control configuration of FIG. 5, the output control units 500 and 510 have the current command value I1 * (I1 * = P1 * / V [1]) obtained from the power command values P1 * and P2 *. Duty ratios DT1 and DT2 can be calculated by feedback control of currents I [1] and I [2] with I2 * (I2 * = P2 * / V [2]) as a reference value.

  Carrier wave generator 560 generates carrier wave CW1 used for controlling DC power supply B1 and CW2 used for controlling DC power supply B2. Carrier waves CW1 and CW2 have the same frequency corresponding to the switching frequency. PWM control unit 550 generates control signals SG1 to SG4 for controlling switching elements S1 to S4 of power converter 50 from duty ratios DT1 and DT2 and carrier waves CW1 and CW2.

(Details of PWM control)
The basic control operation in the parallel boost mode of the power converter 50 is equivalent to the control operation in the parallel boost mode of Patent Document 1. Further, in Patent Document 1, as a technique for reducing the power loss in the switching elements S1 to S4 by adjusting the phase of the reactor current, the carrier wave phase control (hereinafter, referred to as PWM control of the DC power supply B1 and the DC power supply B2) is described. (Also referred to as “carrier phase control”).

  As a comparative example for PWM control for the power converter of the power supply system according to the present embodiment, first, the carrier phase control will be described.

(1) Application of Carrier Phase Control FIG. 6 is a waveform diagram illustrating an operation example in a parallel control mode to which carrier phase control shown as a comparative example is applied.

  Referring to FIG. 6, in carrier phase control, a carrier wave CW1 used for PWM control of DC power supply B1 and a carrier wave CW2 used for PWM control of DC power supply B2 use triangular waves of the same frequency.

  The period of carrier waves CW1 and CW2 corresponds to the switching frequency of each switching element. The voltage width (peak-to-peak) of carrier waves CW1 and CW2 is set to a voltage corresponding to duty ratio DT1 = 1.0 and DT2 = 1.0.

  A control pulse signal SD1 is generated based on a voltage comparison between the duty ratio DT1 for controlling the output of the DC power supply B1 and the carrier wave CW1. Control pulse signal SD1 is set to the H level when the voltage indicating duty ratio DT1 is higher than the voltage of carrier wave CW1, while it is set to the L level when the voltage is lower than the voltage of carrier wave CW1. The ratio of the H level period to the cycle of the control pulse signal SD1 (H level period + L level period), that is, the duty ratio of the control pulse signal SD1 is equivalent to DT1.

  The control pulse signal / SD1 is an inverted signal of the control pulse signal SD1. As the duty ratio DT1 increases, the H level period of the control pulse signal SD1 increases. On the contrary, when the duty ratio DT1 becomes low, the L level period of the control pulse signal SD1 becomes long.

  The control pulse signal SD1 corresponds to a signal for controlling on / off of the lower arms (switching elements S3 and S4) of the first boost chopper circuit described above. On the other hand, the control pulse signal / SD1 corresponds to a signal for controlling on / off of the upper arms (switching elements S1, S2) of the first boost chopper circuit.

  Similarly, control pulse signal SD2 and its inverted signal / SD2 are generated based on voltage comparison between duty ratio DT2 for controlling the output of DC power supply B2 and carrier wave CW2. The duty ratio of the control pulse signal SD2 is the same as that of DT2, and the duty ratio of the control pulse signal / SD2 is equivalent to (1.0−DT2). That is, when the duty ratio DT2 increases, the H level period of the control pulse signal SD2 becomes longer, and conversely, when the duty ratio DT2 decreases, the L level period of the control pulse signal SD2 becomes longer.

  The control pulse signal SD2 corresponds to a signal for controlling on / off of the lower arms (switching elements S2, S3) of the second boost chopper circuit described above. On the other hand, the control pulse signal / SD2 corresponds to a signal for controlling on / off of the upper arms (switching elements S1, S4) of the second boost chopper circuit.

  Control signals SG1 to SG4 are set based on the logical operation of control pulse signals SD1 (/ SD1) and SD2 (/ SD2), as described in Patent Document 1.

  Specifically, the switching element S1 forms an upper arm in each of the first boost chopper circuit (FIG. 3) and the second boost chopper circuit (FIG. 4), so that the control signal SG1 is the control pulse signal / It is generated by the logical sum of SD1 and control pulse signal / SD2.

  The switching element S2 forms an upper arm in the first boost chopper circuit (FIG. 3), and forms a lower arm in the second boost chopper circuit (FIG. 4). Therefore, control signal SG2 is generated by the logical sum of control pulse signal / SD1 and control pulse signal SD2.

  Similarly, the switching element S3 forms a lower arm in both the first boost chopper circuit (FIG. 3) and the second boost chopper circuit (FIG. 4), so that the control signal SG3 is the control pulse signal SD1 and It is generated by the logical sum of the control pulse signal SD2.

  Since the switching element S4 forms a lower arm in the first boost chopper circuit (FIG. 3) and an upper arm in the second boost chopper circuit (FIG. 4), the control signal SG4 is a control pulse signal. It is generated by the logical sum of SD1 and control pulse signal / SD2.

  By turning on and off switching elements S1 to S4 based on control signals SG1 to SG4, reactor currents IL1 and IL2 are controlled as shown in FIG. Reactor current IL1 corresponds to current I [1] of DC power supply B1, and reactor current IL2 corresponds to current I [2] of DC power supply B2. That is, the average values of reactor currents IL1 and IL2 are controlled by duty ratios DT1 and DT2, respectively.

  On the other hand, the phase relationship (current phase) between reactor current IL1 and reactor current IL2 changes without changing the current average value by changing phase difference φ between the triangular waves constituting carrier waves CW1 and CW2. Therefore, the power loss of switching elements S1 to S4 in the parallel boost mode of power converter 50 can be reduced by appropriately adjusting phase difference φ between carrier waves CW1 and CW2 by carrier phase control.

  In the following, as a representative example, control in a state where both DC power sources B1 and B2 are in a power running state, that is, a reactor current IL1> 0 and a reactor current IL2> 0 will be described.

  FIG. 7 is a current waveform diagram for explaining an operation example of carrier phase control in the parallel boost mode. FIG. 8 is a circuit diagram illustrating a current path in power converter 50 in the predetermined period of FIG.

  Referring to FIG. 7, switching elements S2 to S4 are turned on until time Ta, so that the lower arm (first and third current paths) of the boost chopper circuit with respect to both DC power supplies B1 and B2. Is turned on. For this reason, both reactor currents IL1 and IL2 rise.

  At time Ta, the switching element S2 is turned off, so that the lower arm (third current path) of the step-up chopper circuit is turned off with respect to the DC power supply B2, so that the reactor current IL2 decreases from rising to falling. Turn. That is, reactor current IL2 becomes maximum. Instead of switching off the switching element S2, the switching element S1 is turned on.

  After the time Ta, the lower arm (first current path) of the boost chopper circuit is turned on with respect to the DC power supply B1, and the lower arm of the boost chopper circuit is turned off with respect to the DC power supply B2. That is, reactor current IL2 rises, while reactor current IL1 falls. At this time, the current path in the power converter 50 is as shown in FIG.

  As understood from FIG. 8A, after the time Ta, a difference current between the reactor currents IL1 and IL2 passes through the switching element S4. That is, the passing current of the switching element S4 becomes small.

  Referring to FIG. 7 again, when switching element S4 is turned off from the state after time Tb, the lower arm of the step-up chopper circuit is turned off with respect to DC power supply B1, so that reactor current IL1 falls from the rise. Turn to. That is, reactor current IL1 becomes maximum. Further, when switching element S2 is turned on, the lower arm of the step-up chopper circuit is turned on with respect to DC power supply B2, so that reactor current IL2 changes from falling to rising again. That is, reactor current IL2 is minimal.

  Thereby, the current path in the power converter 50 changes from the state of FIG. 8A to the state of FIG. In the state of FIG. 8B, since the difference current between the reactor currents IL1 and IL2 passes through the switching element S2, the passing current of the switching element S2 becomes small.

  Further, by turning off the switching element S4 in the state of FIG. 8A, the current at the time of turning off the switching element S4 is reduced to perform soft switching, and the switching loss can be reduced. Further, by turning on the switching element S2 in the state of FIG. 8B, the current when the switching element S2 is turned on is reduced to perform soft switching, thereby reducing the switching loss.

  Therefore, as shown in FIG. 7, the current phase, that is, the carrier waves CW1 and CW2, is such that the timing at which the reactor current IL1 changes from rising to falling matches the timing at which the reactor current IL2 changes from falling to rising. Adjust the phase difference φ. That is, the phase difference φ is adjusted so that the inflection point (maximum point) of reactor current IL1 and the inflection point (minimum point) of reactor current IL2 are at the same timing. Thereby, at time Tb in FIG. 7, the switching element S2 is turned on and the switching element S4 is turned off.

  Referring to FIG. 7 again, at time Tc, switching element S1 is turned off and switching element S4 is turned on. As a result, the lower arm of the step-up chopper circuit is turned off with respect to the DC power source B1, and the reactor current IL1 changes from falling to rising. That is, reactor current IL2 is minimal. When the switching element S1 is turned on instead of turning off the switching element S2, the lower arm of the step-up chopper circuit is turned on for each of the DC power supplies B1 and B2. Therefore, the state before time Ta described above is reproduced, and both reactor currents IL1 and IL2 rise.

  Thus, when both DC power supplies B1 and B2 are in a power running state, the current phase is such that the maximum point of reactor current IL1 and the minimum point of reactor current IL2 overlap at time Tb in the figure. The phase difference φ between the carrier waves CW1 and CW2 is adjusted. Thereby, the turn-on loss of switching element S2 and the turn-off loss of switching element S4 at time Tb can be reduced.

  As described above, by optimizing the phase difference φ so that φ = φ * in FIG. 6, the phases of the reactor currents IL1 and IL2 are controlled so as to reduce the loss in the switching elements S1 to S4. Can do.

  As understood from FIG. 6, in such a phase difference φ *, the falling timing (or rising timing) of the control pulse signal SD1 and the rising timing (or falling timing) of the control pulse signal SD2 overlap. become.

  The waveforms of the control pulse signals SD1 and SD2 vary depending on the duty ratios DT1 and DT2. Therefore, the optimum phase difference φ * by the carrier phase control also changes according to the duty ratios DT1 and DT2. For this reason, in the carrier phase control of Patent Document 1, a relationship between the duty ratios DT1 and DT2 and the optimum phase difference φ * is obtained in advance, and the phase difference is changed every time the duty ratios DT1 and DT2 change according to the corresponding relationship. Need to change φ. As a result, the problem is that the calculation load on the control device 40 for carrier phase control increases.

  If the control of the phase difference φ is delayed due to the influence of the calculation load, there is a concern that the behavior of the reactor currents IL1 and IL2 becomes unstable. Alternatively, the control cycle of the PWM control may be restricted according to the specifications of the control device 40. On the contrary, there is a possibility that a high specification is required for the control device 40 in order to secure a control cycle of the PWM control.

  Further, as described in Patent Document 1, the preferable phase relationship between reactor currents IL1 and IL2 is, for example, whether DC power supplies B1 and B2 are operating in power running (discharge) / regeneration (charge), that is, Depending on the combination of reactor currents IL1 and IL2 in the power converter 50 (positive / negative).

  FIG. 9 is a chart for explaining an example of control of the current phase according to the direction of the reactor current.

  Referring to FIG. 9, in state A where the reactor current is IL1> 0, IL2> 0, both DC power supplies B1 and B2 described above are in a powering state. In this case, as described with reference to FIGS. 6 to 8, regarding the reactor current, the current phase (hereinafter referred to as “phase pattern A”) where the maximum point (crest) of IL1 and the minimum point (valley) of IL2 are the same timing. ”), The power loss in the switching elements S1 to S4 can be reduced.

  Similarly, in state B where the reactor current is IL1 <0, IL2 <0, both DC power supplies B1 and B2 are in the regenerative state. In this case, since the directions of the reactor currents IL1 and IL2 are opposite to those in the state A, the current phase (hereinafter referred to as “phase”) in which the minimum point (valley) of IL1 and the maximum point (peak) of IL2 are the same timing. In this case, the power loss in the switching elements S1 to S4 can be reduced.

  In the state C where the reactor current is IL1 <0, IL2> 0, the DC power supply B1 is in the regenerative state, while the DC power supply B2 is in the powering state. In this state, by setting the current phase (hereinafter also referred to as “phase pattern C”) at which the local maximum point (crest) of IL1 and the local maximum point (crest) of IL2 have the same timing, switching elements S1 to S4 Power loss can be reduced.

  Similarly, in the state D where the reactor currents IL1> 0 and IL2 <0, the DC power source B1 is in the power running state, while the DC power source B2 is in the regenerative state. In this state, the minimum phase (valley) of IL1 and the minimum point (valley) of IL2 have the same timing (hereinafter also referred to as “phase pattern D”), so that switching elements S1 to S4 Power loss can be reduced.

  Thus, a preferable current phase for reducing power loss in switching elements S1 to S4 according to the direction (positive / negative) of reactor currents IL1 and IL2, which is one of the operating states of power converter 50. Changes between the above four patterns.

  Further, when the above four patterns of current phases are applied to the same combination of reactor currents IL1 and IL2 (positive / negative), the power loss in each of the switching elements S1 to S4, that is, the amount of heat generated, changes. It is understood. Therefore, when the current phase pattern is switched in a time division manner, there is a possibility that the amount of heat generated can be made uniform between the switching elements S1 to S4. In this case, the preferred current phase changes between the four patterns according to the temperature of the switching elements S1 to S4, which is one of the operating states of the power converter 50.

  Therefore, during operation of power supply system 5A, high efficiency is achieved by reducing power loss by current phase control that switches the phase of reactor currents IL1 and IL2 between phase patterns A to D in accordance with the operating state of power converter 50. Alternatively, the performance of the power supply system 5A can be improved through high output by suppressing the element temperature.

  However, when the current phase control is performed by the carrier phase control of the triangular wave, the change in the carrier phase difference becomes large at the time of pattern switching. For this reason, if the influence of the height of the calculation load mentioned above is also taken into consideration, there is a concern that the transient behavior of the reactor current becomes unstable and the current fluctuation becomes excessive.

(2) PWM control according to the present embodiment In order to solve the problems caused by carrier phase control as described above, in the present embodiment, as described below, PWM control using a sawtooth wave as a carrier wave is used. , Current phase control involving switching of the current phase pattern of reactor currents IL1 and IL2 is realized.

  10 to 13 are waveform diagrams for illustrating a carrier wave mode of PWM control applied in the power supply system according to the present embodiment.

  Referring to FIGS. 10 to 13, in the power supply system according to the present embodiment, carrier waves CW <b> 1 and CW <b> 2 are configured by two sawtooth waves whose phases (edge timings) are synchronized at the same frequency. 10 to 13 are the same as FIG. 6 except for the carrier waves CW1 and CW2. That is, the on / off control of the switching elements S1 to S4 based on the control pulse signals SD1 and SD2 is performed in the same manner as in FIG.

  There are two types of sawtooth waves: a right-down shape and an upper-right shape. Therefore, as shown in FIG. 14, it is understood that there are four modes in the carrier waves CW1 and CW2 depending on the combination of the sawtooth waveform. 10 to 13 show PWM waveforms in each of the carrier wave modes 1 to 4 shown in FIG.

  Referring to FIG. 10, in carrier wave mode 1, carrier wave CW1 is constituted by a sawtooth wave STD having a right-bottom shape, and carrier wave CW2 is constituted by a sawtooth wave STU having a right-upward shape.

  As described with reference to FIG. 6, the control pulse signal SD1 is generated according to a voltage comparison between the carrier wave CW1 and the duty ratio DT1. Similarly, control pulse signal SD2 is generated in accordance with voltage comparison between carrier wave CW2 and duty ratio DT2. By control of switching elements S1 to S4 by control signals SG1 to SG4 set according to control pulse signals SD1 and SD2, reactor current IL1 rises during the H level period of control pulse signal SD1, and L level period of control pulse signal SD1. Then, the reactor current IL1 decreases. Similarly, reactor current IL2 increases during the H level period of control pulse signal SD2, and reactor current IL2 decreases during the L level period of control pulse signal SD2.

  Since the carrier waves CW1 and CW2 are synchronized in edge timing at the same frequency, the levels of the control pulse signals SD1 and SD2 transition at time tx, which is the cycle switching timing. At this timing, reactor currents IL1 and IL2 have inflection points. That is, the inflection points of reactor currents IL1 and IL2 can be set to the same timing as in phase patterns A to D shown in FIG. 9 for each cycle of carrier waves CW1 and CW2. Furthermore, the phase patterns A to D can be selected by a combination of sawtooth wave waveforms constituting the carrier waves CW1 and CW2.

  As shown in FIG. 10, reactor current IL1 controlled by a sawtooth wave having a right-bottom shape (hereinafter also simply referred to as “down-sawtooth wave”) STD has a maximum point (mountain) at time tx. On the other hand, reactor current IL2 controlled by a sawtooth wave having an upper right shape (hereinafter also simply referred to as “upward sawtooth wave”) STU has a minimum point (valley) at time tx. Therefore, if the carrier wave mode 1 is applied, the current phase can be controlled to realize the phase pattern A of FIG. The upstream sawtooth wave STU corresponds to the “first sawtooth wave”, and the downstream sawtooth wave STD corresponds to the “second sawtooth wave”.

  Referring to FIG. 11 and FIG. 14, in carrier wave mode 2, carrier wave CW1 is composed of an upstream sawtooth wave STU, while carrier wave CW2 is composed of a downstream sawtooth wave STD.

  As a result, at the same time tx as in FIG. 10, reactor current IL1 has a minimum point (valley), while reactor current IL2 has a maximum point (peak). Therefore, as shown in FIG. 11, if the carrier wave mode 2 is applied, the current phase can be controlled so as to realize the phase pattern B of FIG.

  Referring to FIGS. 12 and 14, in carrier wave mode 3, both carrier waves CW1 and CW2 are configured by uplink sawtooth wave STU.

  As a result, at the same time tx as in FIGS. 10 and 11, both reactor currents IL1 and IL2 have minimum points (valleys). Therefore, as shown in FIG. 12, when the carrier wave mode 3 is applied, the current phase can be controlled so as to realize the phase pattern C of FIG.

  Referring to FIGS. 13 and 14, in carrier wave mode 4, both carrier waves CW 1 and CW 2 are configured by downstream sawtooth waves STD.

  As a result, at the same time tx as in FIGS. 10 to 12, both reactor currents IL <b> 1 and IL <b> 2 have maximum points (mountains). Therefore, as shown in FIG. 13, if the carrier wave mode 4 is applied, the current phase can be controlled so as to realize the phase pattern D of FIG.

  Thus, according to the power supply system according to the first embodiment, by applying the sawtooth wave to carrier waves CW1 and CW2, current phase control for matching the inflection points between reactor currents IL1 and IL2 at the same timing. Can be realized by simple control processing without performing complicated calculation processing such as adjustment of carrier phase difference. Further, the selection of the phase patterns A to D of the reactor currents IL1 and IL2 can be easily realized by selecting the sawtooth waveform. Specifically, the carrier wave generation unit 560 (FIG. 6) changes the operation state of the power converter 50 (the direction of the reactor currents IL1 and IL2 and / or the temperature of the switching elements S1 to S4, etc.) to FIG. By generating carrier waves CW1 and CW2 with the selection of the indicated carrier wave mode, the phase patterns A to D can be selected.

  In power converter 50 shown in FIG. 1, both reactor currents IL1 and IL2 flow through at least one of switching elements S1 to S4 in accordance with the on / off control of switching elements S1 to S4. For this reason, high efficiency or high output can be achieved by current phase control in which the phase patterns A to D shown in FIG. 9 are switched according to the operating state of the power converter 50.

  Therefore, in power supply system 5A including power converter 50 shown in FIG. 1, the reactor current is increased by a simple control process by controlling the outputs of DC power supplies B1 and B2 by PWM control according to the present embodiment. The performance can be improved without fluctuation.

[Modification of Embodiment 1]
In the PWM control according to the first embodiment, when the phase pattern is switched, it is necessary to switch the carrier wave mode for changing the sawtooth waveform between the periods of the carrier waves CW1 and CW2. In the modification of the first embodiment, preferable control at the time of switching the carrier wave mode will be further described.

  FIG. 15 is an operation waveform diagram for illustrating problems at the time of switching of the carrier wave mode in PWM control according to the first embodiment.

  Referring to FIG. 15, inflection points of reactor currents IL1 and IL2 are generated at the same timing for every cycle Tcy of carrier waves CW1 and CW2. Since carrier wave mode 2 is applied before time t1, at times tx1 and tx2, the minimum point (valley) of reactor current IL1 and the maximum point (peak) of reactor current IL2 coincide. That is, the current phase is controlled to the phase pattern B.

  At time t1, the current phase control is switched from the phase pattern B to the phase pattern A according to the operating state of the power converter 50. In response to this, the carrier wave mode is switched after time t1. Specifically, the carrier wave mode 1 in which the carrier wave CW1 is configured by the downstream sawtooth wave STD and the carrier wave CW2 is configured by the upstream sawtooth wave STU is newly selected.

  Between the cycle 200A immediately before time t1 and the cycle 200B immediately after time t1, both the carrier wave CW1 and the carrier wave CW2 are symmetric with respect to the switching time point (time t1). As a result, the reactor current IL1 continues to decrease over a normal double period, and the reactor current IL2 increases over a normal double period. Thereby, the fluctuation | variation of a reactor current becomes large.

  Furthermore, in cycle 200B, it is understood that the average value of reactor current IL1 decreases and the average value of reactor current IL2 increases while duty ratios DT1 and DT2 do not change. Even in the cycle 200B, the ratio of the lower arm on period and the upper arm on period with respect to each of the DC power sources B1 and B2 does not change, but the period length in which the reactor currents IL1 and IL2 continuously change in the same direction changes. The average current will change.

  As a result, even in the period following the period 200B, the average value of reactor currents IL1 and IL2 changes from before time t1. By adjusting the duty ratios DT1 and DT2 by subsequent feedback control, the average value of the reactor currents IL1 and IL2 can be restored to an appropriate value, but current fluctuations occur when the carrier wave mode is switched. Is not preferred.

  As described above, when the carrier wave mode is switched, if the carrier wave waveform is symmetrical with respect to the switching time point (time t1), there is a concern that the transient fluctuation of the reactor current increases.

  FIG. 16 is a waveform diagram for explaining a first control example at the time of carrier wave mode switching in PWM control according to the modification of the first embodiment.

  Referring to FIG. 16, in the modification of the first embodiment, transition period 205 is provided between periods 200A and 200B for switching the carrier wave mode. In the transition period 205, when the waveform of the sawtooth wave is switched by switching the carrier wave mode, the triangular wave TW or the antiphase triangular wave RTW having the same period Tcy as the sawtooth wave is applied to the carrier wave.

  In the example of FIG. 16, as in FIG. 15, when switching from the carrier wave mode 2 to the carrier wave mode 1 is performed from time t <b> 1, a triangular wave is used when switching from the downstream sawtooth wave STD to the upstream sawtooth wave STU. TW is applied to the carrier wave. On the other hand, when switching from the upstream sawtooth wave STU to the downstream sawtooth wave STD, the anti-phase triangular wave RTW is applied. For this reason, in the transition period 205, the carrier wave CW1 is constituted by an antiphase triangular wave RTW, and the carrier wave CW2 is constituted by a triangular wave TW.

  Since the triangular wave TW and the antiphase triangular wave RTW have the same period as the sawtooth wave, the voltage level relationship between the duty ratios DT1 and DT2 and the carrier waves CW1 and CW2 is 2 between the times t1 and tz when the transition period 205 is applied. Change times. As a result, inflection points are generated twice in the reactor currents IL1 and IL2.

  As a result, the continuous current increase or decrease period when switching the carrier wave mode is shorter than that in FIG. Therefore, fluctuations in reactor currents IL1 and IL2 can be reduced.

  On the other hand, when the triangular wave TW or the anti-phase triangular wave RTW is applied as the carrier wave, the average values of the reactor currents IL1 and IL2 change for the same duty ratio DT1 and DT2 as in FIG. . Therefore, in order not to change the average values of reactor currents IL1 and IL2, it is necessary to convert the duty ratio when applying triangular wave TW or antiphase triangular wave RTW.

  FIG. 17 is a waveform diagram for explaining duty ratio conversion when the triangular wave TW is applied as a carrier wave.

  FIG. 17 shows derivation of the conversion duty ratio DTa in the transition period 205 in which the triangular wave TW is applied to the duty ratio DT. In FIG. 17, the duty ratio DT comprehensively represents DT1 and DT2, and the reactor current IL comprehensively represents IL1 and IL2.

  Conversion duty ratio DTa is set so that the average value of reactor current IL does not change between period 200A according to duty ratio DT1 and transition period 205 according to conversion duty ratio DTa.

  Referring to FIG. 17, in period 200A immediately before transition period 205 and period 200B immediately after, transition wave 205, carrier wave CW is a downstream sawtooth wave STD and an upstream sawtooth wave STU. In period 200A, since CW> DT between times t0 and ta (period length T1), reactor current IL decreases. In this period, a current path 121 (FIG. 3B) is formed for the reactor current IL1, and a current path 131 (FIG. 4B) is formed for the reactor current IL2.

  On the other hand, between times ta and t1 (period length T2), CW <DT, so that reactor current IL increases. In this period, a current path 120 (FIG. 3A) is formed for the reactor current IL1, and a current path 130 (FIG. 4A) is formed for the reactor current IL2.

  Here, when the duty ratio DT and the cycle Tcy are used, T2 = Tc × DT and T1 = Tc × (1−DT). The reactor current IL is equal at times t0 and t1 separated by the cycle Tcy.

  First, in the transition period 205, the waveform of the reactor current IL when the duty ratio DT1 equivalent to the period 201 is compared with the triangular wave TW is indicated by a dotted line. In this case, inflection points occur in reactor current IL at times tc and td when DT1 = TW. The period length T5 from time tc to td when TW> DT1 (ie, the upper arm-on period length) is equivalent to the period length T2 in the period 201.

  However, in period 205, the current increase period due to the lower arm on continues after time t1, so even if the upper arm-on period length is secured to be equal to period 201, the average value of reactor current IL is higher than period 201. Resulting in. Therefore, in order to make the average value of reactor current IL equal to period 201, conversion duty ratio DTa needs to be obtained as follows.

  In transition period 205 (time t1 to tz), reactor current IL rises since DTa> CW during time t1 to tb (period length T3) with respect to conversion duty ratio DTa. In this period, a current path 120 (FIG. 3A) is formed for the reactor current IL1, and a current path 130 (FIG. 4A) is formed for the reactor current IL2.

  When the conversion duty ratio DTa is compared with the triangular wave TW, the reactor current IL decreases because CW> DTa from time tb to time te. From time te to tz (period length T7), since DTa> CW again, reactor current IL rises in the same way as from time t1 to tb. From the waveform of the triangular wave TW, T3 = T7 is established. Further, since T3 + T7 = Tc × DTa, it is understood that T3 = T7 = (Tc / 2) × DTa.

  As described above, the period length T5 from time tc to td is equal to the upper arm on period length T1 in the period 201. Therefore, reactor current IL at time tc (hereinafter also referred to as IL (tc)) is equivalent to reactor current IL at time t0 and t1 (hereinafter also referred to as IL (t0) and IL (t1)). Then, the reactor current IL at time td is also equivalent to time ta.

  From the symmetry of the triangular wave TW, T3: T4 = T7: T6. For this reason, when IL (tc) = IL (t1) (= IL (t0)) is realized, the reactor current IL at the time tz at which the cycle 205 is ended and the cycle 202 is started is expressed by the cycle 201. Can be made equal to the minimum value (time ta). In the period 202 in which the upward sawtooth wave is applied, the reactor current IL becomes the minimum value at the time tz when the period 202 is started. As a result, the average value of the reactor current IL can be made equal in each of the period 201, the transition period 205, and the period 202.

  Before and after time t1, the slope when reactor current IL rises and the slope when it falls are unchanged. Therefore, it is understood from the similarity of the current waveform that the conversion duty ratio DTa should be determined so that T1: T2 = T4: T3 is satisfied in order to satisfy IL (tc) = IL (t1). The Here, the following formula (1) is established from T1: T2 = (1-DT): DT and T3 = (Tc / 2) × DTa.

(1-DT): DT = T4: (Tc / 2) × DTa (1)
When the equation (1) is modified, the following equation (2) is obtained.

T4 = (DTa / DT) × (1-DT) × (Tc / 2) (2)
Also, from time tb to td, the following equation (3) is established from the symmetry of the triangular wave TW.

T4 × 2 + T5 = (1−DTa) × Tc (3)
Substituting Equation (2) into Equation (3) and further substituting T5 = Tc × (1−DT) because T1 = T5 where the current change amount is the same between the period 200A and the transition period 205. Then, equation (4) is obtained.

DTa / DT × (1-DT) + (1-DT) = (1-DTa) (4)
Solving equation (4) for DTa yields DTa = DT ^ 2 (DT squared).

  Similarly, when the conversion duty ratio DTb in the transition period 205 to which the anti-phase triangular wave RTW is applied is determined so that the average value of the reactor current IL is equivalent to the period 201, detailed derivation is omitted, but DTb = 1 -(1-DT) ^ 2 is obtained.

  As described above, a list of carrier wave settings in the transition period according to the first control example shown in FIG. 16 is as shown in FIG.

  Referring to FIG. 18, the carrier wave switching mode is indicated by a two-digit integer that represents the carrier wave mode before switching and the carrier wave mode after switching in succession. For example, the switching mode 21 is applied when switching from the carrier wave mode 2 to the carrier wave mode 1 shown in FIG. Therefore, for 4 carrier wave modes, there are 3 × 4 = 12 switching modes.

  FIG. 18 shows carrier waves CW1 and CW2 and applied duty ratios DT1 # and DT2 # in each switching mode. As described above, duty ratios DT1 # and DT2 # are converted values for making the average value of reactor currents IL1 and IL2 equal to period 200A immediately before transition period 205 as well.

  Regarding the carrier wave CW1, in the switching mode 14 and the switching mode 41 where the downstream sawtooth wave is applied both before and after switching, it is not necessary to change the carrier wave CW1 in the transition period 205. For this reason, the downstream sawtooth wave STD is applied to the carrier wave CW1. Similarly, in the switching mode 23 and the switching mode 32 where the upstream sawtooth wave is applied both before and after switching, the upstream sawtooth wave STU is applied to the carrier wave CW1. In these switching modes, duty ratio conversion is not required, so DT1 # = DT1 is set.

For the carrier wave CW1, in the switching mode 12, the switching mode 13, the switching mode 42, and the switching mode 43, the downstream sawtooth wave is applied before switching, while the upstream sawtooth wave is applied after switching, in FIG. Similarly to the carrier wave CW2, the triangular wave TW is applied. In this case, DT1 # = DTa = (DT1) ² (that is, DT1 ^ 2) is set by duty ratio conversion.

On the other hand, in the switching mode 21, the switching mode 24, the switching mode 31, and the switching mode 34 in which an upstream sawtooth wave is applied before switching and a downstream sawtooth wave is applied after switching, the carrier in FIG. Similar to the wave CW1, an antiphase triangular wave RTW is applied. In this case, DT1 # = DTb = 1− (1-DT1) ² (that is, 1− (1-DT1) ^ 2) is set by duty ratio conversion.

  Also in the switching mode 24 and the switching mode 42, the carrier wave CW2 in the transition period 205 is composed of the downstream sawtooth wave STD, as in the carrier wave CW1, as in the carrier wave CW1. . In addition, in the switching mode 13 and the switching mode 31 in which the upstream sawtooth wave is applied before and after switching, the carrier wave CW2 is applied by the upstream sawtooth wave STU. In these switching modes, DT2 # = DT2.

On the other hand, in the switching mode 21, the switching mode 23, the switching mode 41, and the switching mode 43 in which the downstream sawtooth wave is applied before switching, and the upstream sawtooth wave is applied after switching, the carrier in FIG. Similar to the wave CW2, the triangular wave TW is applied. DT2 # = DTa = (DT2) ² (that is, DT2 ^ 2) is set.

On the other hand, in the switching mode 12, the switching mode 14, the switching mode 32, and the switching mode 34, the upstream sawtooth wave is applied before switching, while the downstream sawtooth wave is applied after switching, in FIG. Similarly to the carrier wave CW1, the anti-phase triangular wave RTW is applied. Then, DT2 # = DTb = 1- (1-DT2) ² (that is, 1- (1-DT2) ^ 2) is set.

  In this way, when the carrier wave mode is switched for current phase control that changes the phase relationship between reactor currents IL1 and IL2, the average values of reactor currents IL1 and IL2 are maintained, and fluctuations in reactor currents IL1 and IL2 are maintained. Can be suppressed.

  Note that the application of the triangular wave and the anti-phase triangular wave at the time of switching the carrier wave mode can be reversed from the example of FIG.

  FIG. 19 is a waveform diagram for explaining a second control example at the time of switching the carrier wave mode in the PWM control according to the modification of the first embodiment. 19 also shows switching from the carrier wave mode 2 to the carrier wave mode 1 as in FIG.

  Referring to FIG. 19, in the second control example, on the contrary to the first control example, at the time of switching from the upstream sawtooth wave STU to the downstream sawtooth wave STD, the triangular wave TW is applied to the carrier wave and the downstream sawtooth When switching from the wave STD to the upstream sawtooth wave STU, the anti-phase triangular wave RTW is applied to the carrier wave. Thereby, contrary to the example of FIG. 16, in the transition period 205, the carrier wave CW1 is constituted by the triangular wave TW, and the carrier wave CW2 is constituted by the antiphase triangular wave RTW.

  A list of carrier wave settings in the transition period according to the second control example shown in FIG. 19 is as shown in FIG.

  Referring to FIG. 20, with respect to carrier wave CW1, in switching mode 14 and switching mode 41, a downstream sawtooth wave is applied before and after switching. Therefore, similarly to FIG. 18, a downstream sawtooth wave STD is applied to carrier wave CW1. Thus, DT1 # = DT1 is set. Similarly, in switching mode 23 and switching mode 32, uplink sawtooth wave STU is applied to carrier wave CW1, and DT1 # = DT1 is set.

On the other hand, for the carrier wave CW1, in the switching mode 12, the switching mode 13, the switching mode 42, and the switching mode 43, the downstream sawtooth wave is applied before switching, while the upstream sawtooth wave is applied after switching, Opposite to FIG. 18, the anti-phase triangular wave RTW is applied. In this case, DT1 # = 1- (1-DT1) ² (that is, 1- (1-DT1) ^ 2) is set.

Further, in the switching mode 21, the switching mode 24, the switching mode 31, and the switching mode 34 in which an upstream sawtooth wave is applied before switching and a downstream sawtooth wave is applied after switching, it is the opposite of FIG. A triangular wave TW is applied. Then, DT1 # = (DT1) ² (that is, DT1 ^ 2) is set.

  Similarly, in the switching mode 24 and the switching mode 42, the carrier wave CW2 is composed of the downstream sawtooth wave STD in the transition period 205 and the switching mode 42 in which the downstream sawtooth wave is applied both before and after switching, and DT2 # = DT2. Also in the switching mode 13 and the switching mode 31 where the upstream sawtooth wave is applied before and after switching, the carrier wave CW2 is composed of the upstream sawtooth wave STU in the transition period 205, and DT2 # = DT2 is set. .

On the other hand, in the switching mode 21, the switching mode 23, the switching mode 41, and the switching mode 43 in which a downstream sawtooth wave is applied before switching, and an upstream sawtooth wave is applied after switching, it is opposite to FIG. In addition, the anti-phase triangular wave RTW is applied to the carrier wave CW2. Then, DT2 # = DTb = 1- (1-DT2) ² (that is, 1- (1-DT2) ^ 2) is set.

In addition, in the switching mode 12, the switching mode 14, the switching mode 32, and the switching mode 34 in which the upstream sawtooth wave is applied before switching, and the downstream sawtooth wave is applied after switching, the triangular wave TW is the carrier wave CW2. Applies to Then, DT2 # = DTa = (DT2) ² (that is, DT2 ^ 2) is set.

  Referring to FIG. 19 again, it can be understood that the inflection points of reactor currents IL1 and IL2 are generated twice in transition period 205 also in the second control example. Furthermore, in the second control example, from the phase relationship between the upstream sawtooth wave STU and the triangular wave TW and the phase relationship between the downstream sawtooth wave STD and the anti-phase triangular wave RTW, also at the start timing (time t1) of the transition period 205. Inflection points can be generated in the reactor currents IL1 and IL2.

  Similarly, at the end timing (time tz) of the transition period 205, the reactor current is determined from the phase relationship between the triangular wave TW, the downstream sawtooth wave STD, and the triangular wave TW, and the phase relationship between the reverse-phase triangular wave RTW and the upstream sawtooth wave STU. Inflection points can be generated in IL1 and IL2.

  As a result, by setting the transition period 205 according to the second control example, the number of inflection points of the reactor currents IL1 and IL2 can be increased, so that the average value of the reactor currents IL1 and IL2 is maintained, Variations in reactor currents IL1 and IL2 can be further suppressed.

[Other Modifications of First Embodiment]
(Operation modes other than parallel boost mode)
Regarding power converter 50 described in the first embodiment and its modification 1, as described in Patent Document 1 and other operation modes in which the mode of DC / DC conversion is different from the parallel boost mode. Can be applied.

FIG. 21 shows a list of a plurality of operation modes that the power converter 50 has.
Referring to FIG. 21, in addition to the parallel boost mode described in the first embodiment and its modification example 1 (hereinafter also referred to as PB mode), the operation mode is a series boost mode connected to Patent Document 1 ( Hereinafter, it further includes “single boosting mode by DC power supply B1 (hereinafter, aB mode)” and “single boosting mode by DC power supply B2 (hereinafter, bB mode)”.

  The SB mode is equivalent to the “series connection mode” in Patent Document 1. As described in Patent Document 1, by performing DC / DC conversion in a state where DC power sources B1 and B2 are connected in series, it is possible to improve power conversion efficiency due to a decrease in the step-up ratio. Since the details of the on / off control of the switching elements S1 to S4 can be executed in the same manner as the series connection mode in Patent Document 1, detailed description will not be repeated. Note that Patent Document 1 describes that the control operation in the series boost mode can be simplified by applying carrier phase control. However, instead of triangular wave carrier phase control, according to the first embodiment or a modification thereof. The same effect can be obtained even if PWM control is applied using a sawtooth wave.

  In the aB mode, DC / DC conversion (boost) is executed using only the DC power supply B1. In the aB mode, as long as the output voltage VH is controlled to be higher than the voltage V [2] of the DC power supply B2, the DC power supply B2 is maintained in a state of being electrically disconnected from the power line PL and is not used. The

  Similarly, in the bB mode, DC / DC conversion (boost) is executed using only the DC power supply B2. In the bB mode, as long as the output voltage VH is controlled to be higher than the voltage V [1] of the DC power supply B1, the DC power supply B1 is maintained in a state of being electrically disconnected from the power line PL and is not used. The

  In the PB mode, SB mode, aB mode, and bB mode, for example, the output of DC power supply B1 and / or B2 is controlled by sharing the control configuration of FIG. By executing periodic on / off control of switching elements S1 to S4 according to PWM control for output control, output voltage VH is controlled according to voltage command value VH *.

  As described above, in the power supply system according to the first embodiment and the modification thereof, in addition to the parallel boost mode, the SB mode (series boost mode) having excellent efficiency, and the aB mode and bB mode using only one power supply are provided. Since it can be selected, the utilization efficiency of the DC power supplies B1 and B2 can be increased.

  In the aB mode, the power converter 50 performs on / off control in common with the switching elements S3 and S4 as the lower arm. Furthermore, the switching elements S1 and S2 can also be controlled on and off in common as the upper arm.

  Therefore, in the aB mode, in the configuration of FIG. 5, the operation of the output control unit 510 is turned off, and the output control unit 500 calculates the duty ratio DT1 for VH control. Further, according to the control pulse signal SD1 by PWM control using the duty ratio DT1, the ON period and the OFF period (ON period of the switching elements S1 and S2) of the lower arm (switching elements S3 and S4) are repeatedly provided to output The voltage VH can be controlled according to the voltage command value VH *.

  Similarly in the bB mode, the output voltage VH is set to the voltage command value by using the duty ratio calculated by the output control unit 510 as the duty ratio DT2 for controlling the output of the DC power supply B2 in the configuration of FIG. It can be controlled according to VH *. Furthermore, in power converter 50, switching elements S2 and S3 can be commonly turned on / off as lower arms, and switching elements S1 and S4 can be commonly turned on / off as upper arms. Therefore, according to the control pulse signal SD2 by the PWM control using the duty ratio DT2, the ON period and the OFF period (the ON period of the switching elements S1 and S4) of the lower arm (switching elements S1 and S4) are repeatedly provided to output The voltage VH can be controlled according to the voltage command value VH *.

  Referring to FIG. 21 again, the plurality of operation modes further include a “direct connection mode” for fixing ON / OFF of switching elements S1 to S4. The direct connection mode includes “parallel direct connection mode (hereinafter referred to as PD mode)”, “series direct connection mode (hereinafter referred to as SD mode)”, “direct connection mode of DC power supply B1 (hereinafter referred to as aD mode)”, and “DC power supply” “B2 direct connection mode (hereinafter referred to as bD mode)”.

  In the PD mode, the switching elements S1, S2, and S4 are fixed on, while the switching element S3 is fixed off. Thereby, the state where DC power supplies B1 and B2 are connected in parallel to load 30 (between power lines PL and GL) is maintained. As a result, the output voltage VH is equivalent to the output voltages V [1] and V [2] (strictly, the higher voltage of V [1] and V [2]) of the DC power supplies B1 and B2. . Since the voltage difference between V [1] and V [2] causes a short circuit current in the DC power supplies B1 and B2, the PD mode can be applied only when the voltage difference is small.

  In the SD mode, the switching elements S2 and S4 are fixed off, while the switching elements S1 and S3 are fixed on. Thereby, the state where DC power supplies B1 and B2 are connected in series to load 30 (between power lines PL and GL) is maintained. As a result, the output voltage VH is equivalent to the sum of the output voltages V [1] and V [2] of the DC power supplies B1 and B2 (VH = V [1] + V [2]).

  In the aD mode, the switching elements S1 and S2 are fixed on, while the switching elements S3 and S4 are fixed off. As a result, the DC power supply B2 is disconnected from the power line PL, and the output voltage VH is equivalent to the voltage V [1] of the DC power supply B1 (VH = V [1]). In the aD mode, the DC power source B2 is not used because it is maintained in a state of being electrically disconnected from the power line PL. Note that when the aD mode is applied in a state of V [2]> V [1], a short-circuit current is generated from the DC power sources B1 to B2 via the switching element S2. For this reason, V [1]> V [2] is a necessary condition for applying the aD mode.

  Similarly, in the bD mode, the switching elements S1 and S4 are fixed on, while the switching elements S2 and S3 are fixed off. As a result, the DC power supply B1 is disconnected from the power line PL, and the output voltage VH is equivalent to the voltage V [2] of the DC power supply B2 (VH = V [2]). In the bD mode, the DC power supply B1 is not used because it is maintained in a state of being electrically disconnected from the power line PL. When the bD mode is applied in a state where V [1]> V [2], a short-circuit current is generated from the DC power supply B1 to B2 via the diode D2. For this reason, in order to apply the bD mode, V [2]> V [1] is a necessary condition.

  In each of the PD mode, SD mode, aD mode, and bD mode included in the direct connection mode, the output voltage VH is determined depending on the voltages V [1] and V [2] of the DC power supplies B1 and B2, and therefore directly It becomes impossible to control. For this reason, in each mode included in the direct connection mode, the output voltage VH cannot be set to a voltage suitable for the operation of the load 30, which may increase the power loss in the load 30.

  On the other hand, in the direct connection mode, since the switching elements S1 to S4 are not turned on / off, the power loss of the power converter 50 is significantly suppressed. Therefore, depending on the operating state of the load 30, the application of the direct connection mode increases the power loss reduction amount in the power converter 50 more than the power loss increase amount of the load 30, so that the power loss in the entire power supply system 5 A is reduced. There is a possibility that it can be suppressed.

  As described above, power supply system 5A according to the first embodiment and its modification 1 includes a plurality of operations shown in FIG. 21 including the parallel boost mode to which current phase control using a sawtooth wave as a carrier wave is applied. DC / DC conversion can be performed by appropriately switching the mode according to the operating state of the load 30 and / or the power converter 50. As a result, it is possible to increase the efficiency of the entire power supply system 5A by appropriately selecting other operation modes in addition to the all voltage series (SR) mode with small power loss.

(Circuit configuration arrangement of power converter)
FIG. 22 is a circuit diagram showing a modification of the circuit configuration of power converter 50 according to the first embodiment and its modification.

  Referring to FIG. 22, power converter 50 # has power supply PL and DC power supply B1 and reactor L1 not connected between node N2 and power line GL, as compared with power converter 50 shown in FIG. The difference is that they are connected in series between the nodes N2. Since other configurations of power converter 50 # are similar to those of power converter 50, description thereof will not be repeated.

  Power converter 50 # can execute the same DC / DC conversion as power converter 50 even if the upper arm and the lower arm with respect to DC power supply B1 are replaced because of the symmetry of the circuit compared to power converter 50. Is understood.

  Specifically, in power converter 50 #, it is necessary to control switching elements S1 and S2 to be the lower arm of DC power supply B1 and switching elements S3 and S4 to be the upper arm of DC power supply B1. As a result, in each operation mode of power converter 50 #, switching element S1 is on / off controlled in a pattern equivalent to switching element S4 of power converter 50, and switching element S2 is connected to switching element S3 of power converter 50. On / off control is performed with an equivalent pattern. Similarly, switching element S3 of power converter 50 # is on / off controlled in a pattern equivalent to switching element S2 of power converter 50, and switching element S4 is turned on / off in a pattern equivalent to switching element S1 of power converter 50. Be controlled.

  For example, in parallel boost mode of power converter 50 #, by turning on switching elements S1 and S2, a loop current path including DC power supply B1 and reactor L1 corresponding to current path 120 of FIG. Can be formed. Also, by turning on switching elements S3 and S4, a current path that connects DC power supply B1 and reactor L1 in series between power lines PL and GL, which corresponds to current path 121 in FIG. 3B, can be formed. it can.

  For DC power supply B2, as with power converter 50, current path 130 in FIG. 4A can be formed by turning on switching elements S2 and S3. Further, the current path 131 of FIG. 4B can be formed by turning on the switching elements S1 and S4.

  In this manner, DC / DC conversion can also be performed for power converter 50 # in the respective operation modes shown in FIG. 21, including parallel boost mode, similarly to power converter 50. In parallel boosting, the phase of the reactor current can be easily controlled by controlling the output from each DC power source by applying PWM control using a sawtooth wave according to the first embodiment and its modification 1. it can.

  As described above, in the power supply system according to the first embodiment and its modification example 1, when power converters 50 and 50 # are included, DC power supply B1 and reactor L1 are connected to power line PL with respect to switching elements S1 to S4. Alternatively, it is electrically connected in series between GL and node N2. On the other hand, DC power supply B2 and reactor L2 are electrically connected in series between nodes N1 and N3.

  In each of power converters 50 and 50 #, even if the order of connection of reactor L1 and DC power supply B1 is changed, an electrically equivalent circuit configuration is maintained. Similarly, even if the connection order of the reactor L2 and the DC power supply B2 is changed, an electrically equivalent circuit configuration is maintained.

[Embodiment 2]
In the second embodiment, an example will be described in which the PWM control described in the first embodiment is applied to a power converter having a configuration different from that of power converters 50 and 50 #.
(Circuit configuration of power converter)
FIG. 23 is a circuit diagram illustrating a configuration of power supply system 5B according to the second embodiment of the present invention.

  Compared with FIG. 1, power supply system 5 </ b> B according to the second embodiment is different from power supply system 5 </ b> A shown in FIG. 1 in that power converter 10 is provided instead of power converter 50. . The configuration of other parts of the power supply system 5B is the same as that of the power supply system 5A.

  That is, power supply system 5B is also configured to perform DC / DC conversion between power lines PL and GL connected to load 30 and DC power supplies B1 and B2.

  Similarly to the power converter 50, the power converter 10 controls the output voltage VH to the load 30 according to the voltage command value VH *.

  Referring to FIG. 23, power converter 10 is configured to control DC voltage (output voltage) VH between high voltage side power line PL and low voltage side power line GL.

  Power converter 10 includes switching elements Q1 to Q5 and reactors L1 and L2. Switching elements Q1 to Q5 can control on / off in response to control signals SQ1 to SQ5 from control device 40, respectively. Specifically, the switching elements Q1 to Q5 are turned on when the control signals SQ1 to SQ5 are at the H level, and can enter a current path. On the other hand, the switching elements Q1 to Q5 are turned off when the control signals SQ1 to SQ5 are at the L level, and the current path is cut off.

  Anti-parallel diodes D11 to D14 are arranged for switching elements Q1 to Q4, respectively. The diodes D11 to D14 are arranged so as to form a current path in a direction from the power line GL to the power line PL (a direction from the bottom to the top in the figure) during forward bias. On the other hand, the diodes D11 to D14 do not form the current path during reverse bias. Specifically, diode D11 is connected so that the direction from node N1 toward power line PL is the forward direction, and diode D12 is connected so that the direction from power line GL toward node N11 is the forward direction. Similarly, diode D13 is connected so that the direction from power line GL to node N12 is the forward direction, and diode D14 is connected so that the direction from node N12 to power line PL is the forward direction.

  Switching element Q1 is electrically connected between power line PL and node N11. Reactor L1 and DC power supply B1 are electrically connected in series between node N11 and power line GL. For example, reactor L1 is electrically connected between the positive terminal of DC power supply B1 and node N11, and the negative terminal of DC power supply B1 is electrically connected to power line GL. Switching element Q2 is electrically connected between node N11 and power line GL. Even if the connection order of the reactor L1 and the DC power supply B1 is changed, an electrically equivalent circuit configuration is maintained.

  Switching element Q3 is electrically connected between node N12 and power line GL. Switching element Q4 is electrically connected between power line PL and node N12. Switching element Q5 is electrically connected between nodes N11 and N12. Reactor L2 and DC power supply B2 are electrically connected in series between power line PL and node N12. For example, reactor L2 is electrically connected between the positive terminal of DC power supply B2 and power line PL, and the negative terminal of DC power supply B2 is electrically connected to node N12. Even if the connection order of reactor L2 and DC power supply B2 is changed, an electrically equivalent circuit configuration is maintained.

  In the configuration example of FIG. 23, the node N11 corresponds to a “first node”, and the node N12 corresponds to a “second node”. Further, switching element Q1 and diode D1 correspond to “first semiconductor element”, switching element Q2 and diode D2 correspond to “second semiconductor element”, and switching element Q3 and diode D3 correspond to “third semiconductor element”. Corresponds to "element". Further, the switching element Q4 and the diode D4 correspond to a “fourth semiconductor element”, and the switching element Q5 corresponds to a “fifth semiconductor element”. Reactors L1 and L2 correspond to “first reactor” and “second reactor”, respectively. In the example of FIG. 1, the formation and interruption of the current path can be controlled in each of the first to fifth semiconductor elements by the on / off control of the switching elements Q1 to Q5.

(Circuit operation in parallel boost mode)
The circuit operation and control in the parallel boost mode of power converter 10 to which PWM control equivalent to that in the first embodiment and its modification 1 is applied will be described in detail. As will be apparent from the following description, the power converter 10 has a characteristic that the loss in the switching element in the parallel boost mode is smaller than that of the power converter 50. The power converter 10 also has an operation mode other than the parallel boost mode, similar to the power converter 50, but in this embodiment, the PWM to which a sawtooth wave is applied according to the first embodiment or its modification example. A parallel boost mode in which control is preferably applied will be described.

  In the parallel boost mode, power converter 10 operates in such a manner that two boost chopper circuits are operated in parallel for each of DC power supplies B1 and B2. That is, power converter 10 performs DC / DC conversion in parallel between DC power supplies B1 and B2 and power lines PL and GL (load 30), similarly to the parallel boost mode in power converter 50. The output voltage VH is controlled according to the voltage command value VH *.

  Referring to FIG. 23 again, in power converter 10, the step-up chopper circuit formed for DC power supplies B1 and B2 differs between when switching element Q5 is turned on and when it is turned off. It is a feature.

  In power converter 10, when switching element Q5 is off, nodes N11 and N12 are electrically disconnected. An equivalent circuit of the power converter 10 at this time is shown in FIG.

  Referring to FIG. 24, when switching element Q5 is off, a boost chopper circuit is formed with DC element B2 and diode D12 as the lower arm and switching element Q1 and diode D11 as the upper arm with respect to DC power supply B1. . Similarly, a boost chopper circuit is formed for DC power supply B2 with switching element Q4 and diode D14 as the lower arm and switching element Q3 and diode D13 as the upper arm.

  FIG. 25 shows a current path when the lower arms of DC power supplies B1 and B2 are turned on in the equivalent circuit diagram shown in FIG.

  Referring to FIG. 25, when switching element Q2 is turned on, a current path 191 for storing energy in reactor L1 is formed by the output of DC power supply B1. Thereby, for DC power supply B1, a loop-shaped current path 191 including DC power supply B1 and reactor L1 is formed without including power lines PL and GL. That is, the current path 191 corresponds to the “first current path”.

  Similarly, by turning on switching element Q4, current path 192 for storing energy in reactor L2 is formed by the output of DC power supply B2. Thereby, for DC power supply B2, a loop-shaped current path 192 including DC power supply B2 and reactor L2 is formed without including power lines PL and GL. The current path 192 corresponds to a “third current path”.

  FIG. 26 shows a current path when the upper arms of DC power supplies B1 and B2 are turned on in the equivalent circuit diagram shown in FIG.

  Referring to FIG. 26, by turning off switching element Q2, current path 193 for outputting the stored energy of reactor L1 together with the energy from DC power supply B1 to power line PL via switching element Q1 or diode D11. Is formed. Here, the switching elements Q1 and Q2 are turned on and off in a complementary manner, so that the switching element Q1 is turned on during the off period of the switching element Q2. Switching element Q1 corresponds to the upper arm of the boost chopper circuit formed corresponding to DC power supply B1. Thereby, with respect to DC power supply B1, a current path 193 is formed in which DC power supply B1 and reactor L1 are connected in series between power lines PL and GL. That is, the current path 193 corresponds to a “second current path”.

  Similarly, by turning off switching element Q4, current path 194 for outputting the stored energy of reactor L2 together with the energy from DC power supply B2 to power line PL is formed via switching element Q3 or diode D13. . By switching on and off switching elements Q3 and Q4 in a complementary manner, switching element Q3 is turned on during the off period of switching element Q4. Switching element Q3 corresponds to the upper arm of the step-up chopper circuit formed corresponding to DC power supply B2. Thereby, for DC power supply B2, a current path 194 is formed in which DC power supply B2 and reactor L2 are connected in series between power lines PL and GL. That is, the current path 194 corresponds to a “fourth current path”.

  As understood from FIGS. 25 and 26, by alternately forming current paths 191 and 193, DC / DC conversion between DC power supply B1 and power lines PL and GL is performed. Similarly, DC / DC conversion between DC power supply B2 and power lines PL and GL is executed by alternately forming current paths 192 and 194.

  Hereinafter, the upper arm of the boost chopper circuit formed corresponding to the DC power supply B1 is also referred to as “B1U arm”, and the lower arm is referred to as “B1L arm”. Similarly, the upper arm of the step-up chopper circuit formed corresponding to the DC power supply B2 is also referred to as “B2U arm”, and the lower arm is also referred to as “B2L arm”.

  As can be understood from FIG. 25, when the current path from the node N12 to N11 is formed when the B1L arm and the B2L arm are formed, a short circuit path from the power line PL to the power line GL is formed. It is necessary to interrupt the current path. Similarly, as can be understood from FIG. 26, when the current path from the node N11 to N12 is formed when the B1U arm and the B2U arm are formed, a short-circuit path from the power line PL to the power line GL is formed. It is necessary to interrupt the current path. Therefore, the formation of the short-circuit path can be avoided by turning off the switching element Q5 in each of the formation of the B1L arm and the B2L arm and the formation of the B1U arm and the B2U arm.

  On the other hand, in power converter 10, nodes N11 and N12 are electrically connected when switching element Q5 is on. An equivalent circuit of the power converter 10 at this time is shown in FIG.

  Referring to FIG. 27, regarding DC power supply B1, since node N12 is electrically connected to node N11 by switching element Q5, switching element Q3 connected between node N12 and power line GL is connected to DC power supply B1. A step-up chopper circuit can be formed as the lower arm (B1L arm). Similarly, a step-up chopper circuit can be formed using switching element Q4 electrically connected between node N12 and power line PL as the upper arm (B1U arm) of DC power supply B1.

  For DC power supply B2, a step-up chopper circuit is formed in which switching element Q1 connected between node N11 and power line PL is the lower arm (B2L arm) and switching element Q2 is the upper arm (B2U arm). can do.

  FIG. 28 shows a current path when the lower arms of DC power supplies B1 and B2 are turned on in the equivalent circuit diagram shown in FIG.

  Referring to FIG. 28A, by turning on switching elements Q3 and Q5, current path 195 for storing energy in reactor L1 is formed by the output of DC power supply B1. On the other hand, as shown in FIG. 28B, by turning on the switching elements Q1 and Q5, a current path 196 for storing energy in the reactor L2 is formed by the output of the DC power supply B2.

  FIG. 29 shows a current path when the upper arms of DC power supplies B1 and B2 are turned on in the equivalent circuit diagram shown in FIG.

  Referring to FIG. 29 (a), with respect to DC power supply B1, switching element Q3 is turned off while switching element Q5 is turned on, whereby the stored energy of reactor L1 is changed to DC via switching element Q4 or diode D14. A current path 197 for outputting to power line PL together with energy from power supply B1 is formed. As described above, switching elements Q3 and Q4 are complementarily turned on and off, so that B1L arm can be formed by switching element Q3 and B1U arm can be formed by switching element Q4.

  Referring to FIG. 29B, with respect to DC power supply B2, by turning off switching element Q1 while switching element Q5 is on, the stored energy of reactor L2 is reduced via switching element Q2 or diode D12. A current path 198 for outputting to power line PL together with energy from DC power supply B2 is formed. As described above, switching elements Q1 and Q2 are turned on and off in a complementary manner, so that a B2L arm can be formed by switching element Q1 and a B2U arm can be formed by switching element Q2.

  FIG. 30 shows a correspondence relationship between each arm of the step-up chopper circuit formed when switching element Q5 is turned off and turned on and the switching element is turned on / off.

  Referring to FIG. 30, each arm in the step-up chopper circuit formed when switching element Q5 is turned off (FIGS. 24 to 26) is referred to as a “first arm”, and when switching element Q5 is turned on (FIGS. 27 to 26). Each arm of the step-up chopper circuit formed in 29) will be referred to as a “second arm”.

  When the switching element Q5 is turned off, that is, when the first arm is formed, the B1L arm is turned on when the switching element Q2 is turned on with respect to the DC power source B1, while the switching element Q1 is turned on (switching element Q1). The B1U arm is turned on by turning off Q2. For DC power supply B2, the B2L arm is turned on when switching element Q4 is turned on, while the B2U arm is turned on when switching element Q3 is turned on (switching element Q4 is turned off).

  On the other hand, when the switching element Q5 is turned on, that is, when the second arm is formed, the B1L arm is turned on when the switching element Q3 is turned on, while the switching element Q4 is turned on. The B1U arm is turned on by (off of the switching element Q3). For DC power supply B2, the B2L arm is turned on when switching element Q1 is turned on, while the B2U arm is turned on when switching element Q2 is turned on (switching element Q1 is turned off).

  As described above, in each of the first arm and the second arm, the switching elements Q1 and Q2 are complementarily turned on and off, and the switching elements Q3 and Q4 are complementarily turned on and off, so that each of the DC power sources B1 and B2 In contrast, the upper arm and the lower arm can be controlled to be turned on and off alternately.

  In parallel boost mode of power converter 10 according to the second embodiment, DC / DC conversion is executed using both the first arm and the second arm shown in FIG. However, as shown in FIG. 30, each of the switching elements Q1 to Q5 operates as a first arm for one of the DC power supplies B1 and B2, and as a second arm for the other of the DC power supplies B1 and B2. Operate. It should be noted that the period during which the second arm can be applied is limited by such interference between the first arm and the second arm.

  Specifically, when the second arm is turned on for one of the DC power sources B1 and B2, the first arm on the opposite side to the other side of the DC power sources B1 and B2 is turned on. For example, when switching elements Q3 and Q5 are turned on and the B1L arm of the second arm is turned on (FIG. 28 (a)), in response to the switching element Q3 being turned on, The B2U arm of the first arm is turned on. On the contrary, when the B1U arm of the second arm is turned on by turning on the switching elements Q4 and Q5 (FIG. 29 (a)), the B2L of the first arm is connected to the DC power source B2 as in FIG. The arm turns on.

  As can be understood from FIGS. 28A and 28B, when both the B1L arm and the B2L arm are turned on when the second arm is formed, the switching elements Q1, Q3, and Q5 are turned on. As a result, a short circuit path is formed between the power lines PL and GL. For this reason, as described above, when both the B1L arm and the B2L arm are turned on, it is necessary to apply the first arm (FIGS. 25 and 26) by turning off the switching element Q5.

  Similarly, as understood from FIGS. 29A and 29B, when both the B1U arm and the B2U arm are turned on when the second arm is formed, the switching elements Q4, Q5 in the on state are turned on. A short-circuit path is formed between the power lines PL and GL via Q2. For this reason, as described above, when both the B1L arm and the B2L arm are turned on, it is necessary to apply the first arm (FIGS. 25 and 26) by turning off the switching element Q5.

  Therefore, the period during which the second arm can be used is limited to a period in which the command to the upper arm (on / off) and the command to the lower arm (on / off) are different between the DC power supplies B1 and B2. That is, while the upper arm on is instructed to the DC power source B1, the lower arm on is instructed to the DC power source B2, or the lower arm on is instructed to the DC power source B1. The second arm can be used only during the period when the upper arm on is commanded to the power supply B2.

  FIG. 31 shows a gate logical expression for on / off control of each of switching elements Q1 to Q5 in parallel boost mode of power converter 10.

  In the parallel boost mode of power converter 10, switching element Q2 is on / off controlled in response to control pulse signal SD1, and switching element Q1 is turned on / off in response to control pulse signal / SD1. Further, switching element Q4 is on / off controlled according to control pulse signal SD2, and switching element Q3 is turned on / off in response to control pulse signal / SD2. Further, the switching element Q5 is ON / OFF controlled according to the exclusive OR (XOR) of the control pulse signals SD1 and SD2.

  When the logic levels of the control pulse signals SD1 and SD2 are equal (that is, SD1 = SD2 = H level or SD1 = SD2 = L level), the switching element Q5 is turned off. That is, when the on / off states of switching elements Q2, Q4 are the same, switching element Q5 is turned off. At this time, a boost chopper circuit using the first arm is configured for each of the DC power supplies B1 and B2.

  Therefore, when the first arm is used, it is understood that the logic levels of control pulse signals SD1 and SD2 are equal, so that switching elements Q2 and Q4 are turned on / off in common. Further, switching elements Q1, Q3 are also turned on / off in common. Furthermore, the pair of switching elements Q1 and Q3 and the pair of switching elements Q2 and Q4 are turned on and off in a complementary manner. Therefore, complementary ON / OFF of switching elements Q1 and Q2 and complementary ON / OFF of switching elements Q3 and Q4 are ensured.

  On the other hand, when the logic levels of control pulse signals SD1 and SD2 are different (that is, SD1 = H level, SD2 = L level, or SD1 = L level, SD2 = H level), switching element Q5 is turned on. . That is, when the on / off states of switching elements Q2, Q4 are different, switching element Q5 is turned on. At this time, a boost chopper circuit using the second arm is configured for each of the DC power supplies B1 and B2.

  Therefore, when the second arm is used, switching elements Q2, Q3 are turned on / off in common, and switching elements Q1, Q4 are turned on / off in common. The pair of switching elements Q1 and Q3 and the pair of switching elements Q2 and Q4 are turned on and off in a complementary manner. Therefore, complementary on / off of switching elements Q1 and Q2 and complementary on / off of switching elements Q3 and Q4 are ensured even when the second arm is used.

  As described above, according to the logical operation expression shown in FIG. 31, the switching elements Q1 to Q5 are controlled to be turned on / off according to the control pulse signals SD1 and SD2, so that the boost chopper circuit using the first arm and the second arm The DC / DC conversion in the parallel boost mode can be executed while automatically selecting the boost chopper circuit to be used. In particular, the switching of the first arm and the second arm while avoiding the formation of a short circuit path between the power lines PL and GL by controlling the formation / cutoff of the current path between the nodes N11 and N12 by the switching element Q5. Can do.

  Control pulse signals SD1 (/ SD1) and SD2 (/ SD2) can be generated by the control configuration shown in FIG. 5 as in the parallel boost mode of power converter 50. Further, PWM control unit 550 (FIG. 5) generates control signals SQ1 to SQ5 in accordance with the gate logical expression shown in FIG.

  FIG. 32 is a waveform diagram for explaining a comparative example of the control operation in the parallel connection mode of the power converter 10. In FIG. 32, PWM control using a carrier wave constituted by a triangular wave will be described as a comparative example, similar to FIG. 6 in the first embodiment.

  Referring to FIG. 32, for DC power supply B1, control pulse signal SD1 (/ SD1) is generated by PWM control based on voltage comparison between carrier wave CW1 and duty ratio DT1. As shown in the gate logical expression of FIG. 31, on / off of switching elements Q1, Q2 is controlled based on control pulse signals SD1, / SD1 for output control of DC power supply B1.

  Similarly, control pulse signal SD2 (/ SD2) is generated for DC power supply B2 by PWM control based on voltage comparison between duty ratio DT2 and carrier wave CW2. As shown in the gate logical expression of FIG. 31, on / off of switching elements Q3 and Q4 is controlled based on control pulse signals SD2 and / SD2 for output control of DC power supply B2.

  Switching element Q5 is turned on in a period in which reactor current IL2 increases while reactor current IL2 decreases, and in a period in which reactor current IL2 increases while reactor current IL1 decreases. That is, in switching element Q5, while current path 191 is formed for reactor current IL1, a period during which current path 194 is formed for reactor current IL2, and while current path 193 is formed for reactor current IL1, The reactor current IL2 is turned on during the period in which the current path 192 is formed.

  Control signals SQ1 to SQ5 are generated according to control pulse signals SD1 (/ SD1) and SD2 (/ SD2) obtained by the PWM control in accordance with the gate logical expression shown in FIG. Here, depending on the combination of the H / L level of the control pulse signal SD1 and the H / L level of the control pulse signal SD2, the on / off combination (switching pattern) of the switching elements Q1 to Q5 is 4 shown in FIG. Limited to the street.

  FIG. 33 is a chart showing a list of switching patterns of switching elements Q1 to Q5 in the parallel boost mode.

  Referring to FIG. 32, SD1 = SD2 = H level between times t0 and t1. At this time, as shown in FIG. 33, the control signal SQ1 = SQ3 = SQ5 = L level, while SQ2 = SQ4 = H level. Therefore, while switching element Q5 is turned off and the step-up chopper circuit using the first arm is formed, switching elements Q1 and Q3 are turned off while switching elements Q2 and Q4 are turned on.

  At this time, as understood from FIG. 30, the B1L arm and the B2L arm of the first arm are turned on. That is, lower arm on is commanded to each of DC power supplies B1 and B2. Therefore, both reactor currents IL1 and IL2 rise between times t0 and t1. As is clear from the circuit configuration of power converter 10, reactor current IL1 corresponds to current I [1] of DC power supply B1, and reactor current IL2 corresponds to current I [2] of DC power supply B1.

  Referring again to FIG. 32, since control pulse signal SD2 changes from the H level to the L level at time t1, SD1 = H level and SD2 = L level between times t1 and t2. At this time, as shown in FIG. 15, the control signal SQ2 = SQ3 = SQ5 = H level, while SQ1 = SQ4 = L level. Therefore, while switching element Q5 is turned on and a boost chopper circuit using the second arm is formed, switching elements Q2 and Q3 are turned on, while switching elements Q1 and Q4 are turned off.

  At this time, as understood from FIG. 30, the B1L arm and the B2U arm among the first arms are turned on. That is, the lower arm on is commanded to the DC power supply B1, while the upper arm on is commanded to the DC power supply B2. Accordingly, between times t1 and t2, reactor current IL1 increases while reactor current IL2 decreases.

  Referring to FIG. 32 again, since control pulse signal SD1 changes from the H level to the L level at time t2, SD1 = SD2 = L level between times t2 and t3. At this time, as shown in FIG. 33, the control signal SQ2 = SQ4 = SQ5 = L level, while SQ1 = SQ3 = H level. Therefore, while switching element Q5 is turned off and a boost chopper circuit using the first arm is formed, switching elements Q1 and Q3 are turned on, while switching elements Q2 and Q4 are turned off.

  At this time, as understood from FIG. 30, the B1U arm and the B2U arm among the first arms are turned on. That is, upper arm on is commanded to each of DC power supplies B1 and B2. Accordingly, both reactor currents IL1 and IL2 decrease between times t2 and t3.

  Referring again to FIG. 32, since control pulse signal SD1 changes from the L level to the H level at time t3, SD1 = H level and SD2 = L level between times t3 and t4. Therefore, the switching elements Q1 to Q5 are controlled so that the reactor current IL1 increases while the reactor current IL2 decreases while the first arm is used by reproducing the switching pattern between times t0 and t1. Is done.

  In the operation example of FIG. 32, since DT1> DT2, there is no period in which SD1 = L level and SD2 = H level, contrary to the time t0 to t1, but in this period, 33, the control signal SQ1 = SQ4 = SQ5 = H level, while SQ2 = SQ3 = L level. Therefore, while switching element Q5 is turned on and the step-up chopper circuit using the second arm is formed, switching elements Q1 and Q4 are turned on, while switching elements Q2 and Q3 are turned off.

  At this time, as understood from FIG. 30, the B1U arm and the B2L arm of the second arm are turned on. That is, the lower arm on is commanded to the DC power source B2, while the upper arm on is commanded to the DC power source B1. Therefore, it is understood that the switching elements Q1 to Q5 are controlled so that the reactor current IL1 increases while the reactor current IL1 decreases during the period.

  After time t4 in FIG. 32, switching elements Q1-Q5 can be similarly controlled according to the switching pattern shown in FIG. 33 by PWM control according to duty ratios DT1, DT2.

  Thus, according to power converter 10 according to the second embodiment, in the parallel boost (PB) mode, the gate logic shown in FIG. 31 according to output control duty ratios DT1 and DT2 of DC power supplies B1 and B2. Switching elements Q1-Q5 are on / off controlled according to the equation. Thus, the DC power supplies B1 and B2 are connected to the power lines PL and GL while automatically switching between the period in which the boost chopper circuit using the first arm is formed and the period in which the boost chopper circuit using the second arm is formed. DC / DC conversion can be performed in parallel.

  In particular, in the PB mode of the power converter 10, similarly to the power converter 50, the power distribution between the DC power sources B <b> 1 and B <b> 2 can be controlled and the output voltage VH can be controlled to the voltage command value VH *.

(Power loss of power converter in parallel boost mode)
Next, the power loss reduction effect of the power converter 10 in the parallel boost mode will be described in detail.

  The power converter 10 has two boost chopper circuits connected in parallel as shown in FIG. 29 when the switching element Q5 is OFF, that is, when the boost chopper circuit using the first arm is formed. Circuit configuration. It is understood that the power loss due to the switching elements Q1 to Q5 at this time is equivalent to the power loss for two boost chopper circuits.

  On the other hand, in the power converter 50 (FIG. 1), DC / DC conversion currents of two DC power sources are superimposed on some switching elements in the parallel boost (PB) mode similar to the parallel connection mode of Patent Document 1. Therefore, there is a concern that the conduction loss increases. That is, in the parallel connection mode of the power converter 50, the power loss in the switching element may be higher than the power loss of two boost chopper circuits.

  On the other hand, in the power converter 10, as described below, the conduction loss of the switching element can be reduced by providing a period in which the step-up chopper circuit using the second arm described above is formed. it can.

  Referring to FIG. 33 again, when switching element Q5 is turned on in power converter 10, that is, during the period when the boost chopper circuit using the second arm is formed, switching elements Q2, Q3 and Q5 are turned on. There are only two patterns, a pattern in which Q1 and Q4 are off, and a pattern in which switching elements Q1, Q4, and Q5 are on (Q2 and Q3 are off). That is, when the second arm is used, a different arm is turned on between the DC power supplies B1 and B2.

  As understood from FIG. 27, when switching elements Q1, Q4, and Q5 are turned on (when the second arm is used), switching elements Q1 and Q4 use switching element Q5 as an upper arm of DC power supply B1. Via, it becomes the structure electrically connected in parallel between the node N11 and the power line PL. Furthermore, switching elements Q1 and Q4 are electrically connected in parallel between the positive electrode terminal and the negative electrode terminal of DC power supply B2 via switching element Q5 and reactor L2 as the lower arm of DC power supply B2.

  When switching elements Q2, Q3, and Q5 are turned on, switching elements Q2 and Q3 are electrically connected between node N2 and power line GL via switching element Q5 as the upper arm of DC power supply B2. Are connected in parallel. Furthermore, switching elements Q2 and Q3 are electrically connected in parallel between the positive electrode terminal and the negative electrode terminal of DC power supply B1 via switching element Q5 and reactor L1 as the lower arm of DC power supply B1.

  Therefore, the switching elements Q1 to Q5 are semiconductor elements having linear characteristics, for example, field effect transistors or Schottky barrier diodes having a rising voltage of 0 and a forward current-voltage characteristic in an on state being linear. When configured, a current path by two switching elements exists in parallel for each of the B1L arm, the B1U arm, the B2L arm, and the B2U arm. As a result, due to the shunt effect in the parallel circuit, the passing current of each switching element is compared with that when forming the step-up chopper circuit having the first arm formation, that is, when each arm is composed of one switching element. Reduce. Thereby, the conduction loss of the switching element depending on the amount of current can be reduced.

  On the other hand, when the switching elements Q1 to Q5 are composed of semiconductor elements having nonlinear characteristics such as diodes or IGBTs (Insulated Gate Bipolar Transistors), the conduction loss can be reduced by a mechanism not based on a simple shunt effect. Realized. Below, the mechanism is demonstrated in detail.

  As described above, when the second arm is used, the switching elements Q1, Q4, and Q5 are turned on (Q2 and Q3 are turned off), and the switching elements Q2, Q3, and Q5 are turned on (Q1, Q4 are turned off). There are only two patterns. Since the phenomenon that occurs in any of the above patterns is the same due to the symmetry of the circuit configuration of the power converter 10, in the following, the pattern in which the switching elements Q2, Q3, and Q5 are turned on (Q1 and Q4 are turned off), that is, The operation when the B1L arm and the B2U arm are turned on will be described.

  First, for comparison, consider a case where the B1L arm and the B2U arm are turned on in the boost chopper circuit using the first arm. In this case, switching elements Q1, Q3, and Q5 are turned off, while switching elements Q2 and Q3 are turned on. FIG. 34 shows an equivalent circuit diagram at this time.

  Referring to FIG. 34, switching elements Q2 and Q3 are controlled to a state in which a current path can be formed by setting corresponding control signals SQ2 and SQ3 to the H level. That is, the switching elements Q2 and Q3 are equivalent to a state where diodes are connected in parallel in both directions. On the other hand, since switching element Q5 is turned off, the current path between nodes N11 and N12 is blocked.

FIG. 35 is an enlarged view of a portion surrounded by a dotted line in FIG.
Referring to FIG. 35, in response to turning on of the B1L arm by switching element Q2, reactor current IL1 passing through reactor L1 from DC power supply B1 is formed by switching element Q2, and is a current path from node N11 to power line GL. Flowing.

  Further, in response to turning on of the B2U arm by switching element Q3, reactor current IL2 passing through reactor L2 from DC power supply B2 flows through a current path from power line GL to node N12 formed by switching element Q3. Thus, when the B1L arm and the B2U arm are turned on when the first arm is formed (when Q5 is off), reactor current IL1 flows through switching element Q2, and current IL2 flows through switching element Q3.

  FIG. 36 is an equivalent circuit diagram when the B1L arm and the B2U arm are turned on in the boost chopper circuit using the second arm.

  Referring to FIG. 36, when the second arm is used, control signals SQ2, SQ3, and SQ5 are set to the H level, so that each of switching elements Q2, Q3, and Q5 has a bidirectional current path. It is possible to form, that is, a state where diodes are connected in parallel in both directions.

FIG. 37 is an equivalent circuit diagram of a portion surrounded by a dotted line in FIG.
Referring to FIG. 37, when the second arm is used, unlike FIG. 35, a current path can be formed between nodes N11 and N12 also by switching element Q5. Therefore, the paths of reactor currents IL1 and IL2 change depending on the potential relationship between nodes N11 and N12.

  As shown in FIGS. 35 and 37, the switching element (for example, IGBT) having nonlinear characteristics has characteristics equivalent to those of the diode in the on state. As is generally known, a diode has a non-linear current-voltage characteristic, and in order to make a transition to a conducting state in which a current flows, it is necessary to apply a forward voltage higher than the rising voltage.

  Further, it is known that a diode has a low sensitivity to an increase in forward voltage with respect to an increase in current, and a large current is required to generate a forward voltage more than twice the rising voltage. That is, a forward voltage having substantially the same magnitude is generated in each of the diodes that are in a conductive state and are energized.

  Due to the above property of the diode, in the equivalent circuit shown in FIG. 37, a state (conductive state) in which current flows through all of the switching elements Q2, Q3, and Q5 connected in a loop shape does not occur. This is because the Kirchhoff voltage law does not hold regardless of the direction of each voltage if three substantially equal voltages form a loop-like closed circuit.

  Therefore, in the equivalent circuit shown in FIG. 37, only at least two of the switching elements Q2, Q3, and Q5 can be in a conductive state. Therefore, in the equivalent circuit of FIG. 37, reduction of conduction loss due to a simple shunt effect between the switching elements Q2, Q3, and Q5 cannot be expected.

  However, since the conduction loss differs depending on the combination of the conduction patterns of the switching elements Q2, Q3, and Q5, the conduction loss can be reduced by selecting the conduction path according to the combination with the lowest loss. In particular, in power converter 10, the selection of the conduction path for reducing the conduction loss as described above is performed by turning on all of switching elements Q2, Q3, and Q5 without performing control using a sensor or the like. Only, the conduction path that minimizes the loss is automatically selected. Hereinafter, this loss reduction mechanism will be described in more detail.

  First, in power converter 10, the combinations of directions of reactor currents IL1 and IL2 are classified into four types as shown in FIG.

  Referring to FIG. 38, based on the positive / negative combination of reactor currents IL1 and IL2, the operation region of power converter 10 is a region where both DC power supplies B1 and B2 are in a power running operation (IL1> 0, IL2> 0). A region where the DC power source B1 performs a regenerative operation while the DC power source B2 performs a powering operation (IL1 <0, IL2> 0) and a region where both the DC power sources B1 and B2 perform a regenerative operation (IL1 <0, IL2 < 0) and a region (IL1> 0, IL2 <0) in which the DC power supply B1 performs a power running operation while the DC power supply B2 performs a regenerative operation.

  First, the operation of power converter 10 in the case where both DC power supplies B1 and B2 perform a power running operation, that is, the first quadrant in FIG. 38 will be described. A waveform example of reactor currents IL1 and IL2 in this case is shown in FIG.

  Referring to FIG. 39, reactor currents IL1 and IL2 are positive (IL1> 0, IL2> 0), and B1L arm is turned on (SD1 = H level), while B2U arm is turned off (SD2 (= L level) shows a current waveform in a period T0. That is, in the period T0, since the control pulse signal SD1 = H level and SD2 = L level, the switching elements Q2, Q3, Q5 are turned on.

  Therefore, in period T0, reactor current IL1 increases while reactor current IL2 decreases. The period T0 is divided into a period Tα where IL2> IL1 and a period Tβ where IL1> IL2 with the time ty at which the magnitudes of the reactor currents IL1 and IL2 are reversed as boundaries.

  As described above, even when switching elements Q2, Q3, and Q5 are turned on, not all of switching elements Q2, Q3, and Q5 are simultaneously turned on. Therefore, the current path that can be formed by the equivalent circuit of FIG. 37 is one of the three types of (a) to (c) of FIG.

  Referring to FIG. 40A, when switching elements Q2 and Q3 are turned on, current path 121 is formed. Current path 121 includes a current path through which reactor current IL1 flows through switching element Q2 and a current path through which reactor current IL2 flows through switching element Q3. As a result, the sum Pls1 of conduction losses by the switching elements Q2, Q3, Q5 is expressed by the following equation (5).

Pls1 = Vfe × (| IL1 | + | IL2 |) (5)
In Formula (5), Vfe is the forward voltage of each diode corresponding to the switching element in the on state. Vfe can be regarded as a positive constant value.

  Referring to FIG. 40B, when switching elements Q2 and Q5 are turned on, current path 122 is formed. Current path 122 includes a current path through which current (IL1-IL2) flows through switching element Q2, and a current path through which reactor current IL2 flows through switching element Q5. The conduction loss Pls2 due to the switching elements Q2, Q3, Q5 at this time is expressed by the following equation (6).

Pls2 = Vfe × (| IL2 | + | IL1-IL2 |) (6)
Referring to FIG. 40C, when switching elements Q3 and Q5 are turned on, current path 123 is formed. Current path 123 includes a current path through which current (IL2-IL1) flows through switching element Q3 and a current path through which reactor current IL1 flows through switching element Q5. The conduction loss Pls3 due to the switching elements Q2, Q3, and Q5 at this time is expressed by the following equation (7).

Pls3 = Vfe × (| IL1 | + | IL2-IL1 |) (7)
The current path 121 shown in FIG. 40A is the same as the current path when the B1L arm and the B2U arm are turned on in the step-up chopper circuit using the first arm shown in FIG. Therefore, the conduction loss in FIG. 40A is equivalent to that at the time of forming the first arm.

  FIG. 41 is a waveform diagram showing transition of conduction losses Pls1 to Pls3 in each of the current paths 121 to 123 shown in FIGS. 40 (a) to 40 (c).

  Referring to FIG. 41, as reactor currents IL1 and IL2 change as shown in FIG. 39, conduction losses Pls1 to Pls3 are expressed in accordance with changes in IL1 and IL2 that are both positive (5) ) To (7).

  In the period Tα where IL2> IL1, the conduction loss Pls3 when the current path 123 (FIG. 40C) is formed is equal to the current path 121, as is understood from the comparison of the expressions (5) to (7). , 122 becomes smaller than the conduction loss Pls1, Pls2.

  On the other hand, in the period Tβ where IL1> IL2, the conduction loss Pls2 due to the current path 122 (FIG. 40B) is smaller than the conduction losses Pls1 and Pls3 when the current paths 121 and 123 are formed.

  Here, a current path that can be formed in the period Tα (IL1 <IL2) will be considered. First, in the case of the current path 121 shown in FIG. 40A, the sum of the forward voltages of the switching elements Q2 and Q5 is applied to the switching element Q5. Since the sum of the forward voltages exceeds the rising voltage of the switching element Q5, this phenomenon contradicts the phenomenon in which the switching element Q3 is not conducting. Therefore, the current path 121 shown in FIG. 40A is not formed in the period Tα.

  In the case of the current path 122 shown in FIG. 40B, the current flowing through the switching element Q2 is in the opposite direction to the illustrated direction, and the sum of the forward voltages of the switching elements Q2 and Q5 is applied to the switching element Q3. Will be applied. The sum of the forward voltages exceeds the rising voltage of the switching element Q3. Therefore, the current path 122 in which the switching element Q3 is non-conductive is not formed in the period Tα.

  On the other hand, in the case of the current path 123 shown in FIG. 40C, the voltage applied to the switching element Q2 is the difference between the forward voltages of the switching elements Q3 and Q5, and is almost zero. This phenomenon coincides with an event in which the switching element Q2 is not conducting. In other words, in the period Tα, the current path 123 shown in FIG. 40C is always formed in the equivalent circuit shown in FIG. As shown in FIG. 41, the conduction loss Pls3 due to the current path 123 is minimum in the period Tα.

  Next, a current path that can be formed in the period Tβ (IL1> IL2) is considered. First, in the case of the current path 121 shown in FIG. 40A, the sum of the forward voltages of the switching elements Q2 and Q3 is applied to the switching element Q5. Therefore, the current path 122 in which the switching element Q5 is non-conductive is not formed in the period Tβ.

  In the current path 123 shown in FIG. 40C, the current flowing through the switching element Q3 is in the direction opposite to the illustrated direction, and the sum of the forward voltages of the switching elements Q3 and Q5 is applied to the switching element Q2. become. The sum of the forward voltages exceeds the rising voltage of the switching element Q2. Therefore, in the period Tβ, the current path 123 in which the switching element Q2 is non-conductive is not formed.

  On the other hand, in the case of the current path 122 shown in FIG. 40B, the voltage applied to the switching element Q3 is the difference between the forward voltages of the switching elements Q5 and Q2, and is almost zero. This event coincides with an event in which the switching element Q3 is not conducting. In other words, in the period Tβ, the current path 122 shown in FIG. 40B is always formed in the equivalent circuit shown in FIG. As shown in FIG. 41, the conduction loss Pls2 due to the current path 122 is minimum in the period Tβ.

  As described above, it is understood that the current path formed by the switching elements Q2, Q3, and Q5 is automatically selected at the time ty when the magnitudes of the reactor currents IL1 and IL2 are reversed. Furthermore, the automatically selected current path has the minimum conduction loss in the switching elements Q2, Q3, and Q5 that are turned on among the three current paths shown in FIGS. 40 (a) to 40 (c). Become.

  FIG. 42 is a circuit diagram for explaining a current path formed in period Tα in FIGS. 39 and 41 in power converter 10.

  Referring to FIG. 42, in period Tα, current path 123 shown in FIG. 40C is formed for switching elements Q2, Q3, Q5 that are turned on. That is, the switching element Q2 is turned on but does not pass current. On the other hand, reactor current IL1 passes through switching element Q5, while current (IL1-IL2) passes through switching element Q3. Thus, also in power converter 10 shown in FIG. 23, reactor currents IL1 and IL2 are supplied to a part of switching elements Q1 to Q5 (here, Q3) in accordance with on / off control of switching elements Q1 to Q5. Both flow. Note that both reactor currents IL1 and IL2 can also flow through switching elements Q1 and Q5.

  As shown in FIG. 39, in period Tα, reactor current IL2 decreases while reactor current IL1 increases. Therefore, the current (IL2-IL1) flowing through the switching element Q3 gradually decreases. Then, when IL1 = IL2 at time ty (FIG. 39), the current of switching element Q3 becomes zero. As a result, a current path 122 shown in FIG. 40B where no current flows through the switching element Q3 is formed.

  FIG. 43 shows current paths formed in period Tβ in FIGS. 39 and 41 in power converter 10.

  Referring to FIG. 43, in period Tβ after time ty, switching element Q3 passes reactor current IL2, while switching element Q3 maintains a current of 0, that is, in FIG. The potential of the node N12 changes so that the circuit state is maintained.

  Such a potential change at the node N12 occurs when the reactor current IL1 is shunted to the switching elements Q2 and Q3 and the shunt ratio is changed. That is, in the period Tβ, the switching element Q3 cancels the shunt current of the reactor current IL1 and the reactor current IL2, so that the passing current becomes zero.

  In other words, in the period Tβ, the shunt ratio of the reactor current IL1 automatically changes according to the reactor current IL2 so that the state where the current of the switching element Q3 becomes zero is maintained. Thereby, in the period Tβ, the current path 122 shown in FIG. 40B is continuously formed.

  In the state of FIG. 43 (period Tβ), no conduction loss occurs in the switching element Q3. Further, as shown in the equation (6), the switching element Q5 has a conduction loss corresponding to the reactor current IL2. On the other hand, the reactor element IL1 is shunted to the switching element Q2, thereby causing the switching element Q2 to have a conduction loss. Also, only conduction loss according to | IL1-IL2 | occurs.

  On the other hand, the conduction loss Pls0 of the switching elements Q2 and Q4 when the BIL arm and the B2U arm are turned on in the step-up chopper circuit using the first arm (FIG. 34) is expressed by the following equations (5) to (7): It is shown by Formula (8).

Pls0 = Vfe × (| IL1 | + | IL2 |) (8)
Comparing equation (6) and equation (8), it is understood that (| IL2 | + | IL1-IL2 |) <(| IL1 | + | IL2 |) because IL1 and IL2 have the same sign. Is done. As described above, in the boost chopper circuit using the second arm, the conduction loss of the switching element is suppressed as compared with the boost chopper circuit using the first arm.

  Next, the conduction loss in the step-up chopper circuit using the second arm described in FIGS. 40 to 41 is compared with the conduction loss in the PB mode of power converter 50 (FIG. 1).

  FIG. 44 is a circuit diagram for explaining a current path when B1L arm (DC power supply B1) and B2U arm (DC power supply B2) are turned on in power converter 50. That is, FIG. 44 shows a current path when power converter 50 according to the first embodiment operates in the parallel boost (PB) mode in the same manner as in FIG.

  Referring to FIG. 44, in power converter 50, switching elements S3 and S4 function as the lower arm of DC power supply B1, while switching elements S1 and S4 function as the upper arm of DC power supply B2. Therefore, when the BIL arm and the B2U arm are turned on, switching elements S1, S3, and S4 are turned on according to the logical sum of the two.

  In this state, reactor current IL1 forms a current path that passes through switching elements S3 and S4. On the other hand, reactor current IL2 forms a current path through switching elements S1 and S4.

  Therefore, in power converter 50, conduction loss according to reactor current | IL1 | occurs in switching element S3, and conduction loss according to reactor current | IL2 | occurs in switching element S1. Furthermore, in the switching element S4, conduction loss according to | IL1-IL2 | occurs.

  The conduction loss Pls # in the switching elements S1, S3, and S4 at this time is represented by the equation (9) according to the equations (5) to (8).

Pls # = Vfe × (| IL1 | + | IL2 | + | IL1-IL2 |) (9)
From the comparison of equations (8) and (9), since Pls0 <Pls #, power converter 50 according to the first embodiment has a conduction loss of the switching element in power converter 10 when operating in the PB mode. It is understood that this is larger than when a step-up chopper circuit using the first arm is formed.

  To summarize, in power converter 10 according to the second embodiment, the conduction loss in the boost chopper circuit using the first arm is equivalent to the conduction loss when the two boost chopper circuits operate in parallel, and It is lower than the conduction loss in the PB mode of the power converter 50.

  Furthermore, from Expressions (6), (8), and (9), Pls2 <Pls0 <Pls #. Therefore, in the parallel boost (PB) mode of power converter 10, when each of DC power supplies B1 and B2 performs a power running operation, during the period in which the boost chopper circuit using the second arm is formed, The conduction loss of the switching element is reduced as compared with the case where the boost chopper circuit to be used is formed.

  Referring to FIG. 38 again, even when both DC power supplies B1 and B2 perform a regenerative operation, that is, when IL1 <0 and IL2 <0, current paths 121 shown in FIGS. ˜123 are formed by inverting the current direction. Therefore, in this case as well, a current path that minimizes the conduction loss of the switching element is automatically generated in accordance with changes in the reactor currents IL1 and IL2 by the same mechanism as when both DC power supplies B1 and B2 are in a powering operation. Selected. That is, even when both DC power supplies B1 and B2 perform a regenerative operation, the conduction loss of the switching element during the period in which the step-up chopper circuit is configured using the second arm (the ON period of switching element Q5) It is lower than when a boost chopper circuit is formed.

  Next, the circuit operation of the power converter 10 when one of the DC power supplies B1 and B2 performs a power running operation and the other performs a regenerative operation when the second arm is used will be described. As an example, the operation of power converter 10 when DC power supply B1 performs a power running operation while DC power supply B2 performs a regenerative operation, that is, when IL1> 0 and IL2 <0 will be described. A waveform example of reactor currents IL1 and IL2 in this case is shown in FIG.

  Referring to FIG. 45, reactor current IL1 is positive while IL2 is negative (IL1> 0, IL2 <0), and B1L arm is turned on (SD1 = H level), while B2U A current waveform in a period Tγ during which the arm is turned on (SD2 = L level) is shown. Also in this case, as shown in FIG. 33, since the control pulse signals SD1 = H level and SD2 = L level, the switching elements Q2, Q3, Q5 are turned on. For this reason, the equivalent circuit shown in FIG. 37 is also formed in the period Tγ.

  In the period Tγ, similarly to the period T0, the reactor current IL1 increases while the reactor current IL2 decreases. Since the directions of reactor currents IL1 and IL2 are different, IL1> IL2 is satisfied throughout period Tγ, unlike period T0.

  FIG. 46 shows a current path in an equivalent circuit (FIG. 37) in which switching elements Q2, Q3, and Q5 are turned on during period Tγ. The current path that can be formed at this time is one of the three types of FIGS. 46 (a) to 46 (c), as in FIGS. 40 (a) to 40 (c).

  In FIG. 46 (a), the switching elements Q2 and Q3 are in the conductive state as in FIG. 40 (a). That is, current path 124 is formed such that reactor current IL1 flows through switching element Q2 and reactor current IL2 (IL2 <0) flows through switching element Q3. The total conduction loss in the switching elements Q2, Q3, and Q5 due to the current path 124 is equivalent to Pls1 shown in Expression (5).

  In FIG. 46B, the switching elements Q2 and Q5 are in the conductive state, as in FIG. That is, current path 125 is formed such that current (IL1-IL2) flows through switching element Q2 and reactor current IL2 (IL2 <0) flows through switching element Q5. The total conduction loss in the switching elements Q2, Q3, and Q5 due to the current path 125 is equivalent to Pls2 shown in Expression (6).

  In FIG. 46 (c), the switching elements Q3 and Q5 are turned on, as in FIG. 40 (c). That is, current path 126 is formed such that current (IL1-IL2) flows through switching element Q3 and reactor current IL1 (IL1> 0) flows through switching element Q5. The total conduction loss in the switching elements Q2, Q3, and Q5 due to the current path 126 is equivalent to Pls3 shown in Expression (7).

  Next, the current paths 124 to 126 in the period Tγ (IL1> 0, IL2 <0) will be considered.

  First, in the case of the current path 124 shown in FIG. 46A, the forward voltage difference between the switching elements Q2 and Q3 is applied to the switching element Q5. That is, since the voltage applied to the switching element Q5 is almost 0, this coincides with an event in which the switching element Q5 is not conductive.

  On the other hand, in the case of the current path 125 shown in FIG. 46B, the sum of forward voltages of the switching elements Q2 and Q5 is applied to the switching element Q3. Since the sum of the forward voltages exceeds the rising voltage of the switching element Q3, this phenomenon contradicts the phenomenon in which the switching element Q3 is not conducting. Therefore, the current path 125 shown in FIG. 46B is not formed in the period Tγ.

  Similarly, in the case of the current path 126 shown in FIG. 46C, the sum of the forward voltages of the switching elements Q3 and Q5 is applied to the switching element Q2. Since the sum of the forward voltages exceeds the rising voltage of the switching element Q2, this phenomenon contradicts the phenomenon in which the switching element Q2 is not conducting. Therefore, the current path 126 shown in FIG. 46C is not formed in the period Tγ.

  FIG. 47 shows a comparison of conduction loss in the period Tγ of the current paths 124 to 126 shown in FIG.

  Referring to FIG. 47, since the directions (polarities) of reactor currents IL1 and IL2 are opposite during period Tγ, the term | IL1-IL2 | is larger than both | IL1 | and | IL2 |. .

  Therefore, as can be understood from the comparison of the expressions (5) to (7), Pls1 is the smallest among Pls1 to Pls3 throughout the period Tγ. On the other hand, in the period Tγ, as described in FIGS. 46A to 46C, the current path 124 is automatically selectively formed. Therefore, it is understood that the current path 124 in which the conduction loss is automatically minimized is formed in the switching elements Q2, Q3, and Q5 in the on state throughout the period Tγ.

  Referring to FIG. 38 again, contrary to the above example, when DC power supply B1 performs a regenerative operation (IL1 <0), while DC power supply B2 performs a power running operation (IL2> 0), FIG. The current paths 124 to 126 shown in a) to (c) are formed with the current direction reversed. Therefore, also in this case, the current path 124 in which the conduction loss of the switching element is minimized is automatically selected by the same mechanism as when the DC power supply B1 performs the power running operation while the DC power supply B2 performs the regenerative operation.

  As described above, in the power converter 10, when one of the DC power sources B1 and B2 performs a power running operation and the other performs a regenerative operation when the second arm is used, the switching elements Q2, Q3, and Q5 in the on state are used. The current path that minimizes the conduction loss is automatically selected. The conduction loss Pls at this time is equivalent to the conduction loss in the step-up chopper circuit using the first arm.

  In the pattern in which the second arm is used, the B1U arm and the B2L arm are turned on, that is, the switching elements Q1, Q4, Q5 are turned on (Q2, Q2), contrary to the case described in FIGS. There is a pattern in which Q3 is turned off. However, because of the symmetry of the circuit configuration of power converter 10, the circuit operation when the B1U arm and the B2L arm are turned on is the same as in the above-described pattern in which the B1L arm and the B2U arm are turned on.

  Therefore, in power converter 10, in the step-up chopper circuit using the second arm, when one of DC power supplies B1 and B2 performs a power running operation and a regenerative operation, the conduction loss of the switching element is boosted using the first arm. This is equivalent to the conduction loss in the chopper circuit (when two boost chopper circuits are operated in parallel).

  As a result, even when the power supply / regenerative operations of the DC power supplies B1 and B2 are different throughout the entire period in which the boost chopper circuit using the second arm is formed, the conduction loss of the switching element is boosted using the first arm. This is equivalent to the conduction loss in the chopper circuit. As long as there is a period during which each of the DC power supplies B1 and B2 is in a power running operation or a regenerative operation, the conduction loss of the switching element in the boost chopper circuit using the second arm is the boost using the first arm. It is reduced more than the chopper circuit.

  As described above, in power converter 10 according to the second embodiment, in the parallel boost mode, the DC power supply is used so that the boost chopper circuit using the first arm and the boost chopper circuit using the second arm are automatically used together. B1 and B2 can execute DC / DC conversion in parallel with the power lines PL and GL (load 30).

  By providing a period for forming the boost chopper circuit using the second arm (the ON period of the switching element Q5), the conduction loss of the switching element is less than the conduction loss in the boost chopper circuit using the first arm. Can also be reduced. For this reason, in the parallel boost mode of power converter 10, the DC / DC conversion can be made more efficient by suppressing the conduction loss of the switching element than power converter 50 according to the first embodiment.

  As described above, in power converter 10 according to the second embodiment, the conduction loss of the switching element is reduced by providing the boosting period using the second arm. On the other hand, as can be understood from FIGS. 30, 31, etc., the step-up chopper circuit having the second arm is formed only during a period in which the levels of the control pulse signals SD1 and SD2 are different.

  Therefore, in the period in which each of the DC power supplies B1 and B2 is in the power running operation or the regenerative operation, by taking as long as possible the periods in which the logic levels of the control pulse signals SD1 and SD2 are different from each other with respect to the duty ratios DT1 and DT2 of the same value The conduction loss can be further suppressed. For this reason, when the current phase control by the PWM control in which the carrier wave is configured by the sawtooth wave applied to the power converter 50 in the first embodiment and the modification thereof is applied, the conduction loss of the power converter 10 is further reduced. Can do.

  FIG. 48 is a waveform diagram for explaining application of PWM control similar to that in the first embodiment to power converter 10 according to the second embodiment.

  In FIG. 48, the carrier waves other than the carrier waves CW1 and CW2 are the same as those in FIG. That is, also in FIG. 48, the on / off control of the switching elements Q1 to Q5 based on the control pulse signals SD1 and SD2 is executed similarly to FIG.

  Referring to FIG. 48, by applying sawtooth waves as carrier waves CW1 and CW2, inflection points (inflection points of reactor current IL1 (time tx1, tx2 in FIG. 53) of carrier waves CW1 and CW2 (time tx1 and tx2 in FIG. 53). It is possible to realize current phase control in which the maximum point in the example of FIG. 53 and the inflection point of the reactor current IL2 (the minimum point in the example of FIG. 53) are set at the same timing.

  By such current phase control, the timing at which the control pulse signal SD1 transitions from the H level to the L level (falling edge) is the same as the timing at which the control pulse signal SD2 transitions from the L level to the H level (rising edge). It's time. At this time, the period in which the logic levels of the control pulse signals SD1 and SD2 are different, that is, the H level period (use period of the second arm) of the control signal SQ5 can be secured the longest. Thereby, the conduction loss in the parallel boost mode of the power converter 10 can be further reduced, and the DC / DC conversion can be further improved in efficiency.

  Thus, with respect to power supply system 5B (FIG. 23) according to the second embodiment, the same PWM control that applies sawtooth waves to carrier waves CW1 and CW2 as in the first embodiment and its modification is used. The current phase control for reducing the power loss of the power converter 10 can be easily realized without adjusting the carrier phase difference as in the carrier phase control in FIG.

  As described above, in power converter 10, during the period in which each of DC power supplies B1 and B2 is in the power running operation or the regenerative operation, the period for forming the boost chopper circuit using the second arm (the ON period of switching element Q5) is set. Current phase control is required to make it as long as possible. Therefore, in power supply system 5B according to the second embodiment, current phase control is performed so as to select phase pattern A and phase pattern B among the four patterns of current phases shown in FIG.

  Therefore, in order to select phase pattern A or B, by applying carrier wave mode 1 or carrier wave mode 2 in FIG. 14 and performing PWM control similar to that in Embodiment 1, power converter 10 is About the power supply system 5B including, performance can be improved by a simple control process, without largely changing a reactor current.

  Further, by switching the phase pattern (A / B) according to the direction (positive / negative) of the reactor currents IL1 and IL2, which is one of the operating states of the power converter 10, the switching elements Q1 to Q5 Power loss can be reduced. In addition, as described in the first embodiment, according to the temperature of the switching elements S1 to S4, which is one of the operating states of the power converter 50, so as to suppress the temperature rise at the specific switching element, It is also possible to control so as to switch the carrier wave mode so as to switch the phase pattern. Also in this case, as in FIG. 14, an arbitrary phase pattern can be realized by switching the waveform of the sawtooth wave by switching the carrier wave mode.

  Further, at the time of switching the carrier wave mode, the transition period 205 (FIGS. 16 and 19) can be provided in accordance with FIG. 18 or FIG. 21 as in the first modification of the first embodiment.

[Modification of Embodiment 2]
In the modification of the second embodiment, a modification of the circuit configuration of the power converter 10 illustrated in FIG. 23 will be described. In the configuration of FIG. 23, as described in the second embodiment, the power supply system 5B to which the power converter according to each modification described below is applied instead of the power converter 10 is also described. 1 and its modification example 1 can be applied.

(Deformation by arrangement of bidirectional switch)
FIG. 49 is a circuit diagram for illustrating a configuration of power converter 11 according to the first example of the modification of the second embodiment.

  Referring to FIG. 49, power converter 11 is bi-directional in place of switching element Q5 as a semiconductor element connected between nodes N11 and N12, as compared with power converter 10 shown in FIG. The difference is that a switch QB5 is provided. That is, the bidirectional switch QB5 corresponds to a “fifth semiconductor element”. Since other configurations of power converter 11 are the same as those of power converter 10, detailed description will not be repeated.

  Bidirectional switch QB5 includes a diode D15a and a switching element Q5a electrically connected in series between nodes N1 and N2. Diode D15a is electrically connected between nodes N11 and N12 with the direction from node N11 to node N12 as the forward direction.

  Bidirectional switch QB5 further includes a diode D15b and switching element Q5b electrically connected in series between nodes N11 and N12. Diode D15b and switching element Q5b are connected in parallel to diode D15a and switching element Q5a between nodes N11 and N12. Diode D15b is electrically connected between nodes N11 and N12 with the direction from node N12 toward node N11 as the forward direction.

  Switching elements Q5a and Q5b are on / off controlled in response to control signals SQ5a and SQ5b from control device 40 (FIG. 23), respectively.

  In bidirectional switch QB5, when switching element Q5a is turned on, a diode D15a forms a current path in a direction from node N11 to N12. On the other hand, when switching element Q5a is turned off, the current path in the direction from node N11 to N12 is interrupted.

  When switching element Q5b is turned on, a current path is formed in the direction from node N12 to N11 by diode D15b. On the other hand, when switching element Q5b is turned off, the current path in the direction from node N12 to N11 is interrupted.

  Thus, in the bidirectional switch QB5, when the switching element Q5b is turned on while the switching element Q5b is turned off, a current path from the node N11 to N12 is formed, while a current path from the node N12 to N11 is blocked. Is done. Conversely, when switching element Q5b is turned on while switching element Q5a is turned off, a current path is formed in the direction from node N12 to N11, while the current path from node N11 to N12 is blocked.

  FIG. 50 shows a gate logical expression for on / off control of switching elements Q1-Q4, Q5a, Q5b in power converter 11 in the parallel boost mode.

  Referring to FIG. 50, switching elements Q1-Q4 are on / off controlled according to the gate logic equation common to FIG. 31 in the parallel boost mode of power converter 10.

  That is, the switching element Q2 is turned on / off according to the control pulse signal SD1, while the switching element Q1 is turned on / off according to the control pulse signal / SD1. Similarly, switching element Q3 is turned on / off in response to control pulse signal SD2, while switching element Q4 is turned on / off in response to control pulse signal / SD2.

  Switching elements Q5a and Q5b can be turned on / off in common according to a common gate logic formula with switching element Q5 of power converter 10. That is, it is possible to control both the switching elements Q5a and Q5b to be turned on during the on period of the switching element Q5, while the switching elements Q5a and Q5b are both turned off during the off period of the switching element Q5. That is, switching elements Q5a and Q5b can be turned on / off according to the XOR (exclusive OR) of control pulse signals SD1 and SD2.

  On the other hand, in the PB mode, when the current path between nodes N11 and N12 forms both the B1L arm (switching element Q2 on) and the B2L arm (switching element Q4), the current from node N12 to N11 The route needs to be blocked. Therefore, switching element Q5b can be turned on / off according to the logical sum (OR) of control pulse signals / SD1 and / SD2.

  Similarly, when both the B1U arm (switching element Q1) and the B2U arm (switching element Q3) are formed, it is necessary to cut off the current path from the node N11 to N12. Therefore, switching element Q5a can be turned on / off according to the logical sum (OR) of control pulse signals SD1 and SD2.

  Thus, parallel boost mode can be applied to power converter 11 (FIG. 49) as well as power converter 10, and control pulse signal SD1 is applied by applying PWM control according to the first embodiment and its modification. , SD2 can improve the performance of the power supply system including the power converter 11 by a simple control process.

(Modification for simplification)
Up to this point, in power converters 10 and 11 according to the second embodiment and the modifications thereof, switching elements Q1 to Q4 and antiparallel diodes D11 to D4 are provided for each of “first semiconductor element” to “fourth semiconductor element”. The example which comprises D14 pairs has been described.

  The “fifth semiconductor element” is configured by a switching element Q5 (FIG. 23) in which no antiparallel diode is provided or a pair of switching elements Q5a and Q5b (FIG. 49) for forming a bidirectional switch. An example is shown. That is, the configuration in which all of the “first semiconductor element” to “fifth semiconductor element” are provided with switching elements capable of controlling the formation (ON) and cutoff (OFF) of the current path is illustrated. In these configuration examples, regenerative charging can be applied to both DC power supplies B1 and B2.

  However, in a configuration in which one or both of the DC power supplies B1 and B2 are not regeneratively charged, by omitting either the switching element or the diode for a part of the “first semiconductor element” to the “fourth semiconductor element”. The structure can be simplified. That is, in principle, only a part of the “first semiconductor element” to the “fifth semiconductor element” includes the switching element.

  For example, when the DC power supply B1 is used only for discharging (powering) without regenerative charging, the configuration of the power converter 12a shown in FIG. 51 is used instead of the power converter 10 shown in FIG. be able to.

  Referring to FIG. 51, in power converter 12a, the arrangement of switching element Q1 for controlling regeneration to DC power supply B1 can be omitted as compared with power converter 10 shown in FIG. . That is, the “first semiconductor element” between the node N11 and the power line PL can be configured by only the diode D11.

  Also in power converter 12a, the parallel boost mode can be applied by performing on / off control of switching elements Q2-Q5 according to FIG. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification. Further, in the power converter 12a, there is a possibility that the diode D12 disposed mainly for securing a regenerative current path to the DC power supply B1 may be omitted.

  Similarly, when the DC power supply B2 is used only for discharging (power running) without regenerative charging, the configuration of the power converter 13a shown in FIG. 52 can be used.

  Referring to FIG. 52, in power converter 13a, the arrangement of switching element Q3 for controlling regeneration to DC power supply B2 can be omitted as compared with power converter 10 shown in FIG. . That is, the “third semiconductor element” between the node N12 and the power line GL can be configured by only the diode D13.

  Also in power converter 13a, the parallel boost mode can be applied by controlling on / off of switching elements Q1, Q2, Q4, and Q5 according to FIG. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification. Further, in the power converter 13a, there is a possibility that the diode D14 disposed mainly for securing a regenerative current path to the DC power source B2 may be omitted.

  Furthermore, when both DC power sources B1 and B2 are not regeneratively charged and used only by discharging (powering), the configuration of the power converter 14a shown in FIG. 53 can be used.

  Referring to FIG. 53, in power converter 14a, the arrangement of switching elements Q1, Q3 for controlling regeneration to DC power supplies B1, B2 is omitted as compared with power converter 10 shown in FIG. can do. That is, the “first semiconductor element” between the node N11 and the power line PL can be configured by only the diode D11, and the “third semiconductor element” between the node N12 and the power line GL is configured only by the diode D13. can do.

  Also in power converter 14a, the parallel boost mode can be applied by controlling on / off of switching elements Q2, Q4, and Q5 in accordance with FIG. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification. Furthermore, in the power converter 14a, there is a possibility that the diodes D12 and D14 disposed mainly for securing the regenerative current path to the DC power sources B1 and B2 may be omitted.

  In the power converter 11 shown in FIG. 49, when both DC power sources B1 and B2 are not regenerative and are limited to the power running operation, no current is generated in the direction in which switching element Q5b flows. Alternatively, when only one of DC power supplies B1 and B2 cannot perform regeneration and performs a power running operation, no current flows through switching element Q5.

  Therefore, in the power converter 11 shown in FIG. 49, when any one of the DC power supplies B1 and B2 is not regeneratively charged, a current path from the node N12 to N11 is not always necessary, so that the switching element Q5b and The diode D15b can be omitted. That is, the “fifth semiconductor element” can also be configured to have only a function of turning on and off the current path from the node N11 to N12.

  Therefore, when the DC power supply B1 is used only for discharging (power running) without regenerative charging, the configuration of the power converter 12b shown in FIG. 54 is used instead of the power converter 11 shown in FIG. It is also possible.

  Referring to FIG. 54, power converter 12b controls formation / cut-off of a current path from node N11 to N12 instead of switching element Q5, as compared with power converter 12a shown in FIG. Switching element Q5a and diode D15a are arranged. That is, in the power converter 12b, the arrangement of the switching element Q1 for controlling the regeneration to the DC power source B1 is omitted as compared with the configuration of the power converter 11 shown in FIG. The switching element Q5b and the diode D15b are omitted with respect to the “semiconductor element”.

  Also, the diode D12 can be omitted in the same manner as the power converter 12a (FIG. 51). In the power converter 12b, the parallel boost mode can be applied by controlling on / off of the switching elements Q2 to Q4 and Q5a according to FIG. 50 in the power converter 11. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification.

  When the DC power source B2 is used only for discharging (powering) without regenerative charging, the configuration of the power converter 13b shown in FIG. 55 is used instead of the power converter 11 shown in FIG. It is also possible.

  Referring to FIG. 55, power converter 13b controls formation / cut-off of a current path from node N11 to N12 instead of switching element Q5, as compared with power converter 13a shown in FIG. Switching element Q5a and diode D15a are arranged. That is, in the power converter 13b, the arrangement of the switching element Q3 for controlling regeneration to the DC power supply B2 is omitted as compared with the configuration of the power converter 11 shown in FIG. The switching element Q5b and the diode D15b are omitted with respect to the “semiconductor element”.

  Further, the diode D14 can be omitted in the same manner as the power converter 13a (FIG. 52). In power converter 13b as well, parallel boost mode can be applied by controlling on / off of switching elements Q1, Q2, Q4, and Q5a according to FIG. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification.

  Similarly, when both DC power sources B1 and B2 are used only for discharging (powering) without regenerative charging, the power converter shown in FIG. 56 is used in place of power converter 11 shown in FIG. It is also possible to use the configuration of 14b.

  Referring to FIG. 56, power converter 14b controls the formation / cutoff of a current path from node N11 to N12 instead of switching element Q5, as compared with power converter 14a shown in FIG. Switching element Q5a and diode D15a are arranged. That is, in power converter 14b, the arrangement of switching elements Q1 and Q3 for controlling regeneration to DC power supplies B1 and B2 is omitted as compared with the configuration of power converter 11 shown in FIG. , Regarding the “fifth semiconductor element”, the switching element Q5b and the diode D15b are omitted.

  Also, the diodes D12 and D14 can be omitted in the same manner as the power converter 14a (FIG. 53). Also in power converter 14b, the parallel boost mode can be applied by controlling on / off of switching elements Q2, Q4, Q5a according to FIG. At this time, control pulse signals SD1 and SD2 can be generated by PWM control according to the first embodiment and its modification.

  In addition, in power converter 14b (FIG. 56) that does not recharge both DC power supplies B1 and B2, “first semiconductor element” is configured by diode D11, and “second semiconductor element” is configured by switching element Q2. The “third semiconductor element” is configured by the diode D13, the “fourth semiconductor element” is configured by the switching element Q4, and the “fifth semiconductor element” is at least a current path from the node N11 to the node N12. Is configured to have only a function of turning on and off. This configuration corresponds to a minimum necessary configuration for performing DC power conversion (DC / DC conversion) by switching a plurality of operation modes between DC power supplies B1 and B2 and power lines PL and GL. In the power converter 14a of FIG. 53, the “fifth semiconductor element” has a function that can be commonly turned on / off for the current path from the node N12 to N11 in addition to the current path from the node N11 to N12. It is configured.

  With respect to the configurations of the power converter 14a (FIG. 53) and the power converter 14b (FIG. 56), the DC power supply B1 can be regeneratively charged by further providing a switching element Q1 in the “first semiconductor element”. (FIGS. 52 and 55). In this case, as also shown in FIGS. 52 and 55, it is preferable to connect the diode D12 in antiparallel to the switching element Q2.

  Further, with respect to the configurations of the power converter 14a (FIG. 53) and the power converter 14b (FIG. 54), the DC power supply B2 can be regeneratively charged by further providing a switching element Q3 in the “third semiconductor element”. This is possible (FIGS. 51 and 54). In this case, as shown also in FIGS. 51 and 54, it is preferable to connect the diode D14 in antiparallel to the switching element Q4.

  As in power converter 10 (FIG. 23) or power converter 11 (FIG. 49), each of “first semiconductor element” to “fourth semiconductor element” is configured by a combination of a switching element and a diode. In addition, the “fifth semiconductor element” has a cutoff function for currents in both directions (currents from the nodes N11 to N12 and currents from the nodes N12 to N11), thereby regenerating both the DC power supplies B1 and B2. Charging can be applied.

[Embodiment 3]
In the first and second embodiments, power converter 10 (11, 12a to 14a, 12b to 14b) and power converter 50 (50) having an operation state in which both reactor currents IL1 and IL2 flow in at least a part of the switching elements. For example, by applying PWM control using a sawtooth wave as a carrier wave, an example in which the performance of the power supply system including the power converter is improved by simple control processing has been described.

  In the third embodiment, the application of the PWM control described in the first embodiment and the first modification to the configuration of the power converter in which the paths of the reactor currents IL1 and IL2 do not overlap with each switching element will be described.

(Power system configuration)
FIG. 57 is a circuit diagram showing a configuration example of a power supply system 5C according to the third embodiment of the present invention.

  Referring to FIG. 57, power supply system 5C includes DC power supplies B1 and B2 and power converters 6 and 7.

  Power converter 6 is connected between DC power supply B1 and load 30. The power converter 7 is connected between the DC power source B2 and the load 30. In power supply system 5 </ b> C, DC power supplies B <b> 1 and 20 are connected to load 30 in parallel via power converters 6 and 7.

  Each of power converters 6 and 7 has a so-called boost chopper circuit configuration. Specifically, power converter 6 includes switching elements Q1 # and Q2 # and a reactor L1. Switching elements Q1 # and Q2 # are connected in series between power line PL and power line GL.

  Reactor L1 has terminals 201 and 202. Terminal 201 is electrically connected to the positive terminal of DC power supply B1. Terminal 202 is electrically connected to a connection node of switching elements Q1 and Q2. Thereby, reactor L1 is electrically connected between the positive terminal of DC power supply B1 and the connection node of switching elements Q1 # and Q2 #. Alternatively, reactor L1 can be connected between the negative terminal of DC power supply B1 and switching element Q2 #.

  In power converter 6, by turning on switching element Q2 #, power lines PL and GL are connected to DC power supply B1 similarly to current path 120 (FIG. 3A) and current path 191 (FIG. 25). Without being included, a loop-shaped current path including DC power supply B1 and reactor L1 (that is, “first current path”) can be formed.

  Further, switching element Q2 # is turned off (switching element Q1 # is turned on), so that direct current is connected between power lines PL and GL, similarly to current path 121 (FIG. 3B) and current path 193 (FIG. 26). A current path (that is, a “second current path”) in which power source B1 and reactor L1 are connected in series can be formed.

  Similarly, power converter 7 includes switching elements Q3 # and Q4 # and a reactor L2. Switching elements Q3 # and Q4 # are connected in series between power line PL and power line GL.

  Reactor L2 has terminals 203 and 204. Terminal 203 is electrically connected to the positive terminal of DC power supply B2. Terminal 203 is electrically connected to a connection node of switching elements Q3 # and Q4 #. Thereby, reactor L2 is electrically connected between the positive terminal of DC power supply B2 and the connection node of switching elements Q3 # and Q4 #. Alternatively, reactor L2 can be connected between the negative terminal of DC power supply B2 and switching element Q4 #.

  In power converter 7, by turning on switching element Q4 #, power lines PL and GL are connected to DC power supply B2 similarly to current path 130 (FIG. 4A) and current path 192 (FIG. 25). A loop-shaped current path including the DC power supply B2 and the reactor L2 (that is, the “third current path”) can be formed without the inclusion.

  Further, switching element Q4 # is turned off (switching element Q3 # is turned on), so that direct current is connected between power lines PL and GL, similarly to current path 131 (FIG. 4B) and current path 194 (FIG. 26). A current path in which power supply B2 and reactor L2 are connected in series (ie, “fourth current path”) can be formed.

  In power converters 6 and 7, antiparallel diodes D11 # to D14 # are arranged for switching elements Q1 # to Q4 #. Switching elements Q1 # -Q4 # can control on / off in response to control signals SQ1 # -SQ4 # from control device 40.

  Power converters 6 and 7 operate in parallel to perform DC / DC conversion between DC power supplies B1 and B2 and power lines PL and GL connected to load 30.

  In power converters 6 and 7 constituted by step-up chopper circuits, the ON period ratio between the upper arm (Q1 #, Q3 #) and the lower arm (Q2 #, Q4 #) is shown within a predetermined period (switching period). The DC output is controlled according to the duty ratio. The duty ratio can be executed by PWM control equivalent to the control configuration of FIG.

  Specifically, in the configuration of FIG. 5, PWM control unit 550 generates control signals SQ1 # and SQ2 # according to control pulse signal SD1 according to a voltage comparison between duty ratio DT1 and carrier wave CW1. That is, control signal SQ2 # is set to H level (SQ1 # is L level) during the H level period of control pulse signal SD1, while control signal SQ1 # is set to H level (SQ2 #) during L level period of control pulse signal SD1. Can be set to L level).

  Similarly, PWM control unit 550 generates control signals SQ3 # and SQ4 # according to control pulse signal SD2 according to the voltage comparison between duty ratio DT2 and carrier wave CW2. That is, control signal SQ4 # is set to H level (SQ3 # is L level) during the H level period of control pulse signal SD2, while control signal SQ3 # is set to H level (SQ4 #) during L level period of control pulse signal SD2. Can be set to L level).

(Configuration of magnetically coupled reactor)
In the power supply system according to the third embodiment, in power converters 6 and 7, the paths of reactor currents IL1 and IL2 do not overlap in any of switching elements Q1 # to Q4 #. On the other hand, reactors L1 and L2 are integrally configured by a composite magnetic component using a common core. Thereby, size reduction and weight reduction of the magnetic components which comprise reactor L1, L2 can be achieved.

  FIG. 58 is an example of a schematic external view of a magnetically coupled reactor shown as a composite magnetic component for integrally configuring reactors L1 and L2 of power converters 6 and 7.

58 is a perspective view of the magnetically coupled reactor 100. FIG.
Referring to FIG. 58, magnetically coupled reactor 100 includes a core 150 and windings 121a, 121b, 122a. Windings 121a and 121b are electrically connected in series to form a coil of reactor L1. Winding 122a constitutes a coil of reactor L2. As understood from FIG. 5, the windings 121 a and 121 b constituting the reactor L <b> 1 and the winding 122 a constituting the reactor L <b> 2 are wound around different parts of the common core 150.

  59 is a conceptual cross-sectional view for further explaining the structure of magnetically coupled reactor 100 shown in FIG.

  Referring to FIG. 59, core 150 has magnetic leg portions 151, 152, 153, and 154. The magnetic leg portions 151 to 153 are provided with gaps 161 to 163, respectively. As described above, the gaps 161 to 163 are useful in terms of adjusting the inductance.

  The winding 121a is wound around the magnetic leg 151. The winding 121b is wound around the magnetic leg 152. Windings 121a and 121b are electrically connected in series between terminals 201 and 202. Therefore, reactor current IL1 flowing through reactor L1 flows from terminal 201 to terminal 202 via winding 121a and winding 121b. By the passage of the reactor current IL1, a magnetic field 211 is generated from the winding 121a, and a magnetic field 212 is generated from the winding 121b.

  The winding 122 a is wound around the magnetic leg portion 153. Winding 122 a is electrically connected between terminals 203 and 204. Therefore, reactor current IL2 flowing through reactor L2 flows from terminal 203 to terminal 204 via winding 122a. The magnetic field 213 is generated by the winding 122a by the reactor current IL2. As described above, the magnetic leg portions 151 to 153 correspond to the winding portions of the windings 121a, 121b, and 122a in the core 150. On the other hand, the magnetic leg portion 154 corresponds to a non-winding portion of the winding in the core 150 and functions to form a magnetic path between the magnetic leg portions 151 to 153 around which the winding is wound.

  Windings 121a and 121b are configured such that when common reactor current IL1 flows through windings 121a and 121b, the current flow direction in winding 121a and the current flow direction in winding 121b are opposite to each other. Is done.

  Winding 122a has the same current direction as one of windings 121a and 121b when reactor current IL2 flows in the same direction as reactor current IL1 (eg, IL1> 0 and IL2> 0) The direction of the current is opposite to the other. Hereinafter, an example in which the current flow direction is the same between the windings 121a and 122 will be described. That is, the winding 121a corresponds to the “first winding”, and the winding 121b corresponds to the “second winding”. The winding 122a corresponds to a “third winding”.

  FIG. 60 is a conceptual diagram for explaining an example of a winding mode of each winding shown in FIG. 61 corresponds to a top view of the magnetically coupled reactor 100 shown in FIGS. 58 and 59. FIG.

  Referring to FIG. 60, a reactor current IL1 flows between terminals 201 and 202. The windings 121a and 121b are electrically connected in series by the conducting wire 121c. At this time, the conducting wire 121c is connected between the windings 121a and 121b so that the current direction in the coil constituted by the windings 121a and 121b is opposite.

  As a result, as shown in FIG. 60, the magnetic field 211 generated by the winding 121a has the core upper surface side (upper side in FIG. 59) as the N pole and the core lower surface side (lower side in FIG. 59) as the S pole. Direction. On the other hand, the magnetic field 212 generated by the winding 121b has a direction in which the upper surface side of the core (upper side in FIG. 59) is the S pole and the lower surface side of the core (lower side in FIG. 59) is the N pole. That is, the magnetic fields 211 and 212 generated from the windings 121a and 121b by the reactor current IL1 flow in opposite directions, respectively.

  Furthermore, reactor current IL2 is allowed to flow between terminals 203 and 204 in the same direction as reactor current IL1 (for example, IL1> 0, IL2> 0). As a result, a magnetic field 213 is generated from the winding 122a. The magnetic field 213 has a direction in which the upper surface side of the core (upper side in FIG. 59) is an N pole and the lower surface side of the core (lower side in FIG. 59) is an S pole. That is, the magnetic field 213 generated by the winding 122a by the reactor currents IL1 and IL2 in the same direction is in the same direction as the magnetic field 211 generated by the winding 121a, but is opposite to the magnetic field 212 generated by the winding 121b. is there.

FIG. 61 is a conceptual diagram for explaining another example of the winding mode of each winding shown in FIG.
In the example shown in FIG. 61, the terminal 204 and the conducting wire 121c are provided at positions different from those in FIG. In FIG. 61, the direction of current in each of the windings 121a, 121b, and 122a, that is, the direction of the magnetic fields 211 to 213 is the same as that in FIG. Are the same. In other words, in the configuration of FIG. 60, the number of turns of the windings 121a and 121b is ¼ turn more than that of the winding 122a.

  FIG. 62 is an electrical equivalent circuit diagram of magnetically coupled reactor 100 according to the first embodiment.

  Referring to FIG. 62, windings 121a and 121b connected in series between terminals 201 and 202 constitute a reactor L1. The voltage source 91 applies a reactor voltage VL1 between the terminals 201 and 202. For example, voltage source 91 is configured to generate reactor voltage VL1 in a pulsed manner by on / off control of switching elements Q1 # and Q2 # of power converter 6. Specifically, in power converter 6 in FIG. 57, VL1 = V [1] is satisfied during the ON period of switching element Q2 # (VL1> 0). On the other hand, in the off period of switching element Q2 # (the on period of switching element Q1 #), V [1] −VL1 = VH is established, so that VL1 = V [1] −VH is satisfied (VL1 <0). .

  Similarly, winding 122a connected between terminals 203 and 204 constitutes reactor L2. The voltage source 92 applies a reactor voltage VL 2 between the terminals 203 and 204. For example, voltage source 92 is configured to generate reactor voltage VL2 in a pulsed manner by on / off control of switching elements Q3 # and Q4 # of power converter 7. Specifically, in power converter 7 of FIG. 57, VL2 = V [2] is satisfied (VL1> 0) during the on period of switching element Q4 #. On the other hand, in the off period of switching element Q4 # (on period of switching element Q3 #), V [2] −VL2 = VH is established, so that VL2 = V [1] −VH is satisfied (VL2 <0). .

  Here, as shown in FIG. 59, the windings 121a, 121b, and 122 are wound around a common core 150 in which magnetic leg portions 151 to 153 are integrally formed. Accordingly, the magnetic fluxes generated in the windings 121a, 121b, and 122a interfere with each other. Thereby, reactor currents IL1 and IL2 also indirectly act with each other via the magnetic flux in common core 150.

  Next, the relationship of the magnetic flux generated from each winding in the core will be described with reference to FIGS.

  63 and 64 are conceptual cross-sectional views similar to FIG. FIG. 63 shows the magnetic flux generated by reactor L1 in the core, while FIG. 64 shows the magnetic flux generated by reactor L2 in the core.

  Referring to FIG. 63, the magnetic flux 221 generated by the magnetic field 211 generated from the winding 121 a wound around the magnetic leg portion 151 also acts on the magnetic leg portions 152 and 153 via the magnetic leg portion 154. Similarly, the magnetic flux 222 due to the magnetic field 212 generated from the winding 121 b wound around the magnetic leg portion 152 also acts on the magnetic leg portions 151 and 153 via the magnetic leg portion 154. The magnetic field 212 and the magnetic field 212 form a circuit that includes the magnetic leg portions 151 and 152 in the core 150.

  In each of the magnetic leg portions 151 and 152, the magnetic fluxes 221 and 222 by the magnetic fields 211 and 212 act in the same direction. That is, the magnetic fields 211 and 212 strengthen each other in each of the magnetic leg portions 151 and 152.

  On the other hand, in the magnetic leg portion 153, the magnetic fluxes 221 and 222 by the magnetic fields 211 and 212 act in opposite directions. That is, the magnetic fields 211 and 212 weaken each other at the magnetic leg portion 153.

  Referring to FIG. 64, magnetic flux 223 generated by magnetic field 213 generated from winding 122 a wound around magnetic leg portion 153 also acts on magnetic leg portions 151 and 152 via magnetic leg portion 154.

  63 and 64, in the magnetic leg portion 153 corresponding to the reactor L2, the magnetic flux 221 from the winding 121a and the magnetic flux 222 from the winding 121b cancel each other, while the magnetic flux 223 by the winding 122a passes. To do. That is, the magnitude of the magnetic field at the magnetic leg portion 153 is equivalent to the magnetic field 213 generated by the reactor current IL2.

  On the other hand, between the magnetic leg portions 151 and 152 corresponding to the reactor L1, the magnitude of the magnetic field becomes unbalanced due to interference with the magnetic flux from the reactor L2. In the magnetic leg 152, the magnetic fluxes 211 and 212 by the magnetic fields 211 and 212 and the magnetic flux 223 by the magnetic field 213 (FIG. 64) are in the same direction, so the magnetic fields 211 and 212 and the magnetic field 213 strengthen each other. On the other hand, in the magnetic leg 151, the magnetic fluxes 221 and 222 by the magnetic fields 211 and 212 and the magnetic flux 223 by the magnetic field 213 (FIG. 64) are in opposite directions, so the magnetic fields 211 and 212 and the magnetic field 213 weaken each other. . The magnetic leg portion 151 corresponds to a “first magnetic leg portion”, and the magnetic leg portion 152 corresponds to a “second magnetic leg portion”. The magnetic leg portion 153 corresponds to a “third magnetic leg portion”.

(Operation of non-magnetic coupling mode of magnetic coupling reactor)
In the magnetically coupled reactor 100, the magnetic field generated by each of the reactor currents IL1 and IL2 in one of the magnetic leg portions 151 and 152 (the magnetic leg portion 152 in this embodiment) around which the windings 121a and 121b forming the reactor L1 are wound. Strengthen each other. On the other hand, in the other magnetic leg portion (the magnetic leg portion 151 in this embodiment), the magnetic fields due to the reactor currents IL1 and IL2 cancel each other. Due to such mutual magnetization action, the magnitude of the magnetic field becomes unbalanced between the magnetic leg portions 151 and 152 under the flow of the reactor currents IL1 and IL2.

  Therefore, in the magnetically coupled reactor 100, in the region where the reactor currents IL1 and IL2 are large, if there is a difference in magnetic permeability (relative magnetic permeability) due to magnetic field imbalance between the magnetic leg portions 151 and 152, the magnetic coupling Will cause magnetic interference. Here, the relationship between the magnetic field, magnetic flux density, and permeability will be described with reference to FIGS. 65 and 66. FIG.

  FIG. 65 shows a general magnetization curve (BH curve) of a ferromagnetic material. FIG. 66 shows a magnetization curve 305 (so-called initial magnetization curve) when magnetized from a state where no magnetic field is applied.

  Referring to FIG. 65, magnetic flux density B increases as magnetic field H increases. However, as the magnetic field H increases, the rate of increase of the magnetic flux density B gradually decreases. Eventually, the BH curve becomes horizontal, that is, a phenomenon called magnetic saturation occurs in which the magnetic flux density does not increase any more even when the magnetic field is increased. The magnetic flux density at the time of magnetic saturation is called saturation magnetic flux density Bsmax.

  The slope of the tangent in the magnetization curve (BH curve) shown in FIG. 65 corresponds to the magnetic permeability of the magnetic body (core 150).

  66 shows the change characteristic of the magnetic permeability with respect to the change of the magnetic flux density in the magnetization curve shown in FIG.

  66, in region 310 where magnetic field H <Ha, that is, magnetic flux density B <Ba, magnetic flux density B changes substantially linearly with respect to change in magnetic field H. In the region 310, the magnetic permeability μ has a substantially constant value. Hereinafter, such a region is also referred to as a “linear region 310”.

  On the other hand, in the region of H> Ha, that is, B> Ba, the rate of increase of the magnetic flux density B with respect to the increase of the magnetic field H, that is, the magnetic permeability μ is lower than that of the linear region 310. Further, the magnetic permeability μ further decreases as the magnetic field H increases. Hereinafter, such a region is also referred to as a “nonlinear region” or a “saturation region”. When the magnetic flux density further increases, the magnetic permeability μ further decreases. When B = Bsmax is reached, μ = 0. A magnetic material having the above characteristics, that is, a non-linear region is generally referred to as a non-linear magnetic material.

  On the other hand, if a magnetic material (linear magnetic material) that does not have such a non-linear region is used, the magnetic permeability μ against the change in the magnetic flux density B as indicated by a dotted line 307 in FIG. Is kept constant. Alternatively, even when the magnetic flux density B is limited and used so that the operating point is maintained in the linear region, the reactor can be operated with a constant magnetic permeability as indicated by a dotted line 307.

  As described with reference to FIGS. 63 and 64, in the state where reactor currents IL1 and IL2 are flowing, the magnitude of the magnetic field is unbalanced between magnetic leg portions 151 and 152 corresponding to reactor L1. Specifically, in the magnetic leg portion 152, the magnetic field due to the reactor current IL1 and the magnetic field due to the reactor current IL2 strengthen each other, so that the magnetic field increases. On the other hand, in the magnetic leg 151, the magnetic field due to the reactor current IL1 and the magnetic field due to the reactor current IL2 weaken each other, so that the magnetic field becomes small.

  FIG. 67 is a conceptual diagram illustrating magnetic operating points of the magnetic leg portions of the core in a region where reactor currents IL1 and IL2 are small. In FIG. 67, the magnetic operating points 301 to 303 of the magnetic leg portions 151 to 153 are shown on the BH curve.

  Referring to FIG. 67, the magnetic flux density B is larger on the BH curve at the operating point 302 of the magnetic leg portion 152 where the magnetic fields strengthen each other than the operating point of the magnetic leg portion 153. On the other hand, the magnetic flux density B is smaller on the BH curve at the operating point 301 of the magnetic leg part 151 where the magnetic fields weaken each other than at the operating point of the magnetic leg part 153. As described above, in the magnetic leg portion 153, the magnetic flux 221 from the winding 121a and the magnetic flux 222 from the winding 121b cancel each other, so the magnitude of the magnetic field is equivalent to the magnetic field generated by the reactor current IL2.

  In the region where reactor currents IL1 and IL2 are small, both operating points 301 and 302 are located within linear region 310 shown in FIG. In a state where the operating points 301 to 303 of the magnetic leg portions 151 to 153 are within the linear region 310, no magnetic coupling is generated between the reactors L1 and L2, and the reactors L1 and L2 are operated by making both magnetically non-interfering. Can be made. At this time, the magnetic leg portions 151 to 153 are magnetized in the linear region 310. That is, reactors L1 and L2 operate in the nonmagnetic coupling mode.

  These operating points 301 to 303 depend on the design of the reactors L1 and L2, specifically, the design of the core 150, the windings 121a, 121b, 122a, and the like. For example, the cross-sectional areas SC1 and SC2 of the magnetic leg portions 151 and 152 are set so that the operating points 301 to 303 are within the linear region 310 at the maximum rating, that is, even when the designed maximum current I (max) passes. If designed, the reactors L1 and L2 can be used while maintaining a magnetically non-interfering state.

(Operation of magnetically coupled reactor in magnetic coupling mode)
In order to operate the magnetic coupling reactor 100 only in the non-magnetic coupling mode, there is a concern that the reactor may be enlarged due to the enlargement of the core 150 by securing the cross-sectional areas SC1 and SC2 of the magnetic leg portions 151 and 152. The Therefore, in the present embodiment, the magnetic coupling reactor 100 can be designed so that the reactors L1 and L2 operate even in the magnetic coupling mode.

  In the following description, the maximum current I (max) does not mean only the maximum rated current of reactors L1 and L2 alone, but a power supply system incorporating reactors L1 and L2 (for example, as shown in FIG. 57). It also means the passing current of reactors L1 and L2 at the maximum output of the power supply system 5C). For example, when the maximum allowable current of the system is defined by elements (for example, switching elements) other than the reactor in the power supply system, even if there is a margin in the current capacity of reactors L1 and L2, the power supply system Reactors L1 and L2 can be designed with the reactor current when operating at an allowable current as the maximum current I (max). That is, the maximum current I (max) means the upper limit value of the current usage range of reactors L1 and L2 assumed at the time of design.

  FIG. 68 is a conceptual diagram for explaining the magnetic operating point of each magnetic leg portion of the core in the region where the reactor current is large.

  Referring to FIG. 68, when reactor currents IL1 and IL2 increase, magnetic flux density B further increases at operating point 302 of magnetic leg portion 152 where the magnetic fields strengthen each other as compared with FIG. On the other hand, the magnetic flux density B is further reduced at the operating point 302 of the magnetic leg portion 152 where the magnetic fields weaken each other as compared with FIG. As a result, while the operating point 302 is in the linear region 310, the operating point 301 deviates from the linear region 310 and enters the saturation region. At this time, the magnetic leg 151 is magnetized in the linear region, while the magnetic leg 152 is magnetized in the non-linear region (saturation region).

  As shown in FIG. 66, when the magnetic flux density B is increased and deviates from the linear region 310 and enters the saturation region, the magnetic permeability μ, that is, the relative magnetic permeability of the magnetic leg portion decreases. Therefore, in the state where operating points 301 and 302 are located in the linear region and the saturation region, magnetic interference due to magnetic coupling occurs between reactors L1 and L2. That is, reactors L1 and L2 operate in the magnetic coupling mode.

  In a state where magnetic coupling is generated between the reactors L1 and L2, the influence of magnetic interference acts in the direction of increasing or decreasing the inductance according to the phase relationship between the reactor currents. For this reason, in the configuration in which reactor currents IL1 and IL2 can be controlled independently by power converters 6 and 7, the phase relationship between reactor voltages (currents) can also be controlled. For this reason, it is possible to control the current phase so that the inductances of reactors L1 and L2 are equivalently increased in a state where magnetic coupling occurs.

  Thus, in magnetically coupled reactor 100 according to the present embodiment, reactors L1 and L2 are magnetically non-coupled (state where operating points 301 to 303 are those in FIG. 67), and reactors L1 and L2 are magnetically coupled. It is characterized in that it can operate both in the state of being coupled to (the state where the operating points 301 to 303 are those in FIG. 68).

  As a result, it is not necessary to secure the cross-sectional area SC2 so that the operating point 302 at the maximum current I (max) stops within the linear region 310. Also, the cross-sectional area SC1 can be reduced on the premise of the asymmetric operation for the magnetic leg portions 151 where the magnetic fields weaken each other. Furthermore, since the above-described effect of increasing the inductance is also produced, the required inductance can be ensured even if the core 150 is downsized. As a result, the reactor for obtaining the required inductance can be reduced in size.

(Current phase control for operation in non-magnetic coupling mode)
As described in Patent Document 2, when it is desired to operate the magnetic coupling reactor 100 only in the linear region 310, that is, the non-magnetic coupling mode, the maximum magnetic flux density B (max) in the core is The threshold value Bmax corresponding to the boundary of the linear region 310 must not be exceeded. Since the magnetic flux density changes depending on the reactor currents IL1 and IL2, the maximum magnetic flux density B (max) can be suppressed by current phase control.

  FIG. 69 shows a conceptual waveform diagram for explaining the relationship between the phase of the reactor current and the magnetic flux density.

  Referring to FIG. 69, magnetic flux density B (L1) due to reactor current IL1 is proportional to current IL1, and magnetic flux density B (L2) due to reactor L2 is proportional to reactor current IL2. The maximum magnetic flux density Bmax in the core 150 is proportional to the maximum value of the total magnetic flux density Bt (Bt = B (L1) + B (L2)), that is, the maximum value of the sum of the reactor currents (IL1 + IL2).

  Therefore, the maximum value Bmax of the total magnetic flux density can be suppressed by controlling the current phase so that the maximum point (crest) of reactor current IL1 and the minimum point (valley) of reactor current IL2 are at the same timing. .

  FIG. 70 is a waveform diagram for explaining an example of current phase control in the power supply system 5C for realizing the current phase control as described above.

  Referring to FIG. 70, control signals SQ1 # and SQ2 # for controlling on / off of switching elements Q1 # and Q2 # of power converter 6 are controlled by PWM control comparing duty ratio DT1 and carrier wave CW1. It can be calculated by the control configuration shown in FIG.

  Similarly, control signals SQ3 # and SQ3 # for controlling on / off of switching elements Q3 # and Q4 # of power converter 7 are shown in FIG. 5 by PWM control for comparing duty ratio DT2 and carrier wave CW2. It can be calculated by the control configuration.

  In PWM control for controlling the outputs of these DC power supplies B1 and B2, the carrier waves CW1 and CW2 are configured in accordance with the carrier wave mode 1 (FIG. 14) in the first embodiment, whereby the maximum point (mountain) of the reactor current IL1. ) And the minimum point (valley) of reactor current IL2 can be realized at the same timing. As a result, the maximum value Bmax of the total magnetic flux density can be suppressed by simple control.

  69 shows the current phase control when IL1> IL2 (IL1> 0 and IL2> 0). However, when IL2> IL1, the maximum point (peak) of the reactor current IL2 and the reactor current IL1. It is preferable to control the current phase so that the local minimum point (valley) is at the same timing.

  Moreover, even if the direction (positive / negative) of reactor current IL1, IL2 changes according to the operating state of power converters 6, 7, the current phase can be controlled in the same manner.

  FIG. 71 shows a waveform diagram when reactor currents IL1 <0 and IL2 <0, that is, when the regenerative operation is performed for both DC power supplies B1 and B2.

  Referring to FIG. 71, when both reactor currents IL1 and IL2 are regenerative currents, the minimum point (valley) of the reactor current with the larger absolute value and the maximum point of the reactor current with the smaller absolute value It is preferable that (mountains) have the same timing.

  In the example of FIG. 71, since | IL1 |> | IL2 |, the current phase is controlled so that the minimum point (valley) of reactor current IL1 and the maximum point (crest) of reactor current IL2 have the same timing. Is done. In this case, on / off of switching elements Q1 # to Q4 # in power converters 6 and 7 is controlled by PWM control according to carrier wave mode 2 (FIG. 14) in the first embodiment.

  FIG. 72 shows a waveform diagram when the directions of reactor currents IL1 and IL2 are different. In particular, in the example of FIG. 72, waveforms in the case of IL1> 0 (powering current) and IL2 <0 (regenerative current) are shown.

  When the directions of the reactor currents IL1 and IL2 are different, the magnetic flux cancels out inside the core 150. Therefore, it is preferable to control the current phase so that the maximum value (absolute value) of the power running current and the regenerative current have the same timing. . Therefore, it is preferable that the maximum point (mountain) of reactor current IL1 that is a power running current and the minimum point (valley) of reactor current IL2 that is a regenerative current have the same timing.

  In this case, on / off of switching elements Q1 # to Q4 # in power converters 6 and 7 is controlled by PWM control according to carrier wave mode 1 (FIG. 14) in the first embodiment.

  Further, when IL2> 0 and IL1 <0, the maximum point (peak) of reactor current IL2 and the minimum point (valley) of reactor current IL1 that is a regenerative current are set at the same timing. PWM control according to the carrier wave mode 2 in FIG. 1 (FIG. 14) is applied.

  Thus, in the operation of the magnetic coupling reactor 100 in the non-magnetic coupling mode (non-saturated region), depending on the direction (positive / negative) of the reactor currents IL1 and IL2, which is the operating state of the power converters 6 and 7. The current phase control for suppressing the maximum value Bmax of the total magnetic flux density in the core 150 is performed by a simple control process by performing PWM control in which the carrier wave pattern shown in the first embodiment is appropriately switched. Can be executed. At this time, when the carrier wave mode is switched in accordance with changes in reactor currents IL1 and IL2, as described in the modification of the first embodiment, transition period 205 (see FIGS. 16 and 21) is performed. 19) A transition period 205 can be provided.

(Current phase control for operation in magnetic coupling mode)
In the magnetic coupling mode, the effect of increasing the equivalent inductance in a state where magnetic coupling is generated between reactors L1 and L2 can be enhanced by controlling the current phase of reactor currents IL1 and IL2.

  73 and 74 show an operation example when carrier phase control is applied in the magnetically coupled reactor according to the present embodiment. 73 and 74 show operation waveform diagrams analyzed by the circuit simulator.

  Referring to FIG. 73, FIG. 73 (a) shows a simulation waveform when the reactors L1 and L2 are magnetically non-coupled, and FIG. 73 (b) shows the state between reactors L1 and L2. Simulation waveforms when magnetically coupled are shown. In FIG. 73 (b), the current phase is controlled so that the minimum point of the reactor current IL1 and the maximum point of the reactor current IL2 have the same timing.

  73 (a) and 73 (b), the simulation conditions are determined so that the average values of reactor current IL1 and the average values of IL2 are the same under the same circuit constant. .

  It can be understood from a comparison between the two that the peak-to-peak value (ripple component) of the reactor current IL1 in FIG. 73 (b) is suppressed more than the ripple component of the reactor current IL1 in FIG. 73 (a). Similarly, with respect to the reactor current IL2, the ripple current amplitude in FIG. 73 (b) is suppressed more than in FIG. 73 (a).

  In FIG. 73 (b), it is understood that the peak current suppression of the reactor current IL2 on the small current side is particularly effective. That is, if carrier phase control is performed so that the maximum point of reactor current IL2 and the minimum point of reactor current IL1 are at the same timing, it is effective in suppressing the peak of reactor current IL2.

  In this case, in the PWM control for controlling the outputs of DC power supplies B1 and B2, carrier waves CW1 and CW2 are configured in accordance with carrier wave mode 2 (FIG. 14) in the first embodiment, whereby reactor current IL2 is maximized. It is possible to realize current phase control in which the point (mountain) and the minimum point (valley) of the reactor current IL2 have the same timing.

  Referring to FIG. 74, FIG. 74 (a) shows the same waveform as FIG. 73 (a), that is, a simulation waveform when the reactors L1 and L2 are magnetically non-coupled. FIG. 74 (b) shows a simulation waveform when the reactors L1 and L2 are in a magnetically coupled state. In FIG. 74 (b), the carrier phase control is applied so that the maximum point of the reactor current IL1 and the minimum point of the reactor current IL2 have the same timing, that is, the current phase is equivalent to that in FIG. . Note that the simulation conditions are the same as those in FIGS. 73A and 73B even between FIGS. 74A and 74B.

  It can be understood from the comparison between the two that the peak-to-peak value (ripple component) of the reactor current IL1 in FIG. 74 (b) is suppressed more than the ripple component of the reactor current IL1 in FIG. 74 (a). Similarly, for the reactor current IL2, the ripple current amplitude in FIG. 74 (b) is suppressed more than in FIG. 74 (a).

  In FIG. 74 (b), it is understood that the peak current suppression of the reactor current IL1 on the large current side is particularly effective. That is, if carrier phase control is performed so that the maximum point of reactor current IL1 and the minimum point of reactor current IL2 are at the same timing, it is effective in suppressing the peak of reactor current IL1.

  In this case, in the PWM control for controlling the outputs of DC power supplies B1 and B2, carrier waves CW1 and CW2 are configured in accordance with carrier wave mode 1 (FIG. 14) in the first embodiment, whereby reactor current IL1 is maximized. It is possible to realize current phase control in which the point (mountain) and the minimum point (valley) of the reactor current IL2 have the same timing. As a result, the peak value of the reactor current can be suppressed by simple control.

  From these simulation waveforms, in the magnetically coupled reactor according to the present embodiment, the ripple current amplitude of reactor currents IL1 and IL2 is suppressed, that is, equivalent by operating so that reactors L1 and L2 are magnetically coupled. It can be understood that the inductance can be increased.

  Further, in FIG. 73 (b) and FIG. 74 (b), the period of the slope (change rate) of reactor current IL1 and the sign of the slope (change rate) of reactor current IL2 are different due to the application of current phase control. The period Tn in which both codes are the same can be shortened by increasing Tm. As a result, the effect of increasing inductance in the magnetically coupled reactor can be enhanced. Due to these equivalent inductance increasing effects, a magnetically coupled reactor is configured by a composite magnetic component in which two reactors L1 and L2 are integrated using a common core 150, thereby reducing the size and weight of the reactor. be able to.

  73 and 74, current phase control in a region where reactor currents IL1 and IL2 are both positive (IL1> 0, IL2> 0) has been described. Even if the directions (positive / negative) of reactor currents IL1 and IL2 change, the current phase can be similarly controlled by applying the PWM control according to the first embodiment and the first modification thereof.

  For example, when IL1 <0 and IL2 <0, the relative relationship between the direction of the magnetic field due to reactor current IL1 and the direction of the magnetic field due to reactor current IL2 is the same as when IL1> 0 and IL2> 0. is there. Therefore, also in these operation patterns, the magnetic leg portion 152 strengthens the magnetic field, while the magnetic leg portion 151 weakens the magnetic field.

  When the reactor currents IL1 and IL2 have the same polarity (positive / negative), IL1> 0. As described in the case of IL2> 0, the ripple current of the reactor currents IL1 and IL2 is controlled by controlling the current phase so that the maximum point of one reactor current and the minimum point of the other reactor current have the same timing. Amplitude can be suppressed.

  Therefore, current phase control is executed by selectively applying carrier wave mode 1 or carrier wave mode 2 (FIG. 14) in the first embodiment depending on which one of reactor currents IL1 and IL2 is to be suppressed. can do. Thereby, the peak values of reactor currents IL1 and IL2 can be suppressed.

  On the other hand, when the directions (positive / negative) of reactor currents IL1 and IL2 are different (IL1> 0, IL2 <0, or IL1 <0, IL2> 0), the direction of the magnetic field by reactor current IL1 The relative relationship with the direction of the magnetic field by the reactor current IL2 is opposite to that described with reference to FIGS.

  Therefore, contrary to the description with reference to FIGS. 63 and 64, the magnetic leg portion 151 strengthens the magnetic field, while the magnetic leg portion 152 weakens the magnetic field. In this case, the maximum point of one reactor current and the maximum point of the other reactor current are at the same timing, or the minimum point of one reactor current and the minimum point of the other reactor current are the same timing. The ripple current amplitude of reactor currents IL1 and IL2 can be suppressed by controlling the current phase so that Thereby, the peak values of reactor currents IL1 and IL2 can be suppressed.

  Therefore, current phase control is executed by selectively applying carrier wave mode 3 or carrier wave mode 4 (FIG. 14) in the first embodiment depending on which one of reactor currents IL1 and IL2 is to be suppressed. can do. Thereby, the peak values of reactor currents IL1 and IL2 can be suppressed.

  Thus, even in the operation of the magnetic coupling reactor 100 in the magnetic coupling mode (saturation region), depending on the direction (positive / negative) of the reactor currents IL1 and IL2, which is the operating state of the power converters 6 and 7, Current phase control for suppressing the ripple current amplitude and peak value of reactor currents IL1 and IL2 is performed by a simple control process by performing PWM control in which the carrier wave pattern shown in the first embodiment is appropriately switched. can do. Also in this case, when the carrier wave mode is switched in accordance with changes in reactor currents IL1 and IL2, as described in the modification of the first embodiment, transition period 205 (FIG. 16, FIG. FIG. 19) A transition period 205 can be provided.

  As described above, PWM control using a sawtooth wave according to the first embodiment and its modification 1 can also be applied to power supply system 5C. Here, power supply system 5C does not have a configuration in which the paths of reactor currents IL1 and IL2 do not directly overlap in switching elements Q1 # to Q4 # of power converters 6 and 7, respectively. However, power supply system 5C also has a configuration in which magnetic fluxes generated by reactor currents IL1 and IL2 interfere with each other through core 150, and therefore, by applying PWM control according to the first embodiment and its modification, reactor current IL1, By controlling the phase of IL2, the performance can be improved by a simple control process.

  As described above, the PWM control using the sawtooth wave described in the first embodiment and its modification example 1 is a power supply system having a configuration in which the reactor currents directly act by overlapping each other, and the reactor current passes through the magnetic flux. Therefore, the present invention can be applied to both of the power supply systems that are configured to operate indirectly.

(Modification of the configuration of the magnetically coupled reactor)
Next, a modified example of the configuration of the magnetic coupling reactor will be described.

  FIG. 75 is a perspective view showing a schematic appearance of magnetically coupled reactor 100 # according to the modification.

  Referring to FIG. 75, magnetically coupled reactor 100 # according to the second embodiment includes a core 150 # and windings 121a #, 121b #, 122a #. Windings 121a # and 121b # are electrically connected in series similarly to windings 121a and 121b to form a coil of reactor L1. Winding 122a # constitutes the coil of reactor L2. Also in magnetically coupled reactor 100 #, windings 121a # and 121b # constituting reactor L1 and winding 122a # constituting reactor L2 are wound around different parts of common core 150 #, respectively. .

  FIG. 76 is a plan view showing the appearance of core 150 # of the magnetically coupled reactor shown in FIG.

  Referring to FIG. 76, core 150 # has an annular outer portion and magnetic leg portions 151 # to 153 # extending from the outer portion toward the center of the ring. Magnetic leg portions 151 # to 153 # are integrated at the center of the ring. That is, in core 150 #, magnetic leg portion 154 # similar to magnetic leg portion 154 of magnetically coupled reactor 100 is formed by the outer shape portion and the central portion. Gaps 161 # to 163 # are provided in the magnetic leg portions 151 # to 153 #.

  Magnetic leg portions 151 # to 153 # correspond to winding portions of windings 121a #, 121b #, 122a # in core 150 #. On the other hand, magnetic leg portion 154 # corresponds to a non-winding portion of the winding in core 150 #, and forms a magnetic path between magnetic leg portions 151 # to 153 # around which the winding is wound. Function.

  FIG. 77 is a schematic plan view for illustrating a winding mode of each winding in the magnetic coupling reactor according to the second embodiment.

  Referring to FIG. 77, reactor current IL1 flows between terminals 201 # and 202 #. Electrical leads 121c # are electrically connected in series between windings 121a # and 121b #. FIG. 70 shows the current direction when IL1> 0, IL2> 0, as in FIGS.

  Reactor current IL1 flows through winding 121a # and winding 121b #, thereby generating magnetic field 211 # from winding 121a # and generating magnetic field 212 # from winding 121b #. As a result, magnetic field 211 # has a direction in which the center side of the ring is the N pole and the outer periphery side of the ring is the S pole. On the other hand, magnetic field 212 # has a direction in which the outer peripheral side of the ring is the N pole and the center side of the ring is the S pole. That is, magnetic fields 211 # and 212 # generated from windings 121a # and 121b #, respectively, due to the passage of reactor current IL1 are in opposite directions, and similarly to magnetic fields 211 and 212 shown in FIG. A circular path including magnetic leg portions 151 # and 152 # is formed in core 150 #. Conductive wire 121c # is connected between windings 121a # and 121b # so that such a magnetic field direction is realized.

  Furthermore, reactor current IL2 flows between terminals 203 # and 204 # (IL1> 0, IL2> 0 in FIG. 30). Thereby, magnetic field 213 # is generated from winding 122a #. Magnetic field 213 # has a direction in which the center side of the ring is the N pole and the outer periphery side of the ring is the S pole. That is, magnetic field 213 # generated by winding 122a # by reactor currents IL1 and IL2 in the same direction is in the same direction as magnetic field 211 # from winding 121a #, while magnetic field 212 # from winding 121b #. Is the opposite direction.

  Thus, in magnetic coupling reactor 100 #, the magnetic behavior at magnetic leg portions 151 # to 153 # due to the passage of reactor currents IL1 and IL2 is the same as that of magnetic leg portions 151 to 153 of magnetic coupling reactor 100. is there. That is, in magnetic coupling reactor 100 # according to the second embodiment, magnetic leg portion 151 # corresponds to the “first magnetic leg portion”, and magnetic leg portion 152 # corresponds to the “second magnetic leg portion”. Magnetic leg portion 153 # corresponds to “third magnetic leg portion”.

  In this manner, magnetically coupled reactor 100 # according to the modified example, in the same manner as magnetically coupled reactor 100, causes reactors L1 and L2 to operate in both the nonmagnetic coupling mode and the magnetic coupling mode in accordance with reactor currents IL1 and IL2. Can do.

  Therefore, magnetic coupling reactor 100 # can also be used in place of magnetic coupling reactor 100 in power supply system 5C shown in FIG. Even when reactors L1 and L2 are configured by magnetically coupled reactor 100 #, the phase of the reactor current can be easily controlled by applying the PWM control shown in the first embodiment and the first modification thereof.

  As described in Patent Document 1, in power converters 50 and 50 # of power supply system 5A according to the first embodiment, reactors L1 and L2 are magnetically coupled reactors 100 and 100 # described in the third embodiment. It is also possible to configure by. Similarly, in power supply system 5B according to the second embodiment, in power converters 10, 11, 12a to 14a, and 12b to 14b, reactors L1 and L2 are replaced by magnetically coupled reactors 100 and 100 # described in the third embodiment. It is also possible to configure.

  In addition, in the power supply systems 5A to 5C, the load 30 will be described in a definite manner as long as the load 30 can be configured by any device as long as it is a device that operates with a DC voltage controlled by the power converter. That is, in the present embodiment, the example in which the load 30 is configured to include the electric motor for traveling of the electric vehicle has been described.

  Furthermore, if it is a power converter including two DC power supplies and two reactors, the sawtooth wave according to the first embodiment and its modification example 1 is not limited to the circuit configuration exemplified in the present embodiment. The phase of the reactor current can be easily controlled by controlling the output from each DC power source by applying PWM control using the.

  In the first to third embodiments and the modified examples, the connection examples of the switching elements and the reactors are illustrated and described for the configuration examples of the power converters. However, the constituent elements of the power converters are only these elements. It is not meant to be limited to. That is, in the present embodiment, the description that the components are “electrically connected” means that there are other circuit elements and connector terminals between the two elements, and the above-described components are connected via the other circuit elements. This includes ensuring electrical connection between the components.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  5A, 5B, 5C power supply system, 6, 7, 10, 11, 12a, 12b, 13a, 13b, 14a, 14b, 50, 50 # power converter, 30 load, 32 inverter, 35 motor generator, 36 power transmission gear , 37 drive wheel, 40 control device, 91, 92 voltage source, 100 magnetic coupling reactor, 120-126, 130, 131, 191-198 current path, 121a, 121a #, 121b, 121b #, 122a, 122a # winding , 121c conductor, 150, 150 # core, 151-154, 151 # -154 # magnetic leg, 161-163, 161 # -163 # gap, 201-204, 201 # -204 # terminals, 205 transition period, 221 ˜223, 221 # ˜223 # magnetic flux, 301, 302, 303 operating point, 305 Magnetization curve, 310 linear region, 500, 510 output control unit, 502, 512 deviation calculation unit, 505, 515 PI control unit, 507, 517 addition unit, 550 PWM control unit, 560 carrier wave generation unit, B1, B2 DC power supply , GL, PL power line, CH smoothing capacitor, CW, CW1, CW2 carrier wave, D1-D4, D11-D14, D11 # -D14 # diode, DT, DT1, DT2 duty ratio, DTa, DTb conversion duty ratio, Dff1, Dff2 feedforward control amount, I [1], I [2] current (DC power supply), I maximum current, I1 current command value, I1, Io current command value, IL, IL1, IL2 reactor current, L1, L2 reactor, N1, N2, N3, N11, N12 nodes, Pls, Pls0, Pls 1, Pls2, Pls3 conduction loss, Q1 to Q5, Q5a, Q5b, Q1 # to Q4 #, S1 to S4 Power semiconductor switching element (switching element), QB5 bidirectional switch, RTW antiphase triangular wave, SD1, SD2 control pulse Signal, SG1 to SG4, SQ1 to SQ5, SQ5a, SQ5b, SQ1 # to SQ4 # Control signal (switching element), STD Down sawtooth wave, STU Up sawtooth wave, TW triangular wave, Tcy cycle (carrier wave), V [1] , V [2] Voltage (DC power supply), VH * Voltage command value, VH DC voltage (output voltage), VL1, VL2 Reactor voltage.

Claims (12)

A power supply system for controlling a DC voltage between a first power line on a high voltage side and a second power line on a low voltage side connected to a load,
A first DC power supply;
A second DC power source;
A power converter for performing DC power conversion in parallel between the first and second DC power supplies and the first and second power lines;
A control device for controlling the DC power conversion in the power converter;
The power converter is
A first reactor;
A second reactor,
A plurality of switching elements arranged to switch a current path passing through each of the first and second reactors by on / off control in response to a control signal from the control device;
A current path passing through the first reactor includes a first current path formed between the first DC power source and the first reactor without including both the first and second power lines. A second current path connecting the first DC power source and the first reactor in series between the first and second power lines,
A current path passing through the second reactor includes a third current path formed between the second DC power source and the second reactor without including both the first and second power lines. A fourth current path connecting the second DC power source and the second reactor in series between the first and second power lines,
The controller is
According to the comparison between the first output duty ratio for controlling the output from the first DC power supply and the first carrier wave having a voltage width corresponding to the maximum value of the first output duty ratio, A second output duty ratio for selectively forming a second current path and controlling an output from the second DC power supply; and a voltage width corresponding to a maximum value of the second output duty ratio. Generating the control signals of the plurality of switching elements to selectively form the third and fourth current paths according to a comparison with a second carrier wave having
Each of the first and second carrier waves is one of a first sawtooth wave having a right rising straight portion and a second sawtooth wave having a right falling straight portion having the same frequency and synchronized edge timing. Composed by choosing
In the operation of the power converter, the control device selects the first and second sawtooth waves for each of the first and second carrier waves according to the operating state of the power converter. Switching power supply system. The controller is
When switching the selection of the first and second sawtooth waves in the first carrier wave, a transition cycle having the same length as that of the first and second sawtooth waves is provided, and in the transition cycle The first carrier wave is set to a triangular wave having the same frequency as that of the first and second sawtooth waves, or a reverse-phase triangular wave of the triangular wave, and the average of the first reactor in the transition period Converting the first output duty ratio so that the current is equal to the period immediately before the transition period;
When switching the selection of the first and second sawtooth waves in the second carrier wave, the transition period is provided, and in the transition period, the second carrier wave is the triangular wave or the antiphase triangular wave. The power supply according to claim 1, further comprising: converting the second output duty ratio so that an average current of the second reactor in the transition period is equal to a period immediately before the transition period. system.   The control device sets the anti-phase triangular wave in the transition period when switching from the first sawtooth wave to the second sawtooth wave for each of the first or second carrier waves. On the other hand, when switching from the second sawtooth wave to the first sawtooth wave, the power supply system according to claim 2, wherein the triangular wave is set in the transition period.   The control device sets the triangular wave in the transition period when switching from the first sawtooth wave to the second sawtooth wave for each of the first or second carrier waves. 3. The power supply system according to claim 2, wherein when switching from the second sawtooth wave to the first sawtooth wave, the antiphase triangular wave is set in the transition period. The plurality of switching elements are:
A first switching element electrically connected between a first node and the first power line;
A second switching element electrically connected between a second node and the first node;
A third switching element electrically connected between a third node and the second node;
A second switching line electrically connected between the second power line electrically connected to the negative terminal of the second DC power supply and the third node;
The first reactor is electrically connected in series with the first DC power source between the second node and the second power line,
The second reactor is electrically connected in series with the second DC power source between the first and third nodes,
When the first current path is formed, the third and fourth switching elements are turned on,
When the second current path is formed, the first and second switching elements are turned on,
When the third current path is formed, the second and third switching elements are turned on,
The power supply system according to any one of claims 1 to 3, wherein the first and fourth switching elements are turned on when the fourth current path is formed. The plurality of switching elements are:
A first switching element electrically connected between a first node and the first power line;
A second switching element electrically connected between a second node and the first node;
A third switching element electrically connected between a third node and the second node;
A second switching line electrically connected between the second power line electrically connected to the negative terminal of the second DC power supply and the third node;
The first reactor is electrically connected in series with the first DC power source between the second node and the first power line.
The second reactor is electrically connected in series with the second DC power source between the first and third nodes,
When the first current path is formed, the first and second switching elements are turned on,
The third and fourth switching elements are turned on when the second current path is formed,
When the third current path is formed, the second and third switching elements are turned on,
The power supply system according to any one of claims 1 to 3, wherein the first and fourth switching elements are turned on when the fourth current path is formed. The power converter is
A first semiconductor element electrically connected between the first power line and a first node;
A second semiconductor element electrically connected between the second power line and the first node;
A third semiconductor element electrically connected between a second node and the second power line;
A fourth semiconductor element electrically connected between the first power line and the second node;
Look including a fifth semiconductor element electrically connected between said second node and said first node,
At least the second, fourth, and fifth semiconductor elements include the switching element,
At least the first and third semiconductor elements have diodes arranged with the direction from the second power line toward the first power line as a forward direction,
The first reactor is electrically connected in series with the first DC power source between the first node and the second power line.
The second reactor is electrically connected in series with the second DC power source between the second node and the first power line.
Wherein at the time of formation of the first current path a current path is formed by the front Stories second semiconductor element,
When forming the second current path, a current path is formed by the first semiconductor element,
When the third current path is formed, a current path is formed by the fourth semiconductor element,
When forming the fourth current path, a current path is formed by the third semiconductor element,
The fifth semiconductor element forms a current path in a period in which the first and fourth current paths are formed simultaneously and in a period in which the second and third current paths are formed simultaneously. The power supply system of any one of 1-3.   In at least one of the first and third semiconductor elements, the switching element for forming a current path in a direction opposite to the diode is further provided in parallel with the diode, and the switching element is provided from the control device. The power supply system according to claim 7, wherein the power supply system is controlled to be turned on when the second or fourth current path is formed in response to the signal of the second current path. The fifth semiconductor element is:
In response to a signal from the control device, an on state in which a current path from the first node to the second node is formed between the first and second nodes and an off state in which the current path is interrupted are responded. A first sub-switching element for selectively forming,
In response to a signal from the control device, an on state in which a current path from the second node to the first node is formed between the first and second nodes and an off state in which the current path is cut off are responded to. And a second sub-switching element for selectively forming the power supply system. The first and second reactors are integrally configured by a single composite magnetic component,
The composite magnetic component is
First and second windings electrically connected in series to form the first reactor;
A third winding for constituting the first reactor;
A core composed of a non-linear magnetic material,
The core includes a first magnetic leg portion around which the first winding is wound, a second magnetic leg portion around which the second winding is wound, and the third winding. The third magnetic leg portion to be rotated, and a fourth magnetic leg portion for forming a magnetic path between the first to third magnetic leg portions. Power system. The operating states of the first reactor and the second reactor are changed from the non-magnetic coupling mode in which the first and second reactors operate in a magnetically non-interfering state according to an increase in current. And the second reactor changes to a magnetic coupling mode that operates in a magnetically interfered state,
In the non-magnetic coupling mode, the magnetic permeability in the first and second magnetic leg portions is equal, while in the magnetic coupling mode, the permeability in one of the first and second magnetic leg portions is the same. The power supply system according to claim 10, wherein a magnetic permeability is lower than a magnetic permeability of the other of the first and second magnetic leg portions.   When each of the first and second DC power supplies performs a power running operation, a first magnetic field generated from the first winding and the second winding by a current passing through the first reactor, respectively. And the second magnetic field, and the third magnetic field generated from the third winding by the current passing through the second reactor, the magnetic field of either the first or second magnetic leg portion. The first to third windings are strengthened at the leg, weakened at the other magnetic leg, and the first and second magnetic fields are weakened at the third magnetic leg. The power supply system according to claim 10 or 11, wherein each is wound around the first to third magnetic leg portions.

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