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JP6398270B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP6398270B2
JP6398270B2 JP2014077131A JP2014077131A JP6398270B2 JP 6398270 B2 JP6398270 B2 JP 6398270B2 JP 2014077131 A JP2014077131 A JP 2014077131A JP 2014077131 A JP2014077131 A JP 2014077131A JP 6398270 B2 JP6398270 B2 JP 6398270B2
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Prior art keywords
resin
circuit board
hard resin
fixed
insulating plate
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JP2015198227A (en
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谷口　克己
克己 谷口
堀　元人
元人 堀
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、半導体装置に関し、特に樹脂封止型のパワー半導体モジュールに関する。   The present invention relates to a semiconductor device, and more particularly to a resin-sealed power semiconductor module.

図６は、従来のパワー半導体モジュール５００の要部断面図である。パワー半導体モジュール５００は、回路板１０３、絶縁板１０４及び金属板１０５で構成された絶縁回路基板１０２に半導体素子１０１がはんだ付けされている。さらに半導体素子１０１の表面に形成された電極と回路板１０３などの間にリードフレームなどの接続部材１０９が配置され、また外部端子１１０が回路板１０３に固定されている。上記で構成される部材は、ベース板１０６、ケース１１１及び蓋１１２で構成される筐体内に搭載される。さらに筐体内はシリコーン樹脂などの軟質樹脂１０８で充填され、構成部材を封止している。   FIG. 6 is a cross-sectional view of a main part of a conventional power semiconductor module 500. In the power semiconductor module 500, a semiconductor element 101 is soldered to an insulated circuit board 102 composed of a circuit board 103, an insulating board 104, and a metal board 105. Further, a connecting member 109 such as a lead frame is disposed between the electrode formed on the surface of the semiconductor element 101 and the circuit board 103, and the external terminal 110 is fixed to the circuit board 103. The members configured as described above are mounted in a casing including the base plate 106, the case 111, and the lid 112. Further, the inside of the casing is filled with a soft resin 108 such as a silicone resin to seal the constituent members.

パワー半導体モジュール５００は図示しない冷却フィンの上に取り付けられ、その動作時には半導体素子１０１や絶縁回路基板１０２などに高い電圧が印加されている。このため絶縁回路基板１０２の電界集中部をポリイミド樹脂やエポキシ樹脂などのコーティング膜（図示せず）で被覆することにより、電界緩和を行っている（特許文献１）。   The power semiconductor module 500 is mounted on a cooling fin (not shown), and a high voltage is applied to the semiconductor element 101, the insulating circuit board 102, and the like during the operation. For this reason, electric field relaxation is performed by covering the electric field concentration portion of the insulating circuit substrate 102 with a coating film (not shown) such as polyimide resin or epoxy resin (Patent Document 1).

図７は別の従来例であるパワー半導体モジュール６００の要部断面図である（特許文献２）。図６と異なる点としては、封止樹脂にエポキシ樹脂などの硬質樹脂１０７を用いている点である。   FIG. 7 is a cross-sectional view of a main part of a power semiconductor module 600 which is another conventional example (Patent Document 2). A difference from FIG. 6 is that a hard resin 107 such as an epoxy resin is used as the sealing resin.

図８はさらに別の従来例であるパワー半導体モジュール７００の要部断面図である（特許文献３〜５）。これは半導体素子１０１や回路板１０３、接続部材１０９が配置された絶縁回路基板１０２の上面を弾性率の高い硬質樹脂１０７で被覆し、さらに硬質樹脂１０７や筐体内の他の箇所を軟質樹脂１０８で被覆するものである。   FIG. 8 is a cross-sectional view of a main part of a power semiconductor module 700 which is still another conventional example (Patent Documents 3 to 5). This is because the upper surface of the insulating circuit board 102 on which the semiconductor element 101, the circuit board 103, and the connection member 109 are arranged is covered with a hard resin 107 having a high elastic modulus, and the hard resin 107 and other portions in the housing are soft resin 108. It coats with.

特開平１１−２９７８６９号公報JP 11-297869 A 特開２０１３−１６６８４号公報JP 2013-16684 A 特開２０００−２２３６２３号公報JP 2000-223623 A 特開２０１０−２１９４２０号公報JP 2010-219420 A 特開２０１３−４７６６号公報JP 2013-4766 Gazette

ＳｉＣなどのワイドバンドギャップ（ＷＢＧ）半導体素子は、従来のＳｉ半導体素子と比較して耐電圧が高いため、これを適用すればより高い耐電圧を有するパワー半導体モジュールが実現可能である。一方で、ＷＢＧ半導体素子を適用したパワー半導体モジュールでは、半導体素子以外の構成部材にも高い耐電圧特性が必要となる。例えばパワー半導体モジュールの定格電圧が１０ｋＶを超える場合、ＩＥＣ規格に準拠すると２０ｋＶ程度の耐破壊電圧が必要となり、また構成部材には１０ｋＶ程度の電圧での部分放電耐性も必要となる。   A wide band gap (WBG) semiconductor element such as SiC has a higher withstand voltage than a conventional Si semiconductor element. Therefore, when this is applied, a power semiconductor module having a higher withstand voltage can be realized. On the other hand, in a power semiconductor module to which a WBG semiconductor element is applied, a high withstand voltage characteristic is required for components other than the semiconductor element. For example, when the rated voltage of the power semiconductor module exceeds 10 kV, a breakdown voltage of about 20 kV is required according to the IEC standard, and the component member needs to have a partial discharge resistance at a voltage of about 10 kV.

前述した従来例のパワー半導体モジュールのうち、図６で示した構成にＷＢＧ半導体素子を適用すると、構成部材である軟質樹脂１０８にも高い電圧が印加される。このような高い電圧下において軟質樹脂中に一旦放電が起こると、その放電電荷量が微小であっても放電トリーと呼ばれる樹枝状の破壊痕跡が発生する。そして放電電荷量が大きくなり、更に放電トリーが進展することで絶縁破壊を起こしてしまうという課題がある。また特許文献１に記載のように絶縁回路基板をコーティング膜で覆ったとしても、耐電圧特性を確保することは困難である。   Among the above-described conventional power semiconductor modules, when the WBG semiconductor element is applied to the configuration shown in FIG. 6, a high voltage is also applied to the soft resin 108 as a constituent member. Once discharge occurs in the soft resin under such a high voltage, a dendritic destruction trace called a discharge tree is generated even if the discharge charge amount is very small. Then, there is a problem that the amount of discharge charge is increased, and the breakdown is further caused by further progress of the discharge tree. Moreover, even if the insulating circuit board is covered with a coating film as described in Patent Document 1, it is difficult to ensure withstand voltage characteristics.

一方、図７で示した硬質樹脂１０７を用いた封止では、微小放電が発生しても放電トリーの進展が抑制されるため、放電トリーに起因した絶縁破壊は発生しない。しかしながら、硬質樹脂を用いた封止の場合、樹脂自体の熱硬化時の硬化収縮や他の構成部材との線膨張係数の差異に起因する残留応力が大きい。このため、樹脂とその他の構成部材との間に界面剥離が発生し、あるいは残留応力により樹脂自体に割れが生じるなどの不具合が生じるという課題がある。   On the other hand, in the sealing using the hard resin 107 shown in FIG. 7, since the progress of the discharge tree is suppressed even if a micro discharge occurs, the dielectric breakdown due to the discharge tree does not occur. However, in the case of sealing using a hard resin, there is a large residual stress due to the curing shrinkage at the time of thermosetting of the resin itself and the difference in coefficient of linear expansion from other constituent members. For this reason, there exists a subject that interface peeling generate | occur | produces between resin and another structural member, or the malfunctions that a crack arises in resin itself with a residual stress arises.

この課題に対しては、図８で示した構成が有効な手段となり得る。なぜなら図７の従来例よりも硬質樹脂の使用量が少なく、硬質樹脂に起因する残留応力を低減することができるからである。   For this problem, the configuration shown in FIG. 8 can be an effective means. This is because the amount of hard resin used is smaller than that of the conventional example of FIG. 7, and the residual stress caused by the hard resin can be reduced.

しかしながら本発明者の鋭意研究により、図８で示した構成にＷＢＧ半導体素子を適用した場合、パワー半導体モジュールに必要な耐電圧特性が確保できないことが明らかとなった。その理由は以下の通りである。金属板１０５側の絶縁回路基板１０２の主面には、絶縁板１０４、金属板１０５の端部および軟質樹脂１０８が接し、電界が集中する三重点Ｘが存在する。前述のように軟質樹脂１０８は放電劣化が進展し易く、この放電劣化により回路板１０３側の絶縁板１０４、回路板１０３の端部および硬質樹脂１０７の三重点Ｙまでの絶縁距離が短くなる。このため封止樹脂として一部に硬質樹脂が適用されていても、耐電圧特性が低下する。   However, as a result of diligent research by the present inventor, it has been clarified that when the WBG semiconductor element is applied to the configuration shown in FIG. 8, the withstand voltage characteristic necessary for the power semiconductor module cannot be secured. The reason is as follows. The principal surface of the insulating circuit board 102 on the metal plate 105 side is in contact with the insulating plate 104, the end of the metal plate 105, and the soft resin 108, and there is a triple point X where the electric field concentrates. As described above, the soft resin 108 is prone to discharge deterioration, and this discharge deterioration shortens the insulation distance between the insulating plate 104 on the circuit board 103 side, the end of the circuit board 103 and the triple point Y of the hard resin 107. For this reason, even if a hard resin is partially applied as the sealing resin, the withstand voltage characteristic is lowered.

本発明はこのような点に鑑みてなされたものであり、ＳｉＣなどのワイドバンドギャップ半導体素子を適用したパワー半導体モジュールにおいて、高い耐電圧特性と高い信頼性を有する半導体装置を提供するものである。   The present invention has been made in view of the above points, and provides a semiconductor device having high withstand voltage characteristics and high reliability in a power semiconductor module to which a wide band gap semiconductor element such as SiC is applied. .

前記の目的を達成するために、この発明の一態様では、半導体装置は、主面を有するベース板と、絶縁板、前記絶縁板の第１の主面に固定された回路板、及び、前記絶縁板の第２の主面に固定された金属板を有し、前記金属板の前記絶縁板に固定された面と反対の面が前記ベース板に固定された絶縁回路基板と、おもて面に電極を有し、裏面が前記回路板に固定された半導体素子と、前記半導体素子の電極に一端が固定された導電性の接続部材と、前記絶縁板の端部、前記絶縁板の端部に隣接した前記回路板の端部、前記絶縁板の端部に隣接した前記金属板の端部、前記半導体素子のおもて面、及び前記接続部材を被覆する硬質樹脂と、前記硬質樹脂よりも弾性率が低く、前記硬質樹脂を被覆する軟質樹脂と、を備え、前記ベース板に前記絶縁回路基板より大きい寸法の底面を有する複数の凹部が設けられ、前記複数の凹部の底面にそれぞれ前記絶縁回路基板が固定され、前記凹部の内部が前記硬質樹脂で覆われた構成とする。 In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a base plate having a main surface, an insulating plate, a circuit board fixed to the first main surface of the insulating plate, and the An insulating circuit board having a metal plate fixed to the second main surface of the insulating plate and having a surface opposite to the surface fixed to the insulating plate of the metal plate fixed to the base plate ; A semiconductor element having an electrode on a surface and a back surface fixed to the circuit board; a conductive connecting member having one end fixed to the electrode of the semiconductor element; an end of the insulating plate; an end of the insulating plate A hard resin covering the edge of the circuit board adjacent to the edge, the edge of the metal plate adjacent to the edge of the insulating plate, the front surface of the semiconductor element, and the connecting member; and the hard resin lower elastic modulus than, and a soft resin for covering the hard resin, the insulation on the base plate A plurality of recesses is provided with a bottom surface of the larger dimension than the circuit board, wherein each of the bottom surface of the plurality of recesses insulated circuit board is fixed, a structure in which the inside of the recess is covered with the hard resin.

上記の手段によれば、ＳｉＣなどのワイドバンドギャップ半導体素子を適用したパワー半導体モジュールで、高い耐圧特性と高い信頼性を有するパワー半導体モジュールが実現可能となる。   According to the above means, a power semiconductor module having high breakdown voltage characteristics and high reliability can be realized with a power semiconductor module to which a wide band gap semiconductor element such as SiC is applied.

この発明の実施例１に係るパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module which concerns on Example 1 of this invention. この発明の実施例１に係る耐圧効果を示すグラフである。It is a graph which shows the pressure | voltage resistant effect which concerns on Example 1 of this invention. この発明の実施例１に係るモジュール内の硬質樹脂のせん断応力を示すグラフである。It is a graph which shows the shear stress of the hard resin in the module which concerns on Example 1 of this invention. この発明の実施例２に係るパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module which concerns on Example 2 of this invention. この発明の実施例２に係るパワー半導体モジュールの平面図である。It is a top view of the power semiconductor module which concerns on Example 2 of this invention. この発明の従来例に係るパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module which concerns on the prior art example of this invention. この発明の別の従来例に係るパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module which concerns on another prior art example of this invention. この発明のさらに別の従来例に係るパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module which concerns on another prior art example of this invention.

以下に、本発明の好適な実施形態（実施例）を図面に基づいて説明する。   DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the drawings.

実施の形態を通して共通の構成には同一の符号を付すものとし、重複する説明は省略する。   Throughout the embodiments, common components are denoted by the same reference numerals, and redundant description is omitted.

なおこの実施例は、説明された実施形態に限定されるものではなく、本発明の技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。
[実施例１]
図１は、この発明の実施例１に係る樹脂封止型のパワー半導体モジュール５０の断面図である。 It should be noted that this example is not limited to the described embodiment, and can be variously modified without departing from the scope of the technical idea of the present invention.
[Example 1]
1 is a cross-sectional view of a resin-sealed power semiconductor module 50 according to Embodiment 1 of the present invention.

図示するパワー半導体モジュール５０は、半導体素子１、絶縁回路基板２、ベース板６、硬質樹脂７、軟質樹脂８、接続部材９、外部端子１０、ケース１１、蓋１２などで構成されている。   The illustrated power semiconductor module 50 includes a semiconductor element 1, an insulating circuit board 2, a base plate 6, a hard resin 7, a soft resin 8, a connecting member 9, an external terminal 10, a case 11, a lid 12, and the like.

半導体素子１は、例えばパワーＭＯＳＦＥＴ、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）、ＦＷＤ（還流ダイオード）等の縦型のパワー半導体素子が該当する。これらの半導体素子１はＳｉ半導体素子のみならず、ＳｉＣやＧａＮなどのＷＢＧ半導体素子も適用できる。半導体素子１はおもて面におもて面電極（例えばソース電極やゲート電極）を、裏面に裏面電極（例えばドレイン電極）を備える（いずれも図示せず）。   The semiconductor element 1 corresponds to a vertical power semiconductor element such as, for example, a power MOSFET, IGBT (insulated gate bipolar transistor), or FWD (reflux diode). These semiconductor elements 1 can be applied not only to Si semiconductor elements but also to WBG semiconductor elements such as SiC and GaN. The semiconductor element 1 includes a front surface electrode (for example, a source electrode or a gate electrode) on the front surface and a back surface electrode (for example, a drain electrode) on the back surface (both not shown).

絶縁回路基板２は、回路板３、絶縁板４及び金属板５の積層構造で構成されている。回路板３は絶縁板４の第１の主面（図では上面）に固定されている。回路板３はＣｕやＡｌなどの金属で構成され、パワー半導体モジュール５０に必要な所定の回路が形成されている。また回路板３は半導体素子１の裏面電極とはんだや金属焼結材などの導電性の接合材を介して接合されており、半導体素子１の絶縁回路基板２への固定、及び裏面電極と回路板３との電気的接続が確保されている。   The insulated circuit board 2 has a laminated structure of a circuit board 3, an insulating board 4 and a metal plate 5. The circuit board 3 is fixed to the first main surface (the upper surface in the figure) of the insulating plate 4. The circuit board 3 is made of a metal such as Cu or Al, and a predetermined circuit necessary for the power semiconductor module 50 is formed. The circuit board 3 is bonded to the back electrode of the semiconductor element 1 through a conductive bonding material such as solder or a metal sintered material, and the semiconductor element 1 is fixed to the insulated circuit board 2 and the back electrode and circuit are connected. Electrical connection with the plate 3 is ensured.

絶縁板４はＡｌ２Ｏ３やＡｌＮ、Ｓｉ３Ｎ４などのセラミックスを主材として構成されている。絶縁板４は半導体素子１や回路板３へ印加される高い電圧に対し、外部との絶縁性を確保する目的で配置される。 The insulating plate 4 is mainly composed of ceramics such as Al 2 O 3 , AlN, Si 3 N 4 . The insulating plate 4 is disposed for the purpose of ensuring insulation from the outside against a high voltage applied to the semiconductor element 1 and the circuit board 3.

金属板５は、絶縁板４の第１の主面に対向する第２の主面（図では下面）に固定されている。金属板５はＣｕやＡｌなどの金属で構成される。   The metal plate 5 is fixed to a second main surface (the lower surface in the figure) facing the first main surface of the insulating plate 4. The metal plate 5 is made of a metal such as Cu or Al.

絶縁板４の両主面への回路板３及び金属板５の接合は、例えばＤＣＢ（Ｄｉｒｅｃｔ Ｃｏｐｐｅｒ Ｂｏｎｄｉｎｇ）法やＤＡＢ（Ｄｉｒｅｃｔ Ａｌｕｍｉｎｕｍ Ｂｏｎｄｉｎｇ）法を適用することができる。   For example, a DCB (Direct Copper Bonding) method or a DAB (Direct Aluminum Bonding) method can be applied to the joining of the circuit plate 3 and the metal plate 5 to both main surfaces of the insulating plate 4.

絶縁回路基板２の金属板５はベース板６の主面上に、はんだや金属焼結材などの接合材を用いて接合されている。ベース板６はＣｕやＡｌ、ＡｌＳｉＣなどの熱伝導性の大きい金属で構成され、半導体素子１から発生する高熱を外部へ効率的に放出する目的で配置される。   The metal plate 5 of the insulated circuit board 2 is joined to the main surface of the base plate 6 using a joining material such as solder or a metal sintered material. The base plate 6 is made of a metal having high thermal conductivity such as Cu, Al, or AlSiC, and is disposed for the purpose of efficiently releasing high heat generated from the semiconductor element 1 to the outside.

接続部材９はＣｕやＡｌなどの金属で構成され、回路板３と半導体素子１のおもて面電極の間、回路板３の各回路パターン間などを電気的に接続する目的で配置される。接続部材９はボンディングワイヤやリードフレームで構成可能であるが、本実施例ではリードフレームを用いている。   The connection member 9 is made of a metal such as Cu or Al, and is disposed for the purpose of electrically connecting the circuit board 3 and the front surface electrode of the semiconductor element 1, between circuit patterns of the circuit board 3, and the like. . The connecting member 9 can be composed of a bonding wire or a lead frame. In this embodiment, a lead frame is used.

外部端子１０は、ＣｕやＡｌなどの金属で構成され、回路板３にはんだや金属焼結材などの接合材を介して接合されている。外部端子１０は、外部電源からの電力や信号の入力、外部への電力や信号の出力などのために配置される。   The external terminal 10 is made of a metal such as Cu or Al, and is joined to the circuit board 3 via a joining material such as solder or a metal sintered material. The external terminal 10 is disposed for input of power and signals from an external power source, output of power and signals to the outside, and the like.

ケース１１は第１主面及び第１主面に対向する第２主面の両主面に開口部を有する枠形状であり、第１主面側の第１の開口部（図では下面）を覆うようにベース板６が固定されている。またケース１１の第２主面側の第２の開口部（図では上面）を覆うように蓋１２が固定されている。このようにベース板６、ケース１１および蓋１２は一体となってパワー半導体モジュール５０の筐体を構成している。ケース１１及び蓋１２は、ＰＰＳ（Ｐｏｌｙ Ｐｈｅｎｙｌｅｎｅ Ｓｕｌｆｉｄｅ）樹脂などの耐熱性および耐トラッキング性が高い樹脂で構成されている。さらにケース１１の外部には、外部端子１０の間および外部端子１０とベース板６との絶縁のため、ヒダ構造を設けることもできる。   The case 11 has a frame shape having openings on both the first main surface and the second main surface opposite to the first main surface, and the first opening on the first main surface side (the lower surface in the drawing) is provided. A base plate 6 is fixed so as to cover. A lid 12 is fixed so as to cover the second opening (upper surface in the figure) on the second main surface side of the case 11. As described above, the base plate 6, the case 11, and the lid 12 together constitute a casing of the power semiconductor module 50. The case 11 and the lid 12 are made of a resin having high heat resistance and tracking resistance such as PPS (Polyphenylene Sulfide) resin. Further, a pleated structure can be provided outside the case 11 for insulation between the external terminals 10 and between the external terminals 10 and the base plate 6.

なお各構成部材の接合面には、必要に応じてＮｉ−Ｐ、Ａｕ、Ａｇめっきなどで構成された薄膜が形成されている。   A thin film made of Ni—P, Au, Ag plating or the like is formed on the bonding surfaces of the constituent members as necessary.

パワー半導体モジュール５０の筐体内部は、硬質樹脂７及び軟質樹脂８で封止されている。硬質樹脂７は例えばエポキシ樹脂などの弾性率が１０８Ｎ／ｍ２以上の熱硬化性樹脂で構成され、高い絶縁性および耐熱性を有する。なお硬質樹脂７はエポキシ系樹脂に限定されるものではなく、絶縁性および耐熱性を有する硬質樹脂であれば良く、ポリイミド樹脂、シリコーン樹脂、フェノール樹脂、アミノ樹脂やこれらの混合樹脂を用いることもできる。 The inside of the housing of the power semiconductor module 50 is sealed with a hard resin 7 and a soft resin 8. The hard resin 7 is made of a thermosetting resin having an elastic modulus of 10 8 N / m 2 or more, such as an epoxy resin, and has high insulation and heat resistance. The hard resin 7 is not limited to an epoxy resin, and may be any hard resin having insulating properties and heat resistance. A polyimide resin, a silicone resin, a phenol resin, an amino resin, or a mixed resin thereof may be used. it can.

軟質樹脂８は例えばシリコーン樹脂などのゲル状樹脂で構成され、高い絶縁性および耐熱性を有する。さらに軟質樹脂８は弾性率が１０６Ｎ／ｍ２以下であり、硬質樹脂７よりも軟らかいため、パワー半導体モジュール筐体内の封止樹脂に起因する残留応力を小さくすることができる。なお軟質樹脂８はシリコーン系樹脂に限定されるものではなく、絶縁性および耐熱性を有するゲル状の樹脂であれば良く、ポリイミド樹脂、ポリアミド樹脂、エポキシ樹脂、フェノール樹脂、アミノ樹脂やこれらの混合樹脂を用いることもできる。 The soft resin 8 is made of, for example, a gel resin such as a silicone resin, and has high insulation and heat resistance. Furthermore, since the elastic modulus of the soft resin 8 is 10 6 N / m 2 or less and is softer than the hard resin 7, the residual stress caused by the sealing resin in the power semiconductor module housing can be reduced. Note that the soft resin 8 is not limited to a silicone-based resin, and may be any gel-like resin having insulating properties and heat resistance, such as polyimide resin, polyamide resin, epoxy resin, phenol resin, amino resin, and a mixture thereof Resin can also be used.

図１で示す通り、本実施例では絶縁板４の端部、絶縁板４の端部に隣接した回路板３の端部、絶縁板４の端部に隣接した金属板５の端部、半導体素子１のおもて面及び接続部材９が硬質樹脂７で一体に被覆されている。すなわち前述の三重点Ｙ（絶縁板４、回路板３の端部および封止樹脂が接する点）のみならず、絶縁板４の端部及び前述の三重点Ｘ（絶縁板４、金属板５の端部および封止樹脂が接する点）もすべて硬質樹脂７で被覆されている。これにより、電界が集中する三重点Ｘ、Ｙのいずれでも放電トリーの進展を抑制することができる。さらに回路板３の端部から絶縁板４の端部を通じて金属板５の端部に繋がる沿面破壊を防止することができる。   As shown in FIG. 1, in this embodiment, the end of the insulating plate 4, the end of the circuit board 3 adjacent to the end of the insulating plate 4, the end of the metal plate 5 adjacent to the end of the insulating plate 4, and the semiconductor The front surface of the element 1 and the connection member 9 are integrally covered with the hard resin 7. That is, not only the triple point Y (the point where the insulating plate 4 and the end of the circuit board 3 and the sealing resin are in contact), but also the end of the insulating plate 4 and the triple point X (the insulating plate 4 and the metal plate 5). The point where the end and the sealing resin are in contact with each other) is also covered with the hard resin 7. Thereby, the progress of the discharge tree can be suppressed at any of the triple points X and Y where the electric field concentrates. Furthermore, creeping damage that connects the end of the circuit board 3 to the end of the metal plate 5 through the end of the insulating plate 4 can be prevented.

また硬質樹脂７により、高電圧が印加される半導体素子１および接続部材９も一体に被覆されている。このように樹脂による封止工程を別途設けることなく、高電圧が印加される筐体内の部材を硬質樹脂７で一体に被覆することができることから、コストアップすること無くさらなる高耐電圧化が可能となる。このように、本実施例では図６や図８に記載の従来例よりも高い耐電圧特性を実現することができる。   Further, the semiconductor element 1 and the connection member 9 to which a high voltage is applied are also integrally covered with the hard resin 7. In this way, since a member in the casing to which a high voltage is applied can be integrally covered with the hard resin 7 without separately providing a sealing step with a resin, it is possible to further increase the withstand voltage without increasing the cost. It becomes. Thus, in this embodiment, it is possible to realize a higher withstand voltage characteristic than the conventional examples shown in FIG. 6 and FIG.

さらに図７で示す従来例と異なり、硬質樹脂７を被覆する軟質樹脂８を同時に用いている。このように筐体内の封止樹脂における硬質樹脂７の使用量を低減させているため、パワー半導体モジュール筐体内の封止樹脂に起因する残留応力を低減させることができる。このため封止樹脂とその他の構成部材との間の界面剥離や、封止樹脂自体の割れの発生を防止することができる。   Further, unlike the conventional example shown in FIG. 7, a soft resin 8 covering the hard resin 7 is simultaneously used. Thus, since the usage-amount of the hard resin 7 in the sealing resin in a housing | casing is reduced, the residual stress resulting from the sealing resin in a power semiconductor module housing | casing can be reduced. For this reason, generation | occurrence | production of the interface peeling between sealing resin and another structural member and generation | occurrence | production of the crack of sealing resin itself can be prevented.

このように高い耐電圧特性と低い残留応力を両立させることができることから、高い信頼性を有するパワー半導体モジュール実現することができる。   Thus, since it is possible to achieve both high withstand voltage characteristics and low residual stress, a power semiconductor module having high reliability can be realized.

次に実施例１に係るパワー半導体モジュールの製造工程について述べる。   Next, the manufacturing process of the power semiconductor module according to the first embodiment will be described.

ベース板６上に絶縁回路基板２を、絶縁回路基板２上に半導体素子１を接合材で接合した後、接続部材９と外部端子１０を半導体素子１や回路板３にはんだや超音波などで接合する。接続部材９と外部端子１０をはんだで接合する場合、半導体素子１と絶縁回路基板２の接合時に同時に接合することも可能である。   After the insulating circuit board 2 is bonded to the base plate 6 and the semiconductor element 1 is bonded to the insulating circuit board 2 with a bonding material, the connection member 9 and the external terminal 10 are connected to the semiconductor element 1 and the circuit board 3 with solder, ultrasonic waves, or the like. Join. When the connection member 9 and the external terminal 10 are joined by soldering, it is possible to join the semiconductor element 1 and the insulated circuit board 2 at the same time.

次にベース板６の主面の外縁部に、枠状のケース１１を接着材で接着する。   Next, the frame-shaped case 11 is bonded to the outer edge of the main surface of the base plate 6 with an adhesive.

ケース１１を接着した後、硬質樹脂７として例えばエポキシ系の熱硬化性樹脂を筐体内の接続部材９が覆われる高さまで注入し、熱処理により硬化させる。この際、絶縁回路基板２はベース板６、半導体素子１、接続部材９および外部端子１０が接合された部位以外、全て硬質樹脂７で被覆されている。硬質樹脂７は金属板５とケース１１の間を満たし、ケース１１の内壁に接するように筐体内を封止している。   After the case 11 is bonded, for example, an epoxy thermosetting resin is injected as the hard resin 7 to a height at which the connection member 9 in the casing is covered, and is cured by heat treatment. At this time, the insulated circuit board 2 is all covered with the hard resin 7 except for the portion where the base plate 6, the semiconductor element 1, the connection member 9 and the external terminal 10 are joined. The hard resin 7 fills the space between the metal plate 5 and the case 11 and seals the inside of the housing so as to contact the inner wall of the case 11.

硬質樹脂７を硬化させた後、蓋１２をケース１１の上部に接着剤で接着する。なお蓋１２には外部端子１０の取出し孔およびゲル状の軟質樹脂８を注入するための孔が具備されており、場合によっては熱膨張した軟質樹脂８を逃がす孔も形成されている。   After the hard resin 7 is cured, the lid 12 is bonded to the upper portion of the case 11 with an adhesive. The lid 12 is provided with a take-out hole for the external terminal 10 and a hole for injecting the gel-like soft resin 8, and in some cases, a hole for allowing the thermally expanded soft resin 8 to escape is also formed.

蓋１２を接着した後、軟質樹脂８として例えばシリコーン系のゲル状樹脂を、筐体内の硬質樹脂７の表面から蓋１２に形成されている孔の高さまで、筐体内部がすべて硬質樹脂７及び軟質樹脂８で満たされるように注入して、筐体内部を封止する。この際、特に筐体内部の各外部端子１０の間を確実に封止するようにする。このようにパワー半導体モジュール５０の筐体内部を硬質樹脂７及び軟質樹脂８で封止することにより、高い絶縁性を確保することができる。   After bonding the lid 12, for example, a silicone-based gel resin is used as the soft resin 8 from the surface of the hard resin 7 in the housing to the height of the hole formed in the lid 12. It inject | pours so that it may fill with the soft resin 8, and the inside of a housing | casing is sealed. At this time, the space between the external terminals 10 in the housing is particularly surely sealed. Thus, by sealing the inside of the housing of the power semiconductor module 50 with the hard resin 7 and the soft resin 8, high insulation can be ensured.

本実施例のパワー半導体モジュールを用いて、絶縁試験を行った結果を図２に示す。   The result of conducting an insulation test using the power semiconductor module of this example is shown in FIG.

絶縁試験の方法は、ベース板６を接地電位とし、外部端子１０の間を短絡して外部端子１０側に周波数６０Ｈｚの交流電圧を印加して実施した。そして印加する交流電圧を０Ｖから徐々に上昇させ、部分放電の発生が開始する電圧、部分放電の放電電荷量が１０ｐＣを超える電圧、絶縁破壊を起こす電圧のそれぞれを測定した。また比較例として、図６に示す構成で封止樹脂を全て軟質樹脂であるシリコーン系樹脂としたパワー半導体モジュールにおいても同じ試験を行った。   The insulation test was performed by setting the base plate 6 to the ground potential, short-circuiting between the external terminals 10, and applying an AC voltage having a frequency of 60 Hz to the external terminal 10 side. Then, the applied AC voltage was gradually increased from 0 V, and the voltage at which partial discharge started, the voltage at which the partial discharge discharge charge exceeded 10 pC, and the voltage at which dielectric breakdown occurred were measured. As a comparative example, the same test was performed on a power semiconductor module having a configuration shown in FIG. 6 in which all of the sealing resin is a silicone resin that is a soft resin.

図２に示す結果から、部分放電が発生する電圧は実施例と比較例で大きな差はないことがわかる。しかしながら比較例は直ぐに放電電荷量が上昇して１０ｐＣを超えたのに対し、実施例で放電電荷量が１０ｐＣを超えたのは、部分放電発生電圧からおよそ２倍の電圧を印加した時点であった。更に印加電圧を上昇させ、絶縁破壊電圧を測定すると、比較例では１４．７ｋＶであったが実施例では２７．１ｋＶとなり、絶縁破壊電圧は２倍近い値に改善した。   From the results shown in FIG. 2, it can be seen that the voltage at which the partial discharge occurs is not significantly different between the example and the comparative example. However, in the comparative example, the discharge charge amount immediately increased and exceeded 10 pC, whereas in the example, the discharge charge amount exceeded 10 pC when a voltage approximately twice the partial discharge generation voltage was applied. It was. When the applied voltage was further increased and the dielectric breakdown voltage was measured, it was 14.7 kV in the comparative example, but 27.1 kV in the example, and the dielectric breakdown voltage was improved to a value nearly doubled.

またそれぞれの絶縁破壊の原因を調べた結果、実施例では絶縁板４のセラミック貫通破壊であったのに対し、比較例では回路板３の端部から金属板５の端部に繋がる沿面破壊であることが分かった。このことから比較例の場合、前述のように放電が発生すると樹脂劣化が急速に進展し、放電トリーが成長することで絶縁破壊に至ると考えられる。一方で本実施例では、比較例のように放電電荷量が直ぐに大きくなることは無く、印加電圧の上昇に応じて放電電荷量が上昇している。このことから部分放電による樹脂劣化が抑制された結果、先に絶縁板４の耐電圧限界に達したためセラミックの貫通破壊が発生したと考えられる。この結果から、本実施例の耐電圧特性の改善が確認できた。   In addition, as a result of investigating the cause of each dielectric breakdown, in the example, it was a ceramic penetration failure of the insulating plate 4, whereas in the comparative example, it was a creeping failure connected from the end of the circuit board 3 to the end of the metal plate 5. I found out. From this, in the case of the comparative example, it is considered that when the discharge occurs as described above, the resin deterioration rapidly progresses and the discharge tree grows to cause a dielectric breakdown. On the other hand, in this embodiment, the amount of discharge charge does not increase immediately as in the comparative example, and the amount of discharge charge increases as the applied voltage increases. From this, it is considered that as a result of suppressing the resin deterioration due to the partial discharge, the withstand voltage limit of the insulating plate 4 was reached first, so that the ceramic penetration failure occurred. From this result, it was confirmed that the withstand voltage characteristic of this example was improved.

パワー半導体モジュールの筐体内部を硬質樹脂で封止した場合の、ベース板と樹脂との界面にかかる最大せん断応力を、解析により求めた結果を図３に示す。なおこの解析における樹脂封止面積は１３０ｍｍ２である。 FIG. 3 shows a result obtained by analyzing the maximum shear stress applied to the interface between the base plate and the resin when the inside of the casing of the power semiconductor module is sealed with a hard resin. The resin sealing area in this analysis is 130 mm 2 .

この結果から、封止する硬質樹脂の厚みを減らすことにより、内部応力が大きく低減できることがわかる。また前述のとおり本実施例により、どのような筐体内部の高さであっても、硬質樹脂７の厚みを絶縁性能が確保できる範囲で薄くすることができる。このため信頼性の高いパワー半導体モジュールが可能となる。
［実施例２］
図４に本発明の実施例２に係る樹脂封止型のパワー半導体モジュール６０の断面図を、図５に軟質樹脂８および蓋１２を除いた状態での平面図を示す。 From this result, it can be seen that the internal stress can be greatly reduced by reducing the thickness of the hard resin to be sealed. Further, as described above, according to the present embodiment, the thickness of the hard resin 7 can be reduced within a range in which the insulating performance can be ensured regardless of the height inside the housing. For this reason, a highly reliable power semiconductor module becomes possible.
[Example 2]
FIG. 4 is a cross-sectional view of a resin-encapsulated power semiconductor module 60 according to the second embodiment of the present invention, and FIG. 5 is a plan view in a state where the soft resin 8 and the lid 12 are removed.

実施例２の構成は、ベース板６の形状および外部端子１０の形状を除き実施例1と同構成であることから、実施例1と異なる点を説明する。   Since the configuration of the second embodiment is the same as that of the first embodiment except for the shape of the base plate 6 and the shape of the external terminals 10, differences from the first embodiment will be described.

ベース板６には、あらかじめ底面が絶縁回路基板２より大きい寸法の凹部１３を設けておく。凹部１３の底面に絶縁回路基板２が固定されている。凹部１３の内側は硬質樹脂７で覆われている。凹部１３の寸法は回路板３の端部から凹部１３の角部までが、硬質樹脂７で封止された際に十分絶縁を確保できる距離となるよう適宜最適な寸法とする。また、凹部１３の深さは、絶縁回路基板２上に接合した半導体素子１、および接続部材９が完全に埋没する寸法が望ましい。すなわち、接続部材９は硬質樹脂７の表面より低く、また凸部表面は硬質樹脂７の表面と高さが等しいか、もしくは高く配置している。しかしながら凹部１３によりベース板６の厚さが薄くなり過ぎると、ベース板６と絶縁回路基板２との線膨張係数差で接合部に変形が起こる場合がある。このように接合部に大きな応力が加わるような場合は、ベース板６の厚さを確保するため、凹部１３の深さを浅くして接続部材９の一部を露出させても良い。   The base plate 6 is provided with a recess 13 whose bottom surface is larger than the insulating circuit board 2 in advance. The insulated circuit board 2 is fixed to the bottom surface of the recess 13. The inside of the recess 13 is covered with the hard resin 7. The dimensions of the recess 13 are appropriately optimized so that the distance from the end of the circuit board 3 to the corner of the recess 13 can be sufficiently secured when sealed with the hard resin 7. In addition, the depth of the recess 13 is desirably a dimension in which the semiconductor element 1 and the connection member 9 bonded on the insulating circuit board 2 are completely buried. That is, the connection member 9 is lower than the surface of the hard resin 7, and the height of the convex surface is equal to or higher than the surface of the hard resin 7. However, if the thickness of the base plate 6 becomes too thin due to the recess 13, the joint may be deformed due to a difference in linear expansion coefficient between the base plate 6 and the insulated circuit board 2. When a large stress is applied to the joint portion in this way, in order to secure the thickness of the base plate 6, the depth of the concave portion 13 may be reduced to expose a part of the connection member 9.

絶縁回路基板２の間を電気的に接続するブリッジ形状の外部端子１０は、ベース板６に設けた凹部１３の間にある凸部表面より、軟質樹脂８で封止した際に十分絶縁が取れる距離を確保した寸法とする。図４では便宜上、各外部端子１０のブリッジ高さを変えているが、図５に記載のように平面方向に絶縁距離が取れる場合、各外部端子１０のブリッジ高さを変える必要はない。
硬質樹脂７による封止を凹部１３の内部のみとすることで、硬質樹脂７による封止面積および厚みを小さくすることができる。このため硬質樹脂７とベース板６の剥離や硬質樹脂７自体の割れを抑制できる。但し凹部１３の間の凸部表面に薄い硬質樹脂層が形成されていても、その厚みが十分薄い場合は残留応力の原因とはならず、同等の信頼性を確保することができる。 The bridge-shaped external terminals 10 that electrically connect the insulated circuit boards 2 can be sufficiently insulated when sealed with the soft resin 8 from the convex surface between the concave portions 13 provided in the base plate 6. The dimensions ensure the distance. In FIG. 4, the bridge height of each external terminal 10 is changed for convenience. However, when the insulation distance can be taken in the plane direction as shown in FIG. 5, it is not necessary to change the bridge height of each external terminal 10.
By sealing with the hard resin 7 only inside the recess 13, the sealing area and thickness of the hard resin 7 can be reduced. For this reason, peeling of the hard resin 7 and the base plate 6 and cracking of the hard resin 7 itself can be suppressed. However, even if a thin hard resin layer is formed on the convex surface between the concave portions 13, if the thickness is sufficiently thin, it does not cause residual stress, and equivalent reliability can be ensured.

なお本発明に係る各実施例では、絶縁回路基板２一枚当たりの半導体素子１の搭載数を一個としたが、実際のモジュールでは半導体素子１が複数個での構成の場合もある。また実施例２においてはベース板６に対して絶縁回路基板２を２枚としたが、絶縁回路基板２が更に多い場合もある。
例えば、いわゆる６ｉｎ１モジュールにおいて絶縁回路基板を各アーム毎に設けると、絶縁回路基板は計６枚必要になる。その場合には、凹部は６個形成して各絶縁回路基板をそれぞれの凹部に搭載してもよい。また凹部を３個形成して、上下アームを形成する２枚の絶縁回路基板を一つの凹部にまとめて搭載してもよい。 In each of the embodiments according to the present invention, the number of semiconductor elements 1 mounted on one insulating circuit board 2 is one, but an actual module may have a plurality of semiconductor elements 1. In the second embodiment, two insulating circuit boards 2 are provided for the base plate 6, but there may be more insulating circuit boards 2.
For example, if an insulating circuit board is provided for each arm in a so-called 6-in-1 module, a total of six insulating circuit boards are required. In that case, six recesses may be formed and each insulating circuit board may be mounted in each recess. Alternatively, three recesses may be formed, and two insulating circuit boards forming upper and lower arms may be mounted together in one recess.

１ 半導体素子
２ 絶縁回路基板
３ 回路板
４ 絶縁板
５ 金属板
６ ベース板
７ 硬質樹脂
８ 軟質樹脂
９ 接続部材
１０ 外部端子
１１ ケース
１２ 蓋
１３ 凹部
５０、６０ パワー半導体モジュール DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Insulation circuit board 3 Circuit board 4 Insulation board 5 Metal plate 6 Base board 7 Hard resin 8 Soft resin 9 Connection member 10 External terminal 11 Case 12 Lid 13 Recess 50, 60 Power semiconductor module

Claims (6)

主面を有するベース板と、
絶縁板、前記絶縁板の第１の主面に固定された回路板、及び、前記絶縁板の第２の主面に固定された金属板を有し、前記金属板の前記絶縁板に固定された面と反対の面が前記ベース板に固定された絶縁回路基板と、
おもて面に電極を有し、裏面が前記回路板に固定された半導体素子と、
前記半導体素子の電極に一端が固定された導電性の接続部材と、
前記絶縁板の端部、前記絶縁板の端部に隣接した前記回路板の端部、前記絶縁板の端部に隣接した前記金属板の端部、前記半導体素子のおもて面、及び前記接続部材を被覆する硬質樹脂と、
前記硬質樹脂よりも弾性率が低く、前記硬質樹脂を被覆する軟質樹脂と、
を備え、
前記ベース板に前記絶縁回路基板より大きい寸法の底面を有する複数の凹部が設けられ、
前記複数の凹部の底面にそれぞれ前記絶縁回路基板が固定され、
前記凹部の内部が前記硬質樹脂で覆われた半導体装置。 A base plate having a main surface;
An insulating plate, a circuit board fixed to the first main surface of the insulating plate, and a metal plate fixed to the second main surface of the insulating plate, and fixed to the insulating plate of the metal plate. An insulated circuit board having a surface opposite to the surface fixed to the base plate ;
A semiconductor element having an electrode on the front surface and a back surface fixed to the circuit board;
A conductive connecting member having one end fixed to the electrode of the semiconductor element;
An end portion of the insulating plate; an end portion of the circuit board adjacent to the end portion of the insulating plate; an end portion of the metal plate adjacent to an end portion of the insulating plate; A hard resin covering the connecting member;
A lower elastic modulus than the hard resin, and a soft resin covering the hard resin;
Equipped with a,
The base plate is provided with a plurality of recesses having a bottom surface dimension larger than the insulated circuit board,
The insulated circuit boards are respectively fixed to the bottom surfaces of the plurality of recesses,
A semiconductor device in which the inside of the recess is covered with the hard resin . 前記硬質樹脂が前記凹部の内部のみ封止していることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the hard resin seals only the inside of the recess. 外部端子が、前記絶縁回路基板間を電気的に接続し、前記凹部間にある凸部表面より上で軟質樹脂に封止されていることを特徴とする請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein an external terminal electrically connects the insulated circuit boards and is sealed with a soft resin above the surface of the convex portion between the concave portions. . 主面に第１の開口部、前記主面との対向面に第２の開口部を有し、第１の開口部を覆うように前記ベース板が固定された枠状のケースと、A frame-shaped case having a first opening on a main surface and a second opening on a surface facing the main surface, and the base plate fixed to cover the first opening;
前記ケースの第２の開口部を覆うように固定された蓋を備え、A lid fixed to cover the second opening of the case;
前記ベース板、前記ケース及び前記蓋により筐体が構成され、A casing is constituted by the base plate, the case and the lid,
前記筐体の内部は前記硬質樹脂及び前記軟質樹脂で封止されていることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the inside of the housing is sealed with the hard resin and the soft resin. 前記硬質樹脂は熱硬化性樹脂であり、前記軟質樹脂はゲル状樹脂であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the hard resin is a thermosetting resin, and the soft resin is a gel resin. 前記半導体素子は、ワイドバンドギャップ半導体素子であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor element is a wide band gap semiconductor element.
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