JP6394716B2 - Liquid crystal display device and method for inspecting liquid crystal display device - Google Patents

Description

The present invention relates to a liquid crystal display device and a liquid crystal display device inspection method, and more particularly, to a liquid crystal display device and a liquid crystal inspection method that enable downsizing of constituent pixels and enable accurate pixel inspection.

Conventionally, a sub-frame driving method is known as one of halftone display methods in a liquid crystal display device. In the subframe driving method, which is a type of time axis modulation method, a predetermined period (
For example, in the case of a moving image, each frame is divided into a plurality of subframes, and the subframes are combined in accordance with the gradation to be displayed to drive each pixel. Do. The gradation to be displayed is determined by the ratio of the pixel driving period occupying within a predetermined period. The ratio of the pixel driving period within the predetermined period is determined by the combination of the divided subframes.

As a liquid crystal display device adopting the sub-frame driving method as described above, for example, Patent Document 1
Each pixel has a master latch, a slave latch, a liquid crystal display element,
And what is comprised from a total of three switching transistors of the 1st-3rd is known.

In this case, in each pixel, the master latch applies one bit of first data through the first switching transistor to one of the two input terminals, and applies to the other input terminal. On the other hand, 1-bit second data having a complementary relationship with the first data is applied through the second switching transistor. When a target pixel is selected based on application of a row selection signal through the row scanning line, the first switching transistor and the second switching transistor are turned on, and the first data is written. When the first data has a logical value “1” and the second data has a logical value “0”, the pixel performs display based on the data.

After each data is written to all the pixels by the above-described operation within a certain subframe period, the third switching transistors of all the pixels are turned on within the subframe period. The data written in the master latch is simultaneously read out to the slave latch. The slave latched data is applied to the pixel electrode of the liquid crystal display element.
Data latched by the slave latch is applied. The series of operations described above is repeated for each subframe, and a desired gradation display is performed based on a combination of all subframes within one frame period.

That is, in the liquid crystal display device adopting the subframe driving method, the same or different predetermined display period is assigned to each subframe for all the subframes existing in one frame period. Each pixel performs white display (displayed) in all subframes during maximum gradation display, and does not perform white display (not displayed) in all subframes during minimum gradation display. In other words, the display is black. In cases other than the maximum gradation display and the minimum gradation display, the subframe to be displayed is selected according to the displayed gradation. In addition,
In this conventional liquid crystal display device, input data is digital data indicating gradation, and a digital driving system having a two-stage latch configuration is used.

JP-T-2001-523847

However, in the conventional liquid crystal display device described above, the two latches in each pixel are respectively
Since it is composed of a so-called SRAM (Static Random Access Memory), the number of transistors constituting the circuit increases. Therefore, there is a problem that it is difficult to reduce the size of the pixel.

In addition, each pixel of the above-described conventional liquid crystal display device usually uses a silicon backplane that constitutes a circuit including a shift register, which is a large-scale semiconductor integrated circuit (LSI: Lar).
ge Scale Integrated circuit) process. In the probe inspection after the wafer is created, there is a problem that the pixel inspection cannot be normally performed. The problem is that when pixel inspection is performed, data is input from the column data line to the SRAM in order to check whether the data has been normally written after the data is input to the column data line and the input data is written to the SRAM. This occurs because data is read out, but the SRAM may be rewritten by the charge accumulated in the column data line at this time.

In addition to the discussion so far, the liquid crystal display device described in Patent Document 1 described above is a two-switch type SRAM having two complementary bit lines. However, as a related art, one bit line and one 1 A problem when a one-switch type SRAM composed of two switches is employed will also be described.

For example, in the case of a liquid crystal display device having a so-called full high definition (FHD) resolution,
The number of pixels in the vertical direction of the screen is 1080 pixels, and the capacity of each column data line is about 1 pF. For example, the column data line is set to 0 V at the “L” level. And, for example, the SRAM includes a switching transistor connected to the column data line, and the input terminals of the first inverter are connected to the output terminal of the second inverter, and the input terminal of the second inverter is the first.
The voltage of the input terminal of the inverter connected to the switching transistor among the two inverters connected to the input terminal of the inverter is 3.3 V at the “H” level.
In this case, when the switching transistor is turned on for the purpose of reading the data written in the SRAM for pixel inspection from the column data line, the other inverter whose output terminal is connected to the switching transistor is connected to the switching transistor. A charge capacity of about 1 pF is charged from a power source through a P-channel MOS (Metal Oxide Semiconductor) type field effect transistor (hereinafter referred to as a PMOS transistor).

At this time, since the driving force of the transistor constituting the other inverter is smaller than the driving force of the transistor constituting the one inverter, the charging time tends to be longer. For this reason, the voltage at the input terminal of the one of the inverters tends to be lower than the inverted voltage without the necessary charging being performed completely. Then, the voltage at the input terminal of the one inverter, that is, the data to be written in the SRAM is rewritten. For this reason, there is a problem that the data of the SRAM cannot be output to the column data line, and the accurate pixel inspection cannot be performed.

The present invention has been made in view of the above points, and enables downsizing of the constituent pixels,
An object of the present invention is to provide a liquid crystal display device and a pixel inspection method thereof capable of accurately performing pixel inspection.

In order to achieve the above object, the present invention provides a liquid crystal display device comprising a plurality of pixels provided at each intersection where a plurality of column data lines and a plurality of row scanning lines intersect, wherein the pixels The display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode, and each frame data of the input video signal is displayed using a plurality of subframes whose display period is shorter than one frame period. A first switching unit that performs sampling for the first data through the column data line; and a first switching unit that configures an SRAM together with the first switching unit, and the first switching unit holds the sampled subframe data. A holding unit, a second switching unit for outputting the subframe data held by the first holding unit, and a DRAM together with the second switching unit. And a second holding unit that rewrites the stored content by the subframe data held in the first holding unit input through the second switching unit and applies output data to the pixel electrode; The sub-frame data is repeatedly written to the first holding unit in units of rows in the plurality of pixels, and after the sub-frame data is written to all of the plurality of pixels, the plurality of pixels are generated by a trigger pulse. An operation of turning on all the second switching units and rewriting the storage contents of the second holding unit of the plurality of pixels by the subframe data held in the first holding unit for each subframe. A sense amplifier to which a first fixed data line is connected and a predetermined fixed voltage is applied. To provide a liquid crystal display device, characterized in that it comprises a.

In order to achieve the above object, the present invention provides the above-described inspection method for a liquid crystal display device, comprising: inputting a 1-bit inspection signal to the first data line connected to the pixel; Latching the inspection signal in the SRAM of the pixel, supplying the latched inspection signal to the first data line, the supplied inspection signal, and the predetermined signal And a step of amplifying a potential difference based on a fixed voltage by the sense amplifier. A method for inspecting a liquid crystal display device is provided.

According to the present invention, it is possible to provide a liquid crystal display device and a pixel inspection method thereof capable of downsizing the constituent pixels and enabling accurate pixel inspection.

1 is an overall configuration diagram of a liquid crystal display device 1 according to an embodiment of the present invention. 1 is a circuit diagram according to a first embodiment of the present invention. It is a circuit diagram of an example of an inverter concerning an embodiment of the invention. It is an example of the cross-section figure of the pixel 12 which concerns on embodiment of this invention. 4 is a timing chart for explaining a write / read operation of the pixel 12 of the liquid crystal display device 1 according to the embodiment of the present invention. It is explanatory drawing of the multiplexing as the binary weighted pulse width modulation data of the saturation voltage and the threshold voltage of a liquid crystal of the liquid crystal of the liquid crystal display device 1 which concerns on embodiment of this invention. It is a block diagram of the sense amplifier circuit which concerns on embodiment of this invention. 6 is a timing chart for explaining operations of pixel inspection according to the embodiment of the present invention. FIG. 3 is a schematic diagram of a pixel circuit for explaining a case where the DRAM of the liquid crystal display device 1 according to the embodiment of the present invention is turned on and off.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device 1 according to an embodiment of the present invention. The liquid crystal display device 1 includes an image display unit in which a plurality of pixels 12 are regularly arranged, a timing generator, a vertical shift register, a data latch circuit, a horizontal driver, a sense amplifier, a pixel readout shift register, Consists of

The horizontal driver includes a horizontal shift register, a latch circuit, and a level shifter / pixel driver. The pixel readout shift register is a shift register having a number of stages corresponding to the number of pixels for one row.

The image display unit has one end connected to the vertical shift register and extends in the row direction (X direction).
One (m is a natural number of 2 or more) row scanning lines g1 to gm, and n (n is a natural number of 2 or more) columns that have one end connected to the level shifter / pixel driver and extend in the column direction (Y direction). Data line d1
~ Dn are provided at each intersection where they intersect and are arranged in a two-dimensional matrix, respectively (
m × n) / 2 pixels 12 (in FIG. 1, the image display unit is indicated by a block surrounded by a broken line). All the pixels 12 in the image display unit are commonly connected to trigger pulse trigger lines trig and trigb, one end of which is connected to the timing generator.

The forward trigger pulse transmitted by the forward trigger pulse trigger line trig and the inverted trigger pulse transmitted by the inverted trigger pulse trigger line trigb are always in an inverse logical value relationship (complementary relationship).

The timing generator receives a vertical synchronization signal Vst, a horizontal synchronization signal Hst,
An external signal such as a basic clock CLK is received as an input signal. The timing generator then generates an AC signal FR, V start pulse VST, H based on these external signals.
Start pulse HST, clock signal VCK and clock signal HCK, latch pulse LT
, Trigger pulse trig / trigb, pixel readout shift register clock signal TC
Various internal signals such as K / TCKb are generated.

Among the internal signals, the AC signal FR is a signal whose polarity is inverted every subframe. The AC signal FR is supplied as a common electrode voltage Vcom, which will be described later, to the common electrodes of the liquid crystal display elements in the pixels 12A and 12B constituting the image display unit. Start pulse VS
T is a pulse signal output at the start timing of each subframe described later. Subframe switching is controlled by this start pulse VST.

The start pulse HST is a pulse signal output at the start timing input to the horizontal shift register. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register, and the vertical shift register performs a shift operation in accordance with the timing of the clock signal VCK. The clock signal HCK is a shift clock in the horizontal shift register, and is a signal for shifting data with a 32-bit width. The latch pulse LT is a pulse signal that is output at a timing when the horizontal shift register has finished shifting data corresponding to the number of pixels in one row in the horizontal direction.

Further, the timing generator supplies the normal trigger pulse to all the pixels 12 in the image display section through the normal trigger pulse trigger line trig and the reverse trigger pulse through the reverse trigger pulse trigger line trigger. The forward trigger pulse and the reverse trigger pulse are sequentially output to the first signal holding means (not shown in FIG. 1) provided in the pixel 12 in the image display unit immediately after the data writing is completed. Is done. Then, within the sub-frame period, the data of the first signal holding means of all the pixels 12 in the image display unit is within the same pixel (
The signal is transferred at a time to the second signal holding means (not shown in FIG. 1). The first signal holding means and the second signal holding means will be described in detail later.

The vertical shift register transfers the V start pulse VST supplied at the beginning of each subframe in accordance with the clock signal VCK. The vertical shift register sequentially supplies row scanning signals to the row scanning lines g1 to gm sequentially in 1H units. The vertical shift register supplies row scanning lines to all the row scanning lines g1 to gm in one frame period. As a result, in one frame period, the row scanning lines are sequentially selected in units of 1H from the uppermost row scanning line g1 to the lowermost row scanning line gm in the image display unit.

The data latch circuit latches 32-bit width data divided for each subframe supplied from an external circuit (not shown) based on the basic signal CLK from the host device, and then synchronizes with the basic signal CLK. Output to the shift register.

In this embodiment, one frame of a video signal is divided into a plurality of subframes having a display period shorter than one frame period of the video signal, and gradation display is performed by a combination of the subframes. In the above-described pixel and a higher-order component circuit outside the peripheral circuit, the gradation data indicating the gradation for each pixel of the video signal is displayed for each gradation for displaying the gradation of each pixel in the entire plurality of subframes. It is converted into 1-bit subframe data in units of subframes. Then, in the upper configuration circuit outside these pixels and peripheral circuits, the sub-frame data for 32 pixels in the same sub-frame is further supplied to the data latch circuit as the 32-bit width data.

When viewed in the processing system of 1-bit serial data, the horizontal shift register starts shifting by the H start pulse HST supplied first from the timing generator and clocks the 32-bit width data supplied from the data latch circuit. Shift in synchronization with the signal HCK. The latch circuit has a horizontal shift register n equal to the number n of pixels for one row of the image display unit.
At the time when the data for bits has been shifted, the data for n bits supplied in parallel from the horizontal shift register in accordance with the latch pulse LT supplied from the timing generator (that is, subframe data for n pixels in the same row) Are latched and output to the level shifter of the level shifter / pixel driver.

When the data transfer to the latch circuit is completed, the H start pulse is output again from the timing generator, and the horizontal shift register resumes shifting the 32-bit width data from the data latch circuit in accordance with the clock signal HCK.

A level shifter provided in the level shifter / pixel driver shifts the signal level of n subframe data corresponding to n pixels in one row supplied by being latched by the latch circuit to the liquid crystal driving voltage. A pixel driver provided in the level shifter / pixel driver outputs n subframe data corresponding to n pixels in one row after the level shift to n column data lines d1 to dn in parallel.

The horizontal shift register, the latch circuit, and the level shifter / pixel driver that constitute the horizontal driver output data for the pixel row in which data is written this time within 1H,
Shifting of data relating to pixel rows in which data is written in H is performed in parallel. In a certain horizontal scanning period, the latched n subframe data for one row are simultaneously output in parallel to the n column data lines d1 to dn as data signals.

Here, the column data lines d1 to dn are connected to a sense amplifier, a weak potential signal difference is amplified and converted into VDD and GND signals (where VDD is a power supply voltage and GND is a reference voltage),
For each of the converted pixel inspection signals, when TEST is turned on, pixel inspection signals for the number of pixels that are half of 1H are stored in the pixel readout shift register all at once. Thereafter, TEST is turned off, and a pixel inspection signal is latched in the pixel readout shift register. The pixel readout shift register clock signal TCK is a clock for transferring a signal input from a sense amplifier arranged for every two column data lines. Signals subjected to pixel inspection according to TCK / TCKb are sequentially read out serially from the output terminal TOUT.

Of the plurality of pixels 12 constituting the image display unit, one row of pixels 12 selected by the row scanning signal from the vertical shift register is n pieces of one row output simultaneously from the level shifter / pixel driver. The subframe data is sampled through the n data lines d1 to dn and written in first signal holding means (to be described later) in each pixel 12 (not shown in FIG. 1).

Next, each embodiment of the pixel 12 of the liquid crystal display device of the present invention will be described in detail.
(First embodiment)
One of the many aspects of the present invention will be described below as a first embodiment. An equivalent circuit of the pixel 12 of the liquid crystal display device 1 according to the present embodiment is shown in FIG. 2 together with a sense amplifier of the surrounding pixel inspection circuit. In FIG. 2, a pixel 12 is a pixel connected to an arbitrary row scanning line g in FIG. 1, and the pixel 12 is provided at an intersection between an arbitrary column data line d and an arbitrary row scanning line g. . The column data line d is connected to one input of the sense amplifier, and the other input of the sense amplifier is connected to a wiring mid for inputting a fixed voltage. The sense amplifier is a circuit that amplifies a weak potential difference input from the column data line d and the wiring mid.
The wiring mid can supply an arbitrary analog voltage from the host device. Usually V
DD / 2 is adjusted to an intermediate voltage between the power supply voltage and the reference voltage.

The pixel 12 includes a switch SW11 that is a first switching unit, a first holding unit SM121 that holds a signal (data) according to the on / off state of the switch SW11, a switch SW12 that is a second switching unit, and a switch SW12. The capacitor C11 is a second holding unit that holds a signal according to ON / OFF, the reflective electrode PE1 and the liquid crystal LC1 that are pixel electrodes, and the CE that is a common electrode. The first holding means SM121 includes an inverter INV11 and an inverter INV12. Switch SW11 and first holding means SM12
1 constitutes an SRAM (Static Random Access Memory) (SRAM 1 in FIG. 2).
. The switch SW12 and the capacitor C11 constitute a DRAM (Dynamic Random Access Memory) (DM122 in FIG. 2).

The switch SW11 has a gate commonly connected to the row scanning line g and a drain connected to the column data line d.
And an N channel MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as an NMOS transistor) whose source is connected to the input terminal of the first signal holding means SM121. The first signal holding means SM121 includes two inverters INV11 and INV whose one output terminal is connected to the other input terminal.
This is a self-holding memory consisting of 12.

The inverter INV11 has an input terminal connected to the output terminal of the inverter INV12 and SW11.
Is connected to the source of the NMOS transistor constituting the. The input terminal of the inverter INV12 is connected to the switch SW12 and the output terminal of the inverter INV11.

The inverter INV11, the inverter INV12, the inverter INV21, and the inverter INV22 are all P-channel MOS transistors (hereinafter referred to as PMOS transistors) in which the gates and the drains are connected as shown in FIG. CMOS (Complementary Metal) consisting of PTr and NMOS transistor NTr
Oxide Semiconductor) The inverter configuration is designed so that the drive power of each inverter is different.

That is, the transistor in the input-side inverter INV11 constituting the first signal holding means SM121 as viewed from the switch SW11 is the output-side inverter constituting the first signal holding means SM121 as seen from the switch SW11. A transistor having a larger driving capability than that of the transistor in the INV 12 is used. Further, the NMOS transistor that constitutes the switch SW11 uses a transistor having a larger driving force than the NMOS transistor that constitutes the inverter INV12.

This is because when the voltage on the input side of the switch SW11 is at the “H” level, the current flowing through the switch SW11 is increased on the output side in order for the voltage to reach more than the magnitude that the transistor on the input side of the inverter INV11 is inverted. NM constituting the transistor of the inverter INV12
This is because the current needs to be larger than the current flowing through the OS transistor.

As described above, the driving force of the NMOS transistor constituting the switch SW11 needs to be larger than the driving force of the NMOS transistor constituting the inverter INV12. For this reason, the transistor size of the NMOS transistor constituting the switch SW11 and the transistor size of the NMOS transistor constituting the inverter INV12 need to be determined in consideration of this.

The switch SW12 has a transmission gate configuration composed of an NMOS transistor and a PMOS transistor in which the respective drains are connected to each other and the sources are connected to each other. The gate of the NMOS transistor is connected to the normal trigger pulse trigger line trigger, and the gate of the PMOS transistor is connected to the inverted trigger pulse trigger line trigger.

The switch SW12 has one terminal connected to the first signal holding unit SM121 and the other terminal connected to the capacitor C11 and the reflective electrode PE1 of the liquid crystal display element LCM1.

Accordingly, the switch SW12 indicates that the normal trigger pulse supplied via the normal trigger pulse trigger line trig is at the “H” level (in this case, the reverse trigger pulse trigger line trig).
When the inversion trigger pulse supplied via b is “L” level, it is turned on.
The data stored in the signal holding means SM121 is read out and transferred to the capacitor C11 and the reflective electrode PE1. Further, the switch SW12 indicates that the normal trigger pulse supplied via the normal trigger pulse trigger line trig is at the “L” level (in this case, the reverse trigger pulse trigger line tr
When the inversion trigger pulse supplied via igb is “H” level, it is turned off,
The data stored in the first signal holding means SM121 is not read.

Since the switch SW12 has a transmission gate configuration as described above, a voltage in the range from GND to VDD can be turned on / off. That is, when the signal applied to the gates of the NMOS transistor and the PMOS transistor constituting the transmission gate is the GND side potential ("L" level), the PMOS transistor cannot be turned on, but the NMOS transistor is low. It can be conducted with resistance. On the other hand, when the gate input signal is at the VDD side potential (“H” level), the NMOS transistor cannot be turned on, but the PMOS transistor can be turned on with a low resistance.

Therefore, the normal rotation trigger pulse supplied via the trigger line trig and the trigger line trig
The voltage range from GND to VDD can be switched with low resistance and high resistance by ON / OFF control of the transmission gate constituting the switch SW12 by the inversion trigger pulse supplied via b.

The capacitor C11 constitutes a DM122 DRAM together with the switch SW12. here,
When the storage data of the first signal holding means SM121 and the storage data of the capacitor C11 are different, the switch SW12 is turned on, and when the storage data of the SM 121 is transferred to the capacitor C11, the storage data of the capacitor C11 is It is necessary to replace the data stored in the first signal holding means SM121.

When the retained data in the capacitor C11 is rewritten, the retained data changes due to charging or discharging. The charge / discharge of the capacitor C11 is driven by the output signal of the inverter INV11. When the data held in the capacitor C11 is rewritten from “L” level to “H” level by charging, the output signal of the inverter INV11 is at “H” level. At this time, the PMOS transistor (PTr in FIG. 3) constituting the inverter INV11 is turned on, NM
Since the OS transistor (NTr in FIG. 3) is turned off, the PM of the inverter INV11
The capacitor C11 is charged by the power supply voltage VDD connected to the source of the OS transistor.

On the other hand, when the data held in the capacitor C11 is rewritten from “H” level to “L” level by discharging, the output signal of the inverter INV11 is at “L” level. At this time, the NMOS transistor (NTr in FIG. 3) constituting the inverter INV11 is turned on, and the PMOS
Since the transistor (PTr in FIG. 3) is turned off, the charge stored in the capacitor C11 is discharged to GND through the NMOS transistor (NTr in FIG. 3) of the inverter INV11.

Since the switch SW12 has an analog switch configuration using the transmission gate described above, the capacitor C11 can be charged and discharged at high speed.
Further, in the present embodiment, the driving force of the inverter INV11 is set to be larger than the driving force of the inverter INV12, so that the capacitor C11 can be charged / discharged at high speed.
When the switch SW12 is turned on, the electric charge stored in the capacitor C11 is converted to the inverter I
This also affects the input gate of NV12, but inverter IV12 has inverter I
By setting the driving force of NV11 large, charging / discharging of the capacitor C11 by the inverter INV11 is prioritized over the data input inversion of the inverter INV12, and it is possible to prevent rewriting the stored data of the SM121. .

Further, according to the pixel 12 of the present embodiment shown in FIG. 2, as described above, the liquid crystal display element L
Not only the effect that the applied voltage of CM1 can be set high and the dynamic range can be increased, but also the great effect that the pixel can be miniaturized is obtained. The downsizing of the pixel 12 is achieved by a total of seven transistors and one capacitor C as shown in FIG.
In addition to being able to form a pixel with a smaller number of constituent elements than the conventional pixel, the first signal holding means SM121, DM122, and the reflective electrode PE1 are arranged at the height of the element as described below. This is because it can be effectively arranged in the direction.

FIG. 4 is a cross-sectional configuration diagram of the pixel 12 according to the present embodiment. In the capacitor C11 shown in FIG. 2, a MIM (Metal-Insulator-Metal) capacitor that forms a capacitor between wirings, a diffusion capacitor that forms a capacitor between a substrate and polysilicon, and a capacitor between two layers of polysilicon are formed. PIP (P
(Oly-Insulator-Poly) capacity can be used. FIG. 4 shows a cross-sectional configuration diagram of the liquid crystal display device when the capacitor C11 is configured by the MIM. FIG. 4 is a partial cross-sectional view of the pixel 12.

In FIG. 4, the PMOS transistor P of the inverter INV11 in which the drains are connected to each other by sharing a diffusion layer serving as the drain on the N well formed on the silicon substrate.
Tr11 and a PMOS transistor Tr2 of the switch SW12 are formed. Further, on the P-well formed on the silicon substrate, the NMOS transistor NTr12 of the inverter INV12 and the NMOS transistor Tr1 of the switch SW12, in which the drains are connected by sharing the diffusion layer serving as the drain, are formed. . FIG. 4 shows the NMOS transistor constituting the inverter INV11 and the P constituting the inverter INV12.
The MOS transistor is not shown.

Further, above each of the transistors PTr11, Tr2, Tr1, and NTr12, an interlayer insulating film is interposed between the metals, and the first metal, the second metal, the third metal, the electrode, the fourth,
A metal and a fifth metal are laminated. The fifth metal is a reflective electrode P formed for each pixel.
E1 is configured. NMOS transistors Tr1 and PM constituting the switch SW12
Each diffusion layer constituting each source of the OS transistor Tr2 is electrically connected to the first metal through a contact, and further electrically connected to the second metal, the third metal, the fourth metal, and the fifth metal through a through hole. Connected. That is, the sources of the NMOS transistor Tr1 and the PMOS transistor Tr2 constituting the switch SW12 are electrically connected to the reflective electrode PE.

Furthermore, a passivation film (PSV) is provided as a protective film on the reflective electrode PE (fifth metal).
Are formed and spaced apart from the common electrode CE, which is a transparent electrode. These reflective electrodes P
A liquid crystal LC1 is filled and sealed between E1 and the common electrode CE to form a liquid crystal display element.

Here, an MIM electrode is formed on the third metal via an interlayer insulating film. This MI
The M electrode has a capacitor C11 together with the third metal and an interlayer insulating film between the third metal and the MIM electrode.
Is configured. When the capacitor C11 is configured by the MIM, the first signal holding means SM121
The switch SW11 and the switch SW12 are transistors, one of the first metal and the second metal.
The layer wiring, the two-layer wiring, and a part C11 of the DM 122 can be formed by the MIM wiring using the third metal above the transistor. The MIM electrode is connected to the fourth through the through hole.
Since the fourth metal is electrically connected to the reflective electrode PE1 through the through hole, the capacitor C11 is electrically connected to the reflective electrode PE1.

The light emitted from the light source (not shown in FIG. 4) is transmitted through the common electrode CE and the liquid crystal LCM1, is incident on the reflective electrode PE1 (fifth metal), is reflected, and travels backward through the original incident path to be common. Ejected through the electrode CE.

According to the present embodiment, as shown in FIG. 4, the fifth metal, which is a five-layer wiring, is connected to the reflective electrode PE.
1 to the first signal holding means SM121, a part C11 of DM122,
And it becomes possible to arrange | position the reflective electrode PE1 effectively in the height direction, and pixel miniaturization is realizable. Thus, for example, pixels with a pitch of 3 μm or less can be configured with transistors having a power supply voltage of 3.3V. In this 3 μm pitch pixel, the diagonal length is 0.55 inches and the horizontal direction is 4000.
A liquid crystal display panel having pixels and 2000 pixels in the vertical direction can be realized.

Next, data writing and reading operations of the liquid crystal display device 1 of FIG. 1 using the pixel 12 of the present embodiment will be described with reference to the timing chart of FIG.

As described above, in the liquid crystal display device 1, the row scanning lines are sequentially selected in units of 1H from the row scanning line g1 to the row scanning line gm by the row scanning signal from the vertical shift register. The plurality of pixels 12 constituting the image display unit write data in units of n pixels in one row commonly connected to the selected row scanning line. Then, after writing is completed for all of the plurality of pixels 12 constituting the image display unit, all pixels are read simultaneously based on the trigger pulse.

FIG. 5A schematically shows a writing period and a reading period of one pixel of 1-bit subframe data output from the horizontal driver to the column data lines d1 to dn. A slanting line on the left indicates the writing period. In FIG. 5A, B0b, B1b, and B2b indicate inverted data of the data of bits BO, B1, and B2.

FIG. 5B shows a trigger line tri for forward rotation trigger pulse from the timing generator.
The trigger pulse output to g is shown. This trigger pulse is output every subframe. Since the inversion trigger pulse output to the inversion trigger pulse trigger line trigb always has a reverse logic value with respect to the normal rotation trigger pulse, its illustration is omitted.

First, for a plurality of pixels 12 in one row selected by the row scanning signal, the switch SW11 is turned on, and the normal subframe data of bit B0 of FIG. 5A output to the column data line d at that time is switched. By being sampled by SW11, it is written in SM121.
Hereinafter, similarly, the first signal holding means SM12 of all the pixels 12 constituting the image display unit.
At time T1 shown in FIG. 5 after the writing of the sub-frame data of bit B0 to 1 is completed and the writing operation is completed, the forward rotation trigger pulse of “H” level is displayed as shown in FIG. It is supplied to all the pixels 12 constituting the display unit 11 at the same time.

As a result, the switches SW12 of all the pixels 12 are turned on, so that the normal subframe data of the bit B0 stored in the first signal holding means SM121 is switched to the switch S.
It is simultaneously transferred to and held by the capacitor C11 through W12 and applied to the reflective electrode PE1. The holding period of the normal rotation subframe data of bit B0 by the capacitor C11 is one sub period from time T1 to time T2 when the next “H” level normal rotation trigger pulse is input as shown in FIG. It is a frame period. FIG. 5C schematically shows bits of subframe data applied to the reflective electrode PE1.

Here, when the bit value of the subframe data is “1”, that is, “H” level, the power supply voltage VDD (for example, 3.3 V in this case) is applied to the reflective electrode PE1, and the bit value is “1”.
When it is “0”, that is, “L” level, 0 V is applied to the reflective electrode PE1. On the other hand, the common electrode CE is not limited to GND and VDD, and a free voltage is applied to the common electrode voltage V.
com, and can be switched to a specified voltage at the same time as when an “H” -level forward trigger pulse is input. Here, the common electrode voltage Vcom is set to a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1, as shown in FIG. The

The liquid crystal display element shown in FIG. 2 performs gradation display according to the applied voltage of the liquid crystal LC1, which is the absolute value of the difference voltage between the applied voltage of the reflective electrode PE1 and the common electrode voltage Vcom. Therefore, bit B
In one subframe period from time T1 to time T2 when the normal rotation subframe data of 0 is applied to the reflective electrode PE1, as shown in FIG. 5E, the bit value of the subframe data is applied to the liquid crystal LC1. When it is “1”, it becomes 3.3 V + Vtt (= 3.3 V − (− Vtt)), and when the bit value of the subframe data is “0”, it becomes + Vtt (= 0 V − (− Vtt)).

FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal and the gray scale value of the liquid crystal. As shown in FIG. 6, the gray scale value curve indicates that the black gray scale value is the threshold voltage Vtt of the liquid crystal.
The gray scale value of white corresponds to the RMS voltage of the liquid crystal, and the saturation voltage Vsat of the liquid crystal (= 3.3V +
Vtt) is shifted to correspond to the RMS voltage. It is possible to match the gray scale value to the effective part of the liquid crystal response curve. Therefore, the liquid crystal display element is a liquid crystal L as described above.
When the applied voltage of C is (3.3V + Vtt), white is displayed, and when it is + Vtt, black is displayed.

Subsequently, within the subframe period in which the normal subframe data of bit B0 is displayed, the inverted subframe data of bit B0 is written to the SM 121 of the pixel 12 as indicated by B0b in FIG. Are started in order. And S of all the pixels of the image display unit
The inverted subframe data of bit B0 is written to M121, and at time T2 after the completion of the writing, as shown in FIG. 5B, the “H” level normal rotation trigger pulse is applied to all the pixels constituting the image display unit. Supplied at the same time.

As a result, the switches SW12 of all the pixels 12 are turned on, so that the inverted subframe data of the bit B0 stored in the SM121 passes through the switch SW12 and the capacitor C1.
1 is transferred and held and applied to the reflective electrode PE1. The holding period of the inverted subframe data of bit B0 by the capacitor C11 is one subframe from time T2 to time T3 when the next "H" level normal rotation trigger pulse is input as shown in FIG. It is a period. Here, since the inverted subframe data of bit B0 is always in an inverse logical relationship with the normal subframe data of bit B0, the normal subframe data of bit B0 is “1”.
Is “0”, and when the normal subframe data of bit B0 is “0”, it is “1”.

On the other hand, the common electrode voltage Vcom is set to a voltage higher than the 3.3V threshold voltage Vtt as shown in FIG. 5D during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1. The Therefore, the inverted subframe data of bit B0 is reflected electrode PE.
In one subframe period of time T2 to T3 applied to 1, the applied voltage of the liquid crystal LC1 is −Vtt (= 3.3V− (3.3V + Vtt) when the bit value of the subframe data is “1”.
)), And when the bit value of the subframe data is “0”, −3.3V−Vtt (= 0)
V- (3.3V + Vtt)).

Accordingly, when the bit value of the normal subframe data of bit B0 is “1”, the bit value of the inverted subframe data of bit B0 that is subsequently input is “0”, so the liquid crystal L
The applied voltage of C1 is − (3.3V + Vtt), and the direction of the potential applied to the liquid crystal LC1 is opposite to that of the forward subframe data of the bit B0 but has the same absolute value. Displays the same white color as when normal subframe data of bit B0 is displayed.

Similarly, when the bit value of the normal subframe data of bit B0 is “0”, the bit value of the inverted subframe data of bit B0 that is subsequently input is “1”.
The applied voltage of C1 is -Vtt, and the direction of the potential applied to the liquid crystal LC1 is opposite to that of the forward subframe data of the bit B0, but the absolute value is the same, so the pixel 12 displays black To do.

Accordingly, as shown in FIG. 5E, the pixel 12 displays the same gradation in the bit B0 and the complementary bit B0b of the bit B0 in the two subframe periods from the time T1 to the time T3,
Since the AC drive in which the potential direction of the liquid crystal LC1 is inverted every subframe is performed, the liquid crystal LC1
Can be prevented.

Subsequently, within the subframe period in which the inverted subframe data of the complementary bit B0b is displayed, as shown by B1 in FIG. 5A, the normal subframe data of the bit B1 is transferred to the SM 121 of the pixel 12. Writing starts in sequence. Then, the normal subframe data of bit B1 is written to the first signal holding means SM121 of all the pixels 12 of the image display section, and at time T3 after the completion of the writing, as shown in FIG. A level normal rotation trigger pulse is simultaneously supplied to all the pixels constituting the image display unit.

As a result, the switches SW12 of all the pixels are turned on, so that the normal subframe data of the bit B1 stored in the first signal holding means SM121 is transferred to and held in the capacitor C11 through the switch SW12. And applied to the reflective electrode PE1. The holding period of the normal subframe data of bit B1 by the capacitor C11 is shown in FIG.
As shown in B), this is one subframe period until time T4 when the next “H” level normal rotation trigger pulse is input.

On the other hand, the common electrode voltage Vcom is set to a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal as shown in FIG. 5D during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1. . Therefore, in one subframe period from time T3 to time T4 when the normal rotation subframe data of bit B1 is applied to the reflective electrode PE1, the voltage applied to the liquid crystal LC1 is as shown in FIG.
E) When the bit value of the subframe data is “1”, 3.3V + Vtt (
= 3.3V − (− Vtt)), and when the bit value of the subframe data is “0” +
Vtt (= 0V − (− Vtt)).

Subsequently, within the subframe period displaying the normal subframe data of the bit B1, the first signal of the pixel 12 of the inverted subframe data of the bit B1 as indicated by B1b in FIG. Writing to the holding means SM121 is started in order. Then, the inverted subframe data of bit B1 is written in the first signal holding means SM121 of all the pixels of the image display portion, and at time T4 after the writing is completed, as shown in FIG. The forward rotation trigger pulse is simultaneously supplied to all the pixels constituting the image display unit.

Thereby, since the switches SW12 of all the pixels 12 are turned on, the inverted subframe data of the bit B1 stored in the first signal holding means SM121 is switched to the switch SW1.
2 is transferred to and held by the capacitor C11 and applied to the reflective electrode PE1. The holding period of the inverted subframe data of bit B0 by the capacitor C11 is one subframe from time T4 to time T5 when the next “H” normal rotation trigger pulse is input as shown in FIG. It is a period. Here, the inverted subframe data of bit B1 is bit B1.
It is always in the relationship of the inverse logical value with the normal rotation subframe data.

On the other hand, the common electrode voltage Vcom is set to a voltage higher than the 3.3V threshold voltage Vtt as shown in FIG. 5D during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1. The Therefore, the inverted subframe data of bit B1 is reflected electrode PE.
In one subframe period of time T4 to T5 applied to 1, the applied voltage of the liquid crystal LC1 is −Vtt (= 3.3V− (3.3V + Vtt) when the bit value of the subframe data is “1”.
)), And when the bit value of the subframe data is “0”, −3.3V−Vtt (= 0)
V- (3.3V + Vtt)).

Accordingly, as shown in FIG. 5E, the pixel 12 displays the same gradation in the bit B1 and the complementary bit B1b of the bit B1 during the two subframe periods from the time T3 to the time T5, and the liquid crystal LC1. The liquid crystal LC is driven by alternating current driving in which the potential direction is inverted every subframe.
1 can be prevented. Thereafter, the same operation as described above is repeated, and according to the liquid crystal display device 1 having the pixel 12 of the present embodiment, gradation display can be performed by a combination of a plurality of subframes.

The display periods of bit B0 and complementary bit B0b are the same first subframe period, and the display periods of bit B1 and complementary bit B1b are also the same second subframe period. The subframe period and the second subframe period are not necessarily the same. Here, as an example, the second subframe period is set to be twice the first subframe period. As shown in FIG. 5E, the third subframe period, which is the display period of the bit B2 and the complementary bit B2b, is set to be twice the second subframe period.
The same applies to the other subframe periods. The length of each subframe period is determined to be a predetermined length according to the system, and the number of subframes is also determined to be an arbitrary number.

Next, the basic operation of pixel inspection of the liquid crystal display device according to the embodiment of the present invention will be described with reference to the drawings as appropriate. First, an “H” level row scanning signal is supplied to a specific row scanning line g at the start of pixel inspection to turn on the switch SW11. Also, the wirings trig and trig
An “H” level trigger pulse and an “L” level inversion trigger pulse are respectively supplied to b, and the switch SW12 is also turned on.

Next, “L” level data is supplied to the column data line d as a 1-bit inspection signal. As a result, “L” level data is written at a point, which is a connection point between the input terminal of the inverter INV11 and the output terminal of the inverter INV12, which constitute the first signal holding means SM121 of the pixel 12. Further, “H” level data is written at a point b where the output terminal of the inverter INV11 and the input terminal of the inverter INV12 are connected to the capacitor C11 via the switch SW12. At this time, in the first signal holding means SM121 of the pixel 12, the driving power of the transistors constituting the inverter INV11 is larger than the driving power of the transistors constituting the inverter INV12. Therefore, the point a is the first signal holding means SM121.
The point b functions as the output of the SM 121.

Here, since SW12 is turned on, the capacitor C11 is also in a state in which “H” level data is written.

Next, when the row scanning line g is set to the “L” level, the reflective electrode PE1 of the pixel 12 is in a state in which “H” level data obtained by inverting the input data is latched.

After the writing is completed, the column data line d is opened by setting Tlat shown in FIG. 1 to the “L” level. The sense amplifier input connected to the column data line d is connected to the wiring mid supplied with the intermediate voltage by turning on the sense amplifier input control nu. As a result, the column data line d at the input of the sense amplifier is precharged to an intermediate voltage of 1.65V. Thereafter, the sense amplifier input control nu is turned off. Column data line d
Has a capacity of a signal line, and therefore a voltage of 1.65 V is held.

Next, when the row scanning line g is set to the “H” level, the data written in the pixel 12 is output to the signal line d. Since the pixel 12 is an SRAM in which input and output are determined, 1.65V held in the signal line of d is written in the pixel 12, but data written in the pixel 12 is also applied to the signal line d. As a result, the signal line d1 is affected by the data written in the pixel 12, and the level of the signal line changes. That is, the column data line d is driven to the “L” level by the inverter INV12 by the data written in the pixel 12.

Since the driving force of the inverter INV12 is very small and the column data line capacity is large, it takes time to drive the column data lines d to the “L” level, but if the potential of the column data line d slightly changes, The sense amplifier input from the column data line d and the wiring mid amplifies the potential difference, and the output of the sense amplifier is output to the “L” level.

The signal output from the sense amplifier is shaped in a signal waveform by a buffer. Thereafter, all the column sense amplifier outputs from e1 to en are input to predetermined positions of the pixel readout shift register by controlling the TEST terminal to the “H” level. Thereafter, a signal is serially extracted from the output terminal TOUT in accordance with the TCK / TCKb signal sent from the timing generator.

In the present embodiment, the above-described pixel inspection is performed on the pixel 12 with the first inspection method for inputting a signal of “L” level from the column data line d and reading the signal, and the “H” level from the column data line d. Two types of the second inspection method for inputting the data and reading the signal are executed twice at different timings.

As a result, it is possible to read out the “L” level voltage or the “H” level voltage in the pixel 12, so that the pixel function test of logic as a memory can be performed. At this time, for example, if the capacitor C11 is short-circuited to GND or VDD wiring by a process, it is impossible to read arbitrary data in the pixel inspection. The first signal holding means SM
Even when 121 is short-circuited or disconnected, it is impossible to read arbitrary data in the pixel inspection according to the present embodiment. When the above data reading is impossible, it is determined that the liquid crystal display device has a defective pixel, and it is possible to take a business appropriate measure.

FIG. 7 shows a configuration diagram of the sense amplifier circuit. The differential voltage between the two gate inputs of + − is amplified and outputted in the circuit. A voltage source circuit (indicated by a broken line in FIG. 7) forms an analog voltage supplied to the sense amplifier by resistance division. Note that the sense amplifier circuit is not necessarily configured as shown in FIG. Furthermore, a high-performance sense amplifier with a high gain may be used.

Next, the pixel inspection operation corresponding to the above-described operation failure in this embodiment will be described in more detail with reference to the overall configuration diagram of FIG. 1, the circuit diagram of FIG. 2, and the timing chart of FIG. .

At the time of pixel inspection, first, trig is “H” at the first time t1 at the time of pixel inspection.
The level and trigb are set to the “L” level, and the SW 12 of the pixel 12 is controlled to be turned on. Next, during a period from time T2 to T3, LT is controlled to the “H” level, and predetermined data is written to the column data lines d1 to dn. At this time, as described above, the column data lines d (d1, d2, d3,...
• Write “L” level data to dn).

From time t2 to t4, one row scanning line gx of the image display unit is controlled to the “H” level, and data written to the column data lines d1 to dn from the level shifter / pixel driver is set to 1
Write to row of pixels 12.

At time t4, one row scanning line gx of the image display unit is controlled to the “L” level, and the signal is latched in the first signal holding means SM121 of the pixel 12.

Next, the data written in the pixel is read out. Tlat at time t4.5
Is set to “L” level to open all column data lines. As a result, the column data lines d1 to dn are in a state where the voltage is determined only by the capacitance. At time T5, the sense amplifier input control nu is set to the “H” level, whereby the column data line d is connected to the wiring mid (1.65).
Same as V). As a result, the column data line d becomes 1.65V. After that, by setting the sense amplifier input control nu to “L” level, all the column data lines are opened again. As a result, the column data line d1 is in a state in which the voltage of 1.65 V is held and determined only by the capacitance.

By controlling the row scanning line gx to “H” level at time t6, the data written in the pixel 12 is read out. The column data line d is driven by the inverter INV12 of the pixel 12 at the timing of T6. Since the driving force of the inverter INV12 is very small,
Initially, the potential of the column data line slightly fluctuates, but becomes “L” level data over time. As a result, the column data line d is driven in the “L” level direction.

The slight voltage difference Y between the column data line d and the wiring mid is amplified by the sense amplifier and input to a buffer connected to the output of the sense amplifier. VDD (power supply voltage) by the buffer
And the data is shaped to the GND (reference voltage) level. By controlling TEST to "H" level at time T6, the outputs e1 to e of the buffers connected to the output of the sense amplifier
n is simultaneously latched in the pixel readout shift register. At time t7, TEST is set to “L” level to complete latching of the pixel readout shift register.

From time t7, the control to alternately turn on / off the clock signal TCKb and the clock signal TCK having opposite phases shown in FIG. 8 supplied to the pixel readout shift register is repeated. As a result, among the readout signals stored in the pixel readout shift register, pixel inspection is sequentially performed from the readout signal from the column sense amplifier buffer output en to the readout signal from the column sense amplifier buffer output e1 to the output terminal TOUT. A signal is output. As for the clock signal TCKb and the clock signal TCK, the on / off control of half the number of pixels for one row is repeated, whereby all data is read and the inspection for one row is completed. A pixel inspection can be performed by comparing the readout signal of the pixels for one row with the input inspection signal and determining whether or not they are the same.

After the above operation is completed, this time, by controlling the vertical shift register, each pixel 12 in the next pixel row is selected, and pixel inspection is performed in the same manner as described above. These are repeated, the inspection for the number of pixels in the vertical direction is executed, and the inspection is performed for all the pixels constituting the image display unit.
Note that the input inspection signal does not need to be set to the “L” level on the column data line d1 as described above, and the opposite data may be written and inspected.

Thus, according to the present embodiment, the pixel inspection can be performed accurately. According to this embodiment, since inspection can be performed without increasing the number of inspection transistors in the pixel 12 for pixel inspection, two SRAMs are included in the pixel as in the conventional liquid crystal display device described above.
Compared with a liquid crystal display device using the above, the pixel can be downsized and an accurate pixel inspection can be performed.

The above is the pixel inspection when the DRAM is turned on, but the pixel inspection can also be performed when the DRAM is turned off. At this time, in FIG. 8, trig is set to “L” level, and tigb
It is also possible to perform an inspection with the DRAM turned off by controlling the signal to “H” level. Other timing charts are the same as described above. In this case, it is possible to perform an open inspection of the DRAM by performing two types of pixel inspections when the DRAM is turned on and when the DRAM is turned off, and comparing the inspection results.

9A and 9B are schematic diagrams of pixel circuits for explaining the case where the DRAM of the liquid crystal display device 1 according to this embodiment is turned on and the case where the DRAM is turned off, respectively. DR shown in FIG.
When AM is present, the switch SW12 in FIG. 2 is on, and the DR shown in FIG.
When there is no AM, at point b in FIG. 2, the wiring is cut due to a process failure and the capacitor C1
1 shows a case where no connection is made. In FIG. 9, the difference is whether or not C11 is connected to each INV12 in the pixel circuit.

At this time, when the capacitor C11 is connected to the inverter INV12 (in the case of FIG. 9A), the driving force of the inverter is strong, and when C11 is not connected to the inverter INV12 (in FIG. 9B). In the case), the driving force of the inverter is weak.

This is because the gate voltage constituting the inverter INV12 is determined based on the liquid crystal LC1 and the capacitance of the capacitor C11, but is not shown in FIG. 10 (shown in FIG. 2).
It is determined by charging with the output voltage. The output voltage of the inverter INV11 is the inverter I
Although it is determined by the input voltage level of NV11, the input voltage of the inverter INV11 is 1
. The voltage is determined to be about 1.65 V by the voltage of the column data line d written to 65 V.

That is, when the “L” level voltage is written at the point b in FIG. 2, when reading, the inverter INV11 tries to rewrite the voltage at the point b to 1.65V. However, when the capacitances of the liquid crystal display element LC1 and the capacitor C11 at the point b are large, it takes time to rewrite to 1.65 V, and as a result, a slightly inverted voltage of “H” level is output to the point a. . When the point a becomes slightly “H” level, the inverter INV11 tries to output “L” level slightly. By repeating these steps, the column data line d gradually becomes “H” level.

As a result, when the potential difference between the potential output to the column data line d and the wiring mid reaches an amplitude that can be determined by the sense amplifier, an “H” level (VDD) voltage is output to the output of the sense amplifier to perform pixel inspection. Is possible.

At this time, when the DRAM is disconnected and not connected, the liquid crystal LC1 is displayed at the point b.
There is only a capacity C11. This capacitor C11 is connected to the inverter INV11 by 1.65.
Try to rewrite to V. When the capacitance at the point b is small, it is rewritten to 1.65 V in a short time, so the input voltage of the inverter INV12 becomes 1.65 V, and the voltage at the point a becomes 1.65 V. The voltage at the point c is also 1.65 V, there is almost no potential difference between the connected column data line d and the wiring mid, the sense amplifier becomes insensitive, and a normal determination voltage cannot be output.

Therefore, after time T6 in FIG. 8, the time during which d changes to a predetermined voltage is shown in FIG.
9B is longer than that shown in FIG. 9B. Since the potential difference at which the sense amplifier starts to operate normally is determined, by adjusting the time from time T6 to time T7 to a certain time (X), normal inspection can be performed in the case shown in FIG. FIG. 9 (B)
In the case shown in the above, it is possible to prevent normal inspection.

By connecting and inspecting the DRAM at this time (X) (corresponding to (A) in FIG. 9), the DRAM portion in the pixel is open (corresponding to (B) in FIG. 9). ) And cannot be properly inspected. As a result, an open inspection of the DRAM can be performed. Normally, it is necessary for the open inspection to inspect the pixel electrode with a pixel configuration via a through hole in a series, but according to this method according to the present embodiment, the pixel configuration is not changed, so the pixel pitch DRAM open inspection can be carried out without increasing

Note that the specific numerical values and the like shown in the above-described embodiments are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 12 Pixel CE Common electrode LC1 Liquid crystal PE1 Reflection electrode LCM1 Liquid crystal display element C11 Capacitance SW11, SW12 Switch INV11, INV12 Inverter d Column data line g Row scanning line

Claims (2)

A liquid crystal display device comprising a plurality of pixels provided at each intersection where a plurality of column data lines and a plurality of row scanning lines intersect,
The pixel is
A display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode;
For each frame data of the input video signal, a first switching unit that performs sampling for displaying using a plurality of subframes whose display period is shorter than one frame period via the column data line;
A first holding unit that constitutes an SRAM together with the first switching unit, and in which the first switching unit holds the sampled subframe data;
A second switching unit for outputting the subframe data held by the first holding unit;
The DRAM is configured together with the second switching unit, and the storage content is rewritten by the subframe data held in the first holding unit inputted through the second switching unit, and output data is transferred to the pixel electrode. A second holding unit to be applied;
The sub-frame data is repeatedly written to the first holding unit in units of rows in the plurality of pixels, and after the sub-frame data is written to all of the plurality of pixels, the plurality of pixels are generated by a trigger pulse. An operation of turning on all the second switching units and rewriting the storage contents of the second holding unit of the plurality of pixels by the subframe data held in the first holding unit for each subframe. A pixel control unit for
A first column data line connected to the first switching unit of the pixel, and a sense amplifier to which a predetermined fixed voltage is applied;
The first holding unit includes a first inverter and a second inverter, and an input terminal of the first inverter is connected to an output terminal of the second inverter and the first switching unit, The input terminal of the second inverter is connected to the output terminal of the first inverter and the second switching unit, and the driving force of the first inverter is greater than the driving force of the second inverter. A liquid crystal display device characterized by that. An inspection method for a liquid crystal display device according to claim 1,
Inputting a 1-bit inspection signal to the first column data line connected to the first switching unit of the pixel;
Latching the inspection signal in the SRAM of the pixel;
Turning on the second switching unit of the pixel and latching the inspection signal latched in the SRAM of the pixel in the DRAM of the pixel;
Turning on the second switching unit of the pixel and reading the inspection signal latched in the DRAM of the pixel to the SRAM of the pixel;
Supplying the latched test signal to the first column data line;
And a step of amplifying a potential difference based on the supplied inspection signal and the predetermined fixed voltage by the sense amplifier.

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