JP6379591B2 - Electronic device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic device and a manufacturing method thereof, and more particularly, to an electronic device having a multi-part module structure and a manufacturing method thereof, and more particularly to a semiconductor device having a multi-chip module structure and a manufacturing method thereof.

  Generally, in a communication module in which a plurality of semiconductor chips are mounted on a circuit board, the connection between the terminals of the plurality of semiconductor chips is performed by connecting a plurality of pads by wire bonding using gold or aluminum wires. ing.

  In recent years, in response to demands for high-speed and large-capacity communication, frequencies in the millimeter wave band and sub-terahertz wave band that can secure a wide band have begun to be used. The higher the frequency, the greater the proportion of loss due to parasitic capacitance and resistance variations in the transmission line, and the stabilization of the shape of the connecting portion or the wire bonding loop shape, or the shortening of the wire length is an issue.

  In order to shorten the wiring length, there is a method in which a plurality of semiconductor chips are connected by a bump connection of a flip chip structure instead of the wire bonding.

  The multi-chip module structure disclosed in Patent Document 1 adopting the latter method includes a wiring substrate (base substrate), a semiconductor substrate (intermediate substrate) disposed in the wiring substrate, a wiring substrate, and a semiconductor substrate. And a plurality of semiconductor chips connected face-down across the board. The semiconductor substrate has an inter-chip wiring layer that electrically connects a plurality of semiconductor chips. Therefore, the wiring board and the semiconductor chip are directly electrically connected, and the plurality of semiconductor chips are indirectly electrically connected via the inter-chip wiring layer of the wiring board.

JP 2006-261111 A

  The following analysis is given by the present invention.

  The semiconductor device having a multichip module structure disclosed in Patent Document 1 has at least a problem of low assemblability. The reason will be described below.

  According to the first manufacturing method of the multi-chip module structure, a plurality of semiconductor chips are connected to a semiconductor substrate, an intermediate module reinforced by resin sealing is created, and the intermediate module is inverted and placed on the wiring board. Implement.

  According to the first manufacturing method, when there is a difference or variation in chip thickness between a plurality of semiconductor chips during mounting on a wiring board, the intermediate module is mounted with an inclination, or mounting position accuracy is reduced. There is a risk. In addition, due to the difference in thickness or variation, there is a risk that adsorption of the intermediate module by a mounting device such as a mounting mounter may be difficult, or an unbalanced load may be applied to the intermediate module or the like during mounting.

  According to the second manufacturing method of the multichip module structure, a semiconductor substrate having an interchip wiring layer is first mounted in the wiring substrate, and then a plurality of semiconductor chips straddling the wiring substrate and the semiconductor substrate. Is implemented face-down.

  According to the second manufacturing method, particularly in a semiconductor chip, when the size of the electrode connected to the inter-chip wiring layer and the electrode connected to the wiring board are different, the contact state between the semiconductor chip and the semiconductor substrate There is a tendency that a difference occurs between the contact state between the semiconductor chip and the wiring board. For this reason, strictness is required for condition setting such as load setting at the time of mounting, which may cause a decrease in yield.

  Thus, there is a need for an electronic device having a multi-electronic component module structure that can be easily manufactured, and a manufacturing method that can be easily managed, while suppressing transmission loss between a plurality of electronic components.

In the first aspect, the electronic device is mounted face-up (a main surface faces away from the substrate) on a substrate (including an element integrated with the substrate) and a plurality of mounting regions of the substrate. A plurality of lower layer electronic components and a plurality of lower surface electronic components and a plurality of main surfaces (surfaces on which upper layer electronic components are mounted, circuit surface) are mounted face down (the main surface faces the substrate side). And at least one upper layer electronic component, and an adjustment element formed so that the heights of the plurality of main surfaces across the upper layer electronic component are uniform.
As a modification of the first aspect, the electronic device includes a substrate, a plurality of lower layer electronic components mounted face-up on a plurality of mounting regions included in the substrate, and a plurality of main components included in the plurality of lower layer electronic components. At least one upper layer electronic component mounted face down across the surface, and an adjustment element formed so that the heights of the plurality of main surfaces across the upper layer electronic component are uniform, the lower layer electronic component, different thicknesses from each other, wherein the substrate is a plurality of mounting areas, have a recess or step according to the material thickness of the plurality of lower layer electronic components corresponding circuit in the recess or step is formed Has been .

In a second aspect, an electronic device manufacturing method includes a step of mounting a plurality of lower layer electronic components face up on a plurality of mounting regions of a substrate, and a plurality of main surfaces of the plurality of lower layer electronic components. A step of mounting at least one upper-layer electronic component across the face, and forming an adjustment element so that the heights of the plurality of main surfaces straddling the upper-layer electronic component are uniform before mounting the lower-layer electronic component And a step of performing.
As a modification of the second aspect, an electronic device manufacturing method includes a step of mounting a plurality of lower layer electronic components face up on a plurality of mounting regions of a substrate, and a plurality of main components of the plurality of lower layer electronic components. A step of mounting at least one upper layer electronic component face down across the surface, and an adjustment element so that the heights of the plurality of main surfaces across the upper layer electronic component are uniform before mounting the lower layer electronic component The plurality of lower layer electronic components have different thicknesses, and the substrate has recesses or steps corresponding to the thicknesses of the corresponding lower layer electronic components in the plurality of mounting regions. Yes, and the circuit is formed in the recess or step.

In a third aspect, a method for manufacturing an electronic device includes a step of mounting a plurality of lower layer electronic components face up on a plurality of mounting regions of a substrate, and a plurality of main surfaces of the plurality of lower layer electronic components. A step of mounting at least one upper-layer electronic component face-down across the plurality of lower-layer electronic components in accordance with the distance between input and output terminals of the upper-layer electronic component straddling the plurality of lower-layer electronic components The input / output terminals of the upper layer electronic component mounted on the substrate are input terminals of one of the lower layer electronic components and output terminals of the other lower layer electronic component of the plurality of lower layer electronic components. Each bump is connected to a bump.
As a modification of the third aspect, a method for manufacturing an electronic device includes a step of mounting a plurality of lower layer electronic components face up on a plurality of mounting regions of a substrate, and a plurality of main components of the plurality of lower layer electronic components. Mounting at least one upper layer electronic component face down across the surface, and the plurality of lower layer electronic components have a distance between input and output terminals of the upper layer electronic component straddling the plurality of lower layer electronic components. In addition, the input / output terminal of the upper layer electronic component mounted on the substrate has an input terminal of one of the lower layer electronic components and the other lower layer electronic component of the plurality of lower layer electronic components. Each of the plurality of lower layer electronic components is bump-connected to the output terminal, and the thicknesses of the plurality of lower layer electronic components are different from each other. Parts or have a level difference, circuit is formed in the recess or step.

  According to each of the above viewpoints, transmission loss between a plurality of electronic components can be suppressed, and an electronic device having a multi-electronic component module structure with good assemblability even when electronic components having different thicknesses are used and process management is easy. A manufacturing method thereof is provided.

(A) And (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 1 has, (A) is a top view, (B) is AA sectional drawing of (A). is there. It is a figure for demonstrating the manufacturing apparatus of the semiconductor device shown in FIG. 2 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. It is a figure explaining the multichip module structure which the semiconductor device of Embodiment 2 has. (A) is Embodiment 3 and (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 4 has, respectively. (A) And (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 5 has, (A) is a top view, (B) is AA sectional drawing of (A). is there. (A) And (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 6 has, (A) is a top view, (B) is AA sectional drawing of (A). is there. It is a figure explaining the multichip module structure which the semiconductor device of Embodiment 7 has. (A) And (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 8 has, (A) is a top view, (B) is AA sectional drawing of (A). is there. (A) And (B) is a figure explaining the multichip module structure which the semiconductor device of Embodiment 9 has, (A) is a top view, (B) is AA sectional drawing of (A). is there. It is a figure explaining the multichip module structure which the semiconductor device of Embodiment 10 has.

  Form 1 is as described in the first viewpoint. The lower layer and upper layer electronic components can be selected from one or more of a semiconductor chip, an active component other than the semiconductor chip, or a passive component.

  In a second aspect, the electronic device includes, as the adjustment element, a plurality of bonding layers that are formed between the plurality of mounting regions and the plurality of lower layer electronic components and bond the two. By adjusting the relative thicknesses of the plurality of bonding layers, the heights of the plurality of main surfaces across the upper-layer electronic component are made uniform.

  In the third aspect, the adjustment element is the plurality of mounting areas. By adjusting the relative heights of the plurality of mounting regions, the heights of the plurality of main surfaces across the upper-layer electronic component are made uniform.

  In Mode 4, at least one of a step, a plurality of recesses, a difference in substrate thickness, and a difference in substrate height is formed in the substrate so that the heights of the plurality of mounting regions are different from each other.

  In the fifth aspect, the electronic device is a plurality of lower layer semiconductor chips that are the lower layer electronic components, and the upper layer electronic components that are bump-connected to the plurality of lower layer semiconductor chips in a state parallel to the plurality of lower layer semiconductor chips. And at least one upper layer semiconductor chip.

  In the sixth aspect, one of the lower electronic components has one of the distance between input / output terminals of one upper electronic component and the two lower electronic components straddled by the upper electronic component, and the upper electronic component has The distance between the output terminal connected to the input terminal and the input terminal of the other lower electronic component and connected to the output terminal of the upper electronic component is equal.

  In a seventh aspect, the electronic device has a multi-electronic component module structure in which the heights of the plurality of main surfaces are uniformly adjusted partially or entirely. Electronic components can be stacked in three or more layers.

  Form 8 is as described in the second viewpoint.

  In a ninth aspect, the adjustment element is one or more of a plurality of bonding layers formed between the plurality of mounting regions and the plurality of lower layer electronic components to bond the two and the plurality of mounting regions.

  Form 10 is as described in the third viewpoint.

  The electronic devices and manufacturing methods of the above embodiments are particularly used in electronic devices having a multi-part module structure and manufacturing methods thereof, and in particular, semiconductor devices having a multi-chip module structure and manufacturing methods thereof. A high-frequency communication module that has a multi-chip module structure in which a plurality of semiconductor chips are arranged on a substrate and terminals of the plurality of semiconductor chips are electrically connected, and the terminals are required to be connected at a short distance. It is preferably used.

  An outline of an embodiment of the present invention will be described with reference to the drawings. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

Referring to FIGS. 1A and 1B, the semiconductor device (electronic device) of the embodiment includes the following elements:
Circuit board 1;
A plurality of lower layer electronic components 11, 13, 15 mounted face up on a plurality of mounting areas 1a, 1b, 1c of the circuit board 1;
At least one upper layer electronic component 12, 14 mounted face down across the plurality of main surfaces 11a, 13a, 15a of the plurality of lower layer electronic components 11, 13, 15;
The adjustment element formed so that the height of the some main surface 11a, 13a, 15a may become uniform.

  In the embodiment shown in FIGS. 1A and 1B, the adjustment elements are a plurality of bonding layers 5a, 5b, 5c. By adjusting the thicknesses of the bonding layers 5a, 5b, and 5c, the heights of the plurality of main surfaces 11a, 13a, and 15a across which the upper electronic components 12 and 14 straddle can be easily made uniform.

  In another embodiment shown in FIG. 5A and the like, the adjustment element is a plurality of mounting regions 1a, 1b, and 1c that the circuit board 1 has or is integrated therewith. By adjusting the heights of the plurality of mounting regions 1a, 1b, and 1c, the heights of the plurality of main surfaces 11a, 13a, and 15a across the upper electronic components 12 and 14 can be easily made uniform.

  In the semiconductor device of the embodiment, since the electronic component can be connected to the circuit board or other electronic component using a flip chip structure or a bump, the arrangement length can be shortened and transmission loss between the plurality of electronic components can be suppressed.

  In the semiconductor device of the embodiment, the difference in thickness between the plurality of lower layer electronic components 11, 13, 15 is the adjustment of the thickness of the bonding layers 5 a, 5 b, 5 c, and the plurality of mounting regions 1 a, 1 b, It is compensated by any one or more of the height adjustments of 1c, and the heights of the plurality of main surfaces across the upper electronic components 12 and 14 can be easily made uniform. For example, the upper electronic components 12 and 14 can be stacked while maintaining parallelism with respect to the circuit board 1 and the lower electronic components. Thus, the strength and assemblability of the multi-electronic component module structure are improved.

  Further effects of the semiconductor device of the embodiment will be described in comparison with Patent Document 1 described above.

  The first effect is that the number of terminals for connecting an electronic component, for example, a semiconductor chip to a circuit board can be increased.

  In general, it is advantageous in terms of electrical characteristics that a semiconductor chip has a large number of terminals such as a power source, a ground, and a signal.

  On the other hand, according to Patent Document 1, the semiconductor substrate having the interchip wiring layer cannot be connected to the wiring substrate, but only connected to the semiconductor chip. Further, the area where the connection can be taken out from the semiconductor chip is limited to the area where the semiconductor substrate having the inter-chip wiring layer is not shielded.

  The second effect is that the upper electronic components 12 and 14 are connected with high strength to the lower electronic components 11, 13, and 15 that are firmly fixed to the integrated circuit board 1, thereby reinforcing the multi-electronic component module structure. The underfill resin to be used becomes unnecessary.

  Generally, the underfill resin increases the dielectric constant of a semiconductor device. In multi-chip modules for high frequencies, it is strongly required to keep the dielectric constant low.

  On the other hand, according to the multi-chip module structure of Patent Document 1, reinforcement with an underfill resin is required, which tends to increase the dielectric constant.

  A third effect is that the wiring length of the entire apparatus can be shortened.

  On the other hand, according to the multi-chip module structure of Patent Document 1, the connection between the terminal of the semiconductor chip and the terminal of the semiconductor substrate having the inter-chip wiring layer, which are bump-connected, is compared with the case of wire connection. This shortens the wiring length. However, the overall wiring length becomes longer due to the routing of the wiring inside the interchip wiring layer or the routing to the external connection destination in the semiconductor chip.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, many specific items are made for the purpose of explanation and to help understanding of the present invention.

(Embodiment 1)
The electronic device according to the first embodiment is a semiconductor device having a multichip module structure. In the semiconductor device of the first embodiment, the connection terminal of the upper semiconductor chip mounted face down is aligned with the connection terminal of the lower semiconductor chip mounted face up on the circuit board, and is electrically connected by bump bonding. It is connected. The power source and ground of the semiconductor chip may be directly connected to the circuit board by wire bonding or flip chip bumps individually.

  In the following embodiments and the like, an example in which a semiconductor chip is mainly used as an electronic component will be described. Instead, an active component other than a semiconductor chip or a passive component such as an antenna, a branch pattern, or a capacitor is used. May be. In addition, the semiconductor chip employ | adopted can select suitably what has a various circuit structure according to the objective.

  In the following embodiments and the like, the semiconductor device includes five semiconductor chips that are mounted or stacked on the circuit board 1. However, the number of semiconductor chips is not particularly limited. A semiconductor device having a multi-chip module structure can be configured using an odd number or an even number of semiconductor chips.

Referring to FIGS. 1A and 1B, the semiconductor device of Embodiment 1 includes the following elements:
Circuit board 1;
A plurality of lower layer semiconductor chips 11, 13, 15 mounted face up on a plurality of mounting regions 1a, 1b, 1c of the circuit board 1;
Upper-layer semiconductor chips 12, 14 mounted face-down across a plurality of main surfaces 11a, 13a, 15a of the plurality of lower-layer semiconductor chips 11, 13, 15;
A plurality of bonding layers (adjustment elements) 5a, 5b, and 5c formed between the plurality of mounting regions 1a, 1b, and 1c and the plurality of lower layer semiconductor chips 11, 13, and 15 to bond the two.

  By adjusting the relative thicknesses of the plurality of bonding layers 5a, 5b, 5c, the heights of the plurality of main surfaces 11a, 13a, 15a on the lower semiconductor chips 11, 13, 15 across the upper semiconductor chips 12, 14 are uniform. It becomes.

  In more detail, the configuration of the semiconductor device of the first embodiment will be described.

  One surface of the circuit board 1 is covered with a metal material such as Au or Cu, a flat metal main surface 2 having a ground connection function and a heat dissipation function, and a signal supply terminal 3 covered with a metal material such as Au or Cu. And are provided.

  In the circuit board 1, a metal surface that is electrically connected by a via hole or the like is formed on the opposite surface of the metal main surface 2, and the circuit board 1 can be a double-sided board.

  The lower and upper semiconductor chips 11 to 15 have a signal input terminal 7 and a signal output terminal 8 connected to the signal line on the main surface side. In addition to the signal input terminal 7 and the signal output terminal 8, a terminal connected to the power source and the ground is provided, but the illustration is omitted.

  In the lower layer and upper layer semiconductor chips 11 to 15, the lower layer semiconductor chips 11, 13, and 15 that are face-up and the upper layer semiconductor chips 12 and 14 that are face-down are alternately arranged in the order of signal line connection.

  The signal input terminal 7 and the signal output terminal 8 included in the lower layer and upper layer semiconductor chips 11 to 15 are electrically connected. The signal output terminal 8 (11) of the lower layer semiconductor chip 11 and the signal input terminal 7 (12) of the upper layer semiconductor chip 12 and the signal output terminal 8 (12) of the upper layer semiconductor chip 12 and the signal input terminal 7 (13 of the lower layer semiconductor chip 13) ), The signal output terminal 8 (13) of the lower layer semiconductor chip 13 and the signal input terminal 7 (14) of the upper layer semiconductor chip 14, the signal output terminal 8 (14) of the upper layer semiconductor chip 14 and the signal input terminal 7 of the lower layer semiconductor chip 15. (15) are connected to each other through bumps 6.

  The lower semiconductor chips 11, 13, 15 are bonded to the metal main surface 2 of the circuit board 1 via bonding layers 5 a, 5 b, 5 c. The bonding layers 5a, 5b, and 5c can be formed from a brazing material containing various metals as a main component, or a conductive adhesive containing a metal filler such as Ag or Cu.

  The lower semiconductor chip 11 is located at the head of the signal line, and its signal input terminal 7 (11) is electrically connected to the signal supply terminal 3 provided on the circuit board 1 via the signal connection wire 4. Yes.

  In the lower layer semiconductor chip 13, the distance between the signal output terminal 8 (11) of the lower layer semiconductor chip 11 and the signal input terminal 7 (13) of the lower layer semiconductor chip 13 is the same as the signal input terminal 7 (12) of the upper layer semiconductor chip 12. It is mounted so as to be equal to the distance between the output terminals 8 (12).

  In the lower layer semiconductor chip 15, the distance between the signal output terminal 8 (13) of the lower layer semiconductor chip 13 and the signal input terminal 7 (15) of the lower layer semiconductor chip 15 is the same as that of the signal input terminal 7 (14) of the upper layer semiconductor chip 14. It is mounted so as to be equal to the distance between the output terminals 8 (14).

  The upper layer semiconductor chips 12 and 14 are mounted on the signal input terminal 7 and the signal output terminal 8 of the lower layer semiconductor chips 11, 13 and 15.

  In the upper layer semiconductor chip 12, the positions of the signal input terminal 7 (12) of the upper layer semiconductor chip 12 and the signal output terminal 8 (11) of the lower layer semiconductor chip 11 are aligned, and the signal output terminal 8 (12 ) And the signal input terminal 7 (13) of the lower semiconductor chip 13 are connected to the lower semiconductor chips 11 and 13 through the bumps 6 so that the positions of the signal input terminals 7 (13) are aligned.

  In the upper layer semiconductor chip 14, the positions of the signal input terminal 7 (14) of the upper layer semiconductor chip 14 and the signal output terminal 8 (13) of the lower layer semiconductor chip 13 are aligned, and the signal output terminal 8 (14) of the upper layer semiconductor chip 14 is aligned. ) And the signal input terminal 7 (15) of the lower-layer semiconductor chip 15 are connected to the lower-layer semiconductor chips 13 and 15 through the bumps 6 so as to be aligned.

  Next, a method for making the heights of the plurality of main surfaces 11a, 13a, 15a across the upper electronic components 12, 14 uniform by adjusting the relative thicknesses of the plurality of bonding layers 5a, 5b, 5c will be described in detail. .

  In general, a semiconductor device having a multi-chip module structure uses a plurality of semiconductor chips (lower semiconductor chips 11, 13, 15) having different chip thicknesses. When a plurality of semiconductor chips 11, 13, 15 having different chip thicknesses are mounted on the circuit board 1 as they are, main surfaces of the plurality of semiconductor chips 11, 13, 15 (surfaces on which the upper layer semiconductor chips 12, 14 are mounted, circuit surfaces) ) Steps occur at the heights of 11a, 13a, and 15a. When the upper semiconductor chips 12 and 14 are mounted across the main surfaces 11a, 13a, and 15a having different heights as described above, the upper semiconductor chips 12 and 14 are inclined. That is, bump connection with the lower semiconductor chips 11, 13, and 15 is performed in a state where the surface of the signal input terminal 7 of the upper semiconductor chips 12 and 14 and the surface of the signal output terminal 8 are not parallel. In this case, the connection strength may be reduced, or the connection strength may be different between the input terminal side and the output terminal side, which may reduce connection reliability.

  Therefore, even when a plurality of lower semiconductor chips 11, 13, 15 having different chip thicknesses are used, the lower semiconductor chips 11, 13, 15 and the circuit are arranged so that the heights of the main surfaces 11a, 13a, 15a are equal. The thickness of the bonding layers 5a, 5b, and 5c formed between the metal main surface 2 of the substrate 1 (forming thickness of the bonding material) is adjusted. For example, the thicknesses of the bonding layers 5a, 5b, and 5c may be calculated so that the sum of the thicknesses of the lower semiconductor chips 11, 13, and 15 and the bonding layers 5, 5b, and 5c is constant.

  The thicknesses of the bonding layers 5a, 5b, and 5c are preferably calculated by adding a difference from the thickness of the thickest semiconductor chip to the base reference thickness.

  For example, referring to the thickness of a semiconductor chip in practical use, the thickness of the lower semiconductor chips 11, 13, 15 and the like can be set as follows.

The thickness of the lower semiconductor chip 11: t11 = 0.100mm;
Thickness of lower semiconductor chip 13: t13 = 0.120 mm;
The thickness of the lower semiconductor chip 15: t15 = 0.080 mm;
Standard thickness of bonding layer: t0 (5) = 0.010mm

The thickness of the bonding layer 5a of the lower semiconductor chip 11: t5 (11) = t0 + (t13-t11) = 0.030 mm;
The thickness of the bonding layer 5b of the lower semiconductor chip 13: t5 (13) = t0 + (t13-t13) = 0.010 mm;
The thickness of the bonding layer 5c of the lower semiconductor chip 15: t5 (15) = t0 + (t13−t15) = 0.050 mm.

  In this way, the height of the main surfaces 11a, 13a, and 15a of the lower layer semiconductor chips 11, 13, and 15 mounted face-up (the main surface is facing upward) is 0.130 mm from the metal main surface 2 of the circuit board 1. Unified to height. Thus, in the upper semiconductor chips 12 and 14, the signal input terminal 7 and the signal output terminal 8 are located at the same height, and the input / output terminal surfaces are bump-connected in parallel.

  Next, an example of the manufacturing method of the semiconductor device according to the first embodiment described with reference to FIGS. 1A and 1B will be described with reference to FIGS.

  FIG. 2 shows a chip mounting machine 100 that is preferably used for manufacturing the semiconductor device of the first embodiment.

  The chip mounting machine 100 includes a chip supply stage 101 for setting the semiconductor chips 11 to 15, a chip mounting stage 102 for setting the circuit board 1 on which the lower and upper layer semiconductor chips 11 to 15 are mounted, and a lower layer to be mounted face up. A face-up chip mounting head 103 for handling the semiconductor chips 11, 13, 15, a face-down chip mounting head 104 for handling the upper semiconductor chips 12, 14 mounted face-down, and a chip supply stage 101 A first recognition camera 105 that performs recognition, a second recognition camera 106 that recognizes the input / output terminals 7 and 8 of the upper semiconductor chips 12 and 14 handled by the face-down chip mounting head 104 from below, and chip mounting Third recognition to perform recognition on stage 102 Is provided with a camera 107, a.

  The chip mounting stage 102 has a heating function for curing the bonding layer. The chip mounting stage 102 has a cooling function by an air blow or N2 blow type, and can quickly cool the heated semiconductor chips 11 to 15.

  On the chip supply stage 101, the lower semiconductor chips 11, 13, and 15 are set face up, and the upper semiconductor chips 12 and 14 are set face down.

  On the chip mounting stage 102, the circuit board 1 is set with the metal main surface 2 facing upward.

  In the first embodiment, for convenience, the thicknesses of the lower semiconductor chips 11, 13, 15 are assumed as described above, and the thicknesses of the bonding layers 5a, 5b, 5c are calculated as described above. The calculated values are for facilitating the understanding of the present invention, and the present invention is not limited thereto. The present invention is also suitably applied to a semiconductor chip having a thickness other than the above.

  As the forming material of the bonding layers 5a, 5b, and 5c, the brazing material or the conductive adhesive described above can be used. In the following description, a conductive adhesive containing an Ag filler is used.

  The chip mounting machine 100 uses two mounting heads, a face-up chip mounting head 103 and a face-down chip mounting head 104, but there is no restriction on the portion that contacts the semiconductor chips 11-15. Can share one mounting head. Even if there is a restriction on the contacted part, a single mounting head can be used if the parts at that part can be replaced.

[First manufacturing method]
Next, the first manufacturing method (steps 1 to 14) of the semiconductor device according to the first embodiment shown in FIGS. 1A and 1B using the chip mounting machine 100 shown in FIG. 2 is further illustrated. 3 will be described with reference to the flowchart (S101 to S109).

  The following steps 1 to 8 correspond to steps S101 to S105 in FIG. After completion of step 8, S106 of FIG. 3 is executed, that is, the mounting confirmation of the lower layer semiconductor chips 11, 13, and 15 is executed by the third recognition camera 107 and the like. If the mounting is not completed, the process returns to the process of S104 in FIG. 3, and if completed, the process proceeds to S107 (step 9).

  The step 9 below corresponds to the step S107 in FIG. That is, the lower layer semiconductor chips 11, 13, 15 are fixed to the plurality of mounting regions 1 a, 1 b, 1 c on the circuit board 1.

  The following steps 10 to 14 correspond to the step S108 of FIG. After step 14 described below, S109 in FIG. 3 is executed, and the mounting confirmation of the upper semiconductor chips 12 and 14 is executed by the third recognition camera 107 and the like. If the mounting has not been completed, the process returns to step S108 in FIG. 3, and if completed, the process ends.

  In particular, in step S104 (step 7), before the lower semiconductor chips 11, 13, 15 are mounted on the circuit board 1, the heights of the plurality of main surfaces 11a, 13a, 15a across the upper semiconductor chips 12, 14 are uniform. It is the process of forming an adjustment element so that.

  In particular, in step S105 (step 8), the lower electronic components 11, 13, 15 are matched with the distance between the signal input / output terminals 7, 8 of the upper electronic components 12, 14 straddling the lower electronic components 11, 13, 15. This is a process of mounting on the circuit board 1.

  In particular, in the process of S108 (steps 12 and 14), the input / output terminals 7 and 8 of the upper electronic components 12 and 14 are input to the lower electronic components 11 and 13 of the lower electronic components 11 and 13, respectively. In this step, bumps are connected to the terminals 7 and the output terminals 8 of the other lower electronic components 13 and 15.

[Step 1]
For the upper semiconductor chip 12 on the chip supply stage 101, the outer shape of the chip is recognized by using the first recognition camera 105, picked up by the face-down chip mounting head 104, and moved onto the second recognition camera 106, The position of the signal input terminal 7 (12) and the signal output terminal 8 (12) of the upper semiconductor chip 12 is recognized, and after measuring the distance between the signal input terminal 7 (12) and the signal output terminal 8 (12), the chip Return to the original location of the supply stage 101.

[Step 2]
The upper layer semiconductor chip 14 on the chip supply stage 101 is recognized by the first recognition camera 105 and picked up by the face-down chip mounting head 104 and moved onto the second recognition camera 106. After recognizing the positions of the signal input terminal 7 (14) and the signal output terminal 8 (14) of the upper semiconductor chip 14 and measuring the distance between the signal input terminal 7 (14) and the signal output terminal 8 (14), Return to the original location of the chip supply stage 101.

[Step 3]
In order to form the bonding layer 5a at the position (mounting region 1a) on which the lower semiconductor chip 11 is mounted on the circuit board 1, the bonding material 5 (11), which is a conductive adhesive containing Ag filler, is supplied. The supply amount is considered so that the thickness of the bonding layer 5a becomes a target value when the chip is mounted. In the lower layer semiconductor chip 11, an amount of Ag paste of [t5 (11) × area of the semiconductor chip 11] is supplied.

[Step 4]
For the lower-layer semiconductor chip 11 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outline and the positions of the signal input terminal 7 (11) and the signal output terminal 8 (11) for mounting the face-up chip. The lower semiconductor chip is picked up by the head 103 and moved onto the circuit board 1, the mounting angle is adjusted to a predetermined angle, and the position of the signal input terminal 7 (11) is adjusted to the connection position with the signal input terminal 7. 11 The head 103 for mounting the face-up chip is set so that the height of the back surface is t5 (11) = 0.030 mm from the metal main surface 2 of the circuit board 1 and the height of the main surface (main surface) 11a is 0.130 mm. Lower.

[Step 5]
In order to form the bonding layer 5b at the position (mounting region 1b) where the lower semiconductor chip 13 is mounted on the circuit board 1, the bonding material 5 (13) is supplied. Considering the supply amount so that the thickness of the bonding layer 5b becomes a target value when the chip is mounted, the lower semiconductor chip 13 supplies Ag paste in an amount of [t5 (13) × area of the semiconductor chip 13].

[Step 6]
With respect to the lower layer semiconductor chip 13 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outer shape and the positions of the signal input terminal 7 (13) and the signal output terminal 8 (13), and the face-up mounting head The pickup is picked up at 103 and moved onto the circuit board 1, the mounting angle is adjusted to a predetermined angle, and the signal input terminal 7 (13) of the lower layer semiconductor chip 13 and the signal output terminal 8 (11) of the lower layer semiconductor chip 11 are The signal input terminal 7 (13) of the lower layer semiconductor chip 13 is placed at a position where the distance is equal to the distance between the signal input terminal 7 (12) of the upper layer semiconductor chip 12 and the signal output terminal 8 (12) measured in advance. At the same time, face up so that the height of the back surface of the lower layer semiconductor chip 13 is t5 (13) = 0.010 mm and the height of the main surface (main surface) 13 a is 0.130 mm from the metal main surface 2 of the circuit board 1. Lower the chip mounting head 103. Make.

[Step 7]
The bonding material 5 (15) is supplied to the position on the circuit board 1 where the lower semiconductor chip 15 is mounted. Considering the supply amount so that the thickness of the bonding layer 5c becomes a target value when the chip is mounted, the semiconductor chip 15 supplies Ag paste in an amount of [t5 (15) × area of the semiconductor chip 15].

[Step 8]
For the lower-layer semiconductor chip 15 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outline and the positions of the signal input terminal 7 (15) and the signal output terminal 8 (15) for mounting the face-up chip. Picked up by the head 103 and moved onto the circuit board 1, the mounting angle is adjusted to a predetermined angle, and the signal input terminal 7 (15) of the lower semiconductor chip 15 and the signal output terminal 8 (13) of the lower semiconductor chip 13 The signal input terminal 7 (15) of the lower semiconductor chip 15 is located at a position where the distance between the signal input terminal 7 (14) and the signal output terminal 8 (14) of the upper semiconductor chip 14 is measured in advance. , The height of the back surface of the lower layer semiconductor chip 15 is t5 (15) = 0.050 mm from the metal main surface 2 of the circuit board 1, and the height of the main surface (main surface) 11 a is 0.130 mm. Up-chip mounting head 103 Descent.

[Step 9]
The chip mounting stage 102 is heated to cure the Ag paste. After a predetermined time has elapsed, the height of the main surfaces 11a, 13a, 15a of the lower layer semiconductor chips 11, 13, 15 is 0.130 mm.

[Step 10]
Bumps 6 are placed on the signal input terminals 7 and the signal output terminals 8 of the lower layer semiconductor chips 11, 13, 15. For this reason, a supply function may be added to the chip mounting machine 100, and it may be mounted manually using tweezers or the like.

[Step 11]
For the upper semiconductor chip 12 on the chip supply stage 101, the outer shape of the chip is recognized using the first recognition camera 105, picked up by the head 104 for mounting the face-down chip, moved onto the second recognition camera 106, The positions of the signal input terminal 7 (12) and the signal output terminal 8 (12) of the upper semiconductor chip 12 are recognized.

[Step 12]
The face-down chip mounting head 104 picking up the upper layer semiconductor chip 12 is moved onto the circuit board 1, and the signal input terminal 7 (12) of the upper layer semiconductor chip 12, the signal output terminal 8 (11) of the lower layer semiconductor chip 11, and The signal output terminal 8 (12) of the upper semiconductor chip 12 and the signal input terminal 7 (13) of the lower semiconductor chip 13 are aligned, the face-up chip mounting head 103 is lowered, and the bump 6 is thermocompression bonded. Connect.

[Step 13]
For the upper semiconductor chip 14 on the chip supply stage 101, the outer shape of the chip is recognized using the first recognition camera 105, picked up by the face-down chip mounting head 104, and moved onto the second recognition camera 106. The positions of the signal input terminal 7 (14) and the signal output terminal 8 (14) of the upper semiconductor chip 14 are recognized.

[Step 14]
The face-down chip mounting head 104 picking up the upper layer semiconductor chip 14 is moved onto the circuit board 1, and the signal input terminal 7 (14) of the upper layer semiconductor chip 14, the signal output terminal 8 (13) of the lower layer semiconductor chip 13, and The signal output terminal 8 (14) of the upper layer semiconductor chip 14 and the signal input terminal 7 (15) of the lower layer semiconductor chip 15 are aligned, the face-up chip mounting head 103 is lowered, and the bumps 6 are thermocompression bonded. Connect.

  Thus, the mounting of the lower and upper semiconductor chips 11 to 15 is completed.

  According to the first manufacturing method, when the bonding material (bonding layer) 5 is cured, the lower-layer semiconductor chips 11, 13 and 15 mounted face-up are released from being fixed by the face-up chip mounting head 103. Therefore, it is preferable to consider the possibility that the position is displaced during curing. Therefore, in order to ensure the bump connection between the signal input terminal 7 and the signal output terminal 8, the diameter of the signal input terminal 7 is preferably set larger than the diameter of the signal output terminal 8. As a result, stable connection can be maintained even when the lower-layer semiconductor chips 11, 13, and 15 mounted face-up are displaced in opposite directions (separation directions).

  Also, when the terminal diameter cannot be changed or when the position specifications are strict, the following second manufacturing method [Step 2-1] to [Step 2-15] can be used to mount with high accuracy. Can be executed.

[Second manufacturing method]
In the first manufacturing method, the upper semiconductor chips 12, 14 are mounted in a state where the lower semiconductor chips 11, 13, 15 are not completely fixed. In the second manufacturing method, the lower semiconductor chips 11, 13 and 15 are completely fixed, and then the upper semiconductor chips 12 and 14 are mounted.

  In the first manufacturing method, first, the upper semiconductor chip 12 (14) was measured. In the second manufacturing method, after one lower semiconductor chip 11 (13) is fixed, the upper semiconductor chip 12 (14) is measured, and the other lower semiconductor chip 13 (15) is changed according to the measurement result. Position and fix.

  Next, a second manufacturing method of the semiconductor device of the first embodiment shown in FIGS. 1A and 1B will be described using the chip mounting machine 100 shown in FIG. In addition, about the common point of the 1st and 2nd manufacturing method, the description regarding the 1st manufacturing method can be referred suitably.

[Step 2-1]
A bonding material 5 (11), which is a conductive adhesive containing Ag filler, is supplied to a position (mounting region 1a) on which the lower semiconductor chip 11 is mounted on the circuit board 1. Considering the supply amount so that the thickness of the bonding layer 5a becomes a target value when the chip is mounted, the lower semiconductor chip 11 supplies Ag paste in an amount of [t5 (11) × area of the semiconductor chip 11].

[Step 2-2]
For the lower-layer semiconductor chip 11 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outline and the positions of the signal input terminal 7 (11) and the signal output terminal 8 (11) for mounting the face-up chip. The lower semiconductor chip 11 is moved on the circuit board 1 by using the head 103, the mounting angle is adjusted to a predetermined angle, and the position of the signal input terminal 7 (11) is adjusted to the connection position with the signal output terminal 8. The face-up chip mounting head 103 is lowered so that the height of the back surface is t5 (11) = 0.030 mm from the metal main surface 2 of the circuit board 1.

[Step 2-3]
In this state, the chip mounting stage 102 is heated to cure the Ag paste. After a predetermined time, the height of the back surface of the lower layer semiconductor chip 11 is fixed at 0.030 mm, and the height of the main surface (main surface) 11a is 0.130 mm.

[Step 2-4]
The upper semiconductor chip 12 on the chip supply stage 101 is recognized by the first recognition camera 105 and picked up by the face-down chip mounting head 104 and moved onto the second recognition camera 106. The positions of the signal input terminal 7 (12) and the signal output terminal 8 (12) of the upper layer semiconductor chip 12 are recognized, and the distance between the signal input terminal 7 (12) and the signal output terminal 8 (12) is measured.

[Step 2-5]
The bonding material 5 (13) is supplied to the position (mounting region 1b) where the lower semiconductor chip 13 is mounted on the circuit board 1. Considering the supply amount so that the thickness of the bonding layer 5b becomes a target value when the chip is mounted, the lower semiconductor chip 13 supplies Ag paste in an amount of [t5 (13) × area of the semiconductor chip 13].

[Step 2-6]
For the lower semiconductor chip 13 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outline and the positions of the signal input terminal 7 (13) and the signal output terminal 8 (13) to mount the face-up chip. Picked up by the head 103 and moved onto the circuit board 1, the mounting angle is adjusted to a predetermined angle, and the signal input terminal 7 (13) of the lower layer semiconductor chip 13 and the signal output terminal 8 (11) of the lower layer semiconductor chip 11 are matched. The signal input terminal 7 (13) of the lower layer semiconductor chip 13 is located at a position where the distance between the signal input terminal 7 (12) of the upper layer semiconductor chip 12 and the signal output terminal 8 (12) measured in this step is equal. ), The face-up chip mounting head 103 is lowered so that the height of the back surface of the lower layer semiconductor chip 13 is t5 (13) = 0.010 mm from the metal main surface 2 of the circuit board 1.

[Step 2-7]
In this state, the chip mounting stage 102 is heated to cure the Ag paste. After the elapse of a predetermined time, the height of the back surface of the lower semiconductor chip 13 is fixed at 0.010 mm, and the height of the main surface (main surface) 11a becomes 0.130 mm.

[Step 2-8]
Bumps 6 are placed on the signal output terminals 8 (11) of the lower semiconductor chip 11 and the signal input terminals 7 (13) of the lower semiconductor chip 13.

[Step 2-9]
The face-down chip mounting head 104 picking up the upper layer semiconductor chip 12 is moved onto the circuit board 1, and the signal input terminal 7 (12) of the upper layer semiconductor chip 12, the signal output terminal 8 (11) of the lower layer semiconductor chip 11, and The signal output terminal 8 (12) of the upper semiconductor chip 12 and the signal input terminal 7 (13) of the lower semiconductor chip 13 are aligned, the face-up chip mounting head 103 is lowered, and the bump 6 is thermocompression bonded. Connect.

[Step 2-10]
The upper layer semiconductor chip 14 on the chip supply stage 101 is recognized by the first recognition camera 105 and picked up by the face-down chip mounting head 104 and moved onto the second recognition camera 106. The positions of the signal input terminal 7 (14) and the signal output terminal 8 (14) of the upper layer semiconductor chip 14 are recognized, and the distance between the signal input terminal 7 (14) and the signal output terminal 8 (14) is measured.

[Step 2-11]
The bonding material 5 (15) is supplied to the position (mounting region 1c) where the lower layer semiconductor chip 15 is mounted on the circuit board 1. Considering the supply amount so that the thickness of the bonding material 5 becomes a target value when the chip is mounted, the lower layer semiconductor chip 15 supplies Ag paste in an amount of [t5 (15) × area of the semiconductor chip 15].

[Step 2-12]
For the lower-layer semiconductor chip 15 on the chip supply stage 101, the first recognition camera 105 is used to recognize the chip outline and the positions of the signal input terminal 7 (15) and the signal output terminal 8 (15) for mounting the face-up chip. Picked up by the head 103 and moved onto the circuit board 1, the mounting angle is adjusted to a predetermined angle, and the signal input terminal 7 (15) of the lower layer semiconductor chip 15 and the signal output terminal 8 (13) of the lower layer semiconductor chip 13 The signal input terminal 7 of the lower layer semiconductor chip 15 is located at a position where the distance between the signal input terminal 7 (14) of the upper layer semiconductor chip 14 and the signal output terminal 8 (14) measured in Step 2-10 is equal to the distance. Together with (15), the face-up chip mounting head 103 is lowered so that the height of the back surface of the lower layer semiconductor chip 15 is t5 (15) = 0.050 mm from the metal main surface 2 of the circuit board 1.

[Step 2-13]
In this state, the chip mounting stage 102 is heated to cure the Ag paste. After a predetermined time has elapsed, the height of the back surface of the lower semiconductor chip 15 is fixed at 0.050 mm, and the height of the main surface 15a is 0.130 mm.

[Step 2-14]
The bumps 6 are placed on the signal output terminals 8 (13) of the lower semiconductor chip 13 and the signal input terminals 7 (15) of the lower semiconductor chip 15.

[Step 2-15]
The face-down chip mounting head 104 picking up the upper layer semiconductor chip 14 is moved onto the circuit board 1, and the signal input terminal 7 (14) of the upper layer semiconductor chip 14, the signal output terminal 8 (13) of the lower layer semiconductor chip 13, and The signal output terminal 8 (14) of the upper layer semiconductor chip 14 and the signal input terminal 7 (15) of the lower layer semiconductor chip 15 are aligned, the face-up chip mounting head 103 is lowered, and the bumps 6 are thermocompression bonded. Connect. Thus, the mounting of the lower and upper semiconductor chips 11 to 15 is completed.

  In the manufacturing method described above, the positions of the signal input terminals 7 and the signal output terminals 8 of the upper semiconductor chips 12 and 14 to be mounted face-down in the mounting flow using the two chip mounting heads 103 and 104. Although the recognition and the distance between the signal input / output terminals 7 and 8 are measured, one mounting head may be used if it is picked up and measured in advance and then operated to return to the supply stage.

  Effects of the semiconductor device and the manufacturing method thereof according to the first embodiment will be described.

  The first effect is that the thickness of the bonding material (bonding layers 5a, 5b, 5c) interposed between the metal main surface 2 of the circuit board 1 and the lower semiconductor chips 11, 13, 15 mounted face-up is By setting according to the thickness of the lower layer semiconductor chips 11, 13, and 15, the heights of the main surfaces 11a, 13a, and 15a of the lower layer semiconductor chips 11, 13, and 15 can be made equal in the horizontal direction. As a result, the upper semiconductor chips 12 and 14 mounted across the main surfaces 11a, 13a, and 15a and mounted face-down can be mounted with a good load balance. Therefore, the yield is improved and the connection reliability is improved. .

  The second effect is that, in the connection between the lower semiconductor chips 11, 13, 15 and the circuit board 1, a wire connection can be taken according to the application, the degree of freedom of connection is high, and the connection range is wide. .

  The third effect is that the lower semiconductor chips 11, 13, 15 are firmly fixed to the integrated circuit board 1, and the heights of the terminal surfaces of the adjacent lower semiconductor chips 11, 13, 15 are made constant. Thus, the upper semiconductor chips 12 and 14 mounted face down can be bonded with a good load balance, and the connection reliability is improved. This can eliminate the need for reinforcement with an underfill resin.

  The fourth effect is that the lower semiconductor chips 11, 13 and 15 mounted face up and the upper semiconductor chips 12 and 14 mounted face down are alternately arranged, and the terminals of the semiconductor chips 11 to 15 are bump-connected. As a result, the wiring length is shortened compared to the conventional wire connection or connection by a wiring member.

  The fifth effect is that the lower-layer semiconductor chips 11, 13, and 15 mounted face-up and the upper-layer semiconductor chips 12 and 14 mounted face-down are alternately arranged, thereby providing a chip surface (main surface, circuit surface, or mounting). It is that it can be mounted in layers. As a result, the mounting area can be reduced as compared with the case of mounting on a conventional face-up.

  The sixth effect is that, in the lower layer semiconductor chips 11, 13, 15 and the upper layer semiconductor chips 12, 14, the signal output terminals 8 and the signal input terminals 7 are arranged so as to face each other and are bump-connected, so that wires and wiring members can be connected. This eliminates the need for material costs, and eliminates the need for wire bonding and wiring member connection.

  The seventh effect is that the main surfaces 11a, 13a, 15a of the lower semiconductor chips 11, 13, 15 have the same height, so that the alignment of the upper semiconductor chips 12, 14 and bump connection are facilitated. That is.

(Embodiment 2)
In the second embodiment, differences between the second embodiment and the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for the common points of the two embodiments.

  Referring to FIG. 1A, in the first embodiment, the upper layer semiconductor element 12 (14) is mounted across a plurality of lower layer semiconductor elements 11, 13 (13, 15). Referring to FIG. 4, in the second embodiment, an upper layer semiconductor element 12 is mounted across the lower layer semiconductor element 11 and the circuit board 1.

  Referring to FIG. 4, in the semiconductor device of the second embodiment, the upper layer semiconductor chip 12 mounted face down on the signal output terminal 8 of the lower layer semiconductor chip 11 mounted face up and the signal input terminal 7 of the circuit board 1. The signal input / output terminals 7 and 8 are aligned and joined using bumps 6. As described above, at least one of the plurality of electronic components 1 and 11 across the upper semiconductor chip 12 may be an electronic component other than the semiconductor chip.

(Embodiment 3)
Referring to FIG. 1A, in the first embodiment and the like, a plurality of lower layer semiconductor chips 11, 13, and 15 having different thicknesses are used, and the thickness of the bonding layers 5a, 5b, and 5c is adjusted. The heights of the main surfaces 11a, 13a, and 15a of the lower layer semiconductor element are unified.

  Referring to FIG. 5A, in the third embodiment, the heights of main surfaces 11a, 13a, and 15a are adjusted by adjusting the relative heights of mounting regions 1a, 1b, and 1c on circuit board 1. Unify.

  The thickness adjustment of the bonding layers 5a, 5b, and 5c of the first embodiment and the height adjustment of the mounting regions 1a, 1b, and 1c of the third embodiment are used in combination according to individual differences in the thickness of the semiconductor chip or the dimensional accuracy of the equipment. May be.

  In the third embodiment, differences between the third embodiment and the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for the common points of both embodiments.

  Referring to FIG. 5A, the semiconductor device of the third embodiment is mainly composed of a circuit board 1 and five semiconductor chips 11 to 15 mounted on the circuit board 1.

  Concave portions 51 and 52 are formed in the mounting regions 1a and 1b of the lower semiconductor chips 11 and 13 mounted face up on the circuit board 1 (steps are formed on the circuit board 1). The mounting regions 1a and 1b (the bottom surfaces of the recesses 51 and 52 in which they are provided) and the surface of the mounting region 1c are covered with a metal film (2) such as Au or Cu. It is connected to the ground (metal main surface 2).

  The depths of the recesses 51 and 52 are set so that the sum of the thickness of the circuit board 1 and the thicknesses of the lower semiconductor chips 11, 13, and 15 becomes constant. That is, according to the difference in chip thickness of the lower layer semiconductor chips 11, 13, 15, the recesses 51, 52 are partially formed on the circuit board 1, and the thickness of the circuit board 1 is partially changed, thereby mounting regions The heights of 1a, 1b, and 1c are adjusted to make the main surfaces 11a, 13a, and 15a uniform.

  The depths of the recesses 51 and 52 are calculated by adding a difference from the thickness of the thinnest lower layer semiconductor chip 15. For example, it is calculated as follows from the thickness of a semiconductor chip that is in practical use.

The thickness of the lower semiconductor chip 11: t11 = 0.100mm;
Thickness of lower semiconductor chip 13: t13 = 0.120 mm;
The thickness of the lower semiconductor chip 15: t15 = 0.080 mm.

Recess 51 depth of lower semiconductor chip 11: Recess (11) is t11-t15 = 0.020mm;
Recess 52 depth of lower semiconductor chip 13: Recess (13) is t13-t15 = 0.040mm;
Recess depth of lower semiconductor chip 15 (no recess): Recess (15) is t15-t15 = 0.000 mm.

  The further effect of Embodiment 3 is demonstrated.

  The first effect is that, for example, by providing concave portions 51, 52 or steps corresponding to the thickness of the lower semiconductor chips 11, 13, 15 on the metal main surface 2 on the circuit board 1, for example, That is, the main surfaces 11a, 13a, and 15a of the lower layer semiconductor chips 11, 13, and 15 mounted face-up can be flush with each other in the horizontal direction. As a result, when the upper semiconductor chips 12 and 14 mounted face-down are connected, an equivalent load is applied to the signal output terminal 8 and the signal input terminal 7, and connection reliability is improved.

  The second effect is that the thickness of the bonding layers 5a, 5b, and 5c does not have to be set for each of the lower layer semiconductor chips 11, 13, and 15. This facilitates process management.

  A third effect is that the thicknesses of the bonding layers 5a, 5b, and 5c can be unified to a thickness that ensures a balance between heat dissipation and bonding reliability. This improves the quality.

(Embodiment 4)
In the fourth embodiment, differences between the fourth embodiment and the third embodiment will be mainly described, and the description of the third embodiment will be appropriately referred to for the common points of the two embodiments.

  Referring to FIG. 5B, the semiconductor device of the fourth embodiment is mainly composed of a circuit board 1 and five semiconductor chips 11 to 15 mounted on the circuit board 1. The circuit board 1 has a laminated structure. In the circuit board 1, the heights of the mounting regions 1 a, 1 b, 1 c of the lower semiconductor chips 11, 13, 15 are the same as the sum of the thickness of the circuit board 1 and the lower semiconductor chips 11, 13, 15. Thus, the circuit board 1 is adjusted by being partially thickened or thinned. In the circuit board 1, metal films 2 a, 2 b, 2 c such as Au or Cu are formed between the layers and are electrically connected through the via hole 21.

  In the fourth embodiment, the heights of the mounting regions 1a, 1b, and 1c are adjusted by partially changing the thickness of the circuit board 1 according to the difference in the chip thickness of the lower layer semiconductor chips 11, 13, and 15. The main surfaces 11a, 13a, and 15a are made uniform in height.

  The fourth embodiment can achieve the same effects as the third embodiment.

(Embodiment 5)
In the fifth embodiment, differences between the fifth embodiment and the fourth embodiment will be mainly described, and the description of the fourth embodiment will be appropriately referred to for the common points of the two embodiments.

  Referring to FIGS. 6A and 6B, the semiconductor device of the fifth embodiment is mainly composed of a circuit board 1 and five semiconductor chips 11 to 15 mounted on the circuit board 1. . The circuit board 1 and a plurality of sub-boards 1001a to 1001c are formed to overlap each other. In the mounting regions 1a, 1b, and 1c on which the lower semiconductor chips 11, 13, and 15 mounted face-up are mounted, the sum of the thickness of the circuit board 1 and the lower semiconductor chips 11, 13, and 15 is constant. Sub-substrates 1001a to 1001c are stacked so as to be. As a result, in the circuit board 1, a recess 52 is formed at the center, and steps 54 and 55 are formed on both sides of the recess 52. A metal film such as Au or Cu is formed between the sub-substrates 1001 a to 1001 c and is electrically connected through the via hole 21.

  In the fifth embodiment, the mounting region is obtained by partially changing the thickness of the circuit board 1 by adjusting the stacked state of the sub-boards 1001a to 1001c in accordance with the difference in the chip thickness of the lower layer semiconductor chips 11, 13, and 15. The heights of 1a, 1b, and 1c are adjusted to make the main surfaces 11a, 13a, and 15a uniform.

  The fifth embodiment can achieve the same effects as the fourth embodiment.

(Embodiment 6)
In the sixth embodiment, differences between the sixth embodiment and the third embodiment will be mainly described, and the description of the third embodiment will be referred to as appropriate for the common points between the two embodiments.

  7A and 7B, the semiconductor device of the sixth embodiment is mainly mounted on the circuit board 1, the metal spacer 22 attached to the back surface of the circuit board 1, and the circuit board 1. And five semiconductor chips 11-15.

  The surface of the circuit board 1 is covered with a metal film or metal main surface 2 such as Au or Cu, and each is connected to the ground via a metal wire 20.

  A recess 52 is formed on the metal spacer 22 and corresponding to the mounting region 1 b of the lower semiconductor chip 13. Accordingly, steps 54 and 55 are formed between the intermediate mounting region 1b and the left and right mounting regions 1a and 1c, respectively. In the metal spacer 22 integrated with the circuit board 1, the heights of the left and right surfaces corresponding to the left and right mounting regions 1 a and 1 c and the height of the bottom surface of the recess 52 corresponding to the intermediate mounting region 1 b are part of the metal spacer 22. The total thickness and the thickness of the lower semiconductor chips 11, 13, 15 are formed to be constant with each other.

  The semiconductor device of the sixth embodiment can achieve the effects of the above-described fourth embodiment by using the metal spacer 22 without directly forming a recess or a step in the circuit board 1.

(Embodiment 7)
In the seventh embodiment, differences between the seventh embodiment and the third embodiment will be mainly described, and the description of the third embodiment will be appropriately referred to for the common points of the two embodiments.

  Referring to FIG. 8, the semiconductor device according to the seventh embodiment is mainly mounted on the metal spacer 22, the circuit board 1 attached to the surface of the metal spacer 22, and the circuit board 1 (11, 13, 15). And five semiconductor chips 11-15.

  The circuit boards 1 (11, 13, 15) have different thicknesses. That is, the sum of the thicknesses of the mounting regions 1a, 1b, 1c of the lower layer semiconductor chips 11, 13, 15 mounted with the main surfaces 11a, 13a, 15a facing upward and the thicknesses of the lower layer semiconductor chips 11, 13, 15 are mutually equal. The base material which comprises each circuit board 1 (11, 13, 15) is allocated so that it may become fixed. The surface of the circuit board 1 is covered with a metal film or metal main surface 2 such as Au or Cu, and each is connected to the ground with a metal wire 20.

  The semiconductor device of the seventh embodiment can achieve the effects of the third embodiment described above by using a plurality of circuit boards 1 (11, 13, 15) having different thicknesses.

(Embodiment 8)
In the eighth embodiment, differences between the eighth embodiment and the third embodiment will be mainly described, and the description of the third embodiment will be appropriately referred to for the common points of the two embodiments.

  Referring to FIGS. 9A and 9B, the semiconductor device of the eighth embodiment mainly includes a circuit board 1, a metal spacer (metal board) 22 attached to the surface of the circuit board 1, and a metal spacer 22. It is composed of five semiconductor chips 11 to 15 mounted thereon.

  Concave portions 51 and 52 are formed in the mounting regions 1a and 1b of the lower semiconductor chips 11 and 13 mounted face up on the metal spacer 22 (steps are formed on the metal spacer 22). The bottom surfaces of the recesses 51 and 52 and the surface of the mounting region 1 c are covered with a metal film such as Au or Cu, and each is connected to the ground via the metal wire 20.

  The depths of the recesses 51 and 52 are set such that the sum of the thickness of the metal spacer 22 and the thickness of the lower semiconductor chips 11, 13, and 15 is constant. That is, the recesses 51 and 52 are partially formed on the metal spacer 22 according to the difference in the chip thickness of the lower layer semiconductor chips 11, 13 and 15, and the thickness of the metal spacer 22 integral with the circuit board 1 is partially set. By changing the height, the heights of the mounting regions 1a, 1b, and 1c are adjusted, so that the main surfaces 11a, 13a, and 15a have a uniform height.

  The semiconductor device of the eighth embodiment can achieve the effects of the above-described third embodiment without changing the shape of the circuit board 1 by processing the metal spacer 22 integrated with the circuit board 1 with a step. Furthermore, the lower layer semiconductor chips 11, 13, 15 are directly mounted on the metal spacer 22 having a large heat capacity, so that the heat dissipation is improved. Further, since the lower layer semiconductor chips 11, 13, and 15 are directly mounted on the metal spacer 22, the ground connection can be made.

(Embodiment 9)
In the ninth embodiment, differences between the ninth embodiment and the eighth embodiment will be mainly described, and the description of the eighth embodiment will be appropriately referred to for the common points of the two embodiments.

  Referring to FIGS. 10A and 10B, the semiconductor device of the ninth embodiment mainly includes a circuit board 1, a metal spacer (metal board) 22 inserted in a space formed by hollowing out the inside of the circuit board 1, and It is composed of five semiconductor chips 11 to 15 mounted on the metal spacer 22.

  The metal spacer 22 has a plurality of top surfaces 22a, 22b, 22c provided with mounting regions 1a, 1b, 1c. Steps 54 and 55 are formed between the plurality of top surfaces 22a, 22b and 22c, respectively. The plurality of top surfaces 22a, 22b, 22c are such that the sum of the protruding height of the plurality of top surfaces 22a, 22b, 22c from the surface of the circuit board 1 and the thickness of the lower layer semiconductor chips 11, 13, 15 is constant. Is formed.

  The semiconductor device of the ninth embodiment can achieve the same effects as the semiconductor device of the eighth embodiment described above.

(Embodiment 10)
In the tenth embodiment, differences between the tenth embodiment and the third embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for the common points between the two embodiments.

  Referring to FIG. 11, the semiconductor device of the tenth embodiment mainly includes a circuit board 1, a metal spacer (metal substrate) 22, and five semiconductor chips 11 to 15 mounted on the metal spacer 22. ing.

  The metal spacer 22 has a plurality of top surfaces (mounting regions) 22a, 22b, and 22c on which the mounting regions 1a, 1b, and 1c are provided. Steps 54 and 55 are formed between the plurality of top surfaces (mounting regions) 22a, 22b and 22c, respectively. The plurality of top surfaces (mounting regions) 22a, 22b, and 22c are the sum of the protruding height from the reference surface of the plurality of top surfaces (mounting regions) 22a, 22b, and 22c and the thicknesses of the lower semiconductor chips 11, 13, and 15. Are formed to be constant with respect to each other.

  On the side of the upper semiconductor chips 12 and 14 mounted face down, the circuit board 1 is bonded to form an electric circuit. Thus, by fixing the back surfaces of the upper semiconductor chips 12 and 14 mounted face-down to the circuit board 1, the structure is strengthened and the connection reliability is improved.

  Furthermore, the semiconductor device of the tenth embodiment can achieve the same effects as the semiconductor device of the ninth embodiment described above.

  Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and further modifications and substitutions are made without departing from the basic technical idea of the present invention. Or adjustments can be made.

(Appendix 1)
A substrate,
A plurality of lower layer electronic components mounted face up on a plurality of mounting areas of the substrate,
At least one upper layer electronic component mounted face-down across a plurality of main surfaces of the plurality of lower layer electronic components,
An adjustment element formed so that the heights of the plurality of main surfaces across the upper-layer electronic component are uniform;
With
The adjustment element is the plurality of mounting areas,
An electronic device in which the heights of the plurality of main surfaces across the upper layer electronic component are made uniform by adjusting the relative heights of the plurality of mounting regions according to the difference in thickness of the plurality of lower layer electronic components.
(Appendix 2)
The electronic device according to supplementary note 1, wherein the adjustment element is another substrate that is joined to or fitted to the front surface or the back surface of the circuit board.
(Appendix 3)
The substrate on which the plurality of lower layer electronic components are mounted is a metal plate;
The electronic device according to appendix 1 or 2, wherein the upper electronic component is connected to a circuit board.
(Appendix 4)
Fixing the first and second lower layer semiconductor chips to the first and second mounting regions of the substrate;
Mounting an upper layer semiconductor chip across the fixed first and second lower layer semiconductor chips;
Fixing the upper semiconductor chip to the first and second lower semiconductor chips;
A method for manufacturing a semiconductor device.
(Appendix 5)
Mounting a first lower layer semiconductor chip face up on a first mounting region of a substrate;
Measuring the upper semiconductor chip;
Mounting a second lower layer semiconductor chip electronic component face up on a second mounting region of the substrate according to at least the measurement result of the upper layer semiconductor chip;
Mounting the upper layer semiconductor chip component across the first and second lower layer electronic components;
Fixing the first and second semiconductor chips and the upper semiconductor chip;
A method for manufacturing a semiconductor device comprising:
(Appendix 6)
6. The method of manufacturing a semiconductor device according to appendix 4 or 5, wherein the upper semiconductor chip is bump-connected across the first and second lower semiconductor chips.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Also, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the entire disclosure of the present invention. Is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 Circuit board (board)
1a, 1b, 1c Mounting area 1 (11), 1 (13), 1 (15) Multiple circuit boards 2 Metal main surface (metal mounting surface, ground, heat sink, metal film)
2, 2a, 2b, 2c Metal film 3 Signal supply terminal 4 Signal connection wire 5 Bonding layer (bonding material)
5a, 5b, 5c Bonding layer (bonding material)
6 Bump 7 Signal input terminal 8 Signal output terminal 11, 13, 15 Lower layer electronic component, lower layer semiconductor chip (face-up semiconductor chip)
11a, 13a, 15a Main surface (mounting surface)
12, 14 Upper layer electronic component, upper layer semiconductor chip (face-down semiconductor chip)
20 Metal wire (Ground connection wire)
21 Via hole (via for ground connection)
22 Metal spacer (metal substrate)
22a, 22b, 22c Multiple top surfaces (mounting area)
51, 52 Concave 54, 55 Step 100 Chip mounting machine 101 Chip supply stage 102 Chip mounting stage 103 Face-up chip mounting head 104 Face-down chip mounting head 105 First recognition camera 106 Second recognition camera 107 Third Recognition cameras 1001a to 1001c Sub board

Claims (10)

A substrate,
A plurality of lower layer electronic components mounted face up on a plurality of mounting areas of the substrate,
At least one upper layer electronic component mounted face-down across a plurality of main surfaces of the plurality of lower layer electronic components,
An adjustment element formed so that the heights of the plurality of main surfaces across the upper-layer electronic component are uniform;
With
The plurality of lower layer electronic components have different thicknesses from each other,
The substrate, the plurality of mounting areas, have a recess or step according to the material thickness of the plurality of lower layer electronic components corresponding,
A circuit is formed in the recess or step,
An electronic device characterized by that. As the adjustment element, comprising a plurality of bonding layers formed between the plurality of mounting regions and the plurality of lower layer electronic components to bond both,
2. The electronic device according to claim 1, wherein heights of the plurality of main surfaces across the upper electronic component are made uniform by adjusting a relative thickness of the plurality of bonding layers. The adjustment element is the plurality of mounting areas,
3. The electronic device according to claim 1, wherein heights of the plurality of main surfaces across the upper-layer electronic component are made uniform by adjusting a relative height of the plurality of mounting regions. The heights of the plurality of mounting areas are different from each other.
4. The electronic device according to claim 3, wherein at least one of a step, a plurality of recesses, a difference in substrate thickness, and a difference in substrate height is formed on the substrate. A plurality of lower layer semiconductor chips which are the lower layer electronic components;
At least one upper-layer semiconductor chip that is the upper-layer electronic component that is bump-connected to the plurality of lower-layer semiconductor chips in a state of being parallel to the plurality of lower-layer semiconductor chips;
The electronic device according to claim 1, comprising: A distance between input and output terminals between an input terminal and an output terminal of the one upper-layer electronic component;
Of the two lower electronic components straddling the upper electronic component, one lower electronic component has an output terminal connected to the input terminal of the upper electronic component, and the other lower electronic component has the The distance between the input terminal connected to the output terminal of the upper layer electronic component,
The electronic device according to claim 1, wherein the electronic devices are equal to each other.   The electronic device according to claim 1, wherein the electronic device has a multi-electronic component module structure in which heights of the plurality of main surfaces are uniformly adjusted partially or entirely. Mounting a plurality of lower layer electronic components face-up on a plurality of mounting areas of the substrate;
A process of mounting at least one upper layer electronic component face down across a plurality of main surfaces of the plurality of lower layer electronic components;
Before mounting the lower layer electronic component, forming an adjustment element so that the height of the plurality of main surfaces across the upper layer electronic component is uniform; and
With
The plurality of lower layer electronic components have different thicknesses from each other,
The substrate, the plurality of mounting areas, have a recess or step according to the material thickness of the plurality of lower layer electronic components corresponding,
A circuit is formed in the recess or step,
A method for manufacturing an electronic device.   The adjustment element is any one or more of a plurality of bonding layers formed between the plurality of mounting regions and the plurality of lower layer electronic components to bond the two and the plurality of mounting regions. Item 9. A method for manufacturing an electronic device according to Item 8. Mounting a plurality of lower layer electronic components face-up on a plurality of mounting areas of the substrate;
A process of mounting at least one upper layer electronic component face down across a plurality of main surfaces of the plurality of lower layer electronic components;
With
The plurality of lower layer electronic components are mounted on the substrate in accordance with the distance between input and output terminals of the upper layer electronic component straddling the plurality of lower layer electronic components,
The input / output terminal of the upper layer electronic component is bump-connected to the input terminal of one of the lower layer electronic components and the output terminal of the other lower layer electronic component, respectively, of the plurality of lower layer electronic components,
The plurality of lower layer electronic components have different thicknesses from each other,
The substrate, the plurality of mounting areas, have a recess or step according to the material thickness of the plurality of lower layer electronic components corresponding,
A circuit is formed in the recess or step,
A method for manufacturing an electronic device.

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