JP6365718B1 - Computer system and memory copy method - Google Patents

Abstract

A memory data transfer time is shortened while reducing a load on a CPU. A duplicated computer system that uses a dirty information indicating whether or not data has been rewritten to use a storage area management unit that manages a storage area of a main memory, and a computer system other than the computer system. When performing copy control to copy data, based on dirty information, a data transfer unit for copying only the data in the main memory storage area where data has been rewritten, and data transfer outside copy control The data transfer unit for copying is configured by hardware and is connected to a different bus from the data transfer unit for normal use. [Selection] Figure 11

Description

  The present invention relates to a computer system and a memory copy method for the computer system.

  The memory capacity of a computer system is increasing due to the miniaturization of hardware (HW), and the fault-tolerant system and the virtualization system are required to increase the memory capacity accordingly. In a fault-tolerant system, when moving two systems to dual, in a virtual system, when moving a guest system to another device by live migration, temporarily stop normal processing and wait for memory data from the active system It is necessary to transfer to the system. However, as the memory capacity increases, the copy time of the memory contents becomes longer, and there is a problem that the processing stop time increases. As a countermeasure, memory is managed in units of "pages" of a certain size, and after starting duplication or migration, memory data updated by operating the system is marked as dirty pages, and the memory data is transferred. After that, a method has been proposed in which only the dirty page is transferred to shorten the data transfer time of the memory.

  For example, Patent Document 1 describes performing dirty control regarding access between I / O devices in a multiprocessor system.

Special Table 2002-518734

  However, when performing dirty control, it is necessary to cover the entire area of the memory mounted in the system in order to record and manage the dirty pages that can be used here. However, the dirty page recording and management function implemented in the Translation Lookaside Buffer (TLB) incorporated in many processors has insufficient capacity. For this reason, the method for performing dirty control may use TLB, but the entire area of the memory installed in the system is recorded and managed by an OS (operating system) or software for processing. There was a problem of taking time.

  Further, in the invention described in Patent Document 1, only dirty control is performed with respect to access between I / O devices, and dirty control is performed with respect to a CPU that is assumed to perform the most writing to the memory. There is no disclosure of what to do.

  SUMMARY An advantage of some aspects of the invention is that it provides a computer system and a memory copy method that can reduce the data transfer time of the memory while reducing the burden on the CPU.

A computer system according to the present invention is a duplicated computer system that uses a dirty information indicating whether or not data has been rewritten and uses a storage area management unit that manages a storage area of a main memory, and a computer system other than the computer system. When performing copy control for copying data to a computer system, a copy data transfer unit that transfers only data in the storage area of the main memory that has been rewritten based on dirty information, and other than copy control A normal data transfer unit for transferring data, and the computer system writes dirty information to the copy data transfer unit in accordance with the microcode, and the copy data transfer unit is configured by hardware, and the normal data Connected to a different bus than the transfer unit And wherein the door.

The memory copy method according to the present invention manages the storage area of the main memory using dirty information indicating whether or not the data has been rewritten in a duplicated computer system, and copies the data to a computer system other than the computer system. When performing copy control, only the data in the storage area of the main memory where data has been rewritten is transferred based on the dirty information, and the data is transferred when the computer system performs copy control according to the microcode. writing the dirty data to the copy data transfer unit which performs the transfer, the data transfer unit for copying is configured by hardware, is connected to a different bus than the normal data transfer unit for transferring data in the non-copy control It is characterized by.

  According to the present invention, it is possible to reduce the data transfer time of the memory while reducing the burden on the CPU.

It is a block diagram which shows the structural example of the whole computer system to which the memory copy method by this invention is applied. It is explanatory drawing which shows the microcode of the Store instruction used for writing to the main memory in a computer system. It is explanatory drawing which shows the specific register | resistor in a control register group. It is a block diagram which shows the internal structure of a DMA control part. It is a block diagram which shows the internal structure of a flag control part. It is explanatory drawing which shows the example of the conversion table of the address of a main memory, and the access signal of a flag memory. It is a flowchart which shows operation | movement in case a computer system performs memory copy. It is a flowchart which shows the operation | movement which a main memory read-out control part performs. It is a flowchart which shows the operation | movement which a flag writing control part performs. It is a flowchart which shows the operation | movement which a flag read-out control part performs. It is a block diagram which shows the minimum structural example of a computer system.

  Embodiments of the present invention will be described below with reference to the drawings. In the present invention, the memory copy method copies the data in the main memory while the system is operating in a duplex process in a fault tolerant system or a migration process in a virtual system. At this time, there is a means for recording and managing the page area (dirty page) of the main memory that has been updated after copying, and a means for copying only necessary memory data based on the information of the recorded dirty page. Provided on (HW). Such a configuration is characterized in that the data in the main memory is transferred without increasing the load on the CPU as compared with the case where dirty pages are recorded and managed by an OS (operating system) or software. At that time, in order to be able to use a general processor and memory, it is possible to cope with the addition of firmware (FW) such as microcode and a device connected to the processor without adding a special function to the processor or memory in the hardware. It is characterized by.

  Next, the configuration of a computer system to which the memory copy method according to the present invention is applied will be described. FIG. 1 is a block diagram showing a configuration example of an entire computer system to which a memory copy method according to the present invention is applied. A computer system to which the memory copy method according to the present invention is applied includes a plurality of modules 100 that are identical in hardware. As shown in FIG. 1, the module 100 includes a processor 110, a main memory 120, a copy control unit 130, flag memories 140 and 150, a chip set 160, and an I / O unit 170.

  In the present embodiment, the computer system shown in FIG. 1 is applied, for example, when a duplex process in a fault tolerant system or a migration process in a virtual system is performed.

  The processor 110 has a function of controlling the entire system by understanding software instructions. The main memory 120 (main storage device) is connected to the processor 110 and stores software instructions and data. Further, the copy control unit 130 has a function of efficiently transferring data in the main memory 120 to another module. Further, the flag memories 140 and 150 record (store) dirty flags (flags indicating whether or not data has been rewritten) in all page areas of the memory when transferring data in the memory during system operation. The chip set 160 has a function of transferring data to each functional unit of the computer system by a normal process. The I / O unit 170 has input and output functions for the computer system.

  Also, recent processors have a plurality of high-speed buses that can be connected to other devices. In this embodiment, as shown in FIG. 1, for accessing a chip set 160 for performing normal processing. The copy control unit 130 is connected to a bus different from this bus. With this configuration, in the present embodiment, it is possible to perform dirty flag processing without interfering with normal processing.

  When applied to a fault tolerant system that is completely synchronized in terms of hardware, the chipset 160 may be configured to have a function for synchronization by connecting to another module. In that case, a configuration in which the copy control unit 130 is inserted into the chip set 160 is also possible.

  As shown in FIG. 1, the processor 110 includes a CPU core 111 having an arithmetic function, an internal bus 113 of the processor, a memory I / F 114 for controlling access to the main memory 120, and a device other than the memory. And a bus I / F 115 that performs access. The processor 110 operates using microcode 112 for associating instructions from software with detailed instructions of hardware.

  As shown in FIG. 1, the copy control unit 130 includes a transaction distribution unit 131, a control register group 132, a DMA control unit 133, a flag control unit 134, and flag memories I / F 135 and 136. . The transaction distribution unit 131 has a function of receiving a transaction of the processor 110 and each of the internal functional units and distributing the transaction to an appropriate destination. The control register group 132 is a plurality of registers for controlling the operation of the copy control unit 130 from software. The DMA control unit 133 has a function of accessing the memory of its own module and relaying data transfer with other modules. In addition, the flag control unit 134 has a function of generating and managing a dirty flag by analyzing a transaction input from the processor 110. Further, the flag memory I / Fs 135 and 136 have a function of reading and writing the flag memories 140 and 150 in accordance with a request from the flag control unit 134.

  FIG. 2 is an explanatory diagram showing the microcode of the Store instruction used for writing to the main memory 120 in the computer system. Generally, in the computer system, the operation of writing the value of the register ID = Ri to the address of the main memory 120 indicated by the register ID = Rj by this Store instruction is completed. In contrast, the computer system according to the present embodiment is configured such that the process of writing the value of the register ID = Rj to the flag write address of the flag control unit 134 is further continued in the Store instruction. With this Store instruction, the address of the main memory 120 written from the processor 110 to the main memory 120 can be output to the copy control unit 130.

  A write address to the main memory 120 output from the processor 110 to the copy control unit 130 by the microcode of the Store instruction shown in FIG. 2 is generated, and a dirty flag is generated by the flag control unit 134 in the copy control unit 130 shown in FIG. Under management, only the data of the dirty page (the page in which the data has been rewritten) can be transferred to another module by the DMA control unit 133. Therefore, it is not necessary to generate and manage dirty pages by the OS or software, so that high-speed memory copying can be realized.

  FIG. 3 is an explanatory diagram showing specific registers in the control register group 132. In FIG. 3, as specific registers in the control register group 132, a minimum page address register indicating the value of the minimum page address in an area synchronized with other modules in the main memory 120, and an area synchronized with other modules are shown. And a maximum page address register indicating the value of the maximum page address. These registers are used in common by each functional unit in the copy control unit 130.

  FIG. 4 is a block diagram showing an internal configuration of the DMA control unit 133. In FIG. 4, dotted lines in the figure indicate main control signals and address signals, and solid lines indicate main data signals. As shown in FIG. 4, the DMA control unit 133 includes a DMA control decoder 10, a DMA mode register 11, a page address counter 12, a selector 13, an offset counter 14, a main memory read control unit 15, and a transmission buffer. 16, a reception buffer 17, and a main memory write control unit 18.

  The DMA control decoder 10 analyzes the transaction input from the transaction distribution unit 131, writes a value to the DMA mode register 11, transfers a memory read transaction to the transmission buffer 16, and performs various other operations of the DMA control unit 133. A function for performing an operation for controlling the function is provided.

  The DMA mode register 11 indicates whether the entire memory area synchronized with other modules is copied (all memory copy) or only pages managed as dirty pages (differential memory copy) are copied as DMA operation. Are held as the DMA mode.

  The page address counter 12 stores a page address of the main memory 120 to be copied in the case of all memory copying, and has a function of counting up when copying of the entire page is completed.

  The selector 13 has a function of selecting the page address output from the page address counter 12 and outputting it to the main memory read control unit 15 when the value of the DMA mode register 11 indicates all memory copies. The selector 13 has a function of selecting a page address output from the flag control unit 134 and outputting the page address to the main memory read control unit 15 when the value of the DMA mode register 11 indicates a differential memory copy.

  The offset counter 14 has a function of storing an address in a page of the main memory 120 to be copied and counting up the address by the amount of data that can be transferred in one transaction.

  The main memory read control unit 15 generates (generates) a memory read request transaction for the address of the main memory 120 obtained by combining the page address output from the selector 13 and the address in the page output from the offset counter 14. Is provided. Further, the main memory read control unit 15 has a function of writing the generated memory read request transaction to the transaction distribution unit 131 and simultaneously writing the address of the main memory 120 into the transmission buffer 16.

  The transmission buffer 16 stores a plurality of pairs of the address output from the main memory read control unit 15 and the memory data returned by the memory read transaction corresponding to the address, and sequentially receives the receive buffer of the DMA control unit 133 of the other module. 17 is provided.

  The reception buffer 17 stores a plurality of memory addresses and data transferred from other modules, sequentially passes (outputs) addresses to the main memory write control unit 18 in necessary timing, and passes data to the transaction distribution unit 131 ( Output).

  When the main memory write control unit 18 receives (inputs) a memory address from the reception buffer 17, it generates (generates) a memory write transaction for the corresponding address in the main memory 120, and performs a transaction from the reception buffer 17 at a necessary timing. A function of performing control to output data to the distribution unit 131 is provided.

  FIG. 5 is a block diagram showing an internal configuration of the flag control unit 134. As in FIG. 4, in FIG. 5, dotted lines in the figure indicate main control signals and address signals, and solid lines indicate main data signals. As shown in FIG. 5, the flag control unit 134 includes a flag control decoder 20, a flag selection register 21, a flag permission register 22, a flag write control unit 23, a flag write register 24, a flag detection unit 25, A flag counter 26, a flag read control unit 27, an address pointer 28, a flag read register 29, an address encoder 30, and selectors 31, 32, 33, and 34 are provided.

  The flag control decoder 20 has a function of analyzing the transaction input from the transaction distribution unit 131 and reading / writing the values of the flag selection register 21, the flag permission register 22, and the flag counter 26. In the case of a dirty flag write transaction in which the address of the main memory 120 is written to the flag control unit 134 by the Store instruction shown in FIG. 2, the flag control decoder 20 sends the flag memory 140 to the flag write register 24 or the flag detection unit 25. , 150 outputs a value indicating the position of the dirty flag within the data width, outputs an address for accessing the flag memories 140, 150 to the selectors 31, 32, and controls the function of the flag write control unit 23. A function for performing the operation is provided.

  FIG. 6 is an explanatory diagram showing an example of a correspondence table between the addresses of the main memory 120 and the access signals of the flag memories 140 and 150. In this example, the address of the entire main memory 120 has a 32-bit value, and the page area in units of 4 KB includes a 12-bit page offset of bit 11-0 and a 20-bit page address of bit 31-12. And Of the page address, the lower 4 bits of bit 15-12 are used as the bit position of the data in the flag memory, and the upper 16 bits of bit 31-16 are used as the address of the flag memory. In this case, each of the flag memories 140 and 150 is configured by a memory device having an address of 16 bits and a data width of 16 bits.

  The flag selection register 21 is a register that holds a value for selecting which of the two flag memories 140 and 150 is to be accessed for dirty flag writing and dirty flag reading.

  The flag permission register 22 is a register that holds a value for selecting whether or not to perform a dirty flag write operation.

  The flag writing control unit 23 has a function of controlling various functions of the flag control unit 134 in order to control the entire operation for writing the dirty flag.

  The flag write register 24 temporarily stores the data in the flag memory 140 or the flag memory 150 in order to write the dirty flag only to the corresponding bits of the data in the flag memories 140 and 150, and is output from the flag control decoder 20. It has a function to combine with dirty flag data. For example, it is assumed that “1” indicates that it is dirty and “0” indicates that it is not dirty. In this case, the data read from the flag memory 140 or the flag memory 150 having a data width of 16 bits is binary “0000-1000-0000-0001”, and the position of the dirty flag output from the flag control decoder 20 is LSB. 0 to 0 and “6”, the value synthesized by the flag write register 24 is “0000-1000-0100-0001” in binary.

  The flag detection unit 25 has a function of detecting the value of the bit at the position of the dirty flag output from the flag control decoder 20 among the values read from the flag memory 140 or the flag memory 150 to the flag write register 24. Prepare.

  The flag counter 26 counts up when the value detected by the flag detection unit 25 is “0” when the dirty flag write transaction is received (input) (when the corresponding dirty flag has not yet been set). And a function for storing the number of dirty flags written so far.

  The flag read control unit 27 has a function of controlling various functions of the flag control unit 134 in order to control the entire operation for reading the dirty flag in accordance with a request from the DMA control unit 133.

  The address pointer 28 stores the address of the flag memory 140 or the flag memory 150 used in the dirty flag read operation. The address pointer 28 is realized by, for example, a register.

  The flag read register 29 temporarily stores data read from the flag memory 140 or the flag memory 150 by the dirty flag read operation, and the address of the dirty page passed (output) to the DMA control unit 133. The function of clearing the dirty flag of the bit corresponding to.

  The address encoder 30 has a function of generating (determining) the address of the dirty page of the main memory 120 to be copied next from the value of the address pointer 28 and the value of the flag read register 29.

  According to the value of the flag selection register 21, the selectors 31 and 32 make the access to the flag memories 140 and 150 via the flag memory I / F 135 and 136 an operation for writing a flag or an operation for reading a flag. The function to select whether to do is provided.

  The selector 33 has a function of selecting which of the data read from the flag memories 140 and 150 via the flag memory I / F 135 and 136 is used as flag writing data according to the value of the flag selection register 21. Prepare.

  The selector 34 has a function of selecting which of the data read from the flag memories 140 and 150 via the flag memory I / F 135 and 136 is used as flag read data according to the value of the flag selection register 21. Prepare.

  In the present embodiment, when the value of the flag selection register 21 selects the flag memory 140 for flag writing and the flag memory 150 for flag reading, the selectors 31 to 34 perform the following operations. The selector 31 accesses the flag memory I / F 135 for the address output from the flag control decoder 20 in accordance with the request of the flag write control unit 23, and the write data to the flag memory 140 is output from the flag write register 24. Is used. The selector 32 accesses the flag memory I / F 136 for the address output from the address pointer 28 according to the request of the flag read control unit 27, and “0” is used as the write data to the flag memory 150. The selector 33 selects data in the flag memory 140 via the flag memory I / F 135, and the selector 34 selects data in the flag memory 150 via the flag memory I / F 136. On the other hand, when the value of the flag selection register 21 selects the flag memory 150 for writing the flag and the flag memory 140 for reading the flag, the selectors 31 to 34 have the data and address opposite to the above. And an operation of selecting a control signal.

  Next, the operation will be described. FIG. 7 is a flowchart showing an operation when the computer system performs memory copy. FIG. 7 shows that when the computer system shown in FIG. 1 is applied to a fault-tolerant system or a virtualization system, the system is operated by a duplication process in the fault-tolerant system or a migration process in the virtualization system. The figure shows the operation of a driver or the like that controls duplication or migration when copying data in the main memory 120.

  When the computer system starts memory copying (step S0), it identifies the area of the main memory 120 that needs to be copied, and sets values in the minimum page address register and the maximum page address register (step S1). At this time, in the fault-tolerant system that completely realizes the duplication of the main memory by hardware, the minimum value and the maximum value of the page address of the entire main memory 120 mounted are set. Further, when performing migration of one virtual machine in the virtualization system, the minimum value and the maximum value of the page address of the memory area assigned to the virtual machine are set.

  Thereafter, the computer system resets the flag counter 26 to “0” in order to record and manage the dirty flag by hardware in the copy of the main memory 120, and sets a value for writing the dirty flag in the flag permission register 22. (Step S2). The flag selection register 21 is not described in the flowchart. However, as an initial value, for example, the flag memory 140 is set to be selected for dirty flag writing, and the flag memory 150 is set to be selected for dirty flag reading. It is assumed that

  Thereafter, the computer system sets a value indicating that the entire main memory area synchronized with other modules is copied (all memory copy) in the DMA mode register 11, and issues a DMA start instruction to the main memory read control unit 15. (Step S3).

  Here, the hardware operation after the start of DMA for all memory copies will be described with reference to FIG. FIG. 8 is a flowchart showing an operation performed by the main memory read control unit 15. When starting the DMA (step S100), the main memory read control unit 15 checks the value of the DMA mode register 11 to determine whether or not it is a differential memory copy (step S101). In the state of step S3 shown in FIG. 7, since all memory copies are made, the determination result is “NO”, and the main memory read control unit 15 sets the value of the minimum page address register in the page address counter 12 (step S103). On the other hand, when the value of the DMA mode register 11 is not the differential memory copy, the selector 13 outputs the value of the page address counter 12 to the main memory read control unit 15.

  Thereafter, the main memory read control unit 15 sets the offset counter 14 to “0” (step S104), generates a read request transaction to the minimum address of the main memory area synchronized with other modules, and distributes the transaction. The data is output to the unit 131 (step S105).

  Further, the main memory read control unit 15 confirms whether or not the value of the offset counter 14 is maximum when the output of the transaction is completed (step S106). If not, the main memory read control unit 15 increments the value of the offset counter 14 by one (step S107). In addition, the main memory read control unit 15 generates a read request transaction to the minimum address of the main memory area that is synchronized with another module again using the counted up value, and outputs the transaction to the transaction distribution unit 131 ( Step S105).

  The main memory read control unit 15 repeats the above processing loop, and when the value of the offset counter 14 becomes maximum, the main memory read control unit 15 checks the value of the DMA mode register 11 to determine whether or not the difference memory copy is performed (step S108). Since the state of step S3 shown in FIG. 7 is all memory copies, the determination result is “NO”, and the main memory read control unit 15 compares the page address counter 12 with the value of the maximum page address register (step S111). .

  When the value of the page address counter 12 is smaller than the value of the maximum page address register, the main memory read control unit 15 increments the value of the page address counter 12 by one (step S112). Further, the main memory read control unit 15 sets the value of the offset counter 14 to “0” (step S104), and performs a read request transaction for the main memory 120 at the next page address.

  Issuing (generating) read request transactions in the main memory 120 in order until the value of the page address counter 12 becomes the same as the value of the maximum page address register while executing the processing as described above and counting up the page address. Is performed, the result of comparison between the values of the page address counter 12 and the maximum page address register in step S111 is “YES”.

  The read request transaction of the main memory 120 issued so far is transferred (output) from the transaction distribution unit 131 to the memory I / F 114 via the bus I / F 115 in the processor 110 and the processor internal bus 113. The memory I / F 114 reads data in the main memory 120 at the address position requested by the read request transaction in the main memory 120. Then, it is transmitted as a main memory read transaction addressed to the DMA control unit 133 in the copy control unit 130.

  The main memory read transaction follows the reverse path of the main memory read request transaction, and is passed (output) to the DMA control decoder 10 of the DMA control unit 133. When the DMA control decoder 10 receives (inputs) the main memory read transaction, the main memory read control unit 15 writes the address of the main memory 120 when the main memory read request transaction is issued to the corresponding position in the transmission buffer 16. Write data in memory 120.

  The main memory read control unit 15 waits for the data in the main memory 120 by the main memory read transaction for all issued main memory read request transactions to be written to the transmission buffer 16 (step S113), and ends the DMA processing. (Step S114).

  When the reception buffer 17 of the DMA control unit 133 in the copy destination module 100 of the main memory 120 receives (receives) the address and data value of the main memory 120 from the transmission buffer 16 of the copy source, the main memory write control unit In 18, a write transaction to the address of the corresponding main memory 120 is generated (generated), and the data including the data to the corresponding main memory 120 in the reception buffer 17 is output to the transaction distribution unit 131.

  The main memory write transaction is sent (output) to the memory I / F 114 by the copy destination module 100 via the bus I / F 115 in the processor 110 and the processor internal bus 113. Then, the memory I / F 114 writes data at the address position requested by the write request transaction in the main memory 120.

  By processing as described above, when data for all main memory read request transactions issued by the main memory read control unit 15 in the copy source DMA control unit 133 is written to the copy destination main memory 120, the minimum All data in the main memory 120 between the page address register and the maximum page address register is copied.

  The copy source module 100 of the main memory 120 continues processing as a normal computer system in addition to the copying of the main memory 120 by this DMA. Here, when writing to the main memory 120 occurs in the copy source module 100, the Store instruction shown in FIG. 2 is executed, and the write address to the main memory 120 is sent to the flag control unit 134 along with the writing to the main memory 120. Sent as a dirty flag write transaction.

  FIG. 9 is a flowchart showing an operation performed by the flag writing control unit 23. FIG. 9 shows an operation after the flag write control unit 23 receives a dirty flag write request. Upon receiving (inputting) the dirty flag write transaction, the flag control decoder 20 requests the flag write control unit 23 to write the dirty flag, and the flag write control unit 23 starts the dirty flag write process (step S200). . When the dirty flag writing process is started, the flag writing control unit 23 checks the value of the flag permission register 22 (step S201), and if the dirty flag writing is not valid, the operation ends as it is (step S208).

  When the dirty flag writing is valid, the flag writing control unit 23 compares the address of the main memory 120 where the writing has occurred with the values of the minimum page address register and the maximum page address register, and requires copying. Whether it is within the address range of the area is checked (step S202), and if it is not within the range, the operation is terminated as it is (step S208).

  If it is within the address range of the area that needs to be copied, the flag write control unit 23 reads the value from the flag memories 140 and 150 and sets it in the flag write register 24. In this case, when the flag memory 140 is selected for dirty flag writing and the flag memory 150 is selected for dirty flag reading, the selector 31 receives (inputs) a request and passes through the flag memory I / F 135. The value of the flag memory 140 is read. Then, the flag writing control unit 23 sets the read value in the flag writing register 24 via the selector 33 (step S203).

  When the data of the flag memories 140 and 150 is set in the flag write register 24, the flag write control unit 23 corresponds to the bit position of the data of the flag memories 140 and 150 among the addresses of the main memory 120 designated by the dirty flag write transaction. The corresponding bit of the flag write register 24 is checked with reference to the value to be processed (step S204). Then, the flag writing control unit 23 ends the operation as it is if the corresponding bit is set (step S208).

  If the corresponding bit of the flag write register 24 is not set, the flag write control unit 23 counts up the flag counter 26 (step S205) and sets (sets) the flag of the corresponding bit of the flag write register 24. (Step S206).

  Thereafter, the value of the flag write register 24 is written into the flag memories 140 and 150. If the flag memory 140 is selected for dirty flag writing and the flag memory 150 is selected for dirty flag reading, the selector 31 requests In response (input), the flag writing control unit 23 writes a value to the flag memory 140 via the flag memory I / F 135 (step S207), and ends the operation (step S208).

  By processing as described above, the page address written in the area of the main memory 120 that needs to be copied can be recorded in the flag memories 140 and 150 while the value of the flag permission register 22 indicates that the dirty flag writing is valid. it can.

  When the DMA is completed in step S3 of FIG. 7, the computer system records the number of page addresses (dirty pages) written in the area of the main memory 120 that needs to be copied during the DMA in the flag counter 26. It is determined whether or not the difference is within a preset threshold value (step S4). If the difference is larger than the threshold value, the computer system resets the flag counter 26 to “0”, and sets the flag memory 140 and 150 for dirty flag writing and dirty flag reading for the setting of the flag selection register 21. On the contrary, switching is performed (step S5).

  Thereafter, the computer system sets the value of the DMA mode register 11 to a value indicating that only the page where the dirty flag is set (set) is copied (difference memory copy), and sends it to the main memory read control unit 15. A DMA start instruction is issued (output) (step S6).

  The hardware operation after the start of the differential memory copy DMA will be described with reference to the flowchart of the main memory read control unit 15 shown in FIG. When starting the DMA (step S100), the main memory read control unit 15 checks the value of the DMA mode register 11 to determine whether or not it is a differential memory copy (step S101). Since the state of step S6 shown in FIG. 7 is a differential memory copy, the determination result is “YES”, and the upper 16 bits of the page address of the minimum page address register are stored in the address pointer 28 by resetting the flag reading function of the flag control unit 134. The flag read register 29 is set to “0”, and the main memory read control unit 15 reads a page address to be accessed to the main memory 120 (step S102).

  FIG. 10 is a flowchart showing the operation performed by the flag read control unit 27. The flag read control unit 27 of the flag control unit 134 reads the page address to be accessed to the main memory 120 by the operation of the flowchart shown in FIG. The flag read control unit 27 starts the operation in response to a read request from the DMA control unit 133 (step S300), and checks whether the value of the flag read register 29 is “0” (step S301). In the initial state, the flag read register 29 is reset to “0”, and the flag read control unit 27 compares the values of the address pointer 28 and the maximum page address register (step S302).

  In the initial state, since the address pointer 28 contains the minimum page address register value, the determination result is “NO”, and the flag reading control unit 27 reads the value from the flag memories 140 and 150 and sets the value in the flag reading register 29. Set (step S303).

  In the flag selection register 21, the flag memory 140 is set for flag writing and the flag memory 150 is set for flag reading as initial values. However, all memory copies are completed and differential memory copy is started. Switch at the time. Therefore, the flag memory 150 is set for flag writing, the flag memory 140 is set for flag reading, and data read from the flag memory 140 is stored in the flag reading register 29 as, for example, binary “0000−”. 1000-0100-0001 "is written.

  Thereafter, the flag reading control unit 27 clears the value of the flag memory 140 by writing “0” to the address of the read flag memory 140 (step S304), and the next reading from the flag memories 140 and 150 is performed. In preparation, the address pointer 28 is counted up by one (step S305).

  Thereafter, the flag read control unit 27 returns to step S301 and checks the value of the flag read register 29. Here, since the value of the flag read register 29 is not “0”, the flag read control unit 27 sets the value of the upper 16 bits of the page address indicated by the address pointer 28 by the address encoder 30 and the flag in the flag read register 29. Binary “0000” is added as the value of the lower 4 bits of the page address indicating the position of bit 0, which is the smallest bit in which is set, and is output to the DMA control unit 133 (step S307).

  After that, the flag read control unit 27 clears bit0, which is the smallest bit set in the flag read register 29, to “0” in preparation for the next read, and sets the value of the flag read register 29 to a binary number. "0000-1000-0100-0000" (step S308).

  When the value of the DMA mode register 11 is differential memory copy, the selector 13 outputs the value of the flag control unit 134 read out as described above to the main memory read control unit 15. Thereafter, the main memory read control unit 15 sets the offset counter 14 to “0” (step S104). Further, the main memory read control unit 15 generates a read request transaction to the minimum address of the page area of the main memory for which the dirty flag has been set, and outputs the transaction to the transaction distribution unit 131 (step S105).

  When the output of the transaction is completed, the main memory read control unit 15 checks whether or not the value of the offset counter 14 is maximum (step S106). If not, the main memory read control unit 15 increments the value of the offset counter 14 by one (step S107). In addition, the main memory read control unit 15 generates a read request transaction to the minimum address of the main memory area that is synchronized with another module again using the counted up value, and outputs the transaction to the transaction distribution unit 131 ( Step S105).

  The main memory read control unit 15 repeats the above processing loop, and when the value of the offset counter 14 becomes maximum, the main memory read control unit 15 checks the value of the DMA mode register 11 to determine whether or not the difference memory copy is performed (step S108). Since the state of step S6 shown in FIG. 7 is differential memory copy, the determination result is “YES”, and the main memory read control unit 15 reads the next address from the flag control unit 134 (step S109).

  When the flag read control unit 27 of the flag control unit 134 starts processing in response to a read request for the next address (step S300), it checks the value of the flag read register 29 (step S301). Here, since the value after the first reading is binary “0000-1000-0100-0000”, the flag read control unit 27 uses the address encoder 30 to display the upper 16 bits of the page address indicated by the address pointer 28. And the binary “0110” as the value of the lower 4 bits of the page address indicating the position of bit 6 which is the smallest bit flagged in the flag read register 29, and output to the DMA control unit 133 (Step S307).

  After that, the flag read control unit 27 clears bit 6 which is the smallest bit in the flag read register 29 to “0” in preparation for the next reading, and sets the value of the flag read register 29 to a binary number. "0000-1000-0000-0000" (step S308).

  In this case, after the process of step S109 shown in FIG. 8 is executed, the flag control unit 134 does not send a copy end notification (step S110), and the main memory read control unit 15 returns to the process of step S104. When the main memory read control unit 15 performs the read request transaction for the entire page of the page address read in step S109 while counting up the offset address as before, the main memory read control unit 15 returns to the process of step S109 and controls the flag. The next address is read from the unit 134.

  Each time the main memory read control unit 15 reads an address in step S109, while the flag flag register 29 remains in the flag read register 29 in the process shown in FIG. 10, the minimum bit flag is set. The flag is cleared (step S308) while generating an address (step S307). When the flag read register 29 becomes “0” (step S301), the main memory read control unit 15 reads the next flag memory value (step S303) and increments the address pointer 28 (step S305). ) Continue to generate dirty page addresses.

  When the flag read register 29 finally becomes “0” (step S301) and the address pointer 28 becomes the same as the value of the maximum page address register (step S302), the main memory read control unit 15 finishes copying. Is notified (output) to the DMA control unit 133 (step S306).

  When the copy end is received in the process of step S109 shown in FIG. 8, the main memory read control unit 15 of the DMA control unit 133 detects the copy end in the process of step S110. The main memory read control unit 15 writes the data in the main memory 120 to the transmission buffer 16 by the main memory read transaction for all the main memory read request transactions issued so far, as in the case of all memory copy. Waiting for loading (step S113), the DMA processing is terminated (step S114).

  The operation of the copy destination module 100 in the main memory 120 is the same as in the case of all memory copy, and data is written in the copy destination main memory 120 in accordance with the address position of the main memory 120 received by the reception buffer 17. In this way, the data for the main memory read request transaction of all dirty pages issued by the main memory read control unit 15 in the copy source DMA control unit 133 is written in the copy destination main memory 120.

  Even during this differential memory copy, the copy source module 100 continues processing as a normal computer system. When the write to the main memory 120 occurs, the Store instruction shown in FIG. 2 is executed, and the write address to the main memory 120 is transmitted to the flag control unit 134 as a dirty flag write transaction along with the write to the main memory 120. The At this timing, the flag memory 150 is set for flag writing, and the flag memory 140 is set for flag reading. Therefore, while the flag memory 140 is used for the differential memory copy, it is recorded in the flag memory 150 by a dirty flag write transaction that occurs after that, as in the case of all memory copies, and the number of dirty pages is recorded in the flag counter. It is counted by 26.

  When the differential memory copy is completed in the process of step S6 shown in FIG. 7 (step S6), the computer system checks the number of dirty pages generated in the normal process recorded in the flag counter 26, and is set in advance. It is determined whether the difference is within the threshold value (step S7). If the difference is greater than the threshold value, the computer system returns to step S5 again and performs a difference memory copy. On the other hand, if the process of steps S5 to S7 is repeated several times and the value falls within the threshold value in step S7, the computer system stops the general process for performing the process as a normal computer system (step S8). Similar to steps S5 and S6, differential memory copying is executed in steps S9 and S10. At this time, since the general process is stopped in step S8, no further writing to the main memory 120 is performed, and all the values of the main memory area necessary for the copy destination module 100 are copied when the DMA is completed. It will be in the state.

  Thereafter, the computer system makes a setting for invalidating the writing of the dirty flag in the flag permission register 22 (step S11), and ends the memory copy process (step S12).

  As described above, according to the present embodiment, in the duplication process in the fault tolerant system or the migration process in the virtualization system, when the data in the main memory 120 is copied while the system is operating, the dirty process is performed. All flag recording and management is performed in hardware. This eliminates the need to record and manage the dirty flag on the main memory 120 by the OS or software, and allows the memory copy to be performed to such an extent that the DMA is started or the number of dirty pages is checked when the DMA is completed. . Therefore, the load on the CPU (processor 110) can be suppressed.

  In addition, in a computer system, when recording and managing a dirty page by software, for a write access to the main memory 120 once, data is read from a memory address with a dirty flag, and the bit corresponding to the write access is dirty. Three processes occur: setting the flag and writing the data back to the memory address with the dirty flag. On the other hand, in the present embodiment, it can be realized only by adding the process of writing the address accessed for writing in the flag control unit 134. For example, when the write time to the main memory 120 is 10 ns, the read time is 50 ns, the calculation processing time is 5 ns, and the write time to other than the main memory 120 is 20 ns, the dirty page is set by software. When recording and management are performed, it usually takes 10 + 50 + 5 + 10 = 75 ns to write to the in-memory 120 once. On the other hand, according to the present embodiment, 10 + 20 = 30 ns, and the CPU load is less than half.

  In addition, according to the present embodiment, the flag control unit 134 and the DMA control unit 133 cooperate to realize a differential memory copy of only dirty pages completely in hardware. Therefore, compared with the case of performing memory copy while using the CPU by OS or software, the CPU can be copied with almost no load.

  Also, in the computer system, when dirty pages are recorded and managed by software, memory copy for acquiring dirty page address, memory read of dirty page data, and copy destination to one copy of the main memory 120 are performed. The process of writing data is required. On the other hand, according to the present embodiment, since all are executed by hardware, no load is applied to the CPU.

  In addition, according to the present embodiment, main devices such as a processor and a memory can be realized by a standard function, and the address is assigned to the external bus when writing to the main memory 120 by only handing the microcode of the processor. You can add a function to output to.

  Further, according to the present embodiment, only the copy control unit 130 and the flag memories 140 and 150 are necessary for realizing a computer system to which the memory copy method according to the present invention is applied. Therefore, it becomes realizable by newly adding these devices to the system, and main hardware devices necessary for normal processing can be used as they are.

  From the above, according to the present embodiment, it is possible to shorten the time for data transfer in the memory while suppressing the burden on the CPU.

  Next, a minimum configuration of a computer system to which the memory copy method according to the present invention is applied will be described. FIG. 11 is a block diagram illustrating a minimum configuration example of a computer system. As shown in FIG. 11, the computer system is a duplicated computer system, and includes a flag control unit 134, a copy control unit 130, and a chip set 160.

  The flag control unit 134 has a function of managing the storage area of the main memory using dirty information (dirty flag) indicating whether data has been rewritten. In addition, when performing copy control for copying data to a computer system other than the computer system, the copy control unit 130, based on the dirty information, only the data in the area where the data is rewritten in the storage area of the main memory. It has a function to transfer. The chip set 160 has a function of transferring data other than copy control. The copy control unit 130 is configured by hardware, and is connected to a bus different from the chip set 160. Note that, for example, the copy control unit 130 may be included in the chip set 160.

  According to the computer system having the minimum configuration shown in FIG. 11, it is possible to reduce the time for data transfer in the memory while suppressing the burden on the CPU.

  In the embodiment described above, the characteristic configuration of the computer system as shown in the following (1) to (6) is shown.

(1) The computer system is a duplicated computer system, and uses the dirty information (for example, dirty flag) indicating whether or not the data has been rewritten, and uses the storage area of the main memory (for example, the main memory 120). When performing copy control for copying data to a storage area management unit (for example, flag control unit 134) to be managed and a computer system other than the computer system, data in the storage area of the main memory is based on dirty information. A copy data transfer unit (for example, the copy control unit 130) that transfers only the data in the rewritten area, and a normal data transfer unit (for example, the chip set 160) that transfers data other than the copy control, The data transfer unit for copying consists of hardware and is used for normal use. Characterized in that it is connected to a different bus than the over data transfer unit.

(2) The computer system includes a dirty information storage unit (for example, flag memories 140 and 150) that stores dirty information, and the storage area management unit rewrites data to the dirty information stored in the dirty information storage unit. It may be configured to write information indicating that.

(3) The computer system is configured by hardware and includes a transfer relay unit (for example, a DMA control unit 133) that relays data transfer with a computer system other than the computer system, and includes a storage area management unit and a transfer relay unit May be configured to transfer only the data in the area in which the data has been rewritten by executing the process in cooperation with.

(4) The computer system may be configured to write data to the storage area of the main memory according to microcode (for example, the microcode shown in FIG. 2) and to write dirty information according to the microcode.

(5) The computer system may be configured to perform copy control in a duplex process in a fault tolerant system.

(6) The computer system may be configured to perform copy control in a migration process in the virtualization system.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a computer system that is used as a system that does not allow any downtime for mission-critical applications, or a virtualization system that constructs a plurality of guest systems with a single device. it can.

10 DMA control decoder 11 DMA mode register 12 page address counter 13 selector 14 offset counter 15 main memory read control unit 16 transmission buffer 17 reception buffer 18 main memory write control unit 20 flag control decoder 21 flag selection register 22 flag permission register 23 flag write Control unit 24 Flag write register 25 Flag detection unit 26 Flag counter 27 Flag read control unit 28 Address pointer 29 Flag read register 30 Address encoder 31, 32, 33, 34 Selector 100 Module 110 Processor 111 CPU core 112 Microcode 113 Internal bus 114 Memory I / F
115 Bus I / F
120 Main memory 130 Copy control unit 131 Transaction allocation unit 132 Control register group 133 DMA control unit 134 Flag control unit 135, 136 Flag memory I / F
140,150 flag memory

Claims (7)

A duplicated computer system,
A storage area management unit for managing the storage area of the main memory, using dirty information indicating whether or not the data has been rewritten;
Copy data transfer for transferring only data in the storage area of the main memory in which data has been rewritten based on the dirty information when performing copy control for copying data to a computer system other than the computer system And
A normal data transfer unit for transferring data other than the copy control,
The computer system writes the dirty information in the copy data transfer unit according to microcode,
The copy data transfer unit is configured by hardware and is connected to a different bus from the normal data transfer unit. A dirty information storage unit for storing dirty information;
The computer system according to claim 1, wherein the storage area management unit writes information indicating that data has been rewritten in the dirty information stored in the dirty information storage unit. The computer system is configured by hardware, and includes a transfer relay unit that relays data transfer with a computer system other than the computer system.
The computer system according to claim 1 or 2, wherein only the data in the area where the data has been rewritten is transferred by executing a process in cooperation between the storage area management section and the transfer relay section. Computer system, the computer system according to any one of claims 3 to write no claims 1 to write data in the storage area of the main memory in accordance with the microcode. The computer system according to any one of claims 1 to 4, wherein the computer system performs copy control in a duplex process in a fault-tolerant system. The computer system according to any one of claims 1 to 4, wherein the computer system performs copy control in a migration process in the virtualization system. In the duplicated computer system, using the dirty information indicating whether the data has been rewritten, the storage area of the main memory is managed,
When performing copy control to copy data to a computer system other than the computer system, based on the dirty information, only the data in the area where the data is rewritten in the storage area of the main memory is transferred,
The computer system writes the dirty information in a copy data transfer unit that transfers data when performing the copy control according to microcode,
Before Kiko Phi data transfer unit is constituted by hardware, memory copying method characterized in that it is connected to a different bus than the normal data transfer unit for transferring data in other than the copy control.

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