JP6237726B2 - Imaging device and imaging apparatus - Google Patents

Description

The present invention relates to an imaging element and an imaging apparatus .

  The imaging device described in Patent Document 1 outputs imaging signals read from the pixel unit a plurality of times within one frame period in parallel with N channels. The frame memory stores this image pickup signal for a plurality of frames. The frame addition circuit adds a plurality of frames of signals read from the frame memory to create a standard frame signal.

JP 2009-239398 A

  However, in the method of adding the pixel data converted into the digital value, the addition is performed with the conversion error generated when the A / D conversion is performed on the image signal as it is.

The imaging device of the present invention includes a first pixel that generates a first signal by photoelectrically converted charge, a second pixel that generates a second signal by photoelectrically converted charge, the first pixel, and the second pixel. Connected to the signal line, the first signal and the second signal being output, a first holding unit for holding the first signal output to the signal line, and the first signal output to the signal line A second holding unit that holds two signals, and the third signal is obtained by the first signal held in the first holding unit and the second signal held in the second holding unit. A signal processing unit for generating, and a conversion unit for converting the third signal generated by the signal processing unit into a digital signal , wherein the first pixel is connected to the signal line, and the first signal is A first transistor for outputting to the signal line; It is connected to the Route, a second transistor for outputting the second signal to said signal line.
The imaging element of the present invention includes a first pixel that generates a first signal by photoelectrically converted charge, a second pixel that generates a second signal by photoelectrically converted charge, the first pixel, and the first pixel. A signal line connected to two pixels and outputting the first signal and the second signal; the first signal output to the signal line; and the second signal output to the signal line. Generated by the amplification unit to be amplified, the first signal amplified by the amplification unit, and the second signal amplified by the amplification unit, and a signal processing unit that generates a third signal. A conversion unit that converts the third signal thus converted into a digital signal.
The imaging device of the present invention is generated by a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge, and the electric charge converted by the first photoelectric conversion unit. A signal line for outputting a first signal and a second signal generated by the electric charge converted by the second photoelectric conversion unit, and a first holding for holding the first signal outputted to the signal line And a second holding unit for holding the second signal output to the signal line, the first signal held in the first holding unit, and held in the second holding unit And a signal processing unit that generates a third signal using the second signal, and a comparator that is used to convert the third signal generated by the signal processing unit into a digital signal.
The imaging device of the present invention is generated by a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge, and the electric charge converted by the first photoelectric conversion unit. A signal line for outputting the first signal and the second signal generated by the electric charge converted by the second photoelectric conversion unit, the first signal output to the signal line, and the signal line A signal for generating a third signal by the amplifying unit for amplifying the output second signal, the first signal amplified by the amplifying unit, and the second signal amplified by the amplifying unit A processing unit, and a comparator used to convert the third signal generated by the signal processing unit into a digital signal.
The imaging element of the present invention includes a first pixel that generates a first signal by photoelectrically converted charges, a second pixel that generates a second signal by photoelectrically converted charges, and a first pixel that generates photoelectrically converted charges. A third pixel that generates three signals, a signal line connected to the first pixel, the second pixel, and the third pixel, and from which the first signal, the second signal, and the third signal are output; A first holding unit for holding the first signal output to the signal line; a second holding unit for holding the second signal output to the signal line; and the third holding unit output to the signal line. A third holding unit for holding a signal, the first signal held in the first holding unit, the second signal held in the second holding unit, and the third holding unit A signal processing unit for generating a fourth signal from the held third signal; and the signal processing unit. The generated said fourth signal comprises a converter for converting a digital signal.
Moreover, the imaging device of this invention is equipped with the image pick-up element as described above.

It is a figure which shows the structure of the A / D conversion circuit (ADC) concerning the 1st Embodiment of this invention. It is a time chart for demonstrating operation | movement in case there is no weighting addition operation | movement. It is a time chart for demonstrating operation | movement when there exists weighting addition operation | movement. It is a figure which shows the structure of the A / D conversion circuit concerning the 2nd Embodiment of this invention. 5 is a time chart for explaining the operation (operation with weighted addition) of the ADC 12A shown in FIG. 5 is a time chart for explaining the operation (operation without weighting addition) of the ADC 12A shown in FIG. It is a figure which shows the structure of the A / D conversion circuit concerning the 3rd Embodiment of this invention. It is a time chart for demonstrating operation | movement of ADC12B shown in FIG. It is a figure which shows the example of a solid-state imaging device. It is a figure which shows the structure of a pixel circuit. It is a figure which shows the structure of a normal A / D conversion circuit.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment]
(Description of pixel circuit)
First, the pixel PX constituting the pixel portion in the CMOS type solid-state imaging device will be briefly described. FIG. 10 is a diagram illustrating a configuration of a pixel circuit, and is a circuit diagram illustrating one pixel PX, a vertical signal line VL, and a constant current source TD.
The pixel circuit shown in FIG. 10 includes a photodiode PD as a photoelectric conversion unit, a floating diffusion FD as a charge-voltage conversion unit that receives charge and converts the charge into voltage, and a reset transistor RST that resets the potential of the floating diffusion FD. A selection transistor SEL that supplies a signal corresponding to the potential of the floating diffusion FD to the vertical signal line VL, a transfer transistor TX as a charge transfer unit that transfers charges from the photodiode PD to the floating diffusion FD, and a floating diffusion FD. It has an amplifying transistor SF as an amplifying unit that outputs a signal corresponding to the potential.

  In FIG. 10, VDD is a power supply potential. Note that the transistors SF, TX, RST, and SEL of the pixel PX are all nMOS transistors. The gates of the transfer transistors TX are commonly connected to each row, and a control signal φTX for controlling the transfer transistors TX is supplied from the vertical scanning circuit 3 thereto. The gates of the reset transistors RST are commonly connected to each row, and a control signal φRST for controlling the reset transistors RST is supplied thereto from the vertical scanning circuit 3 (see FIG. 9). The gates of the selection transistors SEL are connected in common to each row, and a control signal φSEL for controlling the selection transistors SEL is supplied from the vertical scanning circuit 3 thereto.

  The photodiode PD of each pixel PX generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX of each pixel PX is turned on during the high level period of the control signal φTX, and transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST is turned on during the high level period of the control signal φRST (the period of the power supply potential VDD), and resets the floating diffusion FD.

  The amplification transistor SF has its drain connected to the power supply potential VDD, its gate connected to the floating diffusion FD, and its source connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line VL. The constant current source TD supplies a current to the vertical signal line VL when the selection transistor SEL of the pixel PX corresponding to the vertical signal line VL is turned on.

  The amplification transistor SF of each pixel PX outputs a voltage to the vertical signal line VL via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor SF to the vertical signal line VL.

(Description of Outline of A / D Conversion Circuit of First Embodiment)
First, an outline of the A / D conversion circuit (ADC 12) of the first embodiment will be described.
FIG. 1 is a diagram showing a configuration of an A / D conversion circuit according to an embodiment of the present invention. The circuit shown in FIG. 1 is configured by connecting an integrating ADC 12C at the subsequent stage of the PGA 11. The PGA 11 and the ADC 12 are arranged for each vertical signal line VL in each column in the solid-state imaging device 1 shown in FIG. Is provided.

  The operations of the PGA 11 and the ADC 12 are controlled by the control unit 21. The control unit 21 controls on / off (connection / release) of each switch in the PGA 11 and the ADC 12 (that is, switching between a conduction state and a non-conduction state), and each signal used in the ADC 12 ( VRT, VRB, VRAMP, etc.). In addition, the control unit 21 includes a course conversion control unit 22 that controls the course conversion processing operation performed in the ADC 12 and a fine conversion control unit 23 that controls the fine conversion processing operation.

  In addition, the control unit 21 includes a counter 24 that is used when course conversion or fine conversion processing is performed, a register that holds digital data of the A / D conversion result, and the like. The counter 24 includes a 3-bit counter 24A for counting the upper 3 bits used for coarse conversion and a lower 12 used for fine conversion when the pixel signal is converted into a digital value with a resolution of 14 bits. And a 12-bit counter 24B for counting bit values (course conversion and fine conversion will be described later).

The ADC 12 shown in FIG. 1 is different from the normal ADC 12C shown in FIG. 11 in that switches S9, S10, S11, S12, and S13 are newly added to the capacitors C1 to C4. Further, the configuration is different in that a switch S13 is added to the node Vcm so that the node Vcm and the node Vcm ′ can be selectively connected. Other configurations are the same as those of the ADC 12C shown in FIG. For this reason, the same code | symbol is attached | subjected to the corresponding structure.
In the ADC 12 shown in FIG. 1, when all the switches S9, S10, S11, S12, and S13 are steadily turned on (connected), the ADC 12 shown in FIG. 1 and the normal ADC 12C shown in FIG. As a result, the configuration is the same (ADC configuration without weighted addition), and the operation is also the same.

  The switch S9 is a switch for holding the pixel signal Sig1 in the capacitor C1, the switches S10 and S11 are switches for holding the pixel signal Sig2 in the capacitors C2 and C3, and the switch S12 is a pixel signal Sig3. Is a switch for holding in the capacitor C4. For example, in a state where the pixel signal Sig1 is input to the node Vcm, when the switch S9 is turned on (however, the switches S10, S11, S12, and S13 are off (opened)), the capacitor C1 is passed through the switch S9 by the pixel signal Sig1. The capacitor C1 holds the pixel signal Sig1.

  Then, after the capacitors C1, C2, C3, and C4 are sequentially charged by the signals Sig1, Sig2, and Sig3, the switches S9 to S12 are simultaneously turned on (however, the switch S13 is turned off) to generate a potential on the node Vcm. Thus, weighted addition of the signals Sig1, Sig2, and Sig3 is performed. The weighting ratio at this time is determined by the capacitance ratio of the capacitor C1, the capacitor C2 + C3, and the capacitor C4.

Here, the capacitances of the capacitors C1, C2, C3, and C4 are C1, C2, C3, and C4, and the voltage levels of the signals Sig1, Sig2, and Sig3 are Sig1, Sig2, and Sig3. Then, in this example, for the signal Sig1, the charge Q1 held in the capacitor C1 is
Q1 = C1 × Sig1.
The charge Q2 held in the capacitors C2 and C3 with respect to the signal Sig2 is because the capacitors C2 and C3 are connected in parallel.
Q2 = (C2 + C3) × Sig2.
For the signal Sig3, the charge Q3 held in the capacitor C4 is
Q3 = C4 × Sig2.

Therefore, the total charge Qtotal held in the capacitors C1, C2, C3, and C4 is
Qtotal = C1 × Sig1 + (C2 + C3) × Sig2 + C4 × Sig3,
It becomes.
Further, the total capacity Ctotal of the capacitors C1, C2, C3, C4 is because the capacitors C1, C2, C3, C4 are connected in parallel.
Ctotal = C1 + (C2 + C3) + C4.

Accordingly, when the switches S9, S10, S11, and S12 are simultaneously turned on and the switch S13 is turned off, the potential of the node Vcm is expressed as Vcm.
Vcm = Qtotal / (C1 + C2 + C3 + C4).

Here, if C1 = C2 = C3 = C4 = C,
Qtotal = C × Sig1 + 2 × C × Sig2 + C × Sig3.
Therefore, since Vcm = Qtotal / Ctotal,
Vcm = {C × Sig1 + 2 × C × Sig2 + C × Sig3} / (4 × C),

Therefore, Vcm = {Sig1 + 2 × Sig2 + Sig3} / 4.
In this way, the weighted addition of “1: 2: 1” can be performed on the signals Sig1, Sig2, and Sig3.

As described above, in the ADC 12 shown in FIG. 1, the pixel signal output from the PGA 11 is weighted and added as an analog signal to generate a potential at the node Vcm, and the potential generated at the node Vcm is generated. A / D conversion is performed. Therefore, when weighted addition is performed on the pixel signal output from the PGA 11, the weighted addition is performed in an analog manner without causing a conversion error (for example, an error due to the influence of noise or a quantization error) in the ADC 12. Can do.
In addition, since weighted addition is performed using the course conversion capacitors C1 to C4 provided in the ADC 12, analog weighted addition can be performed without increasing the layout area.

In the above-described example, weighting is performed by assigning one capacitor C1, two capacitors C2, C3, and one capacitor C4 to each of the three pixel signals Sig1, Sig2, and Sig3. Although an example in which the ratio of addition is “1: 2: 1” has been shown, the present invention is not limited to this. For example, it can be set to a desired ratio such as “1: 3: 1”, “1: 5: 1”, “2: 3: 3” (however, capacitors C1 to C1 prepared for course conversion). There is a limit due to the number of C8). Furthermore, the three pixel signals Sig1, Sig2, and Sig3 can be averaged by setting the weighting ratio to “1: 1: 1”.
In addition, the number of pixel signals to be weighted and added is not limited to three, and weighted addition can be performed on five pixel signals and seven pixel signals (basically an odd number) (however, There is a limit due to the number of capacitors C1 to C8 prepared for course conversion).

(Description of configuration of ADC 12 having weighted addition function)
Next, the configuration of the ADC 12 shown in FIG. 1 will be described in detail. The ADC 12 is an integration type A / D conversion circuit having a weighted addition function, and the ADC 12 reads a pixel signal output from the vertical signal line VL of the solid-state image sensor via the PGA 11 and outputs the pixel signal to the pixel signal. A / D conversion is performed.

  The PGA 11 includes a differential amplifier (AM1), a switch PGA_AZ, a capacitor C11, and a variable capacitor C12. The reference voltage VREF is connected to the positive (+) input of the differential amplifier AM1, and the pixel signal input is connected to the negative (−) input via the capacitor C11. The output of the differential amplifier AM1 is connected to the variable capacitor C12 for negative feedback and the switch PGA_AZ, and to the switch SPL in the ADC 12. Further, the gain of the PGA 11 can be changed by the variable capacitor C12. Note that the maximum value of the signal output from the PGA 11 is, for example, + 1V.

The ADC 12 includes switches SPL and TSW. The ADC 12 includes capacitors C1 to C8, switches S1a, S1b to S8a, S8b, S9 to S13, and SX, and a comparator CP1. The switches SPL and TSW and the switches S1a, S1b to S8a, S8b, S9 to S13, and SX are indicated by contact type switch symbols, but in actuality, for example, they are configured by MOS transistors or semiconductor switches. It is what is done.
The amplified pixel signal output from the PGA 11 is connected to the positive (+) input of the comparator CP1 through the switch SPL and the switch S13. The output of the comparator CP1 is connected to the negative (−) input of the comparator CP1 through the switch ADC_AZ, and a capacitor C10 that holds information on the dark state of the pixel (dark potential Vdark) is connected.

  Capacitors C1 to C8 are capacitors having the same capacitance. Capacitors C1 to C8 are capacitively coupled to node Vcm or node Vcm '. Then, in the course conversion described later, by sequentially switching the switches S1a, S1b to S8a, S8b connected to these capacitors (for example, the switch S1a is turned off and the switch S1b is turned on), the capacitors C1 to C8 are switched. The voltage of the counter electrode is switched between the signals VRT and VRB, and it is determined where the potential of the node Vcm belongs in the eight ranges. The signal VRT is, for example, a + 2V signal, and the signal VRT is, for example, a + 1V signal (note that the voltage of the signal VRT is indicated by the same symbol VRT and the voltage of the signal VRB is indicated by the same symbol VRB). There). Then, a signal (VRT−VRB) having an amplitude of 1V is generated by the signals VRT and VRB (corresponding to the output voltage 1V of the PGA 11) as will be described later. Note that the above-described potential Vdark is approximately 0V.

As shown in FIG. 1, one end of the capacitor C1 is connected to the node Vcm (the potential of the node Vcm may be indicated by the same symbol Vcm) via the switch S9. The other end of the capacitor C1 is connected to the signal line VRT (signal line of the signal VRT) via the switch S1a, and the other end of the capacitor C1 is signal line VRB (the signal line of the signal VRB) via the switch S1b. Connected to.
Further, one end of the capacitor C2 is connected to the node Vcm via the switch S10, and the other end of the capacitor C2 is connected to the signal line VRT via the switch S2a, and is connected to the signal line VRB via the switch S2b. .

Further, one end of the capacitor C3 is connected to the node Vcm via the switch S11, and the other end of the capacitor C3 is connected to the signal line VRT via the switch S3a and to the signal line VRB via the switch S3b. . Note that the switch S11 and the switch S10 are both switches that are simultaneously turned on or simultaneously turned off.
Further, one end of the capacitor C4 is connected to the node Vcm through the switch S12, and the other end of the capacitor C4 is connected to the signal line VRT through the switch S4a and to the signal line VRB through the switch S4b. .

Further, one end of the capacitor C5 is connected to the node Vcm ′, and the other end of the capacitor C5 is connected to the signal line VRT via the switch S5a and to the signal line VRB via the switch S5b.
Further, one end of the capacitor C6 is connected to the node Vcm ′, and the other end of the capacitor C6 is connected to the signal line VRT through the switch S6a and is connected to the signal line VRB through the switch S6b.
Further, one end of the capacitor C7 is connected to the node Vcm ′, and the other end of the capacitor C7 is connected to the signal line VRT via the switch S7a and is connected to the signal line VRB via the switch S7b.
Further, one end of the capacitor C8 is connected to the node Vcm ′, and the other end of the capacitor C8 is connected to the signal line VRT via the switch S8a and is connected to the signal line VRB via the switch S8b. Furthermore, the other end of the capacitor C8 is connected to the signal line VRAMP via the switch SX.
The node Vcm and the node Vcm ′ are connected by the switch S13, and the node Vcm and the node Vcm ′ are selectively connected or opened (disconnected) through the step S13.

  The ADC 12 shown in FIG. 1 operates as a normal A / D conversion circuit (ADC 13C that does not perform weighted addition shown in FIG. 11) by constantly turning on the switches S9 to S13, and switches S9 to S13. By controlling on / off of S13, the circuit operates as an A / D conversion circuit having a weighted addition function.

(Description of operation of ADC 12 without weighted addition)
First, in the ADC 12 shown in FIG. 1, when the switches S <b> 9 to S <b> 13 are constantly turned on, the ADC 12 is operated as a normal A / D conversion circuit (A / D conversion circuit without weighted addition). An example will be described.

  FIG. 2 is a time chart for explaining the operation of the ADC 12 when weighted addition is not performed. The process shown in FIG. 2 is the same process as a normal integral type A / D conversion process (A / D conversion process performed in the solid-state imaging device described in Patent Document 1). Hereinafter, the processing flow will be briefly described with reference to the time chart shown in FIG. 2 (for details, refer to the imaging device described in Patent Document 1).

  The A / D conversion operation in the ADC 12 is performed by a two-stage A / D conversion operation of coarse conversion and fine conversion. Further, during the operation of the A / D conversion process, the switches S9 to S13 remain on. In addition, in the switches S1 to S8 connected to the capacitors C1 to C8, the switches S1a to S8a are initially in an on state and the switches S1b to S8b are in an off state.

Then, when the A / D conversion process in the ADC 12 is started by a control command from the control unit 21, dark capture is started at time T1, a PGA auto-zero signal switch PGA_AZ, an auto-zero signal switch ADC_AZ, and a sampling signal The switch SPL is turned on. Accordingly, the comparator CP1 holds information on the dark state of the pixel as a potential (dark potential Vdark) at the positive potential of the capacitor C10. When the dark capture starting from time T1 is completed, the switch PGA_AZ, the switch ADC_AZ, and the switch SPL are turned off.
Thereafter, at time T2, signal capture (reading of pixel signals) is started, and when the switch SPL is turned on again, the pixel signal output from the PGA 11 is held at the node Vcm as the potential Vcm. When the dark capture is completed, the switch SPL is turned off.

  Then, the course conversion is started from time T3 by the course conversion control unit 22 in the control unit 21. At this time T3, the switch S8a connected to the capacitor C8 is turned off, and the switch S8b connected to the capacitor C8 is turned on. As a result, the voltage at the counter electrode of the capacitor C8 capacitively coupled to the node Vcm ′ (more precisely, the node Vcm and the node Vcm ′ because the switch S13 is on) is changed from VRT (2.0 V) to VRB (1.0 V). To change. At this time, the potential of the node Vcm drops by “(VRT−VRB) / 8”. Further, the value of the course conversion 3-bit counter 24A is "001".

  At time T4, the switch S1a connected to the capacitor C1 is turned off, and the switch S1b connected to the capacitor C1 is turned on. As a result, the counter electrode of the capacitor C1 capacitively coupled to the node Vcm changes from VRT (2.0 V) to VRB (1.0 V). At this time, the potential of the node Vcm further decreases by “(VRT−VRB) / 8”. Further, the value of the 3-bit counter 24A is “010”.

  The same operation is performed at time T5 to T9, and when the potential of the node Vcm further decreases by “(VRT−VRB) / 8” at time T10, the potential of the node Vcm is lower than the potential Vdark (approximately 0 V). At this time, the upper 3 bits of the digital value after A / D conversion of the pixel signal is determined by the count value (in this example, “111”) of the 3-bit counter 24A.

  When the course conversion is completed, after time T11, the fine conversion control unit 23 starts the fine conversion and the determination of the lower 12 bits is started. Therefore, at time T11, the switch SX is turned on, and the signal VRAMP, which is the counter electrode potential of the capacitor C8, is raised to a level corresponding to VRT. Further, the potential of the node Vcm is raised to a level corresponding to one timing before the end of the course conversion. That is, it is raised by “(VRT−VRB) / 8” (for details, see Patent Document 1).

  Then, after time T11, by changing (decreasing) the signal VRAMP in a slope shape, the potential of the node Vcm is lowered in a slope shape, and the potential of the node Vcm becomes lower than the potential of the dark potential Vdark (almost 0V). Is counted by a clock signal (not shown). The clock signal is counted by a 12-bit counter 24B, and the lower 12-bit digital value of the pixel signal is determined by the count value of the 12-bit counter 24B.

  As described above, the ADC 12 determines the upper bits (upper 3 bits) of the pixel information in the coarse conversion and determines the lower bits (lower 12 bits) of the pixel information in the fine conversion, so that the A / D conversion process of the pixel signal is performed. Can be performed at high speed.

(Description of operation of ADC 12 when weighted addition is performed)
Next, an example in which the ADC 12 shown in FIG. 1 operates as an A / D conversion circuit with weighted addition will be described with reference to the time chart of FIG.

  Compared with the time chart shown in FIG. 2, the flowchart shown in FIG. 3 captures the signal Sig1 that starts from time T2a, captures the signal Sig2 that starts from time T2b, and signal that starts from time T2c. The difference is that the respective processing periods of the acquisition of Sig3 and the weighted addition of the signals Sig1, Sig2, and Sig3 starting from time T2d are newly added. Further, the difference is that the signal acquisition started at time T2 in FIG. 2 is changed to weighted signal acquisition started at time T2e in FIG. About others, it is the same as that of the time chart shown in FIG.

  As shown in the time chart of FIG. 3, the dark capturing started at time T1 ends, and when time T2a is reached, the switch S9 is turned on and the signal Sig1 input via the PGA 11 is captured by the capacitor C1. (Capacitor C1 is charged). When the time T2b is reached, the switches S10 and S11 are turned on, and the signal Sig2 input through the PGA 11 is taken into the capacitors C2 and C3 (the capacitors C2 and C3 are charged). When the time T2c is reached, the switch S12 is turned on, and the signal Sig3 input through the PGA 11 is taken into the capacitor C4 (the capacitor C4 is charged). This completes the acquisition of the signals Sig1, Sig2, and Sig3 to be weighted and added into the ADC 12.

  Thereafter, when the time T2d is reached, the four switches S9, S10, S11, and S12 are turned on all at once, and the charges accumulated in the capacitors C1, C2, C3, and C4 are discharged to the node Vcm. , A signal having a voltage obtained by weighted addition of the signals Sig1, Sig2, and Sig3 is generated. Note that the weighting ratio to the signals Sig1, Sig2, and Sig3 is “1: 2: 1” based on the number of capacitors that hold the signals.

When a voltage signal obtained by weighting and adding the signals Sig1, Sig2, and Sig3 is generated at the node Vcm at the time T2d, the switch S13 is turned on at time T2e to connect the node Vcm and the node Vcm ′. Then, the weighted signal is captured on the node Vcm ′.
A waveform Vcm after time T2e indicates a voltage waveform of the node Vcm ′ (node Vcm ′ to which the capacitors C5 to C8 are connected). However, from time T2e to time T2f, the switch S13 is turned on, so that the charge stored in the capacitors C1, C2, and C3 is redistributed among the capacitors C1 to C8. The charging potentials (voltage level L1) of the capacitors C1, C2, C3 before being turned on are schematically shown.
That is, between the time T2e and the time T2f, the switch S13 is turned on to turn on the node Vc.
When m is connected to the node Vcm ′, the potential (voltage level L1) of the node Vcm is redistributed between the capacitors C1, C2, and C3 among the capacitors C1 to C8. The voltage level drops to L2.

Thereafter, course conversion is started at time T3, and fine conversion is started at time T11. The course conversion and fine conversion are basically the same as those in the time chart shown in FIG.
However, in the time chart shown in FIG. 3, the course conversion operation is performed by the switches S5, S6, S7.
, S8 is different from the time chart shown in FIG. 2 in that it is performed using four switches, that is, in the time chart shown in FIG. 2, the course conversion operation is performed in eight stages using the eight switches S1 to S8. In the time chart shown in FIG. 3, the coarse conversion operation is performed in four stages using four switches S5 to S8, while the higher order bits of the A / D conversion value are determined. The upper bit of the A / D conversion value is determined.
This is because the switch S13 is turned off and the capacitors C1, C2, C3, and C4 are disconnected from the node Vcm ′ during the course conversion operation after the time T3, and the switches S1 to S4 connected to the capacitors C1 to C4, respectively. Is not usable for course conversion.
After the time T2d, the course conversion operation can be performed in eight stages using the eight switches S1 to S8 by keeping the switches S9 to S13 on.

  As described above, in the A / D conversion circuit (ADC 12) of this embodiment, the weighted addition of the pixel signals in the vertical direction is performed at the stage of the analog signal before the A / D conversion, thereby performing the A / D conversion. It is possible to perform weighted addition of pixel signals without being affected by noise components and quantization errors generated when performing.

[Second Embodiment]
In the ADC 12 of the first embodiment described above, the A / D is configured such that the upper bits of the digital value of the pixel signal are determined by the coarse conversion process and the lower bits of the digital value of the pixel signal are determined by the fine conversion process. We are trying to speed up the conversion. However, the circuit configuration becomes complicated accordingly. In the A / D conversion circuit of the present invention, it is not always necessary to perform the course conversion process, and it may be configured to perform only the fine conversion process without performing the course conversion process. Thereby, the circuit configuration of the A / D conversion circuit can be simplified. As a second embodiment of the present invention, an example in which only fine conversion is performed in an A / D conversion circuit will be described.

  FIG. 4 is a diagram showing a configuration of an A / D conversion circuit according to the second embodiment of the present invention. The A / D conversion circuit (ADC12A) shown in FIG. 4 is different from the A / D conversion circuit (ADC12) shown in FIG. 1 in that the configuration related to the course conversion processing in the ADC 12 shown in FIG. Different. That is, in the ADC 12 shown in FIG. 1, the capacitors C5 to C7 are deleted, and the switches S1a, S1b to S8a, S8b, and SX are deleted. Other configurations are the same as those of the ADC 12 shown in FIG. For this reason, the same code | symbol is attached | subjected to the same structure and the overlapping description is abbreviate | omitted.

  FIG. 5 is a time chart for explaining the operation of the ADC 12A shown in FIG. Compared with the time chart with weighted addition shown in FIG. 3, the time chart shown in FIG. 5 captures the weighted signal started at time T2e from the dark capture started at time T1 to the node Vcm ′. The operation is the same, except that the fine conversion process is started from time T3 (in the time chart of FIG. 3, the course conversion process is started from time T3).

  Thus, after performing weighted addition of the signals Sig1, Sig2, and Sig3 using the capacitors C1, C2, C3, and C4, the coarse conversion process can be omitted and the fine conversion can be started immediately. For this reason, in an A / D conversion circuit with a low number of bits (resolution), weighting addition by an analog signal can be performed and the circuit configuration can be simplified.

  FIG. 6 is a time chart showing an operation when weighted addition is not performed in the ADC 12A shown in FIG. In the ADC 12A, when weighted addition is not performed, the switches S9 to S13 are all kept on, and after the dark capture starting from time T1 and the signal capture starting from time T2 are completed, The fine conversion process starts from T3.

[Third Embodiment]
In the first and second embodiments, all of the capacitors C1 to C8 connected to the node Vcm have the same capacitance, and hold the respective signals according to the weighting of the pixel signals Sig1, Sig2, and Sig3. The number of capacitors is assigned. For example, in the example shown in FIG. 1, one capacitor C1 is assigned to the pixel signal Sig1, two capacitors C2 and C3 are assigned to the pixel signal Sig2, and one capacitor C4 is assigned to the pixel signal Sig3.
In contrast, in the third embodiment of the present invention, one capacitor is assigned to each of the pixel signals Sig1, Sig2, and Sig3, and weighting is performed by changing the capacitance of each capacitor.

FIG. 7 is a diagram showing a configuration of an A / D conversion circuit according to the third embodiment of the present invention. Compared with the ADC 12 shown in FIG. 1, the ADC 12B shown in FIG. 7 uses only one capacitor C2 as a capacitor for holding the signal Sig2 (in the ADC 12 shown in FIG. 1, the signal Sig2 is converted into two capacitors C2, C3. Is different). Further, the capacitances of the capacitors C1, C2, and C3 are changed according to the weights of the signals Sig1, Sig2, and Sig3 (that is, the capacitances of the respective capacitances are changed, respectively). The point of setting or making each of the capacitances different).
For example, the capacitance ratio of the capacitors C1, C2, and C3 is “1: 2: 1”. Other configurations are the same as those of the ADC 12 shown in FIG. For this reason, the same code | symbol is attached | subjected to the same structure.

  In the example shown in FIG. 7, the capacitances of the capacitors C1, C2, and C3 are changed in accordance with the weights for the signals Sig1, Sig2, and Sig3. For this reason, the capacitances of the capacitors C1, C2, and C3 are different from the capacitances of the capacitors C4 to C8. That is, in the capacitors C1 to C8, there are capacitors having different capacitances (in the ADC 12 shown in FIG. 1, the capacitances of the capacitors C1 to C8 are all the same).

  For this reason, the capacitors C1, C2, and C3 are used only when weighted addition of the signals Sig1, Sig2, and Sig3 is performed. After the weighted addition is performed, the switches S9, S10, and S11 are kept in the OFF state. C1, C2, and C3 are not used for the course conversion performed by the ADC 12B. That is, in the ADC 12B, the course conversion process is performed using the five capacitors C4, C5, C6, C7, and C8.

  FIG. 8 is a time chart for explaining the operation of the ADC 12B shown in FIG. 7, and is a time chart showing the operation when weighted addition is performed. The time chart shown in FIG. 8 is compared with the time chart in the ADC 12 of the first embodiment shown in FIG. 3, and the dark capture starting from time T1 and the signal Sig1 starting from time T2a are captured. Then it is the same. When the time T2b shown in FIG. 8 is reached, the switch S10 is turned on, and the signal Sig2 input through the PGA 11 is taken into the capacitor C2 (the capacitor C2 is charged). Further, when the time T2c is reached, the switch S11 is turned on, and the signal Sig3 input through the PGA 11 is taken into the capacitor C3 (the capacitor C3 is charged). Thereby, the acquisition of the signals Sig1, Sig2, and Sig3 to be subjected to weighted addition to the ADC 12B is completed.

  Thereafter, when the time T2d is reached, the three switches S9, S10, and S11 are turned on simultaneously, and the charges accumulated in the capacitors C1, C2, and C3 are discharged to the node Vcm. When a voltage signal obtained by weighting and adding the signals Sig1, Sig2, and Sig3 is generated at the node Vcm at the time T2d, the switch S13 is turned on at time T2e to connect the node Vcm and the node Vcm ′. Then, the weighted signal is captured on the node Vcm ′. As a result, a voltage signal obtained by weighted addition of the signals Sig1, Sig2, and Sig3 is generated at the node Vcm ′.

Then, course conversion is started at time T3. In the time chart shown in FIG. 8, the course conversion operation is performed using the five switches S4, S5, S6, S7, and S8, and the upper bits of the A / D conversion value are determined as shown in FIG. Different from the time chart.
That is, in the time chart shown in FIG. 3, the coarse conversion operation is performed in four stages using the four switches S5 to S8, whereby the upper bits of the A / D conversion value are determined. In the time chart shown, the course conversion operation is performed in five stages using the five switches S4 to S8, thereby determining the upper bits of the A / D conversion value.
This is because the switch S13 is turned off and the capacitors C1, C2, C3 are disconnected from the node Vcm ′ during the course conversion operation after the time T3, and the switches S1, S2, S3 connected to the capacitors C1, C2, C3. Is not used for course conversion operation, and course conversion is performed using the remaining switches S4 to S8.
When the course conversion is completed, the fine conversion process is started at time T9. This fine conversion process is the same as the case shown in FIGS.

  Thus, in the third embodiment, the weights for the signals Sig1, Sig2, and Sig3 can be set finely by changing the capacitances of the capacitors C1, C2, and C3.

Although the embodiment of the present invention has been described above, the correspondence relationship between the present invention and the above embodiment will be supplementarily described.
The solid-state imaging device according to the present invention corresponds to the solid-state imaging device 1 shown in FIG. 9, and the A / D conversion circuit according to the present invention corresponds to the ADC 12 shown in FIG. The pixel signal in the present invention corresponds to pixel signals (for example, signals Sig1, Sig2, and Sig3) that are generated in the pixel PX shown in FIG. 9 and input to the ADC (A / D conversion circuit) via the vertical signal line VL. To do. The node in the present invention corresponds to the node Vcm (which may include both the node Vcm and the node Vcm ′). Further, the predetermined potential in the present invention is the potential (Vdark) of the pixel signal in the dark state, more precisely, the voltage (dark potential Vdark) held in the capacitor C10 connected to the comparator CP1.
The control means in the present invention corresponds to the control section 21, the course conversion means in the present invention corresponds to the course conversion control section 22, and the fine conversion means in the present invention corresponds to the fine conversion control section 23. The capacitors C1 to C4 correspond to the first group of capacitors in the present invention, the capacitors C5 to C8 correspond to the capacitors in the second group of the present invention, and the switch of the first group in the present invention is the switch S9. To S12, and the second group of switches in the present invention corresponds to the switch S13.

  (1) In the above embodiment, the ADC 12 includes a plurality of capacitors C1 to C8 that are capacitively coupled to the node Vcm to which the pixel signals Sig1, Sig2, and Sig3 are input via the vertical signal line VL of the solid-state imaging device. Pixel signal holding means for holding each of the plurality of pixel signals Sig1, Sig2, and Sig3 input via the vertical signal line VL in advance using some of the capacitors C1 to C4 in the plurality of capacitors C1 to C8 ( Capacitors C1 to C4 and switches S9 to S11) and node potential generation means (capacitors C1 to C4 and switches S9) for synthesizing the respective pixel signals held in some of the capacitors C1 to C4 to generate the potential of the node Vcm. To S11) and the potential of the node Vcm by changing the counter voltage of the capacitors C1 to C8. Comprises changing, the node Vcm potential and the predetermined potential control means for generating a digital value of the pixel signal by comparing the (dark potential Vdark) and (controller 21), the.

In the ADC 12 having such a configuration, each of the plurality of pixel signals Sig1, Sig2, and Sig3 input via the vertical signal line VL of the solid-state imaging device is used as a part of the capacitors C1 to C8 in the ADC 12. Pre-hold using C1-C4. Then, the pixel signals Sig1, Sig2, and Sig3 held in the capacitors C1 to C4 are combined to generate the potential of the node Vcm. Thereafter, the voltage of the node Vcm is changed by changing the voltage of the counter electrodes of the capacitors C1 to C8, and the digital value of the pixel signal is generated by comparing the potential of the node Vcm with a predetermined potential (dark potential Vdark). .
Thereby, in the ADC 12 of the present embodiment, the vertical pixel signals Sig1, Sig2,
By performing the weighted addition of Sig3 at the analog signal stage, the weighted addition can be performed without including an error due to a noise component superimposed at the time of A / D conversion and a quantization error. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area of the solid-state imaging device (chip) is not increased.

(2) In the above embodiment, when the ADC 12 has a plurality of capacitors C1 to C8 each having the same capacitance and performs weighted addition of the pixel signals Sig1, Sig2, and Sig3, When holding each pixel signal in the capacitors C1 to C4, one or more capacitors are assigned from among the plurality of capacitors C1 to C8 according to the weighting of each pixel signal, and the assigned capacitors are charged. The pixel signals Sig1, Sig2, and Sig3 are weighted by adding the charged charges held in the capacitors C1 to C4 after the input of the pixel signals to be weighted and added is completed. Addition is performed, and a potential is generated at the node Vcm by the pixel signal subjected to the weighted addition.
Accordingly, the pixel signals Sig1, Sig2, and Sig3 can be easily weighted and added at the analog signal stage using the capacitors C1 to C4 in the ADC 12. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area is not increased.

(3) In the above embodiment, the control unit 21 changes the potential of the node Vcm stepwise by sequentially switching the voltages of the counter electrodes of the plurality of capacitors C1 to C8, and the potential of the node Vcm and a predetermined potential ( The coarse conversion control unit 22 that compares the dark potential Vdark) to determine the upper bits of a predetermined number of digital values, and the voltage at the counter electrode of the predetermined capacitor C8 in the capacitors C1 to C8 after the completion of the coarse conversion A fine conversion control unit that changes the potential of the node Vcm on the slope by changing VRAMP in a slope shape and compares the potential of the node Vcm with a predetermined potential (dark potential Vdark) to determine the lower bits of the digital value. 23.
As a result, in addition to the effect that weighted addition can be performed without including errors due to superimposed noise components and quantization errors during A / D conversion, the weighted and added pixel signal is converted into a digital value. A / D conversion speed can be increased.

(4) Moreover, in the said embodiment, the control part 21 changes the electric potential of the node Vcm on a slope by changing the voltage VRAMP of the counter electrode of the predetermined | prescribed capacitor | condenser C8 in the capacitors C1-C8 in a slope shape, A fine conversion control unit 23 that compares the potential of the node Vcm with a predetermined potential (Vdark) to generate a digital value is provided.
Thereby, it can also be set as the structure which performs only a fine conversion process, without performing a course conversion process. Thereby, the circuit configuration of the A / D conversion circuit can be simplified.

(5) In the above embodiment, the number of the plurality of capacitors C1 to C8 is n (n = 8), and the number of the first group capacitors C1 to C4 that hold pixel signals in advance is m (m = 4), m first group of switches S9 to S12 that selectively connect between each of the four capacitors C1 to C4 of the first group and the node Vcm, and a plurality of capacitors C1 to C8 (N−m) (four) of the second group of capacitors C5 to C8 excluding the first group of capacitors therein and the node Vcm are selectively connected at one time. The control unit 21 includes a first switch S9 to a first group for each input pixel signal according to the number of pixel signals to be weighted and the weight of each pixel signal. Pre-install one or more switches from S12 When assigning and adding pixel signals that are sequentially input via the vertical signal lines VL and adding them, first, the first group of switches S9 to S12 and the second group of switches S13 are turned off, Is turned on, the switch assigned to the pixel signal in the first group of switches S9 to S12 is turned on, the capacitor connected to the switch is charged, the pixel signal is held, and then the switch is turned on. After all the pixel signals Sig1, Sig2, and Sig3 to be turned off and weighted addition are completed, the first group of switches S9 to S12 are turned on all at once, and the capacitors connected to the first group of switches S9 to S12 The pixel signals are weighted and added by adding the charged charges held in C1 to C4, and the weighted and added pixel signals are added. To generate a potential more node Vcm.
Accordingly, the pixel signals Sig1, Sig2, and Sig3 can be weighted and added at the analog signal stage, and weighted addition can be performed using the capacitors C1 to C4 in the ADC 12.

(6) In the above embodiment, the control unit 21 controls the first group of switches S9 to S12 and the second group of switches S13 to be always on, thereby weighting and adding the input pixel signal. Performs A / D conversion with none.
Thereby, A / D conversion with weighted addition and A / D conversion without weighted addition can be selected and executed.

(7) In the above embodiment, the solid-state imaging device 1 is the solid-state imaging device 1 including the ADC 12 described above, and the pixels PX including the photoelectric conversion elements that convert the optical signal into the electrical signal are arranged in a plurality of matrices. And an image pickup means (pixel unit 2) for outputting the signals of the pixels PX in the selected row through a plurality of vertical signal lines VL wired for each column while sequentially scanning the pixels PX row by row. Is provided corresponding to each of the plurality of vertical signal lines VL, and converts pixel signals (for example, signals Sig1, Sig2, Sig3) output from the vertical signal lines VL from analog signals to digital values.
Thereby, in the solid-state imaging device 1 of the present invention, when the pixel signals (for example, the signals Sig1, Sig2, and Sig3) output from the vertical signal line VL are weighted and added and output as digital values (digital data), Weighted addition of pixel signals can be performed at the analog signal stage. For this reason, the weighted and added digital data can be output without including an error due to a noise component or the like superimposed when the pixel signal is A / D converted. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area is not increased.

  Although the embodiment of the present invention has been described above, the A / D conversion circuit of the present invention is not limited to the above illustrated example, and various modifications are made within the scope not departing from the gist of the present invention. Of course you get.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel part 3 Vertical scanning circuit 4 Horizontal scanning circuit 11 PGA
12 ADC (A / D conversion circuit)
21 Control unit 22 Course conversion control unit 23 Fine conversion control unit 24 Counter C1 to C8 Capacitor C10, C11, C12 Capacitor CP1 Comparator PX Pixel S1a, S4b to S8a, S8b, SX switch S9, S10, S11, S12, S13 Switch Sig1 , Sig2, Sig3 Pixel signal Vcm node

Claims (36)

A first pixel that generates a first signal from the photoelectrically converted charge;
A second pixel that generates a second signal from the photoelectrically converted charge;
A signal line connected to the first pixel and the second pixel and outputting the first signal and the second signal;
A first holding unit that holds the first signal output to the signal line; and a second holding unit that holds the second signal output to the signal line. A signal processing unit that generates a third signal from the held first signal and the second signal held in the second holding unit;
A conversion unit that converts the third signal generated by the signal processing unit into a digital signal;
Equipped with a,
The first pixel includes a first transistor connected to the signal line and outputting the first signal to the signal line;
The second pixel includes a second transistor connected to the signal line and outputting the second signal to the signal line.
Image sensor. The first transistor includes:
Controlled by a control signal supplied from the scanning circuit via the first control line,
The second transistor is
The imaging device according to claim 1 , wherein the imaging element is controlled by a control signal supplied from the scanning circuit via a second control line different from the first control line. The first transistor includes:
A first gate electrode connected to the first control line and not connected to the second control line;
The second transistor is
The imaging device according to claim 2 , further comprising a second gate electrode connected to the second control line and not connected to the first control line. The first holding unit includes a first capacitive element that holds the first signal,
The imaging device according to any one of claims 1 to 3 , wherein the second holding unit includes a second capacitive element different from the first capacitive element that holds the second signal. The imaging device according to claim 4 , wherein the second capacitive element has the same capacitance as the first capacitive element. The imaging device according to claim 4 , wherein the second capacitive element has a capacitance different from that of the first capacitive element. An amplifying unit that amplifies the first signal output to the signal line and the second signal output to the signal line;
The signal processing unit
2. The third signal is generated by the first signal that is disposed between the amplification unit and the conversion unit and amplified by the amplification unit, and the second signal amplified by the amplification unit. The imaging device according to claim 6 . A first pixel that generates a first signal from the photoelectrically converted charge;
A second pixel that generates a second signal from the photoelectrically converted charge;
A signal line connected to the first pixel and the second pixel and outputting the first signal and the second signal;
An amplifying unit for amplifying the first signal output to the signal line and the second signal output to the signal line;
A signal processing unit that generates a third signal from the first signal amplified by the amplification unit and the second signal amplified by the amplification unit;
A conversion unit that converts the third signal generated by the signal processing unit into a digital signal;
An imaging device comprising: The first pixel includes a first transistor connected to the signal line and outputting the first signal to the signal line;
The image sensor according to claim 8 , wherein the second pixel includes a second transistor that is connected to the signal line and outputs the second signal to the signal line. The first transistor includes:
Controlled by a control signal supplied from the scanning circuit via the first control line,
The second transistor is
The imaging device according to claim 9 , wherein the imaging element is controlled by a control signal supplied from the scanning circuit via a second control line different from the first control line. The first transistor includes:
A first gate electrode connected to the first control line and not connected to the second control line;
The second transistor is
The imaging device according to claim 10 , further comprising a second gate electrode connected to the second control line and not connected to the first control line. A first photoelectric conversion unit that converts light into electric charge;
A second photoelectric conversion unit that converts light into electric charge;
A signal line for outputting a first signal generated by the charge converted by the first photoelectric conversion unit and a second signal generated by the charge converted by the second photoelectric conversion unit;
A first holding unit that holds the first signal output to the signal line; and a second holding unit that holds the second signal output to the signal line. A signal processing unit that generates a third signal from the held first signal and the second signal held in the second holding unit;
A comparator used to convert the third signal generated by the signal processing unit into a digital signal;
An imaging device comprising: A first transistor connected to the signal line for outputting the first signal to the signal line;
A second transistor connected to the signal line for outputting the second signal to the signal line;
The imaging device according to claim 12 . The first transistor includes:
Controlled by a control signal supplied from the scanning circuit via the first control line,
The second transistor is
The imaging device according to claim 13 , wherein the imaging element is controlled by a control signal supplied from the scanning circuit via a second control line different from the first control line. The first transistor includes:
A first gate electrode connected to the first control line and not connected to the second control line;
The second transistor is
The imaging device according to claim 14 , further comprising a second gate electrode connected to the second control line and not connected to the first control line. The first holding unit includes a first capacitive element that holds the first signal,
The image sensor according to any one of claims 12 to 15 , wherein the second holding unit includes a second capacitor element different from the first capacitor element that holds the second signal. The imaging device according to claim 16 , wherein the second capacitor element has the same capacitance as the first capacitor element. The imaging device according to claim 16 , wherein the second capacitive element has a capacitance different from that of the first capacitive element. An amplifying unit that amplifies the first signal output to the signal line and the second signal output to the signal line;
The signal processing unit
Is disposed between the amplifying portion and said comparator, said first signal amplified by the amplifying unit, from the claims 12 to generate the third signal by a second signal amplified by the amplifying section The imaging device according to claim 18 . A first photoelectric conversion unit that converts light into electric charge;
A second photoelectric conversion unit that converts light into electric charge;
A signal line for outputting a first signal generated by the charge converted by the first photoelectric conversion unit and a second signal generated by the charge converted by the second photoelectric conversion unit;
An amplifying unit for amplifying the first signal output to the signal line and the second signal output to the signal line;
A signal processing unit that generates a third signal from the first signal amplified by the amplification unit and the second signal amplified by the amplification unit;
A comparator used to convert the third signal generated by the signal processing unit into a digital signal;
An imaging device comprising: A first transistor connected to the signal line for outputting the first signal to the signal line;
A second transistor connected to the signal line for outputting the second signal to the signal line;
The imaging device according to claim 20 . The first transistor includes:
Controlled by a control signal supplied from the scanning circuit via the first control line,
The second transistor is
The imaging device according to claim 21 , wherein the imaging element is controlled by a control signal supplied from the scanning circuit via a second control line different from the first control line. The first transistor includes:
A first gate electrode connected to the first control line and not connected to the second control line;
The second transistor is
The imaging device according to claim 22 , further comprising a second gate electrode connected to the second control line and not connected to the first control line. The signal processing unit
A first holding unit for holding the first signal; a second holding unit for holding the second signal; the first signal held by the first holding unit; and the second holding unit. The image sensor according to any one of Claims 20 to 23 , wherein the third signal is generated by the second signal held in the position. The first holding unit includes a first capacitive element that holds the first signal,
The imaging device according to claim 24 , wherein the second holding unit includes a second capacitive element different from the first capacitive element that holds the second signal. The imaging device according to claim 25 , wherein the second capacitive element has the same capacitance as the first capacitive element. The imaging device according to claim 25 , wherein the second capacitive element has a capacitance different from that of the first capacitive element. A first pixel that generates a first signal from the photoelectrically converted charge;
A second pixel that generates a second signal from the photoelectrically converted charge;
A third pixel that generates a third signal from the photoelectrically converted charge;
A signal line connected to the first pixel, the second pixel, and the third pixel and outputting the first signal, the second signal, and the third signal;
A first holding unit for holding the first signal output to the signal line; a second holding unit for holding the second signal output to the signal line; and the third holding unit output to the signal line. A third holding unit for holding a signal, the first signal held in the first holding unit, the second signal held in the second holding unit, and the third holding unit A signal processing unit that generates a fourth signal using the held third signal;
A conversion unit that converts the fourth signal generated by the signal processing unit into a digital signal;
An imaging device comprising: The first pixel is
A first transistor connected to the signal line for outputting the first signal to the signal line;
The second pixel is
A second transistor connected to the signal line for outputting the second signal to the signal line;
The third pixel is
The imaging device according to claim 28 , further comprising a third transistor connected to the signal line and configured to output the third signal to the signal line. The first transistor includes:
Controlled by a control signal supplied from the scanning circuit via the first control line,
The second transistor is
Controlled by a control signal supplied from the scanning circuit via a second control line different from the first control line;
The third transistor is
30. The imaging device according to claim 29 , controlled by a control signal supplied from the scanning circuit via a third control line different from the first control line and the second control line. The first transistor includes:
A first gate electrode connected to the first control line and not connected to the second control line and the third control line;
The second transistor is
A second gate electrode connected to the second control line and not connected to the first control line and the third control line;
The third transistor is
The imaging device according to claim 30 , further comprising a third gate electrode connected to the third control line and not connected to the first control line and the second control line. The first holding unit includes a first capacitive element that holds the first signal,
The second holding unit includes a second capacitive element that holds the second signal,
The image sensor according to any one of claims 28 to 31 , wherein the third holding unit includes a third capacitor element that holds the third signal. The imaging device according to claim 32 , wherein the second capacitive element has the same capacitance as the first capacitive element and the third capacitive element. The second capacitive element has a capacitance different from that of the first capacitive element and the third capacitive element,
The imaging device according to claim 32 , wherein the first signal, the second signal, and the third signal are output to the signal line in this order. An amplifying unit that amplifies the first signal output to the signal line, the second signal output to the signal line, and the third signal output to the signal line;
The signal processing unit
The first signal disposed between the amplifying unit and the converting unit, amplified by the amplifying unit, the second signal amplified by the amplifying unit, and the third signal amplified by the amplifying unit The imaging device according to any one of claims 28 to 34 , wherein the fourth signal is generated by: An imaging device including the imaging device according to any one of claims 1 to 35 .

Images