JP6229040B2 - Semiconductor integrated circuit device and sensing module having the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device having a power supply terminal, a ground terminal, and a signal terminal, and in particular, a semiconductor having a function of protecting a circuit from an overcurrent or the like even when a wiring is erroneously connected to these terminals. The present invention relates to an integrated circuit device.

  There are various types of sensors that detect physical quantities, for example, those configured by passive devices such as variable resistors, and sensors configured as a sensor module that combines a sensing element and an IC chip. Usually, the sensor is connected to an external device by three lines of a power line, a ground line, and a signal line, and receives power supply from the external apparatus and performs control related to acquisition of sensor measurement values and sensing.

  FIG. 10 is a diagram illustrating a connection method between a general sensor and a device. A cable harness 103 with a connector is often used for connection between the sensor 101 and the device 102. For example, as shown in FIG. 11, there is a signal line voltage as a method of notifying the device 102 of an abnormal state when the connection between the sensor 101 and the device 102 is incomplete or when an abnormality occurs in the sensor 101. There is a method of determining an abnormal state if it deviates from the range. In FIG. 11, “effective range” indicates a voltage range in a normal state, and “error range” indicates a voltage range in an abnormal state. This method does not require a special signal line for notifying an abnormal condition, and is very effective for a digital signal or an analog signal.

  In this abnormal state notification method based on the error range, as shown in FIG. 10, the signal line may be connected to the power supply voltage by the pull-up resistor 104 on the device 102 side, or the signal line may be connected to the ground by the pull-down resistor. Many. The reason is that, as shown in FIG. 12, when the cable is disconnected, the voltage of the signal line becomes equal to the power supply voltage or the ground potential and enters the error range, so that the abnormal state can be detected in the device 102. .

  In the example of FIGS. 10 and 11, the sensor 101 is a variable resistor which is a passive element. Recently, in order to prevent malfunction due to physical wear of the sliding portion of the variable resistor, An increasing number of sensor modules are configured with electronic circuits (such as ICs) by another means for realizing the function of variable resistors (the function of converting position into voltage) in a non-contact manner.

  When the device 102 and the sensor 101 are connected by a cable as shown in FIG. 10, not only the disconnection of the cable (FIG. 12) but also the three terminals of the sensor 101 (power supply terminal and ground terminal) as shown in FIG. Incorrect wiring may be connected to the signal terminal. When such an erroneous connection occurs, an incorrect voltage may be applied to the IC included in the module of the sensor 101, and an overcurrent may flow in the internal circuit of the IC.

  Further, depending on the situation, the power supply line, the ground line, and the signal line may be short-circuited or disconnected in any combination. Furthermore, the connector of the sensor 101 may be mistakenly connected to a connector with a different voltage level.

  Therefore, even if the relative voltage level between the terminals becomes abnormal due to incorrect connection or the like (for example, even when the power supply terminal is lower in potential than the ground terminal), the sensor module IC has an overcurrent. It is desirable not to flow. In such an abnormal state, it is desirable to be able to notify the connected device of the abnormal state.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a current that flows from these terminals to the power supply terminal, the ground terminal, and the signal terminal even if an improper voltage is applied due to an incorrect connection of wiring or the like. It is an object to provide a semiconductor integrated circuit device capable of protecting a circuit by suppressing the above-described problem and notifying an external device of such an abnormal state, and a sensor module including the semiconductor integrated circuit device.

  A semiconductor integrated circuit device according to a first aspect of the present invention provides a ground terminal connected to a ground potential, a power supply terminal for inputting a power supply voltage, a signal terminal, and outputs or inputs a signal at the signal terminal, A signal circuit that sets an output impedance or input impedance at a signal terminal to a high impedance state according to a control signal, and determines whether or not the voltage of the power supply terminal with reference to the voltage of the ground terminal is within a normal range A first determination circuit configured to determine whether a voltage of the signal terminal with respect to a voltage of the ground terminal is within a normal range that is lower than the voltage of the power supply terminal and higher than the voltage of the ground terminal; When it is determined in the determination circuit and the first determination circuit that the voltage of the power supply terminal is not within the normal range, or in the second determination circuit When it is determined that the voltage of the signal terminal is not within the normal range, the control signal output circuit that outputs the control signal that sets the output impedance or input impedance of the signal terminal to a high impedance state, and the voltage of the ground terminal A first voltage selection circuit that selects the highest voltage among the voltage of the power supply terminal and the voltage of the signal terminal. The first voltage selection circuit applies the selected voltage to the bulk of at least some of the P-type MOS transistors included in the entire circuit.

According to the above configuration, the highest voltage among the voltage of the power supply terminal, the voltage of the ground terminal, and the voltage of the signal terminal is selected by the first voltage selection circuit, and the selected voltage is entirely Applied to the bulk of the P-type MOS transistor included in the circuit. As a result, even when the relative voltage level relationship at these terminals becomes abnormal due to misconnection of wirings, no current flows through the parasitic diode formed in the bulk of the P-type MOS transistor.
Further, according to the above configuration, when it is determined in the determination result of the first determination circuit that the voltage of the power supply terminal is not within the normal range, or in the determination result of the second determination circuit, the voltage of the signal terminal Is not in the normal range, the output impedance or input impedance of the signal circuit at the signal terminal is in a high impedance state. Therefore, when an abnormal state such as erroneous wiring, disconnection, or short circuit occurs, the occurrence of the abnormal state is notified to an external device as the high impedance state.

Preferably, the first voltage selection circuit may supply the selected voltage as a power supply voltage to the signal circuit, the first determination circuit, the second determination circuit, and the control signal output circuit.
As a result, even when an abnormal state such as miswiring, disconnection, or short-circuit occurs, the signal circuit, the first determination circuit, the second determination circuit, and the control signal output circuit are supplied with the voltage of the ground terminal. Since a high power supply voltage is supplied, the operation of these circuits may be able to notify an external device of an abnormal state.

  A semiconductor integrated circuit device according to a second aspect of the present invention provides a ground terminal connected to a ground potential, a power supply terminal for inputting a power supply voltage, a signal terminal, and outputs or inputs a signal at the signal terminal, A signal circuit that sets an output impedance or input impedance at a signal terminal to a high impedance state according to a control signal, and determines whether or not the voltage of the power supply terminal with reference to the voltage of the ground terminal is within a normal range A first determination circuit configured to determine whether a voltage of the signal terminal with respect to a voltage of the ground terminal is within a normal range that is lower than the voltage of the power supply terminal and higher than the voltage of the ground terminal; When it is determined in the determination circuit and the first determination circuit that the voltage of the power supply terminal is not within the normal range, or in the second determination circuit When it is determined that the voltage of the signal terminal is not within the normal range, the control signal output circuit that outputs the control signal that sets the output impedance or input impedance of the signal terminal to a high impedance state, and the voltage of the ground terminal A first voltage selection circuit that selects the highest voltage among the voltage of the power supply terminal and the voltage of the signal terminal; and a second voltage selection circuit that selects a higher voltage among the voltage of the ground terminal and the voltage of the power supply terminal. A voltage selection circuit; and a regulator circuit that converts a power supply voltage input at the power supply terminal into an internal power supply voltage and supplies the internal power supply voltage to the internal circuit. The first voltage selection circuit applies the selected voltage to a bulk of a P-type MOS transistor included in the signal circuit, the second determination circuit, and the control signal output circuit. The second voltage selection circuit applies the selected voltage to a bulk of a P-type MOS transistor included in the first determination circuit and the regulator circuit.

According to the above configuration, the highest voltage among the voltage of the power supply terminal, the voltage of the ground terminal, and the voltage of the signal terminal is selected by the first voltage selection circuit, and the selected voltage is The signal is applied to the bulk of the P-type MOS transistor included in the signal circuit, the second determination circuit, and the control signal output circuit. A high voltage is selected by the second voltage selection circuit among the voltage at the ground terminal and the voltage at the power supply terminal, and the selected voltage is a P-type MOS transistor included in the first determination circuit and the regulator circuit. Applied to the bulk. As a result, even when the relative voltage level relationship at these terminals becomes abnormal due to misconnection of wirings, no current flows through the parasitic diode formed in the bulk of the P-type MOS transistor.
Further, according to the above configuration, when it is determined in the determination result of the first determination circuit that the voltage of the power supply terminal is not within the normal range, or in the determination result of the second determination circuit, the voltage of the signal terminal Is not in the normal range, the output impedance or input impedance of the signal circuit at the signal terminal is in a high impedance state. Therefore, when an abnormal state such as erroneous wiring, disconnection, or short circuit occurs, the occurrence of the abnormal state is notified to an external device as the high impedance state.

Preferably, the first voltage selection circuit may supply the selected voltage as a power supply voltage to the signal circuit, the second determination circuit, and the control signal output circuit, and the second voltage selection circuit includes the first voltage selection circuit. The selected voltage may be supplied as a power supply voltage to one determination circuit.
As a result, even when an abnormal state such as miswiring, disconnection, or short-circuit occurs, the signal circuit, the first determination circuit, the second determination circuit, and the control signal output circuit are supplied with the voltage of the ground terminal. Since a high power supply voltage is supplied, the operation of these circuits may be able to notify an external device of an abnormal state.

Preferably, the internal circuit may include a circuit that records a signal indicating a determination result output from at least one of the first determination circuit, the second determination circuit, and the control signal output circuit.
Thereby, more detailed information regarding the abnormal state is acquired.

  Preferably, the first determination circuit generates a reference voltage that is constant with respect to the voltage of the voltage dividing circuit including a plurality of resistors connected in series between the ground terminal and the power supply terminal. A reference voltage generating circuit, a comparison circuit for comparing a plurality of detection voltages divided by different voltage dividing ratios in the voltage dividing circuit with the reference voltage, and the ground terminal based on a comparison result of the comparison circuit And a determination signal output circuit that outputs a first determination signal indicating a determination result as to whether or not the voltage of the power supply terminal is within a normal range.

Preferably, the semiconductor integrated circuit device may include a control terminal that receives a power supply voltage common to the power supply terminal during a normal operation, and receives the ground potential or is opened during a non-normal operation. . In this case, the plurality of resistors included in the voltage dividing circuit are connected in series between the ground terminal and the control terminal instead of being connected in series between the ground terminal and the power supply terminal. It's okay.
As a result, during the non-normal operation, the first determination circuit determines that the voltage of the power supply terminal is not within the normal range, and the output impedance or input impedance of the signal circuit at the signal terminal is in a high impedance state.

Preferably, the reference voltage generation circuit outputs a status signal indicating whether or not the reference voltage is generated, and the comparison circuit indicates that the status signal indicating that the reference voltage is not generated is the reference voltage generation circuit. Is output from the first determination signal indicating that the voltage of the power supply terminal is within a normal range.
As a result, when there is a possibility that the erroneous first determination signal is output based on the reference voltage that is not normal, the first determination signal indicating that the voltage of the power supply terminal is within the normal range is output. It will not be done.

  Preferably, when the first detection voltage in the plurality of detection voltages changes from a state lower than the reference voltage to a higher state, the comparison circuit outputs a signal indicating that the voltage of the power supply terminal is higher than the upper limit of the normal range. When the second detection voltage higher than the first detection voltage in the plurality of detection voltages changes from a state higher than the reference voltage to a lower state, the voltage of the power supply terminal is lower than the upper limit of the normal range A first hysteresis comparator that outputs a signal; and a third detection voltage that is higher than the second detection voltage in the plurality of detection voltages changes from a state that is lower than the reference voltage to a state that is higher than the reference voltage. A signal indicating that the value is higher than the lower limit of the first detection voltage, and a fourth detection voltage higher than the third detection voltage among the plurality of detection voltages is higher than the reference voltage. When changing from state to a low state, the voltage of the power supply terminal may comprise a second hysteresis comparator for outputting a signal indicating that the lower limit of the normal range. The determination signal output circuit outputs a signal indicating that the voltage of the power supply terminal is higher than the upper limit of the normal range in the first hysteresis comparator, or the voltage of the power supply terminal in the second hysteresis comparator. When a signal indicating that the voltage is lower than the lower limit of the normal range is output, the first determination signal indicating that the voltage of the power supply terminal is not within the normal range may be output.

  A sensor module according to a third aspect of the present invention includes a sensor unit and the semiconductor integrated circuit device that outputs a signal corresponding to a sensing result of the sensor unit from the signal terminal.

  According to the present invention, even if an improper voltage is applied to the power supply terminal, the ground terminal, and the signal terminal due to misconnection of the wiring, the current flowing from these terminals can be suppressed to protect the circuit, and such It is possible to notify an external device that there is an abnormal state.

It is a figure which shows an example of a structure of the sensor module which concerns on embodiment of this invention. 1 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit device according to a first embodiment. It is a figure which shows an example of a structure of a hysteresis comparator. It is a figure which shows an example of the circuit which determines whether a signal voltage exists in a normal range. It is a figure which shows an example of a structure of a voltage selection circuit. It is a figure for demonstrating the parasitic diode of a P-type MOS transistor. 6A shows a structure of a P-type MOS transistor, and FIG. 6B shows an example of a circuit including a P-type MOS transistor. It is a figure which shows the modification of the semiconductor integrated circuit device which concerns on 1st Embodiment. It is a figure which shows an example of a structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. It is a figure which shows an example of a level shift circuit. It is a figure which shows the connection method of a general sensor and apparatus. It is a figure for demonstrating the notification method of the abnormal condition using an error range. It is a figure which shows the case where the cable has cut | disconnected. It is a figure which shows the case where the connection of a sensor and an apparatus is incorrect.

<First Embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a configuration of a sensor module 1 according to an embodiment of the present invention. A sensor module 1 shown in FIG. 1 includes a sensor unit 6 that detects a physical quantity such as a position and speed as an electrical signal, and a semiconductor integrated circuit device 5 that outputs a signal (sensing signal) corresponding to a sensing result of the sensor unit 6. Have. The sensor unit 6 may be a component independent of the semiconductor integrated circuit device 5 or may be formed on the same semiconductor chip as the semiconductor integrated circuit device 5.

  The semiconductor integrated circuit device 5 of the sensor module 1 includes three terminals (a power supply terminal T1, a ground terminal T2, and a signal terminal T3), and each terminal corresponds to a corresponding terminal (T21 to T23) of the external device 2. Connected. In the example of FIG. 1, the sensor module 1 and the device 2 are connected via a cable harness 3 with a connector. Even if an incorrect voltage is applied to the three terminals (the power supply terminal T1, the ground terminal T2, and the signal terminal T3) due to miswiring, disconnection, or short circuit inside the cable harness 3, the semiconductor integrated circuit device 5 Prevent overcurrent from flowing through the circuit.

  Also, the semiconductor integrated circuit device 5 has an output impedance at the signal terminal T3 when an improper voltage is applied to the three terminals (power supply terminal T1, ground terminal T2, signal terminal T3) due to miswiring, disconnection, or short circuit. Set to high impedance state. In the example of FIG. 2, since the signal terminal T23 of the device 2 is connected to the power supply terminal T21 via the pull-up resistor 4, when the signal terminal T3 of the semiconductor integrated circuit device 5 is in a high impedance state, the signal terminal T23 The voltage rises to the power supply voltage VDD. If the voltage at the signal terminal T23 is included in the error range close to the power supply voltage VDD, the device 2 determines that the semiconductor integrated circuit device 5 of the sensor module 1 is in an abnormal state in which an incorrect voltage is applied.

  Note that the pull-up resistor 4 in FIG. 1 may be replaced with a pull-down resistor connected between the signal terminal T23 and the ground terminal T12. In this case, when the signal terminal T3 of the semiconductor integrated circuit device 5 is in a high impedance state, the voltage of the signal terminal T23 of the device 2 decreases to the ground potential VSS. In this case, the error range for determining an abnormal state in the device 2 is set near the ground potential VSS.

FIG. 2 is a diagram illustrating an example of the configuration of the semiconductor integrated circuit device 5 according to the first embodiment.
The semiconductor integrated circuit device 5 shown in FIG. 2 includes a power supply terminal T1, a ground terminal T2, a signal terminal T3, a signal circuit 10, determination circuits 20 and 30, a control signal output circuit 40, and a voltage selection circuit 51. Have
The power terminal T1 is an example of a power terminal in the present invention.
The ground terminal T2 is an example of the ground terminal in the present invention.
The signal terminal T3 is an example of a signal terminal in the present invention.
The signal circuit 10 is an example of a signal circuit in the present invention.
The determination circuit 20 is an example of a first determination circuit in the present invention.
The determination circuit 30 is an example of a second determination circuit in the present invention.
The control signal output circuit 40 is an example of the control signal output circuit in the present invention.
The voltage selection circuit 51 is an example of a first voltage selection circuit in the present invention.

  The signal circuit 10 is a circuit that outputs a sensing signal according to the sensing result of the sensor unit 6 at the signal terminal T3. For example, the signal circuit 10 is an amplifier circuit that amplifies and outputs a weak sensing signal input from a circuit (not shown). In response to the control signal S40 output from the control signal output circuit 40, the signal circuit 10 sets the output impedance at the signal terminal T3 to a high impedance state. Specifically, the signal circuit 10 operates as an amplifier circuit that amplifies the sensing signal when the control signal S40 is “1”, and sets the output impedance to a high impedance state when the control signal S40 is “0”. .

  Further, the signal circuit 10 includes an output short circuit protection circuit that prevents an overcurrent from flowing to the output even when the signal terminal T3 is short-circuited to the power supply terminal T1 or the ground terminal T2.

  The determination circuit 20 determines whether or not the voltage (power supply voltage VDD) of the power supply terminal T1 based on the voltage of the ground terminal T2 (ground potential VSS) is within a normal range. For example, the determination circuit 20 determines an abnormal state when the power supply voltage VDD is lower than the lower limit threshold voltage or higher than the upper limit threshold voltage, and when the power supply voltage VDD is higher than the lower limit value and lower than the upper limit value. Judged as normal.

  The threshold voltage at which the determination changes from the abnormal state to the normal state and the threshold voltage at which the determination changes from the normal state to the abnormal state may be the same or different. By making the two threshold voltages different from each other, it is possible to prevent the determination result from frequently changing due to a minute fluctuation of the power supply voltage VDD when the power supply voltage VDD is in the vicinity of the threshold voltage.

  For example, the determination circuit 20 uses two threshold voltages Vth1 and Vth2 (Vth1> Vth2) for determination of the upper limit, and uses two threshold voltages Vth3, Vth4 (Vth3> Vth4) for determination of the lower limit. The determination circuit 20 determines that the power supply voltage VDD has changed to an abnormal state when the power supply voltage VDD is higher than the upper limit threshold voltage Vth1 when determining that the power supply voltage VDD is normal, and determines that the power supply voltage VDD is upper limit when the power supply voltage VDD is determined to be abnormal. When it becomes lower than the threshold voltage Vth2, it is determined that the normal state has been changed. The determination circuit 20 determines that the power supply voltage VDD has changed to an abnormal state when the power supply voltage VDD is lower than the lower limit threshold voltage Vth4 when determining that the power supply voltage is normal, and determines that the power supply voltage VDD is determined to be abnormal. Is higher than the lower threshold voltage Vth3, it is determined that the state has changed to the normal state.

In the example of FIG. 2, the determination circuit 20 includes a voltage dividing circuit 21, a reference voltage generation circuit 22, a comparison circuit 23, and a determination signal output circuit 24.
The voltage dividing circuit 21 is an example of a voltage dividing circuit in the present invention.
The reference voltage generation circuit 22 is an example of the reference voltage generation circuit in the present invention.
The comparison circuit 23 is an example of a comparison circuit in the present invention.
The determination signal output circuit 24 is an example of a determination signal output circuit in the present invention.

  The voltage dividing circuit 21 is a circuit that outputs a plurality of detection voltages (Vs1 to Vs4) divided by different voltage dividing ratios, and a plurality of resistors (series) connected in series between the power supply terminal T1 and the ground terminal T2. R1-R5). The resistors R1, R2, R3, R4, and R5 are connected in series in this order. One end on the resistor R1 side in the series circuit of the resistors R1 to R5 is connected to the ground terminal T2, and the other end on the resistor R5 side is connected to the power supply terminal T1. The detection voltage Vs1 is generated at the connection node of the resistors R1 and R2, the detection voltage Vs2 is generated at the connection node of the resistors R2 and R3, the detection voltage Vs3 is generated at the connection node of the resistors R3 and R4, and the detection voltage Vs4 is the resistance Occurs at the connection node of R4 and R5. The voltage level relationship with respect to the ground potential VSS is “Vs1 <Vs2 <Vs3 <Vs4”.

  The reference voltage generation circuit 22 generates a constant reference voltage Vref with respect to the ground potential VSS. The reference voltage generation circuit 22 outputs a status signal R_RDY indicating whether or not the reference voltage Vref is generated. As a result, when the correct reference voltage Vref cannot be generated due to an abnormality in the power supply voltage VDD, the state is notified to the comparison circuit 23.

  The comparison circuit 23 compares the plurality of detection voltages (Vs1 to Vs4) divided by the different voltage dividing ratios in the voltage dividing circuit 21 with the reference voltage Vref, and the comparison result indicates whether the power supply voltage VDD exceeds the upper limit. A signal Sh1 indicating whether or not the power supply voltage VDD is below the lower limit, and a signal Sh2 indicating whether or not the power supply voltage VDD is lower than the lower limit.

  However, the comparison circuit 23 indicates that the power supply voltage VDD is within the normal range when the state signal R_RDY indicating that the normal reference voltage Vref is not generated in the reference voltage generation circuit 22 is output. The output of the signals Sh1 and Sh2 is suppressed. In this case, for example, the comparison circuit 23 outputs at least one of the signal Sh1 indicating that the power supply voltage VDD exceeds the upper limit and the signal Sh2 where the power supply voltage VDD is lower than the lower limit. As a result, when there is a possibility that erroneous signals Sh1 and Sh2 are output based on the reference voltage Vref that is not normal, the signals Sh1 and Sh2 indicating that the power supply voltage VDD is within the normal range are output. Can be prevented.

In the example of FIG. 2, the comparison circuit 23 includes hysteresis comparators 231 and 232.
The hysteresis comparator 231 is an example of a first hysteresis comparator in the present invention.
The hysteresis comparator 232 is an example of a second hysteresis comparator in the present invention.

  When the detection voltage Vs1 changes from a state lower than the reference voltage Vref to a higher state, the hysteresis comparator 231 outputs a signal Sh1 indicating that the power supply voltage VDD is higher than the upper limit of the normal range (for example, Sh1 = “0”). When the voltage Vs2 changes from a state higher than the reference voltage Vref to a state lower than the reference voltage Vref, a signal Sh1 indicating that the power supply voltage VDD is lower than the upper limit of the normal range is output (for example, Sh1 = “1”).

  The detection voltages Vs1 and Vs2 are expressed by the following equations using upper limit threshold voltages Vth1 and Vth2 (Vth1> Vth2), respectively.

[Equation 1]
Vs1 = Vref × (VDD / Vth1) (1)
Vs2 = Vref × (VDD / Vth2) (2)

From Expression (1), when the detection voltage Vs1 changes from a state lower than the reference voltage Vref to a higher state, the power supply voltage VDD becomes higher than the upper threshold voltage Vth1 (becomes an abnormal state higher than the upper limit of the normal range). Show). In this case, the hysteresis comparator 231 outputs “0” as the signal Sh1.
Further, according to equation (2), when the detection voltage Vs2 changes from a state higher than the reference voltage Vref to a lower state, the power supply voltage VDD becomes lower than the upper threshold voltage Vth2 (becomes lower than the upper limit of the normal range). ). In this case, the hysteresis comparator 231 outputs “1” as the signal Sh1.

  When the detection voltage Vs3 changes from a state lower than the reference voltage Vref to a higher state, the hysteresis comparator 232 outputs a signal Sh2 indicating that the power supply voltage VDD is higher than the lower limit of the normal range (for example, Sh2 = “1”), and is detected. When the voltage Vs4 changes from a higher state to a lower state than the reference voltage Vref, a signal Sh2 indicating that the power supply voltage VDD is lower than the lower limit of the normal range is output (for example, Sh2 = “0”).

  The detection voltages Vs3 and Vs4 are respectively expressed by the following equations using lower limit threshold voltages Vth3 and Vth4 (Vth3> Vth4).

[Equation 1]
Vs3 = Vref × (VDD / Vth3) (3)
Vs4 = Vref × (VDD / Vth4) (4)

From Expression (3), when the detection voltage Vs3 changes from a state lower than the reference voltage Vref to a higher state, the power supply voltage VDD becomes higher than the lower limit threshold voltage Vth3 (becomes higher than the lower limit of the normal range). ). In this case, the hysteresis comparator 232 outputs “1” as the signal Sh2.
Further, from the equation (4), when the detection voltage Vs4 changes from a state higher than the reference voltage Vref to a lower state, the power supply voltage VDD becomes lower than the lower threshold voltage Vth4 (an abnormal state lower than the lower limit of the normal range). To become). In this case, the hysteresis comparator 232 outputs “0” as the signal Sh2.

  FIG. 3 is a diagram illustrating an example of the configuration of the hysteresis comparators 231 and 232. In the example of FIG. 3, the hysteresis comparator 231 includes comparators CP1 and CP2 and a flip-flop FF1. Hysteresis comparator 232 includes comparators CP3 and CP4 and flip-flop FF2.

The output signal Scp1 of the comparator CP1 becomes “1” when the detection voltage Vs1 is higher than the reference voltage Vref, and becomes “0” when it is lower. The output signal Scp2 of the comparator CP2 becomes “0” when the detection voltage Vs2 is higher than the reference voltage Vref, and becomes “1” when it is lower. The output signal Sh1 of the flip-flop FF1 becomes “0” when the signal Scp1 = “1” and the signal Scp2 = “0”, and the previous state when the signal Scp1 = “0” and the signal Scp2 = “0”. When the signal Scp1 = “0” and the signal Scp2 = “1”, the value is “1”.
When the detection voltage Vs1 becomes higher than the reference voltage Vref (Vs2>Vs1> Vref), since the signal Scp1 = “1” and the signal Scp2 = “0”, the hysteresis comparator 231 outputs “0” as the signal Sh1. When the detection voltage Vs1 is lower than the reference voltage Vref and the detection voltage Vs2 is higher than the reference voltage Vref (Vs2>Vref> Vs1), the signal Scp1 = “0” and the signal Scp2 = “0”, so that the hysteresis comparator 231 The value of does not change. When the detection voltage Vs2 becomes lower than the reference voltage Vref (Vref>Vs2> Vs1), since the signal Scp1 = “0” and the signal Scp2 = “1”, the hysteresis comparator 231 outputs “1” as the signal Sh1.

The output signal Scp3 of the comparator CP3 becomes “1” when the detection voltage Vs3 is higher than the reference voltage Vref, and becomes “0” when it is lower. The output signal Scp4 of the comparator CP4 becomes “0” when the detection voltage Vs4 is higher than the reference voltage Vref, and becomes “1” when it is lower. The output signal Sh2 of the flip-flop FF2 becomes “1” when the signal Scp3 = “1” and the signal Scp4 = “0”, and the previous state when the signal Scp3 = “0” and the signal Scp4 = “0”. When the signal Scp3 = “0” and the signal Scp4 = “1”, the value is “0”.
When the detection voltage Vs3 becomes higher than the reference voltage Vref (Vs4>Vs3> Vref), since the signal Scp3 = “1” and the signal Scp4 = “0”, the hysteresis comparator 232 outputs “1” as the signal Sh2. When the detection voltage Vs3 is lower than the reference voltage Vref and the detection voltage Vs4 is higher than the reference voltage Vref (Vs4>Vref> Vs3), the signal Scp3 = “0” and the signal Scp4 = “0”, so the hysteresis comparator 232 The value of does not change. When the detection voltage Vs4 becomes lower than the reference voltage Vref (Vref>Vs4> Vs3), since the signal Scp3 = “0” and the signal Scp4 = “1”, the hysteresis comparator 232 outputs “0” as the signal Sh2.

Returning to FIG.
Based on the comparison result of the comparison circuit 23, the determination signal output circuit 24 outputs a determination signal Sc1 indicating the determination result of whether or not the power supply voltage VDD is within the normal range. That is, the determination signal output circuit 24 outputs the signal Sh1 (= “0”) indicating that the power supply voltage VDD is higher than the upper limit of the normal range in the hysteresis comparator 231 or the power supply voltage VDD is output in the hysteresis comparator 232. When the signal Sh2 (= “0”) indicating that it is lower than the lower limit of the normal range is output, the determination signal Sc1 (= “0”) indicating that the power supply voltage VDD is not within the normal range is output. When the power supply voltage VDD is within the normal range (when Sh1 = “1” and Sh2 = “1”), the determination signal output circuit 24 outputs “1” as the determination signal Sc1. In the example of FIG. 2, the determination signal output circuit 24 is configured by an AND circuit that calculates a logical product of the signal Sh1 and the signal Sh2.

  The determination circuit 30 determines whether or not the voltage at the signal terminal T3 (signal voltage VSIG) is within a normal range lower than the power supply voltage VDD and higher than the ground potential VSS.

  FIG. 4 is a diagram illustrating an example of the configuration of the determination circuit 30. In the example of FIG. 4, the determination circuit 30 includes comparators CP5 and CP6 and an AND circuit 303. The comparator CP5 outputs “1” when the signal voltage VSIG is lower than the power supply voltage VDD, and outputs “0” when it is higher. The comparator CP6 outputs “1” when the signal voltage VSIG is higher than the ground potential VSS, and outputs “0” when it is lower. The AND circuit 303 outputs “1” as the determination signal Sc2 when the outputs of the comparators CP5 and CP6 are both “1”, and outputs “0” otherwise. According to the configuration shown in FIG. 4, when the signal voltage VSIG is in a normal range lower than the power supply voltage VDD and higher than the ground potential VSS, “1” is output from the AND circuit 303 as the determination signal Sc2. When the signal voltage VSIG is not within the normal range (when VSIG> VDD or VSS> VSIG), “0” is output from the AND circuit 303 as the determination signal Sc2.

Returning again to FIG.
When the determination circuit 20 determines that the power supply voltage VDD is not within the normal range, or when the determination circuit 30 determines that the signal voltage VSIG is not within the normal range, the control signal output circuit 40 A control signal S40 for controlling the signal circuit 10 is output so that the output impedance at T3 is in a high impedance state. In the example of FIG. 2, the control signal output circuit 40 is configured by an AND circuit that calculates the logical product of the determination signal Sc <b> 1 of the determination circuit 20 and the determination signal Sc <b> 2 of the determination circuit 30.

  The voltage selection circuit 51 selects the highest voltage among the ground potential VSS, the power supply voltage VDD, and the signal voltage VSIG, and outputs it as the selection voltage VBULK. For example, as shown in FIG. 5, the voltage selection circuit 51 is configured using three diodes (D1, D2, D3). The power supply voltage VDD is input to the anode of the diode D1, the signal voltage VSIG is input to the anode of the diode D2, and the ground potential VSS is input to the anode of the diode D3. The cathodes of the diodes D1, D2, and D3 are commonly connected, and the selection voltage VBULK is output at the commonly connected node.

  A selection voltage VBULK output from the voltage selection circuit 51 is applied to the bulk of the P-type MOS transistor included in the entire circuit of the semiconductor integrated circuit device 5 shown in FIG. That is, the highest voltage input to the semiconductor integrated circuit device 5 at the three terminals (T1 to T3) is applied to the bulk of the P-type MOS transistor.

  Further, in the semiconductor integrated circuit device 5 shown in FIG. 2, in order to be able to notify the external device 2 of an abnormal state even when the power supply voltage VDD is lower than the ground potential VSS due to reverse connection or the like, At least some of the circuits including the determination circuit 20, the determination circuit 30, and the control signal output circuit 40 are supplied with the selection voltage VBULK of the voltage selection circuit 51 instead of the power supply voltage VDD. As a result, even in an abnormal state such as reverse connection, the selection voltage VBULK higher than the ground potential VSS is supplied to these circuits as a power supply voltage, so that an operation similar to the normal state is possible.

Here, the operation of the semiconductor integrated circuit device 5 having the above-described configuration will be described.
First, the protection operation when an improper voltage is applied to the terminals T1 to T3 due to misconnection of wiring (when the relative voltage level of the terminals T1 to T3 is abnormal) will be described.

  FIG. 6 is a diagram for explaining a parasitic diode of a P-type MOS transistor. 6A shows the structure of the P-type MOS transistor Qp, and FIG. 6B shows an example of a circuit including the P-type MOS transistor Qp. An N type diffusion region (N well) is formed on the surface of the P type substrate. On the surface of the N well, there are two P type diffusion regions (p +) to be the source (S) and drain (D) of the P type MOS transistor Qp, and N for connecting the N well to the bulk electrode (B). A mold diffusion region (n +) is formed. In the example of FIG. 6, the source (S) of the P-type MOS transistor Qp is connected to the power supply line (VDD), and its drain (D) is connected to the ground (VSS) via the element 91 such as an N-type MOS transistor. The

As shown in FIG. 6, parasitic diodes Dp1 and Dp2 are formed between the source (S) and drain (D) and the bulk (N well) in the P-type MOS transistor Qp, respectively. The parasitic diodes Dp1 and Dp2 become conductive when the source (S) and the drain (D) have a higher voltage than the bulk (N well).
A parasitic diode Dp3 is also formed between the bulk (N well) of the P-type MOS transistor Qp and the P-type substrate. The parasitic diode Dp3 becomes conductive when the P-type substrate has a higher voltage than the bulk (N well) of the P-type MOS transistor Qp.

  In general, the bulk (N well) voltage Vbk of the P-type MOS transistor Qp is equal to the power supply voltage VDD. In this case, when the power supply voltage VDD becomes lower than the ground potential VSS as shown by a dotted line in FIG. There is a possibility that a current flows through 91 and the parasitic diode Dp2. On the other hand, in the semiconductor integrated circuit device 5 shown in FIG. 2, since the bulk (N well) voltage Vbk is equal to the selection voltage VBULK, the cathode side of the parasitic diodes Dp1, Dp2, Dp3 becomes the highest voltage. No current flows through the parasitic diode.

  In the semiconductor integrated circuit device 5 shown in FIG. 2, the internal logic circuit may be configured so that the high level voltage of the logic signal becomes a voltage based on the selection voltage VBULK. For example, the logic circuit included in the semiconductor integrated circuit device 5 may be supplied with the selection voltage VBULK instead of the power supply voltage VDD as a high level voltage. Thereby, even if the power supply voltage VDD becomes lower than the ground potential VSS, the selection voltage VBULK does not become lower than the ground potential VSS. Therefore, the P-type MOS transistor Qp that outputs a high level voltage has In the abnormal state, no current flows in the opposite direction to that in the normal state.

  In this case, if the determination circuits 20 and 30 determine that the state is abnormal (when both of the determination signals Sc1 and Sc2 are “0”), the internal logic circuit is configured to output a high-level logic signal. It may be. As a result, the highest voltage (select voltage VBULK) is applied to the gate voltage Vg of the P-type MOS transistor Qp in the logic circuit in the abnormal state, and the channel of the P-type MOS transistor Qp is turned off. No current flows through the channel of the P-type MOS transistor Qp.

  Next, the abnormal state notification operation will be described.

[When power supply voltage VDD is not within the normal range]
When the power supply voltage VDD is not within the normal range, the determination signal Sc1 of the determination circuit 20 is “0” and the control signal S40 of the control signal output circuit 40 is “0”, so that the output impedance of the signal circuit 10 is high. It becomes an impedance state. Then, no current flows through the signal line connected to the signal terminal T3, and the voltage at the signal terminal T23 of the device 2 rises to the power supply voltage by the pull-up resistor 4 and enters the error range. Is done.

[When signal voltage VSIG is higher than power supply voltage VDD or lower than ground potential VSS]
When the signal voltage VSIG is higher than the power supply voltage VDD or lower than the ground potential VSS, the determination signal Sc2 of the determination circuit 30 is “0” and the control signal S40 is “0”, so that the output impedance of the signal circuit 10 is It becomes a high impedance state. As a result, the voltage at the signal terminal T23 of the device 2 falls within the error range as described above, so that the device 2 is notified of the abnormal state.

[When the signal line is short-circuited with the power line]
When the signal line is short-circuited with the power supply line, the voltage of the signal terminal T23 of the device 2 becomes equal to the power supply voltage VDD and enters the error range, so that the device 2 is notified of the abnormal state.

[When the signal line is shorted to the ground line]
When the signal line is short-circuited with the ground line, the voltage of the signal terminal T23 of the device 2 becomes equal to the ground potential VSS and enters the error range, so that the device 2 is notified of the abnormal state.

[When the power line is disconnected]
Since the power supply terminal T1 is connected to the ground terminal T2 via the resistors (R1 to R5) of the voltage dividing circuit 21, when the power supply line is disconnected, the voltage of the power supply terminal T1 (power supply voltage VDD) is the ground terminal. It becomes equal to the voltage of T2 (ground potential VSS). On the other hand, since the signal terminal T3 is connected to the power supply line on the device 2 side via the pull-up resistor 4 in the device 2, the voltage (signal voltage VSIG) of the signal terminal T3 is higher than the ground potential VSS. Accordingly, since the signal voltage VSIG becomes higher than the power supply voltage VDD, the determination circuit 30 outputs “0” as the determination signal Sc2 indicating an abnormal state.
Further, since the power supply voltage VDD becomes equal to the ground potential VSS, the power supply voltage VDD becomes lower than the lower limit of the normal range, so that the determination circuit 30 also outputs “0” as the determination signal Sc1 indicating an abnormal state.

  Since the determination signals Sc1 and Sc2 are “0”, the control signal S40 is also “0”, and the output impedance of the signal circuit 10 is in a high impedance state. As a result, almost no current flows through the signal line connected to the signal terminal T3, and the voltage of the signal terminal T23 of the device 2 rises to the power supply voltage by the pull-up resistor 4 and enters the error range. The status is notified.

  When the signal terminal T23 of the device 2 is not connected to the power supply line by the pull-up resistor 4, but is connected to the ground line by the pull-down resistor, the power supply to the semiconductor integrated circuit device 5 due to the disconnection of the power supply line. Supply is cut off. In this case, since no current flows through the entire circuit of the semiconductor integrated circuit device 5 and no current can flow from the signal circuit 10 to the pull-down resistor, the voltage at the signal terminal T23 of the device 2 becomes equal to the ground level. Therefore, since the voltage at the signal terminal T23 of the device 2 is in the error range, the device 2 is notified of the abnormal state.

[When the ground wire is disconnected]
Since the signal terminal T3 is connected to the power supply line on the device 2 side via the pull-up resistor 4 in the device 2, the power supply to the semiconductor integrated circuit device 5 is cut off if the ground line is disconnected. In this case, since no current flows through the entire circuit of the semiconductor integrated circuit device 5 and current cannot flow from the power supply line of the device 2 to the signal circuit 10 via the pull-up resistor 4, the voltage at the signal terminal T23 of the device 2 Becomes equal to the power supply voltage. Therefore, since the voltage at the signal terminal T23 of the device 2 is in the error range, the device 2 is notified of the abnormal state.

When the signal terminal T23 of the device 2 is not connected to the power supply line by the pull-up resistor 4 and is connected to the ground line by the pull-down resistor, the signal terminal T23 on the device 2 side is connected from the signal circuit 10 through the pull-down resistor. Since current flows through the ground line, the voltage of the signal terminal T3 (signal voltage VSIG) is lower than the voltage of the power supply terminal T1 (power supply voltage VDD). On the other hand, since the ground terminal T2 is connected to the power supply terminal T1 through the resistors (R1 to R5) of the voltage dividing circuit 21, when the ground line is disconnected, the voltage (ground potential VSS) of the ground terminal T2 is It becomes equal to the voltage of the power supply terminal T1 (power supply voltage VDD). Accordingly, since the signal voltage VSIG becomes lower than the ground potential VSS, the determination circuit 30 outputs “0” as the determination signal Sc2 indicating an abnormal state.
Further, since the power supply voltage VDD becomes equal to the ground potential VSS, the power supply voltage VDD becomes lower than the lower limit of the normal range, so that the determination circuit 30 also outputs “0” as the determination signal Sc1 indicating an abnormal state.

  Since the determination signals Sc1 and Sc2 are “0”, the control signal S40 is also “0”, and the output impedance of the signal circuit 10 is in a high impedance state. As a result, almost no current flows through the signal line connected to the signal terminal T3, and the voltage at the signal terminal T23 of the device 2 is lowered to the ground level by the pull-down resistor and enters the error range. Be notified.

  As described above, according to the present embodiment, the highest voltage among the voltage (VDD) of the power supply terminal T1, the voltage (VSS) of the ground terminal T2, and the voltage (VSIG) of the signal terminal T3 is the selection voltage VBULK. The voltage is selected by the voltage selection circuit 51, and the selection voltage VBULK is applied to the bulk of the P-type MOS transistor included in the entire circuit. As a result, even when the relative voltage level relationship at these terminals becomes abnormal due to misconnection of wiring, etc., current does not flow through the parasitic diode formed in the bulk of the P-type MOS transistor. The current flowing into the semiconductor integrated circuit device 5 from these terminals can be suppressed to protect the internal circuit.

  Further, according to the present embodiment, when the power supply voltage VDD is out of the predetermined normal range, or when the signal voltage VSIG is out of the normal range higher than the ground potential VSS and lower than the power supply voltage VDD, the signal circuit 10 Becomes the high impedance state. Therefore, when an abnormal state such as erroneous wiring, disconnection, or short circuit occurs, the external device 2 can be notified of the occurrence of the abnormal state.

  A modification of the semiconductor integrated circuit device 5 according to the first embodiment will be described with reference to FIG.

  In the semiconductor integrated circuit device 5 shown in FIG. 2, one end of the voltage dividing circuit 21 is connected to the power supply terminal T1, but in the semiconductor integrated circuit device 5 shown in FIG. 7, one end of the voltage dividing circuit 21 is connected to the power supply terminal T1. Instead, it is connected to the control terminal T4. A plurality of resistors (R1 to R5) included in the voltage dividing circuit 21 are connected in series between the control terminal T4 and the ground terminal T2.

  When the power supply voltage VDD is supplied to the control terminal T4, the operation of the semiconductor integrated circuit device 5 shown in FIG. 7 is the same as that of the semiconductor integrated circuit device 5 shown in FIG. In a normal use state, the power supply voltage VDD is supplied to the control terminal T4.

  On the other hand, when the ground potential VSS is supplied to the control terminal T4 or when the control terminal T4 is opened, the detection voltages Vs1 to Vs4 of the voltage dividing circuit 21 are all zero (ground potential VSS). Therefore, the determination circuit 20 determines that the state is abnormal, the control signal S40 becomes “0”, and the output impedance of the signal circuit 10 becomes a high impedance state. Further, in the semiconductor integrated circuit device 5 shown in FIG. 7, when the control signal S40 becomes “0” (when it is determined that the determination circuit 20 or 30 is in an abnormal state), dynamic operations such as clock oscillation are stopped. The logic circuit is configured as described above. Therefore, by supplying the ground potential VSS from an external device to the control terminal T4 (or making the control terminal T4 open), the semiconductor integrated circuit device 5 can be put into a standby state with low current consumption. In addition, since the dynamic operation of the semiconductor integrated circuit device 5 is stopped, it is possible to perform static current measurement (IDDQ test) which is one of the circuit element evaluation methods in this standby state.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.
FIG. 8 is a diagram illustrating an example of the configuration of the semiconductor integrated circuit device 5 according to the second embodiment. The semiconductor integrated circuit device 5 shown in FIG. 8 has the same configuration as that of the semiconductor integrated circuit device 5 shown in FIG. 2, and includes a voltage selection circuit 52, a regulator circuit 60, an internal circuit 70, and level shift circuits 71 and 80. And have.
The voltage selection circuit 52 is an example of a second voltage selection circuit in the present invention.
The regulator circuit 60 is an example of a regulator circuit in the present invention.
The internal circuit 70 is an example of an internal circuit in the present invention.

  The voltage selection circuit 52 selects a higher voltage from the ground potential VSS and the power supply voltage VDD and outputs it as the selection voltage VBULK2. The voltage selection circuit 52 can be configured using, for example, two diodes whose cathodes are commonly connected, similarly to the voltage selection circuit 51 shown in FIG.

  The regulator circuit 60 converts the power supply voltage VDD input at the power supply terminal T1 into an internal power supply voltage VDD2 of a predetermined level and supplies it to the internal circuit 70. The regulator circuit 60 may include a protection circuit that prevents current from flowing in the reverse direction from the output to the input when the power supply voltage VDD is lower than the ground potential VSS. Thereby, since the internal power supply voltage VDD2 does not become lower than the ground potential VSS, it is possible to prevent a reverse abnormal power supply current from flowing due to the negative power supply voltage being applied to the internal circuit 70.

  The internal circuit 70 is a circuit that operates based on the internal power supply voltage VDD2, and includes a logic circuit such as a CPU, for example. The internal circuit 70 includes a circuit for recording determination signals Sc1 and Sc2 input via the level shift circuit 71.

  The level shift circuit 80 is a circuit that changes the high level voltage of the determination signal Sc1 output from the determination circuit 20 and inputs it to the control signal output circuit 40A.

  In the semiconductor integrated circuit device 5 shown in FIG. 8, the selection voltage VBULK2 of the voltage selection circuit 52 is supplied as a power supply voltage to the determination circuit 20 and the regulator circuit 60, and the bulk of the P-type MOS transistors included in these circuits The selection voltage VBULK2 is also applied. On the other hand, in the signal circuit 10, the determination circuit 30, and the control signal output circuit 40A, the selection voltage of the voltage selection circuit 51 is used as the power supply voltage and the bulk voltage of the P-type MOS transistor, as in the semiconductor integrated circuit device 5 shown in FIG. VBULK is supplied. Therefore, the high level voltage of the determination signal Sc1 is the selection voltage VBULK2, and the high level voltage of the control signal output circuit 40A is the selection voltage VBULK, and the signal levels of both are different. Therefore, the level shift circuit 80 that converts the signal level of the determination signal Sc1 is required.

  FIG. 9 is a diagram illustrating an example of the level shift circuit 80. The level shift circuit 80 shown in FIG. 9 has an N-type MOS transistor Qn1 and resistors R10 and R11. The ground potential VSS is input to the source and bulk of the MOS transistor Qn1, the selection voltage VBULK is input to the drain via the resistor R11, and the determination signal Sc1 is input to the gate. Resistor R10 is connected between the gate and source of MOS transistor Qn1. At the drain of the MOS transistor Q, the level-shifted determination signal Sc1A is output.

  In the level shift circuit 80 shown in FIG. 9, the determination signal Sc1A after the level shift is logically inverted with respect to the determination signal Sc1 before the level shift. That is, when the determination signal Sc1 is at a high level (VBULK2), the determination signal Sc1A is at a low level (VSS), and when the determination signal Sc1 is at a low level (VSS), the determination signal Sc1A is at a high level (VBULK). Therefore, the control signal output circuit 40A in FIG. 8 calculates a logical product of the result of logical inversion of the determination signal Sc1A and the determination signal Sc2, and the control signal S40 having the same logical level as the control signal output circuit 40 in FIG. Is output.

  The level shift circuit 71 converts the determination signals Sc1 and Sc2 having different signal levels into the signal level of the internal power supply voltage VDD2 as described above and inputs the signal to the internal circuit 70. The level shift circuit 71 can be configured using an N-type MOS transistor, for example, similarly to the level shift circuit 80 shown in FIG.

  According to the semiconductor integrated circuit device 5 having the above-described configuration, the selection voltage VBULK2, which is the higher of the power supply voltage VDD or the ground potential VSS, is applied to the bulk of the P-type MOS transistor configuring the regulator circuit 60. . If the selection voltage VBULK of the voltage selection circuit 51 is applied to the bulk of the P-type MOS transistor of the regulator circuit 60, the bulk of the P-type MOS transistor becomes higher than the power supply voltage VDD when the signal voltage VSIG is the highest voltage. In this case, the threshold voltage of the P-type MOS transistor may change due to the substrate bias effect, and the internal power supply voltage VDD2 output from the regulator circuit 60 may decrease. When the internal power supply voltage VDD2 greatly decreases, an unstable phenomenon such as the operation of a logic circuit such as a CPU being reset in the internal circuit 70 occurs. By applying the selection voltage VBULK2 to the bulk of the P-type MOS transistor of the regulator circuit 60, the unstable phenomenon of the internal circuit 70 due to the substrate bias effect of the P-type MOS transistor can be made difficult to occur.

  Further, according to the semiconductor integrated circuit device 5 having the above-described configuration, the internal circuit 70 can be easily operated even in an abnormal state where the signal voltage VSIG is higher than the power supply voltage VDD. It becomes possible to record Sc2. By recording such an abnormal state, verification and reliability of the system including the sensor module 1 can be increased.

  In addition, this invention is not limited only to embodiment mentioned above, Various modifications are included.

  For example, a determination circuit that determines whether or not the internal power supply voltage VDD2 of the regulator circuit 60 has reached a specified voltage is provided, and a determination signal indicating that the voltage has not reached the specified voltage is output from the determination circuit May output the control signal S40 from the control signal output circuit 40 so that the output impedance of the signal circuit 10 is in a high impedance state. Alternatively, a determination circuit for determining whether or not the operation is started is provided based on a reset signal of the CPU or logic circuit included in the internal circuit 70 to determine that the CPU or the logic circuit is in a state before the operation is started. When a signal is output from the determination circuit, the control signal S40 may be output from the control signal output circuit 40 so that the output impedance of the signal circuit 10 is in a high impedance state. As a result, the output impedance of the signal circuit 10 is in a high impedance state until an operation of the CPU or logic circuit is started, for example, at the time of power activation, and an unnecessary signal is not output from the signal terminal T3. Stability can be further improved.

  In the above-described embodiment, an example is given in which the signal circuit 10 is a circuit that outputs a sensing signal, but the present invention is not limited to this. In another embodiment of the present invention, the signal circuit 10 may include a circuit that inputs a signal from the device 2 at the signal terminal T3. In this case, the signal circuit 10 sets the input impedance to a high impedance state according to the control signal S40 of the control signal output circuit 40. When the input impedance of the signal circuit 10 is in a high impedance state, the voltage of the signal line falls within an error range near the power supply voltage VDD or near the ground potential VSS due to the pull-up resistor or pull-down resistor provided on the device 2 side. The status is notified to the device 2.

  DESCRIPTION OF SYMBOLS 1 ... Sensor module, 2 ... Apparatus, 3 ... Cable harness, 4 ... Pull-up resistor, 5 ... Semiconductor integrated circuit device, 6 ... Sensor part, 10 ... Signal circuit, 20, 30 ... Judgment circuit, 21 ... Voltage divider circuit, DESCRIPTION OF SYMBOLS 22 ... Reference voltage generation circuit, 23 ... Comparison circuit, 231, 232 ... Hysteresis comparator, 24 ... Determination signal output circuit, 40, 40A ... Control signal output circuit, 51, 52 ... Voltage selection circuit, 60 ... Regulator circuit, 70 ... Internal circuit 71, 80 ... Level shift circuit, T1 ... Power supply terminal, T2 ... Ground terminal, T3 ... Signal terminal, T4 ... Control terminal, R1-R5 ... Resistance.

Claims (10)

A ground terminal connected to the ground potential;
A power supply terminal for inputting power supply voltage;
A signal terminal;
A signal circuit that outputs or inputs a signal at the signal terminal, and sets an output impedance or input impedance at the signal terminal to a high impedance state according to a control signal;
A first determination circuit for determining whether or not the voltage of the power supply terminal with respect to the voltage of the ground terminal is within a normal range;
A second determination circuit that determines whether the voltage of the signal terminal with respect to the voltage of the ground terminal is within a normal range that is lower than the voltage of the power supply terminal and higher than the voltage of the ground terminal;
When the first determination circuit determines that the voltage of the power supply terminal is not within the normal range, or when the second determination circuit determines that the voltage of the signal terminal is not within the normal range, A control signal output circuit for outputting the control signal for setting the output impedance or input impedance at the signal terminal to a high impedance state;
A first voltage selection circuit that selects the highest voltage among the voltage of the ground terminal, the voltage of the power supply terminal, and the voltage of the signal terminal;
The first voltage selection circuit applies the selected voltage to the bulk of at least some of the P-type MOS transistors included in the entire circuit.
A semiconductor integrated circuit device. The first voltage selection circuit supplies the selected voltage as a power supply voltage to the signal circuit, the first determination circuit, the second determination circuit, and the control signal output circuit. A semiconductor integrated circuit device according to 1. A ground terminal connected to the ground potential;
A power supply terminal for inputting power supply voltage;
A signal terminal;
A signal circuit that outputs or inputs a signal at the signal terminal, and sets an output impedance or input impedance at the signal terminal to a high impedance state according to a control signal;
A first determination circuit for determining whether or not the voltage of the power supply terminal with respect to the voltage of the ground terminal is within a normal range;
A second determination circuit that determines whether the voltage of the signal terminal with respect to the voltage of the ground terminal is within a normal range that is lower than the voltage of the power supply terminal and higher than the voltage of the ground terminal;
When the first determination circuit determines that the voltage of the power supply terminal is not within the normal range, or when the second determination circuit determines that the voltage of the signal terminal is not within the normal range, A control signal output circuit for outputting the control signal for setting the output impedance or input impedance at the signal terminal to a high impedance state;
A first voltage selection circuit that selects the highest voltage among the voltage of the ground terminal, the voltage of the power supply terminal, and the voltage of the signal terminal;
A second voltage selection circuit for selecting a higher voltage among the voltage of the ground terminal and the voltage of the power supply terminal;
A regulator circuit that converts a power supply voltage input at the power supply terminal into an internal power supply voltage and supplies the internal power supply voltage, and
The first voltage selection circuit applies the selected voltage to a bulk of a P-type MOS transistor included in the signal circuit, the second determination circuit, and the control signal output circuit,
The semiconductor integrated circuit device, wherein the second voltage selection circuit applies the selected voltage to a bulk of a P-type MOS transistor included in the first determination circuit and the regulator circuit. The first voltage selection circuit supplies the selected voltage as a power supply voltage to the signal circuit, the second determination circuit, and the control signal output circuit,
The semiconductor integrated circuit device according to claim 3, wherein the second voltage selection circuit supplies the selected voltage as a power supply voltage to the first determination circuit. The internal circuit includes a circuit that records a signal indicating a determination result output from at least one of the first determination circuit, the second determination circuit, and the control signal output circuit. 5. The semiconductor integrated circuit device according to 3 or 4. The first determination circuit includes:
A voltage dividing circuit including a plurality of resistors connected in series between the ground terminal and the power supply terminal;
A reference voltage generating circuit for generating a constant reference voltage with respect to the voltage of the ground terminal;
A comparison circuit for comparing a plurality of detection voltages divided by different voltage dividing ratios in the voltage dividing circuit with the reference voltage, respectively;
And a determination signal output circuit that outputs a first determination signal indicating a determination result of whether or not the voltage of the power supply terminal with respect to the voltage of the ground terminal is within a normal range based on the comparison result of the comparison circuit. The semiconductor integrated circuit device according to claim 1, wherein: A power supply voltage common to the power supply terminal is input during normal operation, and the ground potential is input during non-normal operation or a control terminal that is open.
The plurality of resistors included in the voltage dividing circuit are connected in series between the ground terminal and the control terminal instead of being connected in series between the ground terminal and the power supply terminal. 7. The semiconductor integrated circuit device according to claim 6, wherein: The reference voltage generation circuit outputs a status signal indicating whether or not the reference voltage is generated;
The comparison circuit, when the status signal indicating that the reference voltage is not generated is output from the reference voltage generation circuit, the first determination indicating that the voltage of the power supply terminal is within a normal range 8. The semiconductor integrated circuit device according to claim 6, wherein output of a signal is suppressed. The comparison circuit is
When the first detection voltage in the plurality of detection voltages changes from a state lower than the reference voltage to a higher state, a signal indicating that the voltage of the power supply terminal is higher than the upper limit of the normal range is output, and the plurality of detection voltages A first hysteresis comparator that outputs a signal indicating that the voltage at the power supply terminal is lower than the upper limit of the normal range when a second detection voltage higher than the first detection voltage changes from a higher state to a lower state than the reference voltage in FIG. When,
When a third detection voltage higher than the second detection voltage in the plurality of detection voltages changes from a state lower than the reference voltage to a higher state, a signal indicating that the voltage of the power supply terminal is higher than the lower limit of the normal range is output. When the fourth detection voltage higher than the third detection voltage in the plurality of detection voltages changes from a state higher than the reference voltage to a lower state, a signal indicating that the voltage at the power supply terminal is lower than the lower limit of the normal range A second hysteresis comparator that outputs
The determination signal output circuit outputs a signal indicating that the voltage of the power supply terminal is higher than the upper limit of the normal range in the first hysteresis comparator, or the voltage of the power supply terminal in the second hysteresis comparator. The first determination signal indicating that the voltage of the power supply terminal is not within the normal range is output when a signal indicating that the voltage is lower than the lower limit of the normal range is output. The semiconductor integrated circuit device according to any one of the above. A sensor unit;
10. A sensor module comprising: the semiconductor integrated circuit device according to claim 1, wherein a signal corresponding to a sensing result of the sensor unit is output from the signal terminal.