JP6223083B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that performs a predetermined game.

  As a gaming machine, when a game medium such as a game ball is launched into a game area by a launching device, and the game medium wins a prize area such as a prize opening provided in the game area, a prize game medium such as a predetermined number of prize balls is obtained. Some are paid out to players. Furthermore, a display device capable of variably displaying identification information (also referred to as “variation”) when a game medium wins in a predetermined winning area (start condition is established) is provided, and display of variable display of identification information on the display device There is a configuration in which a game value advantageous to a player is given (for example, controlled to a jackpot game state) when the result is a special game result (a jackpot symbol).

  As such a gaming machine, there is one in which a plurality of buffers are provided as image data storage means, and the buffers for storing image data are sequentially switched. For example, a VDP (Video Display Processor) including a display control unit can draw (store) image data to the effect control CPU when the output of image data for one frame to the effect display device is completed. A V blank interrupt signal indicating the start of the period is output. The effect control CPU instructs the VDP to switch the buffer that outputs the image data at the timing when the V blank interrupt signal is input (see, for example, Patent Document 1). Alternatively, the effect control CPU instructs the VDP to switch the buffer to which the image data is to be output prior to the storage of the image data and the image display based on the image data after the timing for starting the generation of the image data ( For example, see Patent Document 2). The VDP confirms whether or not there is a buffer switching instruction in synchronization with a predetermined period (for example, a frame period), and when there is a buffer switching instruction, switches the buffer that outputs image data according to the instruction.

JP 2012-143598 A JP 2009-201631 A

  However, for example, when the CPU for effect control executes other processing such as timer interruption processing in preference to the processing for buffer switching instruction, the buffer switching instruction confirms whether there is a switching instruction in VDP. As a result, there may be a problem in switching the buffer to which image data is to be output.

  FIG. 29 is a diagram for explaining a problem of switching a buffer to which image data is to be output. In FIG. 29, an effect display device is provided, and image data corresponding to an image for one frame displayed on the display device is alternately drawn in the buffer A and the buffer B. Further, the image output to the effect display device is performed. As a process, the process in which the same image data is output twice from the buffer A and the process in which the same image data is output twice from the buffer B are alternately repeated. 29A is a timing chart showing output of image data to the effect display device, V sync (start timing of the frame period) and V blank of the effect display device, and FIG. 29B shows VDP. FIG. 29C is a timing chart showing confirmation of a buffer (swap setting confirmation) in which image data is to be output, and FIG. Swap configuration and a timing chart showing the drawing to the buffer by the presentation control CPU and VDP. Specifically, the display control unit including the VDP or the like starts the period during which an image can be drawn to the effect control CPU when the output of the image data for one frame to the effect display device is completed. The V blank interrupt signal shown is output. The effect control CPU sets the switching of the buffer to which the image data is to be output every time the V blank interrupt signal is input twice, in other words, every time twice the frame period of the effect display device ( (Swap setting) is performed, and then the display control unit is controlled to control the drawing of the image data in the buffer. Thus, every time the V blank interrupt signal is input twice to the effect control CPU, the swap setting is performed, and the buffer for outputting image data is set in the buffer A and the buffer B is set. And the process of drawing image data in the buffer A and the process of drawing image data in the buffer B are alternately repeated.

  On the other hand, as shown in FIG. 29 (b), the display control unit outputs the V blank interrupt signal twice, in other words, every predetermined time for every time twice the frame period of the effect display device. After performing this standby, the swap setting is confirmed by the above-described effect control CPU. Thereby, the display control unit recognizes whether the buffer to which the image data is to be output is the buffer A or the buffer B. The display control unit recognizes the buffer A or the buffer that is recognized as the buffer to which the image data is to be output in the confirmation of the previous swap setting every time the timing of the V sync that is the start timing of the frame period of the effect display device arrives. Processing for outputting image data from B to the effect display device is performed. Here, the process of outputting the same image data from the buffer A to the effect display device is performed twice continuously, and then the process of outputting the same image data from the buffer B to the effect display device is performed twice. Done.

  When such processing is performed, as shown in FIG. 29C, while the swap setting indicates output of image data from the buffer B to the effect display device (buffer A off, buffer B on), Assume that the effect control CPU generates a switch check interrupt while waiting for the V blank, and the effect control CPU preferentially performs timer interrupt processing corresponding to the switch check interrupt over other processing. In this case, there is a possibility that the VDP confirms the swap setting before the effect control CPU performs a new swap setting (buffer A on, buffer B off). If the swap setting is confirmed before the new swap setting as described above, the display control unit in the VDP keeps the swap setting on the buffer A off and the buffer B on. In spite of the fact that the image data should be output to the effect display device, as shown in FIG. 29A, the image data is continuously output from the buffer B to the effect display device.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of appropriately performing image display when a plurality of image data storage means are used.

(1) In order to achieve the above object, a gaming machine according to the first aspect of the present application is:
Gaming machine performing Yu technique (e.g., pachinko machine 1) a pre Ki遊 Technical display Update to display based images on a predetermined frame cycle related (e.g., the main effect display device 9, the sub-director Display devices 11a, 11b, 11c, 11d), and a plurality of image data storage means (for example, a buffer A and a buffer B in the VRAM area) for temporarily storing image data of an image displayed on the display device; presentation control means for controlling the presentation before Ki遊 technique (e.g., effect control for CPU 86) and, said display control means in response to control by the presentation control means performs display control of the display device (e.g., VDP262) and the The display control means corresponds to a signal synchronized with a frame period of the display device (for example, sub-effect display devices 11a, 11b, 11c, and 11d). (Blank interrupt signal) at a predetermined timing after output to the effect control means (for example, timing when the standby time has elapsed from the output of the V blank interrupt signal corresponding to the sub effect display devices 11a, 11b, 11c, and 11d). Confirm storage location designation information (for example, swap setting information for designating an output buffer of image data) for designating image data storage means to output the image data among the plurality of image data storage means (for example, , Confirmation of the swap setting in step S723 of FIG. 24 by the display control unit 216 in the VDP 262), and switching of image data storage means for outputting the image data according to the contents of the storage destination designation information (for example, display in the VDP 262) The output of the image data in steps S853 and S854 of FIG. The effect control means executes a drawing process for storing the image data in the image data storage means in accordance with a signal synchronized with the frame period of the display device (for example, the step of FIG. In step S712, the drawing instruction is stored in the system register 202), and the storage destination designation information is set after the drawing process is completed and before the predetermined timing (for example, the step of FIG. (Swap setting information is stored in the system register 202 in the swap setting in S715).

According to such a configuration, the effect control unit executes the drawing process according to the signal synchronized with the frame period of the display device output by the display control unit, and after the drawing process is finished, at a predetermined timing. before, it sets the storage destination specifying information that specifies the image data storage means to be output image data, the display control means, said predetermined after the output of the signal synchronized with the frame period of the display device The storage location designation information is confirmed at the timing, and the image data storage means for outputting the image data is switched according to the contents of the storage location designation information. As a result, it is possible to secure a grace period from the setting of the storage location designation information by the effect control means to the confirmation of the storage location setting information by the display control means, and there is a process that has priority over the drawing process. Even if the setting of the specified information is delayed, the display control means does not confirm the storage destination setting information before the setting of the storage destination specifying information by the effect control means, and the image data is output. It is possible to prevent an error from occurring in the image data storage means.

  (2) In the gaming machine of the above (1), the effect control means is a V blank interrupt corresponding to a predetermined signal (for example, sub-effect display devices 11a, 11b, 11c, 11d) output by the display control means. The storage location designation information is set according to the signal) (for example, swap by the effect control CPU 86 according to the input of the V blank interrupt signal corresponding to the sub effect display devices 11a, 11b, 11c, and 11d from the VDP 262) (Storing swap setting information in the system register 202 in setting).

  According to such a configuration, even when a predetermined signal is input from the display control unit, the storage destination designation information is set by the effect control unit. Therefore, the storage destination designation information is set after the drawing process is completed. Even when the operation is not performed, the setting can be appropriately performed.

  (3) In the gaming machine of the above (2), the effect control means executes an interrupt process (for example, by the effect control CPU 86) that is executed with priority over the drawing process and is generated by a timer interrupt that occurs periodically. Switch check interrupt processing), and a period from the output of the predetermined signal by the display control means until the display control means confirms the storage location designation information (for example, sub-effect display devices 11a, 11b by VDP262) , 11c, 11d until the confirmation of the swap setting in step S723 in FIG. 24 by the display control unit 216 in the VDP 262 from the output of the V blank interrupt signal corresponding to 11c, 11d), the effect control means requires the interrupt processing It may be longer than the period.

  According to such a configuration, even if an interruption process occurs in the effect control means and the setting of the storage location designation information is delayed, the display control means is set after the setting of the storage location designation information by the effect control means. Since the storage destination setting information can be confirmed, it is possible to prevent an error from occurring in the image data storage unit that outputs the image data.

  (4) In the gaming machine according to any one of (1) to (3), the display control means outputs the content of the storage location designation information every time a signal synchronized with the frame period of the display device is output a plurality of times. The image data storage means for outputting the image data is switched accordingly (for example, the second sub-effect display devices 11a, 11b, 11c from the start of the latest drawing in step S721 of FIG. 24 by the display control unit 216 in the VDP 262) , 11d when it is determined that a V blank interrupt signal corresponding to 11d has been input, confirmation of the swap setting in step S723 in FIG. 24 and image data output processing in FIG. 27), the effect control means executes the drawing processing When the number of times that a signal synchronized with the frame period of the display device has been input reaches one less than the plurality of times, The storage destination designation information is set to the contents for switching the image data storage means for outputting the image data (for example, the first sub-effect display devices 11a and 11b after the drawing control is started in step S713 of FIG. 23 by the effect control CPU 86). , 11c, 11d, the swap setting in step S715 when it is determined that the V blank interrupt signal corresponding to the input has been input.

  According to such a configuration, the image data storage means for outputting the image data can be appropriately switched even when the storage of the image data is longer than the period of the signal synchronized with the frame period of the display device.

  (5) The gaming machine according to any one of (1) to (4), wherein the display device includes a plurality of display devices (for example, main effect display device 9, sub effect display devices 11a, 11b, 11c, and 11d), and the display control. The means performs display control of the plurality of display devices in accordance with control by the effect control means, and the effect control means sets the storage location designation information common to the plurality of display devices (for example, swap setting) The information may be common to the main effect display device 9 and the sub effect display devices 11a, 11b, 11c, and 11d).

  According to such a configuration, even when a plurality of display devices are provided, it is possible to appropriately switch the image data storage unit that outputs image data while synchronizing the display devices.

  (6) In the gaming machine of the above (5), the display control means performs display control of the plurality of display devices in synchronization with the predetermined frame period (for example, the VDP 262 has sub-effect display devices 11a, 11b, The image data output process of FIG. 27 may be performed in synchronization with the frame periods of 11c and 11d).

  According to such a configuration, even when a plurality of display devices are provided, display control can be performed while synchronizing the display devices.

1 is a front view showing a pachinko gaming machine according to an embodiment of the present invention. (A) is a front view showing each effect display device when the main effect display device and the sub effect display device are in a non-overlapping state, and an AA cross-sectional view in the front view, (b) It is the front view which shows each effect display apparatus when a main effect display apparatus and a sub effect display apparatus are in a superimposition state, and BB sectional drawing in this front view. It is a block diagram which shows the circuit structural example of a pachinko gaming machine. It is a block diagram showing a circuit configuration example in the effect control board. It is a block diagram which shows the circuit structural example in a signal separation board | substrate. It is a figure which shows the VRAM area | region in SDRAM. It is a figure which shows each drawing area of each production | presentation display apparatus and main frame buffer when a main production | presentation display device and a sub production | presentation display device are in a superposition state. It is a figure showing each drawing display area of each effect display device and the main frame buffer when the main effect display device and the sub effect display device are in a non-superimposed state. (A) is a figure which shows the state which drawn the main image in the main frame buffer, (b) is a figure which shows the state which drawn the sub image in the sub-frame buffer. (A) is a figure which shows the state which replicated the sub image to the main frame buffer, (b) is a figure which shows the state which reproduced the sub image in the sub frame buffer again. It is a figure which shows the state which arrange | positions the structure data of a sub image in a synthesized image storage area. (A) is a figure which shows the separation process of the image data in a signal separation board | substrate, (b) is a figure which shows the pixel size of the image data in a signal separation board | substrate. It is a figure which shows the drawing order in the case of performing a cooperation effect. It is a figure which shows the drawing order in the case of not performing a cooperation effect. It is a figure which shows the drawing order in the case of performing the cooperation production as a modification. (A) is a front view which shows the sub production | presentation display apparatus in Example 2, (b) is a figure which shows the pixel size of each image data. (A) is a figure which shows the separation process of the image data in the signal separation board | substrate in Example 2, (b) is a figure which shows the pixel size of the image data in a signal separation board | substrate. (A) is a timing chart which shows the dot clock of the transmission circuit of a signal separation board, (b) is a timing chart which shows the dot clock of a sub production | presentation display apparatus, (c) is a dot chart of image data. It is a figure for demonstrating a color according to the said timing chart, (d) is a figure for demonstrating the color of the dot of a sub effect display apparatus according to the said timing chart. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows an example of the program of a special symbol process process. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is a flowchart which shows production control process processing. It is a flowchart which shows a swap setting process. It is a flowchart which shows a swap setting confirmation process. It is a flowchart which shows a frame period reset process. It is a flowchart which shows an image data drawing process. It is a flowchart which shows an image data output process. (A) is a timing chart showing output of image data to the sub effect display device, V sync and V blank of the sub effect display device, and (b) is an output of image data to the main effect display device, main It is a timing chart which shows V sink and V blank of an effect display device, (c) is a timing chart which shows swap setting confirmation by VDP, (d) is V blank waiting by an effect control CPU, and swap setting FIG. 10 is a timing chart showing drawing on the buffer by the effect control CPU and the VDP. FIG. It is a timing chart in the conventional pachinko gaming machine, (a) is a timing chart showing output of image data to the effect display device, V sink and V blank of the effect display device, (b) is swap by VDP It is a timing chart which shows a setting check, (c) is a timing chart which shows V blank waiting and swap setting by CPU for effect control, and drawing to the buffer by CPU for effect control and VDP.

  A mode for carrying out a gaming machine according to the present invention will be described below based on examples.

  First, the overall configuration of a pachinko gaming machine that is an example of the gaming machine of the present invention will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. In the following description, the front side (player side) in FIG. 1 will be described as the front side of the pachinko gaming machine 1, and the back side (inward side) will be described as the back side. In addition, the front surface of the pachinko gaming machine 1 in this embodiment is an opposing surface that faces the player when the pachinko gaming machine 1 is viewed from the player side.

  The pachinko gaming machine 1 is mainly configured by an outer frame (not shown) formed in a vertically long rectangular shape and a front frame (not shown) attached to the outer frame so as to be openable and closable. A glass door frame 102 and a lower door frame 103 are provided on the front surface of the front frame so as to be openable and closable around one side.

  As shown in FIG. 1, the upper front portion of the lower door frame 103 attached to the lower side of the glass door frame 102 is a game ball storage unit that can store pachinko balls (hitting balls) as game media (game balls). An upper plate portion 3a having a hitting ball supply tray (also referred to as an upper plate) 3 formed on the upper surface thereof projects toward the front of the pachinko gaming machine 1 (front direction of the pachinko gaming machine 1). Also, below this upper plate portion 3a, an operation lever 600, which will be described later, is pivotally supported, and a lower plate portion 4a (also called a lower plate) 4 is formed on the upper surface. The projecting portion) is projected toward the front of the pachinko gaming machine 1 (front direction of the pachinko gaming machine 1). A hitting operation handle (operation knob) 5 for firing a pachinko ball is provided on the right side.

  The operation lever 600 includes an operation rod that is held by the player, and a trigger switch is provided at a predetermined position of the operation rod (for example, a position where the index finger of the operator is applied when the player holds the operation rod). A trigger button is provided. The trigger button can be operated in a predetermined direction by performing a push / pull operation with a predetermined operation finger (for example, index finger) while the player holds the operation lever of the operation lever 600 with an operation hand (for example, the left hand). What is necessary is just to be comprised. Lever switches 510a to 510d arranged in four directions in order to detect a tilting operation with respect to the operating rod may be provided inside the main body of the lower plate 4a below the operation lever 600.

  In addition, the member that forms the upper plate 3 can be operated by a player to perform a predetermined instruction operation by, for example, pressing a predetermined position on the upper surface of the upper plate 3 main body (for example, above the operation lever 600). An operation button 516 is provided. The operation button 516 may be configured to be able to detect a predetermined instruction operation such as a pressing operation from a player mechanically, electrically, or electromagnetically. A button switch 516a (see FIG. 3) for detecting an operation action of the player performed on the operation button 516 may be provided inside the main body of the upper plate at the installation position of the operation button 516. A pair of left and right speakers 27a and 27b, which will be described later, are disposed on the front left and right sides of the lower door frame 103.

  A transparent game board 6 detachably attached to the front frame 101 is disposed on the back surface of the glass door frame 102. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, a main effect display device 9 including a plurality of variable display areas, each of which displays a decorative pattern for an effect (also referred to as an effect symbol) (also referred to as a variable display), and the main effect display Four sub-effect display devices 11a to 11d smaller than the device 9 are provided on the back side of the game board 6 so that they can be seen through the transparent game board 6 (see FIG. 2). In the following description, the four sub-effect display devices 11a to 11d may be collectively referred to as the sub-effect display device 11.

  As shown in FIG. 2A, the main effect display device 9 and the sub effect display devices 11a to 11d have different display areas and display pixel densities. In the present embodiment, the total number of pixels of the main effect display device 9 is 800 dots in the X-axis direction (horizontal direction) and 600 dots in the Y-axis direction (vertical direction), and each of the sub-effect display devices 11a to 11a. The total number of pixels of 11d is 480 dots in the X-axis direction (horizontal direction) and 234 dots in the Y-axis direction (vertical direction). In the present embodiment, the actual dimensions of the main effect display device 9 are about 12 cm in the X-axis direction (lateral direction) and about 9 cm in the Y-axis direction (vertical direction), and each sub-effect display device 11a. The actual dimensions of ˜11d are about 6 cm in the X-axis direction (lateral direction) and about 3 cm in the Y-axis direction (vertical direction). That is, the main effect display device 9 and the sub effect display devices 11a to 11d have different numbers of pixels per square centimeter.

  In addition, a liquid crystal panel 9 ′ having a large display area (display area) is used for the main effect display device 9, and a small display area (display area) is provided for the sub-effect display devices 11a to 11d. The liquid crystal panels 11a ′ to 11d ′ are used. The main effect display device 9 and the sub effect display devices 11a to 11d are provided with a frame portion so as to surround each display portion.

  Further, as described above, the main effect display device 9 is configured to variably display effect decorative patterns, and the sub effect display devices 11a to 11d are associated with variable display of the main effect display device 9. An effect image is displayed (see FIGS. 7 and 8). In other words, the effect control board 80 to be described later executes an effect of displaying display contents linked to each other by the main effect display device 9 and the sub-effect display devices 11a to 11d.

  The sub-effect display devices 11a to 11d not only display the display contents linked to the display image of the main effect display device 9, but also display individual effect images that are not linked to the display image of the main effect display device 9. (See FIG. 14).

  Further, the main effect display device 9 and the sub effect display devices 11a to 11d are horizontally long displays. In addition, the vertical arrangement of the main effect display device 9 is such that the direction recommended for use when designing the main effect display device 9 (the direction in which the screen is horizontally long), that is, the horizontal line of the display screen is horizontal. Be placed. On the other hand, the vertical orientation of each of the sub-effect display devices 11a to 11d is the direction recommended when the sub-effect display devices 11a to 11d are designed (the orientation in which the screen is horizontally long), that is, the horizontal line of the display screen. It is arranged in a state of being rotated clockwise or counterclockwise with respect to the horizontal, not in a horizontal orientation. That is, the sub-effect display devices 11a to 11d are arranged in a state where the horizontal line of the display screen is rotated by a predetermined angle with respect to the horizontal (a state where the horizontal line is rotated by a predetermined angle about the normal line of the display surface).

  In the present embodiment, the sub-effect display device 11a arranged at the upper left of the main effect display device 9 is arranged by rotating counterclockwise at an angle of 45 ° and arranged at the upper right of the main effect display device 9. The sub-effect display device 11b is rotated at an angle of 45 ° clockwise, and the sub-effect display device 11c arranged at the lower left of the main effect display device 9 is rotated at an angle of 45 ° clockwise. The sub effect display device 11d arranged at the lower right of the main effect display device 9 is arranged to rotate counterclockwise at an angle of 45 °.

  In the present embodiment, the four sub-effect display devices 11 a to 11 d are arranged adjacent to the four corners of the main effect display device 9, and the sub-effect display devices 11 a to 11 d are more than the main effect display device 9. Is also disposed on the front side (see the AA cross-sectional view of FIG. 2A). Furthermore, in this embodiment, four movement motors 59a to 59d (see FIG. 3) for moving the sub effect display devices 11a to 11d are provided on the back side of the sub effect display devices 11a to 11d. ing.

  Further, as shown in FIG. 2A, the sub-effect display devices 11a to 11d and the movement motors 59a to 59d have the same configuration, and therefore, the sub-effect display device 11c and the movement motor 59c will be described as an example. The sub effect display device 11c and the moving motor 59c are connected via a link mechanism 60, and the sub effect display device 11c does not overlap the main effect display device 9 by driving the moving motor 59c. The position of the sub-effect display device 11c is changed between the position (see FIG. 2A) and the superimposed position where the sub-effect display device 11c overlaps the main effect display device 9 (see FIG. 2B). can do. In addition, the arrangement position of each sub production | presentation display apparatus 11a-11d is not only arrange | positioned in a non-superimposition position or a superposition position, but stops each sub production display apparatus 11a-11d in the intermediate position of a non-superimposition position and a superposition position. It can also be made.

  Further, the moving motors 59a to 59d of the present embodiment are stepping motors that operate in synchronization with the pulse power and can accurately control rotation. Then, the production control microcomputer 81 that controls the movement motors 59a to 59d responds to the rotation speed of the movement motors 59a to 59d and the rotation speed based on the pulse power sent to the movement motors 59a to 59d. The movement distances of the sub-effect display devices 11a to 11d can be grasped.

  In this embodiment, driving means for moving the sub-effect display devices 11a to 11d is configured by driving the movement motors 59a to 59d. However, the present invention is not limited to this, and the present invention is not limited thereto. You may comprise the drive means to which the sub production | presentation display apparatuses 11a-11d are moved by driving a cylinder etc. Furthermore, a chain, a belt, or the like may be used to transmit the driving force from the driving means to the sub-effect display devices 11a to 11d. In this embodiment, the sub effect display device 11c and the moving motor 59c are connected via the link mechanism 60. However, the sub effect display devices 11a to 11d and the moving motor are used by using a rack and a pinion. And may be connected to each other.

  In this embodiment, since the transparent game board 6 is used, no opening is provided in front of the main effect display device 9 and the sub effect display devices 11a to 11d. However, when an opaque game board is used. The game board 6 may be provided with an opening for allowing the player to visually recognize the display of the main effect display device 9 and the sub-effect display devices 11a to 11d.

  A special symbol display (special symbol display device) 8 (see FIG. 3) for variably displaying special symbols as a plurality of types of identification information that can identify each of them is provided at predetermined locations on the game board 6. The main effect display device 9 has, for example, three variable display areas (symbol display areas) of “left”, “middle”, and “right”. The main effect display device 9 is a decoration (effect) symbol during the special symbol variation display period by the special symbol display 8, and the variation of the decoration symbol as a plurality of types of identification information that can be distinguished from each other. (Variable) display. The main effect display device 9 and the sub effect display devices 11a to 11d are controlled by devices such as an effect control microcomputer 81 (see FIG. 3) mounted on an effect control board 80 described later.

  The special symbol display 8 is realized by a simple and small display (for example, 7-segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 has a first special symbol display 8a that variably displays the first special symbol as the first identification information, and a second special symbol display that variably displays the second special symbol as the second identification information. A vessel 8b is provided.

  The variable display of the first special symbol is a variable display start condition (for example, after the first start condition, which is a variable display execution condition) is established (for example, a game ball has won a first start port 15a described later). When the number of reserved memories is not 0, the variable display of the first special symbol is not executed and the jackpot game is not executed) When the time (variable display time) elapses, the display result (stop symbol) is derived and displayed. The variable display of the second special symbol is a variable display start condition after a second start condition, which is a variable display execution condition, is satisfied (for example, a game ball has won a second start port 15b described later). (For example, when the number of reserved memories is not 0, the variable display of the second special symbol is not executed, and the big hit game is not executed) is started based on When the variation time (variable display time) elapses, the display result (stop symbol) is derived and displayed. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  As will be described later, the variable display on the first special symbol display 8a and the second special symbol display 8b and the variation (variable) display on the main effect display device 9 are the first special symbol display 8a. In conjunction with the start of variable display on the second special symbol display 8b, and in conjunction with the stop of variable display on the first special symbol display 8a and the second special symbol display 8b. The decorative design variation (variable) display that is identification information in the main effect display device 9 also satisfies the first start condition or the second start condition, which is a variable display execution condition. For example, after a game ball has won a first starting port 15a or a second starting port 15b, which will be described later), a variable display start condition (for example, when the number of reserved memories is not 0 and the first special symbol Is a state in which the variable display of the second special symbol is not executed and the big hit game or the small hit game is not executed), and the variable display time (fluctuation time) is When the time has elapsed, a display result (a stop symbol by a combination of decorative symbols) is derived and displayed.

  Below the main effect display device 9, there is provided a start winning device 15 having a first start port 15a and a second start port 15b as a winning area that can accept a pachinko ball. In the start winning device 15, the first start port 15a is provided in the upper part, and the second start port 15b is provided in the lower part. A pair of movable pieces 13 and 13 are provided on the left and right sides of the second start port 15b in such a manner that an opening / closing operation can be performed. The first start port 15a is open upward and is always in a state where a pachinko ball can enter (accept). On the other hand, the second start port 15b is provided with a structure around the first start port 15a above and the movable pieces 13 and 13 are provided on the left and right, so that the movable pieces 13 and 13 are in a closed state. When the movable pieces 13 and 13 are in an open state, the pachinko ball can enter (accept). Thus, the first start port 15a does not change the easiness of winning, and the second start port 15b changes the easiness of winning according to the opening / closing operation of the movable pieces 13, 13.

  The starting prize-winning device 15 is able to win in the state where the movable pieces 13 and 13 are in the closed state, although it is difficult to win in the second starting port 15b (that is, the pachinko ball has won a prize). It may be configured to be difficult). In addition, the start winning device 15 may be provided with only the first start port 15a that does not change the easiness of winning as a start port, and it is easy to win by opening and closing the movable pieces 13 and 13. Only the second start port 15b whose height changes may be provided.

  The movable pieces 13 and 13 of the start prize-winning device 15 are driven by the solenoid 16 when an opening condition described later is satisfied, so that the movable pieces 13 and 13 are opened from the closed state for a predetermined period and then closed. When the movable pieces 13 and 13 of the start winning device 15 are in the open state, the pachinko ball is easy to win the second start port 15b (easy to start start) and is advantageous to the player (first state). ) On the other hand, when the movable pieces 13 and 13 of the start winning device 15 are in the closed state, the pachinko ball does not win the second start opening 15b (it becomes difficult to start winning), which is a disadvantageous state for the player (second state). State). The winning ball that has entered the first start port 15a is guided to the back of the game board 6 and detected by the first start port switch 14a. The winning ball that has entered the second start port 15b is guided to the back of the game board 6 and detected by the second start port switch 14b.

  The predetermined number of the game board 6 displays four numbers indicating the number of effective winning balls that have entered the first starting port switch 14a or the second starting port switch 14b, that is, the number of reserved memories (also referred to as starting memory or starting winning memory). A special symbol storage memory display 18 (see FIG. 3) is provided. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold memory display 18 increases the stored data in the hold memory by 1 and increases the number of LEDs in the lit state by 1 every time there is a start winning in the first start port 15a or the second start port 15b. Each time the special symbol display 8 starts the variable display, the special symbol storage memory display 18 decreases the storage data of the storage by 1 and decreases the number of LEDs in the lit state by 1 (that is, one LED Is turned off. Specifically, the special symbol hold storage display 18 shifts the lighting state every time the special symbol display 8 starts the variable display. In this example, an upper limit number (up to 4) is provided for the number of reserved memories by winning to the first start port 15a or the second start port 15b. However, the present invention is not limited to this, and the upper limit number of the reserved storage number may be a value of 4 or more, or may be a value less than 4.

  A special variable winning ball device 20 using an opening / closing plate that is opened and closed by a solenoid 21 is provided below the start winning device 15. The special variable winning ball apparatus 20 is provided with a big winning opening that is opened and closed by an opening / closing plate, and the opening / closing plate is controlled to an open state (first state) advantageous to the player in the big hit gaming state, and the big hit gaming state In other states, the open / close plate is controlled to a closed state (second state) which is disadvantageous to the player. As described above, the special variable winning ball apparatus 20 satisfies the release condition when it enters the big hit gaming state. Of the winning balls that are won in the special variable winning ball apparatus 20 and guided to the back of the game board 6, the winning ball that has entered one (V winning area: special area) and the pachinko ball that has entered the other area are counted as they are. 23. A solenoid 21a (see FIG. 3) for switching the route in the special winning opening is also provided on the back of the game board 6.

  When the pachinko ball passes through the gate 32 and is detected by the gate switch 32a, the variable display on the normal symbol display 10 which displays the normal symbols as a plurality of types of identification information in a variable manner is started. In this embodiment, left and right LEDs (not shown) are turned on alternately by turning on the LEDs alternately (for example, the symbols can be visually recognized). For example, if the left LED is turned on at the end of the change display, it becomes a hit. . When the stop symbol on the normal symbol display 10 becomes a predetermined symbol (winning symbol), the opening condition of the movable pieces 13 and 13 of the start winning device 15 is established, and the movable pieces 13 and 13 in the start winning device 15 are 13 is opened for a predetermined number of times for a predetermined time. In the vicinity of the normal symbol display 10, the normal symbol holding memory display 41 (see FIG. 3) having a display unit with four LEDs for displaying the number of memorized effective passing spheres that have passed through the gate 32, that is, the starting passing memorized number. ) Is provided. Every time there is a pachinko ball passing through the gate 32, the stored data of the start passing memory is incremented by 1, and the normal symbol holding memory display 41 increments the LED to be lit by 1. Then, every time the variable display on the normal symbol display 10 is started, the stored data of the start passage memory is decreased by 1, and the LED to be lit is decreased by 1.

  The game board 6 is provided with a plurality of normal winning ports including a first normal winning port 29 and a second normal winning port 30 as a winning area of a winning device that accepts a pachinko ball and allows winning. The winning of the pachinko ball to the first normal winning opening 29 is detected by the first winning opening switch 29a. The winning of the pachinko ball in the second normal winning opening 30 is detected by the second winning opening switch 30a. The first starting port 15a, the second starting port 15b, and the big winning port also constitute a winning area of the winning device that accepts a pachinko ball and allows winning. In addition, decorative light emitting portions 25L and 25R in which decorative LEDs 25a blinking and displayed during the game are provided around the left and right of the game area 7, and an out port 26 for collecting pachinko balls that have not won a prize is provided at the bottom. There is.

  Two speakers 27L and 27R that emit sound effects are provided at the left and right upper portions outside the game area 7, and two speakers 27a and 27b that emit sound effects are provided at the left and right lower portions. In the following description, the speakers 27L, 27R, 27a, and 27b may be collectively referred to as speakers 27. On the outer periphery of the game area 7, there is a ceiling lamp module 530 in which various LEDs such as a rotating body LED are incorporated, a left light emitting unit 28L in which a left frame LED 28b (see FIG. 3) is incorporated, and a right frame LED 28c (see FIG. 3). ) Is built in. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The LED for the rotating body, the left frame LED 28b, the right frame LED 28c, and the decoration LED are examples of the decoration light emitter provided in the pachinko gaming machine 1.

  In this example, a prize ball LED 51 that is lit during award ball payout is provided at a predetermined position of the left light emitting unit 28L, and a ball break LED 52 that is lit when a supply ball is cut is provided at a predetermined position of the right frame LED 28c. Is provided.

  Various light emitting means such as prize ball LED 51, ball-out LED 52, decoration LED 25 a, left frame LED 28 b, right frame LED 28 c, and each LED in the top lamp module 530 are based on the effect control command output from the main board 31. Lighting control (LED control) is performed based on a signal output from the computer 81. In addition, sound generation control (sound control) from the speakers 27L, 27R, 27a, and 27b is also performed by the effect control microcomputer 81.

  Pachinko balls launched from a hitting ball launcher (not shown) by operating the hitting operation handle 5 of the player enter the game area 7 through the hitting guide rail (not shown), and then flow down the game area 7. When a pachinko ball enters the first start port 15a and is detected by the first start port switch 14a, or enters the second start port 15b and is detected by the second start port switch 14b, a special symbol variation display is displayed. If it can be started, the special symbol on the special symbol display 8 starts to be displayed in a variable manner. If the special symbol variable display is not ready to start, the number of reserved memories is increased by one.

  The symbol variation display on the special symbol display 8 and the main effect display device 9 stops when the variation display time set every time the variation display is performed. If the symbol at the time of stop (stop symbol) is a jackpot symbol (also referred to as a jackpot display result) as a specific display result, it will be a jackpot and the game will shift to a jackpot gaming state. In the big hit gaming state, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, ten) of pachinko balls wins. Then, if the pachinko ball wins the V winning area while the special variable winning ball apparatus 20 is opened and is detected by the count switch 23, a continuation right is generated and the special variable winning ball apparatus 20 is opened again. The generation of the continuation right is permitted with a predetermined number of times such as 15 rounds as an upper limit value. Such control is called repeated continuation control. In the repeated continuation control, a state in which the special variable winning ball apparatus 20 is opened is called a round.

  When the symbols on the special symbol display unit 8 and the main effect display device 9 at the time of the stop are predetermined special jackpot symbols (probable variation jackpot symbols) of the jackpot symbols, it is determined that the jackpot is made after the jackpot gaming state. The probability variation state (hit probability) is higher than that in the normal game state, which is a normal state different from the big hit game state, which is a more advantageous state for the player. Hereinafter, the probability variation state is also referred to as a high probability state (sometimes abbreviated as a high probability state). Further, the non-probable change state is also referred to as a low probability state (sometimes abbreviated as a low probability state).

  In addition, when the display result of the symbols when the variable display is stopped on the special symbol display 8 and the main effect display device 9 is the probability variation big hit symbol, the predetermined time short state which is the variable time reduction state after the big hit gaming state is predetermined. Controlled over a period of time. Compared to the normal gaming state, the short time state means that each of the special symbol display 8, the main effect display device 9, and the normal symbol display 10 has a variable display time (from the start of the change until the display result is derived and displayed). This is a control state in which the display result is derived and displayed at an early stage by shortening (time). Further, during the time-short state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time of the movable pieces 13 and 13 of the start winning device 15 is lengthened and the number of times of opening is increased. In other words, so-called electric Chu support control is executed. During the time-short state, since the display time of the symbol variation is shortened, the number of reserved memories to be described later is digested early, and the start winning that occurs exceeding the upper limit (for example, “4”) of the number of reserved memories becomes invalid. Since it is easy to derive and display the jackpot display result early in the short term, it is easy to derive and display the jackpot display result early, so the display result of the variable display is likely to become the display result of the jackpot symbol from a time efficient viewpoint It becomes a gaming state advantageous to the player. As described above, in the case of a probable big hit, the high probability state and the short time state are controlled in a predetermined period after the end of the big hit gaming state. The short-time state over a predetermined period after the end of the jackpot gaming state is either the next jackpot gaming state occurs, or until the special symbols and decorative symbols are displayed a predetermined number of times (100 times). It continues until the condition of is satisfied.

  Also, when considering the payout of pachinko balls according to the winning, the time-short state is shorter than the non-time-short state and the normal symbol variation display time is shortened, and the stop symbol in the normal symbol display 10 becomes a winning symbol. The probability is increased, the opening time of the movable pieces 13 and 13 of the start winning device 15 at the time of winning is lengthened, and the number of times of opening the movable pieces 13 and 13 of the starting winning device 15 at the time of hitting is increased. Based on this, the movable pieces 13 and 13 of the start winning device 15 are likely to be in an open state as compared with the normal gaming state. Accordingly, in the short-time state, it is easy to generate a prize (including both a case where the start prize is valid and a case where the prize is invalid) in the second start port 15b, so the number of pachinko balls ( The ratio of the number of pachinko balls (the number of balls to be paid out) to be paid out as winning balls according to the winning is greater than the number of hitting balls) as compared to the normal gaming state. In general, the ratio of the number of paid-out balls for winning a prize to the number of shot balls is called “base”. For example, when there are 40 payout balls with respect to 100 shot balls, the base is 40 (%). In the case of this embodiment, for example, a time-short state having a higher base than a non-time-short state such as a normal gaming state is called a high base state, and conversely, a base game state having a lower base compared to such a high base state. Such a non-short-time state is called a low base state.

  In this way, the ratio of the number of award balls paid out by winning a prize to the number of balls launched is generally called “base”, but the maximum number of pachinko balls fired per unit time such as 1 minute is limited to a certain number. ing. For this reason, the “base” can also be indicated by a total value of the number of winning balls paid out by winning a plurality of winning openings provided in the game area in a unit time. For example, assuming that the maximum number of pachinko balls fired per unit time is 100, the total number of award balls paid out by winning in a unit time matches the general “base” value. Based on such relevance, in the present embodiment, each of the first start port 15a, the second start port 15b, the first normal winning port 29, and the second normal winning port 30 is an abnormality monitoring target winning port, A total value of the number of paid-out balls of the winning ball due to the winning of the abnormality monitoring target winning opening is called a base, and is used as an object of abnormality monitoring related to winning.

  Whether the probability variation state (high probability state) or the non-probability variation state (low probability state) is determined based on whether or not the probability variation flag, which is a flag set in the probability variation state, is set. . Also, whether the time-short state (high base state) or the non-time-short state (low base state) is determined based on whether or not the time-short flag, which is a flag set in the time-short state, is set. Is done.

  In addition, in the state that is not controlled to the above-mentioned time-short state, every time the number of special symbols on-hold storage becomes a predetermined number or more, the memory that controls to the memory variation shortened state that shortens the variation display time of the special symbol and the decorative symbol Fluctuation shortening control is performed. The memory fluctuation shortening control ends when the number of reserved symbols for special symbols is less than a predetermined number. Therefore, even in a state where the time-short state is not controlled, there is a case where the variation display time of the special symbol and the decorative symbol is shortened.

  The decorative symbols that are variably displayed on the main effect display device 9 are variably displayed with a predetermined relationship with the variably displayed special symbols in order to enhance the decoration effect of the variable symbol special display on the special symbol display 8. It has a decorative meaning. The predetermined relationship for such symbols includes, for example, the relationship in which the variation display of the decorative symbol starts when the variation display of the special symbol is started, and the display result of the special symbol at the end of the variation display of the special symbol. This includes a relationship in which the decorative symbol display result is derived and displayed and the decorative symbol variation display is terminated. When a special jackpot symbol is derived and displayed as a display result by the special symbol display 8, the main effect display device 9 derives and displays a combination of jackpot symbols whose left, middle, and right symbols are flattered as a display result. Is done. Such a display result of the jackpot symbol by the special symbol and the display result of the combination of the jackpot symbol by the decoration symbol are referred to as a jackpot display result.

  The special symbol display 8 and the main effect display device 9 have a correspondence relationship as described above, and therefore, in the following description, these may be collectively referred to as a variation display unit.

  Next, the reach display mode (reach) will be described. The reach display mode (reach) in the present embodiment is that the symbols that have not been stopped when the stopped symbols constitute a part of the jackpot symbol, and that all or This is a state where some symbols are synchronously displayed while constituting all or part of the jackpot symbol.

  For example, in the main effect display device 9, an effective line (one effective line in the case of this embodiment) that becomes a big hit when the symbol stops is determined in advance, and in a part of the display area on the effective line A state in which the variable display is performed in the display area on the active line that has not been stopped when the predetermined symbol is stopped (for example, the left, middle, and right variable display areas in the main effect display device 9) Of the left and right display areas, while the same display is stopped and displayed, the display area in the middle is still in a variable display state), and all or part of the display area on the active line A state in which the symbols are synchronously displayed while constituting all or part of the jackpot symbol (for example, the variable display is performed in all of the left, middle and right display areas in the main effect display device 9). Always the same conditions) the variation displayed with the symbol are aligned is made that reach the display mode or reach.

  In addition, during the reach, an unusual effect may be performed with an LED or sound. This production is called reach production. These reach effects include a reach notification effect for notifying that the reach has been reached (see FIG. 7). In addition, during the reach, a character (an effect display imitating a person or the like, which is different from a design (decoration design, etc.)) or a display mode (for example, color) of the main effect display device 9 is displayed. Etc.) may be changed. This change in character display and background display mode is called reach effect display. In addition, some reach is set so that when it appears, a big hit is likely to occur compared to a normal reach. Such special (specific) reach is called super reach.

  Further, for the main effect display device 9, there is a case where a jackpot notice effect such as a pseudo-ream for notifying that there is a possibility of winning a big hit in the variable display that triggers the occurrence of the big hit may be performed.

  In this embodiment, as the big hit, a plurality of types of big hits such as a normal big hit C and a probable big hit A are provided as will be described later. In the following description, when “big hit” is simply indicated without specifying the types of big hits, it is a case where these multiple types of big hits are representatively shown.

  Normally, the big hit C is a big hit (non-probable big hit) that does not become the above-described probability change state after the big hit gaming state and becomes a low-probability state and a high base state by becoming a short time state. Such a state having a low probability state and a high base state is referred to as a low probability high base state. The probability variation jackpot A is a jackpot that becomes a probability variation state after the end of the jackpot gaming state and is in a high probability state in which the time is short for a predetermined period and in a high base state. Such a state with a high probability state and a high base state is referred to as a highly accurate high base state. After the probability variation big hit, when the predetermined period elapses, the time reduction state ends, and the state becomes a high probability state and a low base state. Such a state having a high probability state and a low base state is referred to as a high probability low base state.

  FIG. 3 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 3 also shows a payout control board 37 and an effect control board 80 mounted on the pachinko gaming machine 1. The main board (game control board) 31 includes a game control microcomputer 156 serving as a basic circuit for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a first start port switch 14a, and a second start port switch 14b. In addition to the signals from the count switch 23, the first prize opening switch 29a and the second prize opening switch 30a, an input circuit 58 for supplying various signals such as a power-off signal and a clear signal to the game control microcomputer 156, and a start prize The solenoid 16 for opening and closing the movable pieces 13 and 13 of the device 15, the solenoid 21 for opening and closing the special variable winning ball device 20, and the solenoid 21a for switching the path in the special winning opening are given as commands from the game control microcomputer 156. Therefore, an output circuit 79 to be driven is mounted.

  The game control microcomputer 156 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as a storage means used as a work memory, and a CPU 56 that is a processor that performs a control operation according to the program. , I / O port 57 is included. The game control microcomputer 156 is a one-chip microcomputer.

  In the game control microcomputer 156, the CPU 56 executes control according to a program stored in the ROM 54. Therefore, the execution (or processing) of the game control microcomputer 156 as described below specifically means that the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a game control microcomputer 156 including a CPU 56.

  The game control microcomputer 156 includes a clock circuit that generates a clock signal, a reset controller that functions as a system reset unit, a random number circuit, and a CTC that sends an interrupt request signal to the CPU 56.

  The random number circuit is a hardware circuit used for generating a random number for determination for determining whether or not to win a jackpot based on the display result of the variation display of the special symbol and the decorative symbol. The random number circuit updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and at random timing. Based on the fact that the start winning time generated is the time of reading (extracting) the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The game control microcomputer 156 reads the numerical data from the random number circuit as a random number value R (random R) when a start winning to the first start port switch 14a or the second start port switch 14b occurs, and converts the numerical data into the numerical data. Based on this, it is determined whether or not to make a jackpot display result as a specific display result, that is, whether or not to make a jackpot. When it is determined that the game is a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player. The determination as to whether or not to win is actually performed based on the random number value extracted at the time of starting winning, at the start of the variable symbol display of special symbols and decorative symbols. Whether the random number generated by the random number circuit is a big hit, such as a random number for probability variation determination for determining whether or not to make a probability variation, and a random number for variation pattern determination for determining a variation pattern of a special symbol. It may be used as a random number for determination other than determination.

  The clock circuit outputs a system clock signal to the CPU 56, and outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal to each random number circuit. When a low level signal is input for a certain period, the reset controller outputs a predetermined initialization signal to the CPU 56 and each random number circuit to reset the game control microcomputer 156 as a system.

  The RAM 55 is a backup RAM as a volatile storage means that is partly or wholly backed up by a backup power source created on a power supply board (not shown). That is, even when the power supply to the pachinko gaming machine 1 is stopped, a part of the RAM 55 is kept for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged). Or the entire contents are preserved. In particular, at least data corresponding to the control state of the game (special symbol process flag or the like) and data indicating the number of unpaid prize balls are stored in the RAM 55 as backup data. The data corresponding to the control state is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like.

  Further, a power-off signal indicating that the power supply voltage from the power supply board (not shown) has dropped below a predetermined value is input to the input circuit 58. The power-off signal is input to the input port of the game control microcomputer 156 via the input circuit 58. A clear signal indicating that the clear switch for instructing clearing of the contents of the RAM is operated is input to the input circuit 58 at the input port of the game control microcomputer 156. The clear signal is input to the input port of the game control microcomputer 156 via the input circuit 58.

  Each of the plurality of switches is connected to the input port of the game control microcomputer 156 via the input circuit 58. Thereby, the game control microcomputer 156 receives an input detection signal indicating the input state of each switch from each of the plurality of switches.

  Further, the output circuit 78 mounted on the game control microcomputer 156 transmits (outputs) the effect control command output by the CPU 56 to the effect control board 80. The output circuit 78 transmits (outputs) a control signal output from the CPU 56 to the special symbol display 8, the special symbol hold storage display 18, the normal symbol display 10, and the normal symbol hold storage display 41.

  The game control microcomputer 156 outputs an effect control command (effect control signal) as a control signal for instructing the effect control board 80 to perform effect control including display control, sound control, and LED control. Send through.

  The effect control commands transmitted to the effect control board 80 by the game control microcomputer 156 include a customer waiting demonstration designation command and a variable display command.

  The customer waiting demonstration designation command is an effect control command (customer waiting demonstration designation command) for designating the display during the customer waiting demonstration by the game control microcomputer 156, and a predetermined time has elapsed after the change of the special symbol is finished. When the customer waiting demonstration designation command is sent to the effect control board 80, a predetermined customer waiting demonstration screen is displayed on the main effect display device 9. In other words, normally, when a player changes, there is a period in which the player is absent, so it is assumed that these waiting-for-demo demonstration designation commands are due to the player changing. When it is output.

  The variable display command is an effect control command transmitted at the start of the change in order to designate a change pattern of the decorative pattern that is variably displayed on the main effect display device 9 in response to the variable display of the special symbol. This command is used to specify the start.

  The effect control board 80 receives the effect control command from the game control microcomputer 156, and controls the display of the effect display and the sound effect (effect sound) on the main effect display device 9 and the sub effect display devices 11a to 11d. Electric component control means such as an effect control microcomputer 81 for performing output control is mounted.

  In this embodiment, the effect control microcomputer 81 mounted on the effect control board 80 receives the effect control command from the game control microcomputer 156, and displays the main effect display device 9 that variably displays decorative symbols. Control, display control of the four sub-effect display devices 11a to 11d, and sound output control from the speakers 27L, 27R, 27a, and 27b are performed.

  The main effect display device 9 is directly connected to a main display system output unit (one output unit) MK of a VDP 262 described later mounted on the effect control board 80. On the other hand, the four sub-effect display devices 11a to 11d are connected to the sub-display system output unit (other output units) of the VDP 262 mounted on the effect control board 80 via one signal separation board (data separation means) 220 described later. , Common output unit) SK.

  Further, the main effect display device 9 and the sub effect display device 11 have liquid crystal panels 9 ′ and 11a ′ to 11d ′, and a display unit (display area) is formed by the liquid crystal panels 9 ′ and 11a ′ to 11d ′. Is formed. As described above, in the present embodiment, the display unit is configured using the liquid crystal panels 9 ′ and 11a ′ to 11d ′, but the present invention is not limited to this, and the main effect display device 9 and The sub-effect display device 11 may be a display device other than liquid crystal, such as a CRT (Cathode Ray Tube), as long as it can display an image of a decorative design or the like with a predetermined resolution (display pixel density). , FED (Field Emission Display), PDP (Plasma Display Panel), dot matrix LED, organic or inorganic electroluminescence (EL) panel, and other display devices. In the main effect display device 9, the decorative symbol is displayed in a variable manner during the special symbol variable display period by the special symbol indicator 8.

  In addition, the effect control microcomputer 81 mounted on the effect control board 80 detects the detection signals from the lever switches 510a to 510d and the button switch 516a, thereby operating the operation lever 600 and the player of the operation button 516. Detects operations by.

  In addition, the production control microcomputer 81 performs display control of the stage LED 25b provided on the game board 6, and the prize ball LED 51, the ball cut LED 52, the left frame LED 28b, the right frame LED 28c provided on the frame side, Moreover, lighting control of each LED in the top lamp module 530 is performed.

  Further, as shown in FIG. 3, four movement motors 59a to 59d for operating (moving) the four (plural) sub-effect display devices 11a to 11d are connected to the effect control board 80. The production control microcomputer 81 controls the movements of the movement motors 59a to 59d, whereby the movements of the sub production display devices 11a to 11d are controlled.

  As shown in FIG. 4, the effect control board 80 includes an effect control microcomputer 81 including an effect control CPU 86 and a RAM 85. In the effect control board 80, the effect control CPU 86 operates in accordance with a program stored in the built-in ROM 84, and receives an effect control command via the input circuit 260. Among these, in the ROM 84, data relating to images to be displayed on the main effect display device 9 and the sub effect display devices 11a to 11d in various effects, a time chart of display start timing and end timing, and the like for each effect type. It is remembered. Further, the effect control CPU 86 causes the main effect display device 9 such as generation of an image to be displayed on the main effect display device 9 and adjustment of the light emission intensity of the backlight to the VDP (video display processor) 262 based on the effect control command. The first display control process for performing the display control of the sub-effects and the second display control process for performing the display control of the sub-effect display devices 11a to 11d such as generation of images to be displayed on the sub-effect display devices 11a to 11d. To do.

  In this embodiment, a VDP (display control means) 262 that performs display control of the main effect display device 9 and the sub-effect display devices 11a to 11d in cooperation with the effect control microcomputer 81 is mounted on the effect control board 80. ing.

  As shown in FIG. 4, the VDP 262 stores data such as characters (image data of people, animals, characters, figures, symbols, etc., and CG data) as image element data (original image) used as a sprite image. The CGROM 205 and the SDRAM (synchronous DRAM) 210 used as a VRAM area (image data storage means) constitute a display control circuit.

  The effect control CPU 86 outputs to the VDP 262 a command for reading out necessary data from the image data ROM in which various image data are stored in accordance with the received effect control command. The image data ROM is character image data or moving image data displayed on the main effect display device 9 or each of the sub-effect display devices 11a to 11d, specifically, a person, a character, a figure, a symbol, etc. (including decorative designs). And a ROM for storing the image data of the background image in advance. The VDP 262 reads the image data from the image data ROM in response to a command from the effect control CPU 86. The VDP 262 performs display control based on the read image data.

  The VDP 262 is a system register 202 that stores various settings of the VDP 262, and attributes (parameters used when drawing the character. The drawing order of the character, the number of colors, the scaling ratio, the palette number, the coordinates, etc. Specified data) is stored in the attribute register 203, each frame buffer (to be described later) in the VRAM area, a drawing control unit 206 that controls drawing of an image in the composite image storage area, and the CG data stored in the CGROM 205 in the VRAM area. A data transfer control unit 211 that performs transfer control, a data signal (R (red), G (green), B (blue)) signal for displaying image data stored in an image display area (to be described later) of the VRAM area And the synchronization signal are output to the main effect display device 9 and the sub effect display devices 11a to 11d. A display control unit 213 which is an integrated circuit mounted.

  The VDP 262 is provided with a system bus and a CG bus. The system bus and the CG bus are connected to the effect control CPU 86 of the effect control microcomputer 81 via the CPU interface 201. It is connected to the CGROM 205 via the CG bus interface 204. A system register 202 is connected to the system bus, and an attribute register 203 is connected to the CG bus, so that the effect control CPU 86 can access the system register 202 and the attribute register 203.

  The drawing control unit 206, the data transfer control unit 211, and the display control unit 213 are connected to the system bus so that the system register 202 can be accessed. The drawing control unit 206 and the data transfer control unit 211 are connected to the CG bus so that the CGROM 205 and the attribute register 203 can be accessed.

  Further, a VRAM bus is further provided inside the VDP 262, and the VRAM bus is connected to the SDRAM 210 via the VRAM bus interface 209. A drawing controller 206, a data transfer controller 211, and a display controller 213 are connected to the VRAM bus so that the VRAM area of the SDRAM 210 can be accessed via the VRAM bus.

  The system register 202 includes a system control register for storing instructions such as initial setting, drawing, and data transfer, an interrupt control register for storing an output instruction of an interrupt signal, an image drawing area in a VRAM area to be described later, a palette data A drawing register for storing an arrangement area, a transfer source address for data transfer, a data transfer register for storing a transfer destination address, a display register for storing an address of an image display area in the VRAM area, and the like are allocated. .

  In the system register 202 of the VDP 262, each area data (address) of the first drawing area (first storage area) and each second drawing area (second storage area) in the main frame buffer of the VRAM area is registered. The effect control microcomputer 81 corresponds to each position of the display area of each of the sub-effect display devices 11a to 11d based on the moving distance of each of the sub-effect display devices 11a to 11d. Each area data of the second drawing area is updated.

  The CPU interface 201 outputs a V sync interrupt signal to the effect control CPU 86, the drawing control unit 206, and the display control unit 216 at each V sync timing corresponding to the sub effect display devices 11a to 11d. Alternatively, the CPU interface 102 outputs a V blank interrupt signal to the effect control CPU 86 and the drawing control unit 206 every time the V blank corresponding to the sub effect display devices 11a to 11d is started. Further, the CPU interface 201 outputs various other interrupt signals to the CPU 86 for effect control.

  The timing of V sync is the start timing of the frame cycle of the corresponding effect display device, and arrives at every frame cycle. Furthermore, in the present embodiment, the output timing of image data from the VRAM area is started. Here, the frame period is calculated by multiplying the dot clock value (period for outputting image data for one dot) by the number of dots for the frame period of the corresponding effect display device. The number of dots for the frame period of the effect display device is specified by the number of dots in the X-axis direction (horizontal direction) and the number of dots in the Y-axis direction (vertical direction), and is physically included in the display unit of the effect display device. More than the number of dots in the X-axis direction and the number of dots in the Y-axis direction are set. The CPU interface 201 outputs V sync interrupt signals corresponding to the sub-effect display devices 11a to 11d at the V sync timing. The V blank is a period during which an image can be drawn, and the start timing of the V blank differs among the main effect display device 9, the main effect display device 9, and the sub effect display devices 11a to 11d. The start timing of the V blank corresponding to the main effect display device 9 is the timing when the output of the image data for one frame to the main display device 9 is completed. On the other hand, the timing of the V blank corresponding to the sub effect display devices 11a to 11d is the timing when the output of the image data for one frame is completed for all of the sub effect display devices 11a to 11d. In this embodiment, the time required to output one frame of image data for all of the sub-effect display devices 11a to 11d is longer than the time required to output one frame of image data to the main display device 9. ing. The CPU interface 201 monitors the end of the output of image data for one frame to the sub-effect display devices 11a to 11d by the display control unit 213, and V corresponding to the sub-effect display devices 11a to 11d at the end timing. Outputs a blank interrupt signal. Here, the display control unit 213 outputs the image data for one frame to the sub-effect display devices 11a to 11d within one frame period of the sub-effect display devices 11a to 11d. Therefore, the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d is output for each frame period of the sub-effect display devices 11a to 11d, and the V blank corresponding to the sub-effect display devices 11a to 11d. The average period of the interrupt signal is the frame period of the sub-effect display devices 11a to 11d.

  The display control unit 213 outputs the image data in the VRAM area designated by the display register and the output image data Z stored in the composite image storage area described later as data signals.

  As shown in FIG. 5, the VDP 262 mounted on the effect control board 80 includes a main display system output unit MK to which a data signal of main image data displayed on the main effect display device 9 is transmitted, and each sub-effect display device. It has two signal output lines with a sub display system output unit SK to which a data signal of output image data to be described later displayed on 11a to 11d is transmitted. Of these two signal output lines, the main display system output unit MK is connected to the liquid crystal panel side receiving circuit 225 of the main effect display device 9, and is output from the VDP 262 via the liquid crystal panel side receiving circuit 225. A signal is input to the first liquid crystal panel 9 ′.

  Further, as will be described later, the sub display system output unit SK is a signal for transmitting a data signal for transmitting image data output from the sub display system output unit SK to each of the sub effect display devices 11a to 11d. The separation substrate 220 is connected, and is connected to the liquid crystal panel side reception circuits 224 a to 224 d of the sub-effect display devices 11 a to 11 d via the signal separation substrate 220. The data signals output from the VDP 262 via the liquid crystal panel side receiving circuits 224a to 224d are input to the second liquid crystal panels 11a 'to 11d'. The signal separation board 220 is mounted on the pachinko gaming machine 1 as a separate board different from the effect control board 80.

  The signal separation board 220 includes a primary separation circuit 221 that separates the data signal of the sub display system output unit SK (one system) output from the sub display system output unit SK of the VDP (display control means) 262 into two systems. The secondary separation circuits 222a and 222b for separating the signals of each system (each one system) separated and output by the primary separation circuit 221 into two systems, and the secondary separation circuits 222a and 222b Transmission circuits 223a to 223d for transmitting the data signals of the respective systems (one system each) output to the sub-effect display devices 11a to 11d.

  The display control unit 213 of the VDP 262 is configured to send a data signal with a frequency of 40 MHz as a dot clock value (period for outputting image data for one dot), and the main effect display device 9 is connected to the VDP 262. The same dot clock value receives a data signal having a frequency of 40 MHz and displays an image. On the other hand, as described later, each of the sub-effect display devices 11a to 11d receives a data signal having a dot clock value of 10 MHz and displays an image. Therefore, the data signal having a dot clock value of 40 MHz output from the VDP 262 is converted into a data signal having a dot clock value of 10 MHz by the signal separation board 220 and output (FIG. 12). reference).

  In this signal separation board 220, the data signal having a frequency of 40 MHz dot clock value output from the VDP 262 is converted into a data signal having a frequency of 20 MHz dot clock value by the primary separation circuit 221 and further subjected to secondary separation. The circuit 222a, 222b converts the dot clock value into a data signal having a frequency of 10 MHz and outputs it (see FIG. 12).

  The display control unit 213 of the VDP 262 displays the image data output to the main display system output unit MK in order to display an image on the main effect display device 9 and the sub display to display images on the sub effect display devices 11a to 11d. Color tone correction of the image data output to the system output unit SK is performed. For the color tone correction, for example, brightness correction for adjusting the brightness and contrast of images displayed on the main effect display device 9 and the sub-effect display devices 11a to 11d, and gamma correction for adjusting numerical values indicating image tone response characteristics. There are methods. Specifically, the main effect display device 9 and the sub-effect display devices 11a to 11d are performed by filtering the image data using a mask pattern prepared by recording the image data in the ROM 84 or RAM 85 in advance. The color tone of the image displayed at is corrected.

  In the present embodiment, the display control unit 213 performs color tone correction on the images displayed on the sub-effect display devices 11a to 11d having a small display area so as to match the main effect display device 9 having a large display area. Specifically, the display control unit 213 first specifies a reference color (for example, white) and matches the color tone of the sub-effect display devices 11a to 11d with the main effect display device 9 for the specified color. To correct. The correction amount is recorded in a predetermined area of the ROM 84 or RAM 85 as a mask pattern or the like, and all colors other than the specified color are corrected using the mask pattern or the like.

  Thereby, for example, even if the portion displayed in white in the main effect display device 9 is displayed in a blue color or in a yellow color in the sub effect display devices 11a to 11d, by correcting the color tone, A difference in color with the main effect display device 9 can be suppressed. That is, even when the same image data is displayed on a plurality of effect display devices having different characteristics, such as the main effect display device 9 and the sub-effect display devices 11a to 11d, a display without a sense of discomfort among the plurality of effect display devices is realized. be able to. Moreover, since it matches with the main effect display device 9 having a large display area, it is possible to reduce a sense of incongruity according to a large conspicuous place. Further, by correcting all colors based on a specific color, it is possible to realize a display that does not give a sense of discomfort among a plurality of display devices such as the main effect display device 9 and the sub effect display devices 11a to 11d.

  In addition, you may perform color tone correction | amendment about the image displayed on the main effect display apparatus 9 so that it may suit sub effect display apparatus 11a-11d. Further, by adjusting the color tone of the main effect display device 9 to the sub effect display devices 11a to 11d and adjusting the color tone of the sub effect display devices 11a to 11d to the main effect display device 9, the main effect display device 9 Between the sub-effect display devices 11a to 11d. Thereby, for example, it is possible to cope with a case where correction cannot be performed beyond the range in which the color tone can be corrected, such as trying to make white more white.

  Further, in the present embodiment, as shown in FIG. 2B, the main effect display device 9 and the sub effect display devices 11a to 11d may overlap each other, and as shown in FIG. When the sub effect display devices 11a to 11d are physically superimposed on the front surface of the effect display device 9, a display area covered with the sub effect display devices 11a to 11d is generated on the main effect display device 9. As shown in FIG. 7B, in the main frame buffer of the VRAM area, the first drawing area and the second drawing are displayed in accordance with the physical arrangement state of the main effect display device 9 and the sub effect display devices 11a to 11d. Since the area is set, the same images as the sub-effect display devices 11a to 11d are displayed in the display area covered by the main effect display device 9. Specifically, for the image displayed on the main effect display device 9, the display control unit 213 displays an image in a state where the image of the second drawing area in the main frame buffer is superimposed on the display area covered by the first drawing area. Output to the main display system output unit MK.

  Even when the sub-effect display devices 11a to 11d are physically superimposed on the front surface of the main effect display device 9, the images displayed in the display areas of the superimposed sub-effect display devices 11a to 11d are superimposed on the main effect display device. Since it is displayed in the display area covered with 9, it can be shown well even if it is visually recognized from a gap or the like.

  FIG. 6 is a diagram showing the configuration of the VRAM area of the SDRAM 210. As shown in FIG. The VRAM area includes a palette area in which palette data is arranged, a character buffer in which necessary characters are read and stored from the image data ROM, and palette data (character display) when the drawing control unit 206 draws an image. Each area such as a CG buffer for temporarily storing CG data is allocated to temporarily store (data in which color is defined) and when the drawing control unit 206 draws an image.

  In addition, a buffer A area and a buffer B area are allocated to the VRAM area. The buffer A and the buffer B are respectively an image display area for storing each image data displayed on the main effect display device 9 and the sub effect display devices 11a to 11d, and the main effect display device 9 and each sub effect display device 11a. It becomes an image drawing area in which each image data displayed in .about.11d is drawn. In the present embodiment, the time required for drawing image data in the image drawing area is longer than one frame period of the sub-effect display devices 11a to 11d and shorter than two frame periods. For this reason, the image display area and the image drawing area each time the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d is input to the drawing control unit 206 twice, that is, the sub-effect display devices 11a to 11a. When the buffer A and the buffer B are used as an image display area, the other of the buffer A and the buffer B is used as an image drawing area. More specifically, at the timing when a V blank interrupt signal corresponding to a certain sub-effect display device 11a to 11d is input, the buffer A becomes an image drawing area, and drawing of image data of each image is started. The buffer B becomes an image display area, and output of image data of each already drawn image is started. Further, at the timing when the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d after the second time is input, the buffer A becomes an image display area, and output of the image data of each image already drawn is started. At the same time, the buffer B becomes an image drawing area, and drawing of image data of each image is started.

  Each image drawing area (each image display area) in the VRAM area includes a first drawing area (first storage area) in which main image data displayed on the main effect display device 9 is stored, as will be described later. A main frame buffer, a sub frame buffer having storage areas (second storage areas) for storing sub image data displayed on the sub effect display devices 11a to 11d, and storage areas of the sub frame buffers. A composite image storage area in which the sub image data is combined and stored as output image data Z is allocated. By specifying each of these areas in the display register, the display control unit 213 outputs the main image data to the main effect display device 9, and outputs the output image data Z to the sub-effect display devices 11a to 11d. Output toward. Thereby, the image drawn and stored in the first drawing area is displayed on the main effect display device 9, and the images stored in the composite image storage region are displayed on the sub-effect display devices 11a to 11d. In the present embodiment, the display control unit 213 outputs image data at the timing of V sync corresponding to sub-effect display devices 11a to 11d described later, and outputs the same image data from the buffer A twice in succession. And the process of continuously outputting the same image data twice from the buffer B are alternately repeated. Which of the buffer A and the buffer B should output image data is indicated by swap setting information described later.

  As described above, the effect control CPU 86 can access the system register 202 and the attribute register 203 via the CPU interface 201, and the main effect display device 9 and the sub effect display devices 11a to 11d described above can be accessed. The VDP 262 is indirectly controlled by storing execution instructions and necessary data in the system register 202 and the attribute register 203 according to the process data defining the display pattern.

  In the process data, the setting contents that the effect control CPU 86 performs on the system register 202 and the attribute register 203 for each V blank corresponding to the sub effect display devices 11a to 11d are determined. The setting contents of the system register 202 include drawing, data transfer command, CG data and palette data for data transfer, attribute setting, dot clock value which is an output cycle of image data, frame cycle of the main effect display device 9 And the number of dots for each frame period of the sub-effect display devices 11a to 11d. Here, the number of dots for the frame period of the main effect display device 9 is specified by the number of dots in the X-axis direction (horizontal direction) and the number of dots in the Y-axis direction (vertical direction). More than the physical number of dots in the X-axis direction and the number of dots in the Y-axis direction are set. Similarly, the number of dots for each frame period of the sub-effect display devices 11a to 11d is specified by the number of dots in the X-axis direction (horizontal direction) and the number of dots in the Y-axis direction (vertical direction). It is set to be larger than the physical number of dots in the X-axis direction and the number of dots in the Y-axis direction that constitute the display units of the display devices 11a to 11d.

  In the present embodiment, the drawing control unit 206 in the VDP 262 sets the dot clock value (40 MHz), the number of dots for the frame period of the main effect display device 9, and the sub effect display devices 11a to 11a set in the system register 202. Based on the number of dots for each frame period of 11d, one frame period is set for the main effect display device 9 and one frame period is set for the sub-effect display devices 11a to 11d. Specifically, the frame period coincides with the V sync period, for example, 1/60 second, and the start timing of the frame period coincides with the V sync timing. The frame period is set in the system register 202.

  However, the V sync cycle, which is the frame cycle of the main effect display device 9, includes the dot clock value, the number of dots in the X-axis direction (horizontal direction), which is the number of dots for the frame cycle of the main effect display device 9, and the Y axis. Calculated by multiplying the number of dots in the direction (vertical direction). On the other hand, the frame period of the sub effect display devices 11a to 11d is the number of dots of the sub effect display devices 11a to 11d corresponding to the dot clock value for each of the sub effect display devices 11a to 11d. It is calculated by multiplying the number and the number of dots in the Y-axis direction (vertical direction), and adding the multiplied values. For this reason, the frame period of the main effect display device 9 and the frame period of the sub effect display devices 11a to 11d cannot be strictly 1/60 seconds, and the frame period of the main effect display device 9 and the sub effect There is a difference between the frame periods of the display devices 11a to 11d.

  In the present embodiment, in the initial state (the state before the frame cycle of the main effect display device 9 is changed), the frame cycle (unique frame cycle) of the sub-effect display devices 11a to 11d is the frame of the main effect display device 9. It is longer than the period (inherent frame period). However, the effect control CPU 86 determines that the frame period of the main effect display device 9 obtained by multiplying the dot clock value by the number of dots for the frame period of the main effect display device 9 is the dot effect value and the sub effect display devices 11a to 11d. The number of dots for the frame period of the main effect display device 9 is increased from the initial state value so as to be longer than the frame period of the sub-effect display devices 11a to 11d obtained by multiplying the number of dots for the frame period. And set in the system register 202. Thereby, the frame period of the main effect display device 9 set by the drawing control unit 206 in the VDP 262 is longer than the frame period of the sub effect display devices 11a to 11d, and is a unique frame period of the main effect display device 9. Longer than.

  The setting contents of the attribute register 203 are attributes, that is, parameters used when drawing a character.

  In the process data, attributes are set so that the image is updated (drawn) for each V blank corresponding to the sub-effect display devices 11a to 11d. For this reason, the update of an image will be performed for every V blank corresponding to sub effect display apparatus 11a-11d.

  Here, the drawing control will be briefly described. In order for the drawing control unit 206 to perform the drawing process, it is necessary that characters necessary for drawing be arranged in the VRAM area. In other words, it is necessary to place a character as image element data of the sprite image in the VRAM area.

  For this reason, when executing the various effects, the effect control CPU 86 issues a transfer command from the CGROM 205 to the VRAM area for all the characters necessary to execute the effects. As a result, the data transfer control unit 211 arranges all the characters necessary for the performance in the VRAM area. When performing an effect, the same character is often used for drawing repeatedly, but the data stored in the CGROM 205 is compressed, and it takes time to read it. By arranging all necessary characters in the VRAM area at the initial stage of performing the performance, the time required for drawing can be reduced compared to reading data from the CGROM 205 for each frame. In this embodiment, when the effect control CPU 86 executes the effect, a transfer command from the CGROM 205 to the VRAM area for all the characters necessary for reproducing the moving image is issued. A character transfer command may be issued each time.

  Further, in order for the drawing control unit 206 to perform drawing processing, it is necessary to set an attribute in the attribute register 203. Since the attribute is different for each V blank corresponding to the sub effect display devices 11a to 11d, the attribute according to the process data is stored in the attribute register 203 for each V blank corresponding to the sub effect display devices 11a to 11d.

  Then, after starting the effect, the effect control CPU 86 sets an attribute in the attribute register 203 for each V blank corresponding to the sub-effect display devices 11a to 11d, and then commands execution of reading of the attribute. Along with this, the drawing control unit 206 reads the attribute of the attribute register 203 and instructs the output of the reading end interrupt signal when the reading is completed. In response to this, the effect control CPU 86 commands execution of drawing, and the drawing control unit 206 draws each image data in each frame buffer according to the read attribute.

  Next, FIG. 7 to FIG. 7 show the processing contents in each frame buffer for storing each image data displayed on the main effect display device 9 and each of the sub-effect display devices 11a to 11d, the composite image storage area, and the signal separation board 220. 15 will be described in detail. Since each frame buffer and composite image storage area allocated to each image drawing area (each image display area) in the VRAM area described above executes the same processing contents with the same configuration, one image drawing area ( Each frame buffer in the image display area) and the composite image storage area will be described as an example.

  As shown in FIGS. 7A and 8A, in the movable display effect, the notice effect, the reach effect, the effect in the big hit gaming state, the main effect display device 9 and the sub effect display devices 11a to 11d are provided. Display images and video in combination. At that time, as shown in FIG. 7B and FIG. 8B, the images displayed on the main effect display device 9 and the sub effect display devices 11a to 11d are first displayed on the main effect display device 9 and the sub effect display. Drawing is performed in the first drawing area and the second drawing area of the main frame buffer in accordance with the physical arrangement state of the devices 11a to 11d. 7 shows a case where the main effect display device 9 and the sub effect display devices 11a to 11d are in a superimposed state, and FIG. 8 shows that the main effect display device 9 and the sub effect display devices 11a to 11d are not superimposed. This is the case.

  As described above, the main frame buffer, the subframe buffer, and the composite image storage area are allocated to the VRAM area. As shown in FIG. 9A, a first drawing area in which main image data displayed on the main effect display device 9 is stored is assigned to the main frame buffer. A memory area capable of storing pixel data of 800 dots in the X-axis direction (horizontal direction) and 600 dots in the Y-axis direction (vertical direction) is allocated.

  Further, as shown in FIG. 9B, each storage area for storing sub-image data to be displayed on each of the sub-effect display devices 11a to 11d is assigned to the sub-frame buffer. Is assigned a memory area capable of storing pixel data of 480 dots in the X-axis direction (horizontal direction) and 234 dots in the Y-axis direction (vertical direction). Furthermore, as shown in FIG. 11, in the composite image storage area in which the sub image data of each storage area of the subframe buffer is combined and stored as output image data, 1920 dots in the X-axis direction (horizontal direction) A memory area capable of storing 234 dot pixel data is allocated in the Y-axis direction (vertical direction). That is, the number of dots in the X-axis direction allocated to the composite image storage area corresponds to four dots (for four display devices) in the X-axis direction of the storage area of the subframe buffer.

  In the present embodiment, when displaying images on the main effect display device 9 and the sub-effect display devices 11a to 11d, the drawing control unit 206 of the VDP 262 first selects the character that is the image element data of the sprite image in the main frame buffer. In addition to drawing in the first drawing area, drawing is performed in the second drawing area of the subframe buffer (see FIGS. 13A and 13B). Here, when performing the joint effect which displays the display content which mutually cooperated with the main effect display apparatus 9 and the sub effect display apparatuses 11a-11d, each sub image data (drawn in each storage area of a sub-frame buffer ( An unprocessed image) is copied to the main frame buffer, and effect processing (predetermined rendering processing) is performed for rendering effect image data (common image data) used for cooperative effects in the main frame buffer. . The effect image is, for example, a radial lightning image drawn in common across the main effect display device 9 and the sub effect display devices 11a to 11d (see FIG. 10A).

  As shown in FIG. 10A, each main image buffer can be assigned with each second drawing area in which each sub-image data drawn in each storage area of the sub-frame buffer is copied and drawn. Each second drawing area is set according to the physical arrangement state of each sub-effect display device 11a to 11d, and each second drawing area is arranged adjacent to each of the four corners of the first drawing area. . Furthermore, each 2nd drawing area | region is set in the state rotated by the predetermined angle according to the physical rotation state of each sub effect display apparatus 11a-11d.

  In the present embodiment, when each sub image data is duplicated from the second drawing area of the subframe buffer by the drawing control unit 206 of the VDP 262, the first image area arranged at the upper left of the first drawing area in the main frame buffer. The sub-image data to be duplicated in the second drawing area is rotated and rotated at an angle of 45 ° counterclockwise, and the sub-image data to be duplicated in the second drawing area arranged at the upper right of the first drawing area is The sub-image data that is rotated clockwise by an angle of 45 ° and replicated in the second drawing area that is arranged at the lower left of the first drawing area is rotated and arranged by an angle of 45 ° clockwise. The sub-image data duplicated in the second drawing area arranged at the lower right of the first drawing area is arranged by being rotated counterclockwise at an angle of 45 °.

  In the present embodiment, the main effect display device 9 is a display device having a resolution (display pixel density) lower than that of the sub-effect display devices 11a to 11d. Each of the sub-effect display devices 11a to 11d has a physical size (actual size) ratio relative to the display portion of the main effect display device 9 (the display area ratio of each display portion). The drawing area is set to be reduced (lower resolution) than each storage area of the subframe buffer. Then, each sub image data drawn in each storage area of the subframe buffer is duplicated in each second drawing area of the main frame buffer in a reduced (lower resolution) state.

  By doing in this way, the 1st drawing area and each 2nd drawing area in a main frame buffer are the physical magnitude | sizes of the display part of the main effect display apparatus 9, and the display part of each sub effect display apparatus 11a-11d. The first drawing area and the second drawing area are set when the effect image data used for the cooperation effect is drawn over the first drawing area and each second drawing area. It becomes possible to draw as a single area.

  The drawing control unit 206 (see FIG. 4) of the VDP 262 performs the drawing control of each image data in each drawing area of the main frame buffer, and the first drawing area registered in the system register 202 and each second drawing area. With reference to each area data (address) of the drawing area, the X value in the X-axis direction (horizontal direction) and the Y value in the Y-axis direction (vertical direction) in the main frame buffer, that is, the memory address of the SDRAM 210 are set. Each image data is drawn in the set drawing area (see FIG. 10A).

  And when drawing the effect image data used for the cooperation effect over the first drawing area and each second drawing area, the effect is obtained by drawing the first drawing area and the second drawing area as a single area. Information on the X value and Y value of the image element data that is the original image data can be used as it is to specify the X value and Y value in the main frame buffer, that is, the memory address of the SDRAM 210, and the main frame buffer. The control for performing the drawing can be simplified.

  Further, the production control microcomputer 81 (see FIG. 4) grasps the movement distance of each of the sub-production display devices 11a to 11d based on the pulse power sent to the movement motors 59a to 59d. The microcomputer 81 uses the area of the second drawing area of the system register 202 so as to correspond to the position of the display area of each of the sub-effect display devices 11a to 11d based on the moving distance of each of the sub-effect display devices 11a to 11d. Update the data.

  As shown in FIG. 7A, when the sub-effect display devices 11a to 11d are at the overlapping positions overlapping the main effect display device 9, each second drawing area in the main frame buffer also overlaps the first drawing area. The overlapping position is set (see FIG. 7B). Further, as shown in FIG. 8A, when each of the sub-effect display devices 11a to 11d is at a non-overlapping position that does not overlap with the main effect display device 9, each second drawing area in the main frame buffer is also the first drawing area. Is set to a non-overlapping position that does not overlap (see FIG. 8B).

  As shown in FIG. 10A, in the cooperative performance, after effect processing is performed in the main frame buffer, each sub image data in each second drawing area in the main frame buffer is stored in each storage area in the sub frame buffer. Re-replication (see FIG. 13C). When each sub-image data is re-replicated from the main frame buffer to the sub-frame buffer, a process of rotating each sub-image data by a predetermined angle in the opposite direction to that when the sub-frame buffer is replicated from the main frame buffer. Is supposed to do.

  In the present embodiment, when each sub image data is re-replicated, the sub image data stored in the second drawing area arranged at the upper left of the first drawing area of the main frame buffer is 45 ° clockwise. The sub image data rotated at an angle and re-replicated to the storage area of the sub-frame buffer and stored in the second drawing area arranged at the upper right of the first drawing area of the main frame buffer is 45 ° counterclockwise. The sub image data rotated by the angle and re-replicated in the storage area of the sub-frame buffer and stored in the second drawing area arranged at the lower left of the first drawing area of the main frame buffer is 45 ° counterclockwise. The sub-image data that is rotated at an angle, reproduced again in the storage area of the sub-frame buffer, and stored in the second drawing area arranged at the lower right of the first drawing area of the main frame buffer. But it is re-replicated is rotated at an angle of 45 ° clockwise in the storage area of the sub-frame buffer (see Figure 10 (b)).

  As shown in FIGS. 10A and 10B, when each sub-image data is re-replicated, a rectangular range around the second drawing area is set as a duplication range in the main frame buffer. Then, the sub image data is rotated for each duplication range and re-duplicated in the sub frame buffer. By doing in this way, in the main frame buffer, it is compared with a case where only each second drawing area rotated by a predetermined angle is re-replicated according to the physical rotation state of each of the sub-effect display devices 11a to 11d. Thus, the designation of the X value and Y value necessary for re-duplication in the main frame buffer, that is, the memory address of the SDRAM 210 is simplified.

  As shown in FIG. 10B, the sub-image data including the duplication range re-duplicated from the main frame buffer is enlarged to the original size before being reduced to the main frame buffer and duplicated (higher resolution). ) And re-replicated (see FIG. 13E). In addition, the sub image data including the duplication range is arranged such that the storage areas for storing the sub image data are separated from each other by a predetermined distance (empty drawing area) so that the duplication ranges of the sub frame buffer do not overlap each other. Is done. In this way, when the sub image data read from the second drawing area of the main frame buffer is reversely rotated by a predetermined angle and stored in the storage area, the mutual storage area and the duplication range in the rotation range are Since interference can be avoided, it is possible to prevent an inappropriate error image from being displayed on each of the sub-effect display devices 11a to 11d. In addition, even if the copy range includes a part of the main image data drawn in the first drawing area of the main frame buffer, the storage areas have predetermined predetermined values so that the copy ranges do not overlap. By disposing them at a distance (empty drawing area), there is no possibility that a part of the main image data included in the replication range around one storage area will interfere with another storage area.

  As shown in FIG. 11, the sub-image data A to D stored in each storage area of the sub-frame buffer are divided in the X-axis direction (lateral direction) by the drawing control unit 206 of the VDP 262, and the X-axis direction Image data (configuration data) arranged in the Y-axis direction (vertical direction) for each dot is generated. In FIG. 11, in order to help understanding, the width in the X-axis direction is enlarged and divided as image data of each column (for example, sub image data A is from A1 column to A12 column). In an actual embodiment, the image data is divided as image data of each row arranged in the Y-axis direction one dot at a time (each sub-image data is divided into 480 equal one dots in the X-axis direction). Have been).

  The drawing control unit 206 of the VDP 262 sequentially arranges the image data of each column divided from each of the sub image data A to D in the readout direction (X-axis direction) in the composite image storage area, and stores the composite image. The output image data Z is generated by being stored in the area. In this embodiment, the image data of the A1 column divided from the sub image data A, the image data of the C1 column divided from the sub image data C, the image data of the B1 column divided from the sub image data B, the sub The image data of each column of the sub-image data A to D is stored in the composite image storage area in the order of the image data of the D1 column divided from the image data D (see FIG. 13F).

  As shown in FIG. 12B, the size of the output image data Z stored in the composite image storage area is 1920 dots in the X-axis direction (horizontal direction) and 234 dots in the Y-axis direction (vertical direction). ing. That is, the output image data Z has an image size obtained by combining four pieces of sub image data A to D. Then, as shown in FIG. 12 (a), the output image data Z is subjected to color tone correction as described above, and then the signal separation board 220 (see FIG. 5) from the sub display system output unit SK of the VDP 262. (See FIG. 13G). The main image data stored in the first drawing area of the main frame buffer described above is directly read out from the first drawing area and output from the main display system output unit MK of the VDP 262 toward the main effect display device 9. Is done. The main effect display device 9 displays the main image data directly received from the VDP 262 on the display unit (see FIG. 13D).

  As shown in FIG. 12A, when the output image data Z is output from the sub-display system output unit SK of the VDP 262, one dot data is output in the X-axis direction (lateral direction). Then, the output image data Z input to the signal separation substrate 220 one dot at a time is alternately distributed by the primary separation circuit 221 of the signal separation substrate 220 and separated into two systems, and each secondary separation circuit 222a, It is output toward 222b. That is, the output image data Z is output after being separated for each period of a predetermined frequency.

  Here, out of the 1-dot data in each row of the output image data Z arranged in the X-axis direction, 1-dot data (sub-image data A and C data) in which the X-axis is an odd row is one secondary separation. One-dot data (sub-image data B and D data) whose X-axis is an even-numbered column is output to the circuit 222a, and is output to the other secondary separation circuit 222b (see FIG. 5).

  Thus, by separating the image data of each of the sub-effect display devices 11a to 11d, the dot clock value output from the VDP 262 has a frequency of 40 MHz, and the data signal is output from the primary separation circuit 221. The value is converted into a data signal having a frequency of 20 MHz (1/2 division).

  Further, the image data composed of the data signal input to one of the secondary separation circuits 222a is defined as separated image data V (image data obtained by combining the sub image data A and C), and the other secondary separation circuit 222b. When image data composed of input data signals is described as separated image data W (image data obtained by combining sub-image data B and D), the sizes of the separated image data V and W are in the X-axis direction (lateral Direction) and 234 dots in the Y-axis direction (vertical direction). That is, the size of each separated image data V and W is an image size obtained by combining two sub image data.

  Further, when the separated image data V and W are output from the secondary separation circuits 222a and 222b, they are alternately distributed and separated by the secondary separation circuits 222a and 222b. That is, of the 1-dot data of each row arranged in the X-axis direction of the separated image data V output from one secondary separation circuit 222a, 1-dot data whose X-axis is an odd-numbered row (data of sub-image data A) Is output to one transmission circuit 223a, and 1-dot data (sub-image data B data) whose X-axis is an even-numbered column is output to another transmission circuit 223b. That is, the separated image data V is separated and output every cycle of a predetermined frequency.

  Similarly, among the 1-dot data of each row arranged in the X-axis direction of the separated image data W output from the other secondary separation circuit 222b, 1-dot data (sub-image data C Data) is output to one transmission circuit 223c, and 1-dot data (data of sub-image data D) whose X-axis is an even-numbered column is output to another transmission circuit 223d. That is, the separated image data W is separated and output for each cycle of the predetermined frequency.

  In addition, the image size of each of the sub image data A to D at the stage of output from each of the secondary separation circuits 222a and 222b is similar to the image size stored in each storage area of the sub frame buffer (in the X-axis direction (horizontal). Direction) and 234 dots in the Y-axis direction (vertical direction).

  The data signal with a dot clock value of 20 MHz output from the primary separation circuit 221 is converted into a data signal with a dot clock value of 10 MHz at the stage of output from each of the secondary separation circuits 222a and 222b. (1/2 division).

  The sub image data A to D transmitted from the transmission circuits 223a to 223d are received by the reception circuits 224a to 224d of the sub effect display devices 11a to 11d. Furthermore, each sub production | presentation display apparatus 11a-11d displays each received sub image data AD on a display part (refer FIG.13 (h)). Each of the sub image data A to D input to the sub effect display devices 11a to 11d is a data signal having a dot clock value of 10 MHz, and as described above, each of the sub effect display devices 11a to 11d. Since the dot clock value corresponds to a data signal having a frequency of 10 MHz, each received sub-image data A to D can be displayed.

  Next, with reference to FIG. 14, the case where a cooperation effect is not performed by the main effect display apparatus 9 and the sub effect display apparatuses 11a-11d is demonstrated. In the example of FIG. 13, when performing a collaborative effect, each sub-image data drawn in each storage area of the sub-frame buffer is duplicated in the main frame buffer, and the effect used for the collaborative effect in this main frame buffer. When the image data is drawn but the cooperation effect is not performed, the step of copying each sub image data of the sub frame buffer to the main frame buffer, and each sub image data copied to the main frame buffer The step of re-duplicating the data into the subframe buffer is omitted.

  As shown in FIG. 14, when the collaborative effect is not performed, first, main image data is drawn in the first drawing area of the main frame buffer (see FIG. 14A). The main image data stored in the first drawing area of the main frame buffer is output from the main display system output unit MK of the VDP 262 toward the main effect display device 9, and the main effect display device 9 Is displayed on the display unit (see FIG. 14D).

  Further, the sub image data A to D are drawn in the storage areas of the sub frame buffer, and the sub image data A to D stored in the storage areas of the sub frame buffer are arranged in the X-axis direction (horizontal direction). Image data (configuration data) divided and arranged in the Y-axis direction (vertical direction) for each dot in the X-axis direction is generated (see FIG. 14B). Then, the image data of each column divided from each of the sub image data A to D is sequentially arranged in the reading direction (X-axis direction) in the composite image storage area, stored in the composite image storage area, and output image Data Z is generated (see FIG. 14F).

  The output image data Z is output from the sub display system output unit SK of the VDP 262 toward the signal separation board 220 (see FIG. 5) after color correction (see FIG. 14G). Then, the output image data Z is divided into sub image data A to D by the signal separation board 220, and the sub image data A to D are transmitted to the sub effect display devices 11a to 11d. And each sub production | presentation display apparatus 11a-11d displays each received sub image data AD on a display part (refer FIG.14 (h)).

  FIG. 15 is an example showing a drawing order (in the case where a spare virtual drawing area is used) in the case of performing a collaboration effect. In the example of FIG. 13, main image data displayed on the main effect display device 9 is first drawn in the first drawing area of the main frame buffer. In this example, the first drawing area is drawn. Before the main image data is stored in the main image data, the main image data is drawn in the preliminary virtual drawing area.

  As shown in FIG. 15, in this example, a spare virtual drawing area in which main image data is drawn is provided. This spare virtual drawing area includes a main frame buffer, a subframe buffer, and a composite image in a VRAM area. Allocated with storage area. In the preliminary virtual drawing area, the total number of pixels that can store pixel data having the same size as the first drawing area of the main frame buffer is allocated to the memory area. Then, the main image data drawn in the spare virtual drawing area is duplicated in the first drawing area of the main frame buffer (see FIG. 15A).

  Each sub image data A to D is drawn in each storage area of the sub frame buffer, and each sub image data A to D stored in each storage area of the sub frame buffer is used as each second drawing of the main frame buffer. It is reduced to an area and duplicated (see FIG. 15B). Then, effect processing for drawing the effect image data used for the cooperation effect is performed in the main frame buffer (see FIG. 15C).

  Further, after effect processing is performed in the main frame buffer, each sub image data in each second rendering area in the main frame buffer is enlarged and re-replicated in each storage area in the sub frame buffer (FIG. 15E). reference). Then, the sub image data A to D stored in the storage areas of the sub frame buffer are divided, and the image data of the divided columns are sequentially read in the readout direction (X-axis direction) in the composite image storage area. The image data Z for output is generated by being arranged and stored in the composite image storage area (see FIG. 15F).

  The output image data Z is output from the sub display system output unit SK of the VDP 262 toward the signal separation board 220 (see FIG. 5) after color correction (see FIG. 15 (g)). The output image data Z is divided into sub image data A to D by the separation substrate 220, and the sub image data A to D are transmitted to the sub effect display devices 11a to 11d to display the sub effect display. The devices 11a to 11d display the received sub image data A to D on the display unit (see FIG. 15 (h)).

  The main image data stored in the first drawing area of the main frame buffer is output from the main display system output unit MK of the VDP 262 toward the main effect display device 9, and the main effect display device 9 outputs the main image data. It is displayed on the display unit (see FIG. 15D).

  This example is an embodiment that is particularly effective when the main effect display device 9 is physically rotated. For example, in the preliminary drawing area, the main image data is drawn in a state similar to the state where the main effect display device 9 is not physically rotated, and then the physical effect display device 9 is brought into a physical rotation state. Accordingly, the main image data drawn in the preliminary drawing area is copied to the main frame buffer set in a state rotated by a predetermined angle, and the effect processing is performed together with the sub image data. By doing so, it is possible to simplify processing such as designation of a pixel position when processing main image data in the preliminary drawing region.

  Next, processing contents of each image data displayed on each of the sub-effect display devices 11a to 11d and each of the sub-effect display devices 11a to 11d will be described in detail with reference to FIGS. In order to simplify the description, the drawing order in the case where the cooperation effect is not performed will be described as an example (see FIG. 14), but it is needless to say that the drawing order is applicable even when the cooperation effect is performed.

  As shown in FIG. 16A, the total number of pixels of the sub-effect display devices 11a to 11d is 800 dots in the X-axis direction (horizontal direction) and 480 dots in the Y-axis direction (vertical direction). The size of the original image of the sub image data A to D displayed on the sub effect display devices 11a to 11d is 400 dots (pixels) in the X axis direction (horizontal direction) and 240 dots in the Y axis direction (vertical direction). (Pixel) (see FIG. 16B).

  As shown in FIG. 16B, when the original images of the sub image data A to D are drawn in the storage areas of the sub frame buffer, the sub image data A to D in the Y-axis direction (vertical direction). Draw with the number of dots doubled. Each storage area of this subframe buffer is 400 dots in the X-axis direction (horizontal direction) and 480 dots in the Y-axis direction (vertical direction). Then, the sub image data A to D stored in the storage areas of the sub frame buffer are divided, and the image data of the divided columns are sequentially read in the readout direction (X-axis direction) in the composite image storage area. The output image data Z is generated by being arranged and stored in the composite image storage area.

  Here, the size of the output image data Z stored in the composite image storage area is 1600 dots in the X-axis direction (horizontal direction) and 480 dots in the Y-axis direction (vertical direction). That is, the output image data Z has an image size obtained by combining four pieces of sub image data A to D.

  Note that the size of a general high-definition image is 1920 dots in the X-axis direction (horizontal direction) and 1080 dots in the Y-axis direction (vertical direction). When the size is 800 dots in the X-axis direction (horizontal direction) as in the total number of pixels of the sub-effect display devices 11a to 11d, the output image is a combination of four pieces of sub-image data A to D. The image size of the data Z becomes 3200 dots, which exceeds 2050 dots that can normally be controlled (mapped) in the X-axis direction (horizontal direction), making it impossible to use a general-purpose VDP. However, since the output image data Z has the above-described image size, it is possible to use a generally distributed VDP corresponding to a high-definition image. Therefore, it is possible to procure the VDP at a low cost.

  As shown in FIG. 17A, the output image data Z is output from the sub display system output unit SK of the VDP 262 toward the signal separation board 220 (see FIG. 5). Then, the output image data Z input to the signal separation board 220 is alternately distributed by the primary separation circuit 221 of the signal separation board 220 and separated into two systems, toward the secondary separation circuits 222a and 222b. Is output (see FIG. 5).

  The data signal with a dot clock value of 40 MHz output from the VDP 262 is converted into a data signal with a dot clock value of 20 MHz at the stage of output from the primary separation circuit 221.

  Further, the image data composed of the data signal input to one secondary separation circuit 222a is defined as separated image data V (image data obtained by combining the sub image data A and C), and the other secondary separation circuit 222b. When image data composed of input data signals is described as separated image data W (image data obtained by combining sub-image data B and D), the sizes of the separated image data V and W are in the X-axis direction (lateral Direction) and 800 dots in the Y-axis direction (vertical direction). That is, the size of each of the separated image data V and W is an image size obtained by combining two sub image data (see FIG. 17B).

  Further, when the separated image data V and W are output from the secondary separation circuits 222a and 222b, they are alternately distributed and separated by the secondary separation circuits 222a and 222b.

  In addition, the image size of each of the sub image data A to D at the stage of output from each of the secondary separation circuits 222a and 222b is similar to the image size stored in each storage area of the sub frame buffer (in the X-axis direction (horizontal). Direction) and 400 dots in the Y-axis direction (vertical direction) (see FIG. 17B).

  The data signal having a dot clock value of 20 MHz output from the primary separation circuit 221 is converted into a data signal having a frequency of 10 MHz dot clock value at the stage of output from each of the secondary separation circuits 222a and 222b. . Further, when the data signals output from the secondary separation circuits 222a and 222b are output from the transmission circuits 223a to 223d (see FIG. 5), the frequency of the data signal is doubled (one pixel signal is converted into one pixel signal). Doubling to two pixel signals). As a specific method, each of the transmission circuits 223a to 223d inputs 20 MHz which is twice as an operation clock (transmission timing clock), and outputs the same two signals as the input one signal. As a result, the data signal for one pixel becomes a data signal for two pixels expanded in the X-axis direction (lateral direction).

  The sub image data A to D transmitted from the transmission circuits 223a to 223d are received by the reception circuits 224a to 224d of the sub effect display devices 11a to 11d. Here, each of the sub-effect display devices 11a to 11d corresponds to a data signal having a frequency of a dot clock value of 20 MHz as the number of display pixels is large. And as above-mentioned, in each sub production | presentation display apparatus 11a-11d which received the data signal output from each transmission circuit 223a-223d and frequency doubled, each sub image data AD is X-axis direction ( (Horizontal direction) is displayed in a state of being doubled. Each of the sub image data A to D is an image of 800 dots in the X-axis direction (horizontal direction) and 480 dots in the Y-axis direction (vertical direction), like the total number of pixels of the sub-effect display devices 11a to 11d. Displayed in size.

  Referring to FIG. 18 in detail, each of the transmission circuits 223a to 223d transmits the secondary image data A to D to the secondary separation circuits 222a and 222b when transmitting one dot at a time in the X-axis direction (horizontal direction). When transmitting a 1-dot data signal among the data signals of the sub-image data A to D having a frequency of 10 MHz, the dot clock value output from (see FIG. 18A), the dot clock value is 20 MHz. Double to frequency. Then, the data signal for one pixel is input to the sub-effect display devices 11a to 11d as the data signal for two pixels expanded in the X-axis direction (lateral direction) (see FIG. 18B). ).

  For example, when the 1-dot data signal input from the secondary separation circuits 222a and 222b to the transmission circuits 223a to 223d is a red 1-dot data signal (see FIG. 18C), The frequency is doubled at the stage of transmission from the transmission circuits 223a to 223d, and a red one-dot data signal is continuously input twice to the sub-effect display devices 11a to 11d (FIG. 18 ( d)). Further, data from each secondary separation circuit 222a, 222b to each secondary separation circuit 222a, 222b, one dot for each color, such as one yellow dot, one orange dot, one pink dot, and so on. When a signal is input to each transmission circuit 223a to 223d, each transmission circuit 223a to 223d has two dots for each color, such as two yellow dots, two orange dots, two pink dots, and so on. Are transmitted to the sub-effect display devices 11a to 11d. That is, in each of the sub effect display devices 11a to 11d, the received sub image data A to D are displayed in a state where the number of dots in the X-axis direction (horizontal direction) is doubled.

  Next, the operation of the pachinko gaming machine 1 will be described. When power is supplied to the pachinko gaming machine 1 and power supply is started, the input level of the reset terminal to which the reset signal is input becomes high level, and the game control microcomputer 156 (specifically, the CPU 56). After executing a security check process that is a process for confirming whether or not the content of the program is valid, a main process (not shown) after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). After initialization of the built-in device (CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits)) is performed (step S4), the RAM is accessible (Step S5). In the interrupt mode 2, the address synthesized from the value (1 byte) of the specific register (I register) built in the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is This mode indicates an interrupt address.

  Next, the CPU 56 checks the state of the output signal (clear signal) of a clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S10 to S15).

  If the clear switch is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  When it is confirmed that the power supply stop process has been performed, the CPU 56 performs data check of the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 returns the internal state of the game control means (CPU) 56 and the control state of the electrical component control means such as the effect control means (effect control CPU) 86 to the state when the power supply is stopped. Game state recovery processing (steps S41 to S43) for the purpose. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents remain as they are in the portion of the work area that should not be initialized. The part that should not be initialized is, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, probability variation flag, time reduction flag, etc.), and the area where the output state of the output port is saved (output port buffer) ), A portion in which data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 transmits a power failure recovery designation command as an initialization command at the time of power supply recovery (step S43). Then, the process proceeds to step S14. In this embodiment, the CPU 56 also transmits, to the effect control board 80, a total pending storage number designation command in which the value of the total pending storage number counter stored in the backup RAM is set in step S43.

  In this embodiment, it is confirmed whether the data in the backup RAM area is stored using both the backup flag and the check data. However, only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The RAM clear process initializes predetermined data (for example, count value data of a counter for generating a random number for normal symbol determination) to 0, but an arbitrary value or a predetermined value It may be initialized to. In addition, the entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a random number for normal symbol determination) may be left as it is. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing in steps S11 and S12, for example, a normal symbol per-determination random number counter, a special symbol buffer, a total award ball number storage buffer, a special symbol process flag, and other flags for selectively performing processing according to the control state are initialized. Value is set.

  Further, the CPU 56 is an initialization designation command for initializing a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 156 has executed initialization processing). Is transmitted to the sub-board (step S13). For example, when the effect control microcomputer 81 receives the initialization designation command, the main effect display device 9 performs screen display for informing that the control of the gaming machine has been initialized, that is, initialization notification. .

  Further, the CPU 56 executes a random number circuit setting process for initial setting of the random number circuit 503 (step S14). For example, the CPU 56 performs setting according to the random number circuit setting program to cause the random number circuit 503 to update the value of the random R.

  In step S15, the CPU 56 sets a CTC register built in the game control microcomputer 156 so that a timer interrupt is periodically generated every predetermined time (for example, 2 ms). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining a stop symbol of a special symbol when it is not a big hit, or a random number for determining whether to reach when it is not a big hit, The random number update process is a process for updating the count value of a counter for generating a display random number. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. In this embodiment, the initial value random number determines the initial value of the count value of a counter for generating a random number for determining whether or not to win a normal symbol (ordinary random number generation counter for normal symbol determination). It is a random number to do. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 156 controls itself a game device such as an effect display device, a variable winning ball device, a ball payout device, etc. provided in the gaming machine. In the process of transmitting a command signal to be controlled by another microcomputer, or a game machine control process), the count value of the random number for determination per normal symbol is one round (the random number for determination per normal symbol is taken). When the value is incremented by the number of values between the minimum value and the maximum value of the possible values), an initial value is set in the counter.

  In this embodiment, the reach effect is executed using an effect symbol (decorative symbol) variably displayed on the main effect display device 9. Further, when the display result of the special symbol is a jackpot symbol, the reach effect is always executed. When the display result of the special symbol is not a jackpot symbol, the game control microcomputer 156 determines whether or not to execute the reach effect by lottery using a random number. However, it is the production control microcomputer 81 that actually executes the reach production control.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S20 to S34 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S20). The power-off signal is output, for example, when a power supply monitoring circuit mounted on the power supply board detects a decrease in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals from the gate switch 32a, the first start port switch 14a, the second start port switch 14b, and the count switch 23 are input via the input circuit 58, and their state is determined (switch processing: step S21). .

  Next, the CPU 56 performs display control to perform display control of the first special symbol display 8a, the second special symbol display 8b, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41. Processing is executed (step S22). About the 1st special symbol display 8a, the 2nd special symbol display 8b, and the normal symbol display 10, a drive signal is output with respect to each display according to the content of the output buffer set by step S32, S33. Execute control.

  In addition, a process of updating the count value of each counter for generating each random number for determination such as a random number for determination per ordinary symbol used for game control is performed (determination random number update process: step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process, corresponding processing is executed in accordance with a special symbol process flag for controlling the first special symbol indicator 8a, the second special symbol indicator 8b, and the big prize opening in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S27). In the normal symbol process, the CPU 56 executes a corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 81 (effect control command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the first start port switch 14a, the second start port switch 14b, and the count switch 23 (step S30). Specifically, the payout control micro mounted on the payout control board 37 in response to winning detection based on any of the first start port switch 14a, the second start port switch 14b and the count switch 23 being turned on. A payout control command (prize ball number signal) indicating the number of prize balls is output to the computer. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. Is output to the output port (step S31: output process).

  Further, the CPU 56 performs a special symbol display control process for setting special symbol display control data for effect display of special symbols in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S32). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 outputs a drive signal in step S22 in accordance with the display control data set in the output buffer, whereby the first special symbol on the first special symbol display 8a and the second special symbol display 8b and Variable display of the second special symbol is executed.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S33). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 in accordance with the display control data set in the output buffer.

  Thereafter, the interrupt permission state is set (step S34), and the process is terminated.

  With the above control, in this embodiment, the game control process is started every 2 ms. The game control process corresponds to the processes in steps S21 to S33 (excluding step S29) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed in the main process. It may be executed.

  When the lost symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b and the main effect display device 9, the variable display state of the effect symbol is started after the effect symbol variable display is started. May not reach the reach state, and a predetermined combination of effect symbols that do not become reach may be stopped and displayed. Such a variable display mode of the effect symbol is referred to as a variable display mode of “non-reach” (also referred to as “normal loss”) when the variable display result is a losing symbol.

  When the lost symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b and the main effect display device 9, the variable display state of the effect symbol is started after the effect symbol variable display is started. After reaching the reach state, a reach effect is executed, and a combination of predetermined effect symbols that do not eventually become a jackpot symbol may be stopped and displayed. Such a variable display result of the effect design is referred to as a variable display mode of “reach” (also referred to as “reach lose”) when the variable display result is “losing”.

  In this embodiment, when the big hit symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b, the reach effect is executed after the variable display state of the effect symbol becomes the reach state. Eventually, the effect symbols are all stopped and displayed in the “left”, “middle”, and “right” symbol display areas of the main effect display device 9.

  When a predetermined symbol (predetermined symbol corresponding to the type of small hit) is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b, in the main effect display device 9, As in the case where the variable display mode of the effect symbol is “probability big hit B” to be described later, after the variable display of the effect symbol is performed, a predetermined small hit symbol (the same symbol as the probability change big hit B symbol. For example, “355”, etc. ) May be stopped. The display effect on the main effect display device 9 corresponding to the fact that a predetermined symbol (symbol) as a small hit symbol is stopped and displayed on the first special symbol indicator 8a or the second special symbol indicator 8b is “small hit”. This is called a variable display mode.

  FIG. 20 is a flowchart showing an example of a special symbol process (step S26) program executed by the game control microcomputer 156 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the first special symbol display 8a or the second special symbol display 8b and the special winning opening is executed. In the special symbol process, if the first start port switch 14a for detecting that the game ball has won the first start port 15a is turned on, that is, the start winning to the first start port 15a is made. If it has occurred, the first start port switch that determines whether the winning is a super hit or the super reach in the variation display corresponding to the start winning, and transmits a start winning determination result specifying command including the determination result A passing process is executed (steps S311 and S312). If the second start port switch 14b for detecting that the game ball has won the second start port 15b is turned on, that is, if a start win to the second start port 15b has occurred, A determination is made as to whether or not a big win or super reach is reached, and a second start-port switch passing process for transmitting a start winning determination result specifying command including the determination result is executed (steps S313 and S314). Then, any one of steps S300 to S310 is performed. If the first start winning port switch 13a or the second start port switch 14b is not turned on, any one of steps S300 to S310 is performed according to the internal state.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 156 is in a state where variable display of a special symbol can be started, the game control microcomputer 156 checks the number of numerical data stored in the reserved storage number buffer (total number of reserved storage). The stored number of numerical data stored in the pending storage number buffer can be confirmed by the count value of the total pending storage number counter. If the count value of the total pending storage number counter is not 0, it is determined whether or not the display result of the variable display of the first special symbol or the second special symbol is a big hit. In case of big hit, set big hit flag. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The jackpot flag is reset when the jackpot game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol. Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result designation command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result designation command to the effect control microcomputer 81 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S304 (4 in this example).

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. The variable display on the first special symbol display 8a or the second special symbol display 8b is stopped, and the stop symbol is derived and displayed. In addition, control for transmitting a symbol confirmation designation command to the effect control microcomputer 81 is performed. If the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the small hit flag is set, the internal state (special symbol process flag) is updated to a value (8 in this example) corresponding to step S308. If neither the big hit flag nor the small hit flag is set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (in this example, 0). The effect control microcomputer 81 controls the main effect display device 9 to stop the effect symbol when the symbol confirmation designation command transmitted by the game control microcomputer 156 is received.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting an effect control command for a round display during the big hit gaming state to the effect control microcomputer 81, a process for confirming the establishment of the closing condition of the big prize opening, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control for causing the production control microcomputer 81 to perform display control for notifying the player that the big hit gaming state has ended is performed. In addition, a process for setting a flag indicating a gaming state (for example, a probability change flag or a time reduction flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the pre-opening process for small hits, control is performed to open the big prize opening. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S309 (9 in this example). It should be noted that the small hit pre-release process is executed for each round, but when the first round is started, the small hit pre-release process is a process for starting the small hit game.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. Processing to confirm the establishment of the closing condition of the big prize opening is performed. If the closing condition for the big prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value corresponding to step S308 (8 in this example). When all rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end process (step S310): executed when the value of the special symbol process flag is 10. Control for causing the production control microcomputer 81 to perform display control for notifying the player that the small hit gaming state has ended is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Next, the operation of the effect control board 80 will be described. FIG. 21 is a flowchart showing a main process executed by the effect control microcomputer 81 (specifically, the effect control CPU 86) mounted on the effect control board 80. The effect control CPU 86 starts executing the main process when the power is turned on. In the main process, the effect control CPU 86 first clears the RAM area, sets various initial values, and initializes a timer to determine the activation control activation interval (for example, 2 ms). (Step S700).

  In the initialization process, the effect control CPU 86 performs the timing of the V sync that is the start timing of the frame period of the main effect display device 9 and the timing of the V sync that is the start timing of the frame period of the sub-effect display devices 11a to 11d. To match. For example, the effect control CPU 86 instructs the VDP 262 to start V sync that is the start timing of the frame period of the main effect display device 9, and V sync that is the start timing of the frame period of the sub-effect display devices 11a to 11d. At the same time. Further, the effect control CPU 86 starts a timer (not shown).

  Thereafter, the effect control CPU 86 performs a restoration process (step S700a). As described above, the CPU interface 201 outputs a V blank interrupt signal to the effect control CPU 86 every time the V blank corresponding to the sub effect display devices 11a to 11d is started. For example, the effect control CPU 86 starts a timer (not shown) at the timing when the V blank interrupt signal is input, and thereafter, when the value of the timer becomes a value corresponding to a predetermined time, in other words, V blank. When an interrupt signal is not input for a predetermined time or longer, a recovery process is performed. The predetermined time is longer than the frame period, and is, for example, 1/30 second that is twice the frame period.

  In the restoration process, the effect control CPU 86 restarts the main effect display device 9, the sub effect display devices 11a to 11d, and the VDP 262. For example, the effect control CPU 86 performs control to stop power supply to the main effect display device 9, the sub effect display devices 11a to 11d, and the VDP 262, and then supply the power again. The effect control CPU 86 may restart only the main effect display device 9 and the sub-effect display devices 11a to 11d, or may restart only the VDP 262.

  Thereafter, the effect control CPU 86 executes a random number update process for updating the count value of the counter for generating a random number such as a jackpot symbol determining random number (step S701).

  Thereafter, the process proceeds to a loop process for monitoring the timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 86 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 86 clears the flag (step S703) and executes the following effect control process. If no timer interrupt has occurred, the random number update process of step S701 is performed, and the process returns to step S702 again.

  In the effect control process, the effect control CPU 86 first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S704). Next, the effect control CPU 86 performs effect control process processing (step S705). Thereafter, the process proceeds to step S701. In the effect control process, a process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the main effect display device 9 is executed.

  The effect control command transmitted from the game control microcomputer 156 is received by an interrupt process based on the effect control INT signal and stored in a buffer area formed in the RAM. In the command analysis process, which command is the effect control command stored in the buffer area is analyzed.

  Further, in addition to the processing of steps S703 to S705, the reserved memory display for displaying the storage status of the number of reserved memories displayed on the special symbol storage memory display 18 set in the display area of the main effect display device 9 You may make it implement the pending | holding memory | storage display control process for controlling the display of an area | region. It should be noted that in this on-hold storage display control process, it is determined from the start winning time determination result designation command transmitted in the first start port switch passing process or the second start port switch passing process described above that it will be a super reach or a big hit. By changing the display of the reserved memory to a special display mode different from the normal display mode with a predetermined probability, it is predicted that there is a high possibility that the variable display corresponding to the reserved memory will be a super reach or a big hit. You may make it implement the process for performing the prefetch notice effect to perform.

  In addition, similar to these pre-reading notice effects, it is highly likely that a super-reach or a big hit will occur in the variable display corresponding to the reserved memory, and the variable display multiple times before the variable display corresponding to the reserved memory is performed. In addition, for example, the prefetching continuous notice process for carrying out the prefetching continuous notice that is notified by performing a countdown display or the like may be performed in addition to the processes of steps S703 to S705.

  FIG. 22 is a flowchart showing the effect control process (step S705) in the effect control main process shown in FIG. In the effect control process, the effect control CPU 86 performs any one of steps S450 to S456 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the main effect display device 9 is controlled and variable display of the effect symbol (decorative symbol) is realized, but the effect symbol (decorative symbol) synchronized with the variation of the first special symbol. The control regarding the variable display and the control regarding the variable display of the effect symbol (decoration symbol) synchronized with the change of the second special symbol are executed in one effect control process.

  Fluctuation pattern command reception waiting process (step S450): This process is executed when the value of the effect control process flag is zero. It is confirmed whether or not a variation pattern command is received from the game control microcomputer 156. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S451).

  Effect symbol variation start process (step S451): This process is executed when the value of the effect control process flag is 1. Control is performed so that the variation of the effect design (decoration design) is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S452).

  Effect symbol changing process (step S452): This process is executed when the value of the effect control process flag is 2. The switching timing of each fluctuation state (fluctuation speed) constituting the fluctuation pattern is controlled, and the end of the fluctuation time is monitored. Then, when the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S453). In addition, when the occurrence timing of reach is reached during the fluctuation, a screen for notifying the generation of reach to the main effect display device 9 and the sub-effect display devices 11a to 11d (for example, the reach notification screen shown in FIG. 7). Production control to display is performed.

  Effect symbol variation stop process (step S453): This process is executed when the value of the effect control process flag is 3. Based on the reception of the effect control command (design determination designation command) for instructing the stop of all symbols, control is performed to stop the variation of the effect symbol (decoration symbol) and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the hit display process (step S454) or the variation pattern command reception waiting process (step S450).

  Winning display process (step S454): executed when the value of the effect control process flag is 4. Effect control for displaying a screen (for example, a big hit notification screen shown in FIG. 8) for notifying the occurrence of a big hit or a small hit on the main effect display device 9 and the sub-effect display devices 11a to 11d after the end of the variation time. I do. Then, the value of the effect control process flag is updated to a value corresponding to the hit game process (step S455).

  Process during winning game (step S455): This process is executed when the value of the effect control process flag is 5. Control during big hit game or small hit game. For example, when a command for opening a special prize opening or a designation command after opening a special prize opening is received, display control of the number of rounds in the main effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the hit end effect process (step S456).

  Winning end effect process (step S456): executed when the value of the effect control process flag is 6. In the main effect display device 9, display control is performed to notify the player that the big hit gaming state or the small hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S450).

  In the present embodiment, when a small hit occurs, in Steps S454 to S456, by performing the same effect processing as when the probability changing big hit B occurs, the occurrence is shifted to the probability changing state. The player cannot determine whether the probability variation big hit B or the small hit that does not shift to the probability variation state has occurred.

  In the effect symbol variation start process, a message prompting the operation of the operation button 516 or the operation lever 600 is displayed as a notice effect that suggests the possibility of a big hit in the variation, and the operation is performed on the condition In addition, the setting for performing the operation advance notice effect for displaying any one of a plurality of characters having different degrees of expectation to be a big hit may be performed at a predetermined ratio.

  Next, a swap setting process performed by the effect control CPU 86 and a swap setting confirmation process performed by the VDP 262 at the time of image display performed in the above-described effect control process will be described.

  FIG. 23 is a flowchart showing swap setting processing in the effect control CPU 86.

  First, the effect control CPU 86 determines whether or not a V blank interrupt signal corresponding to the sub effect display devices 11a to 11d from the CPU interface 201 in the VDP 262 is input (step S711).

  When the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d is not input (step S711; No), a series of processing ends. On the other hand, when the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d is input (step S711; Yes), the effect control CPU 86 performs buffer A and buffer B configured in the VRAM area of the SDRAM 210. Control for drawing image data in any of the above (control for storing image data in either buffer A or buffer B) is performed (step S712).

  For example, a flag (drawing destination flag) indicating whether the drawing destination of the immediately preceding image data is the buffer A or the buffer B is set in the RAM 85. For example, the drawing destination flag is turned on when the drawing destination of the immediately preceding image data is the buffer A, and is turned off when the drawing destination of the immediately preceding image data is the buffer B. The effect control CPU 86 refers to the drawing destination flag, and when it is on, that is, when the drawing destination of the immediately preceding image data is the buffer A, it determines that the drawing destination of the image data is the buffer B and turns off. In other words, when the drawing destination of the immediately preceding image data is the buffer B, the drawing destination of the image data is determined as the buffer A. Further, the effect control CPU 86 outputs a drawing command (drawing command) designating the drawing destination of the image data to the system register 202 in the VDP 262. The drawing command is stored in the system register 202. When this drawing command is stored, the VDP 262 starts drawing processing of image data shown in FIG.

  Next, the effect control CPU 86 determines whether or not a V blank interrupt signal corresponding to the first sub effect display devices 11a to 11d is input after the drawing control is started (step S713).

  When the V blank interrupt signal corresponding to the first sub-effect display devices 11a to 11d is not input after the start of the drawing control (step S713; No), a series of processing ends. On the other hand, when the V blank interrupt signal corresponding to the first sub-effect display devices 11a to 11d is input after the drawing control is started (step S713; Yes), the effect control CPU 86 uses the buffer A or the buffer It is determined whether or not drawing of image data on B is completed (step S714).

  For example, the RAM 85 is provided with a counter that counts the number of input times of the V sink interrupt signal corresponding to the sub-effect display devices 11a to 11d. The effect control CPU 86 resets the value of this counter at a swap setting timing described later, and increments it by 1 at the timing when the V sink interrupt signal from the CPU interface 201 in the VDP 262 is input. When the value of this counter reaches 2, in other words, when the second V sync interrupt signal is input from the start of the drawing control, the effect control CPU 86 draws in the buffer A or the buffer B. Determine that completed. Alternatively, when a predetermined signal (drawing completion signal) is input at the timing when drawing of the image data from the CPU interface 201 in the VDP 262 is completed, the effect control CPU 86 receives the drawing completion signal. Then, it is determined that the drawing to the buffer A or the buffer B is completed.

  When the drawing to the buffer A or the buffer B has not been completed (step S714; No), a series of processing ends. On the other hand, when the drawing of the image data in the buffer A or the buffer B is completed (step S714; Yes), the effect control CPU 86 performs swap setting (step S715). For example, when image data drawing control is performed on the buffer A in the previous step S712, the effect control CPU 86 indicates that the image data should be output from the buffer A. Swap setting information which is a flag for turning off B is generated and output to the system register 202 in the VDP 262. When image data drawing control is performed on the buffer B in the previous step S712, the effect control CPU 86 indicates that the image data should be output from the buffer B. Swap setting information for turning B on is generated and output to the system register 202 in the VDP 262. The swap setting information is stored in the system register 202 and is updated each time new swap setting information is input. When the drawing destination flag described above is used, the drawing destination flag is updated from on to off or from off to on in step S715.

  As described above, when the drawing of the image data in the buffer A or the buffer B is completed in step S714, swap setting is performed in step S715. However, some interrupt processing is performed preferentially. There may be a case where the swap setting in step S715 is not performed. In such a case, the effect control CPU 86 performs swap setting when the V blank interrupt signal corresponding to the sub effect display devices 11a to 11d is input thereafter. At this time, the effect control CPU 86 generates swap setting information that should originally be set in step S715 and outputs the generated swap setting information to the system register 202 in the VDP 262. Even if the swap setting is performed in step S715, the effect control CPU 86 performs the swap setting when the V blank interrupt signal corresponding to the sub effect display devices 11a to 11d is input thereafter. You may go. At this time, the effect control CPU 86 generates swap setting information having the same content as that set in step S 715, and outputs it to the system register 202 in the VDP 262.

  FIG. 24 is a flowchart showing swap setting confirmation processing in the VDP 262.

  The display control unit 216 in the VDP 262 determines whether or not a V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d has been input since the start of drawing image data in the latest frame buffer ( Step S721). For example, the system register 202 is provided with a counter that counts the number of input times of the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d. The display control unit 216 resets the value of the counter every time image data drawing to the frame buffer is started, and increments the value by 1 at the timing when the V blank interrupt signal is input. When the value of this counter reaches 2, the drawing control unit 206 receives a V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d from the start of drawing image data on the latest frame buffer. It is determined that it has been input.

  If the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d has not been input after the start of drawing of the image data to the latest frame buffer (step S721; No), the series of operations ends. . On the other hand, when the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d is input after the start of drawing the image data to the latest frame buffer (step S721; Yes), the display control unit 216 Then, it is determined whether or not the standby time has elapsed from the input timing of the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d after the start of the drawing of the image data to the latest frame buffer (step) S722).

  The standby time is the time from the input timing of the V blank interrupt signal until the V sync interrupt signal corresponding to the sub effect display devices 11a to 11d is input, and the effect control CPU 86 has priority over the drawing control. This time is longer than the time required for the switch check interrupt process, which is an interrupt process by a periodically generated timer interrupt. The standby time is set to the dot clock value for each of the sub-effect display devices 11a to 11d, rather than the number of dots in the physical X-axis direction of the display unit for setting the frame period for the corresponding sub-effect display devices 11a to 11d. It is calculated by multiplying the total number of dots increased by the number of dots increased in the number of dots in the Y-axis direction, and adding these multiplication values. The display control unit 216 calculates the elapsed time from the timing when the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d is input after the start of drawing the image data to the latest frame buffer. When the standby time obtained by the above is reached, it is determined that the standby time has elapsed.

  When the standby time has not elapsed since the input timing of the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d after the start of the drawing of the image data to the latest frame buffer (step S722; No) The series of operations ends. On the other hand, when the standby time has elapsed from the input timing of the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d after the start of drawing the image data to the latest frame buffer (step S722; Yes). The display control unit 213 should output image data from either the buffer A or the buffer B based on the swap setting information in the system register 202, in other words, the buffer that is the output source of the image data. Is confirmed (step S723).

  Next, from the VDP 262, a frame period reset process in the effect control CPU 86, an image data drawing process in the VDP 262, and an image display performed in the above-described effect control process are performed in synchronization with the frame period. An image data output process for the main effect display device 9 and the sub effect display devices 11a to 11d will be described.

  FIG. 25 is a flowchart showing a frame cycle reset process in the effect control CPU 86.

  The effect control CPU 86 determines whether it is the reset timing of the V sink of the main image display device 9 (step S751). Specifically, determination by the following first method and second method is performed.

  In the first method, the effect control CPU 86 monitors the value of the timer activated in the initialization process of step S700 in FIG. 21, and when the timer value reaches a predetermined value, the main image display device 9 It is determined that this is the V sync reset timing. Here, the predetermined value is a value corresponding to the frame period of the sub-effect display devices 11a to 11d. Further, the effect control CPU 86 resets (restarts) the timer each time the V sink interrupt signal corresponding to the sub effect display devices 11a to 11d is input from the CPU interface 201.

  In the second method, the effect control CPU 86 receives the V sync reset timing of the main image display device 9 when the V sync interrupt signal corresponding to the sub effect display devices 11a to 11d is input from the CPU interface 201. It is determined that In this case, the effect control CPU 86 gives priority to the V sync interrupt signal over the other interrupt signals, and performs the processing from step S751 onward.

  When it is not the reset timing of the V sync of the main image display device 9 (step S751; No), the frame cycle reset process is ended. On the other hand, when it is the reset timing of the V sync of the main image display device 9 (step S751; Yes), the effect control CPU 86 resets the V sync corresponding to the main effect display device 9 (step S752). For example, the display control unit 213 calculates a frame period corresponding to the main effect display device 9 by multiplying the dot clock value by the number of dots for the frame period of the main effect display device 9. The display control unit 213 starts a timer (not shown) at the timing when the V sync is started, and every time corresponding to the value of the timer becomes an integral multiple of the frame period corresponding to the main effect display device 9. Further, the start timing of the frame period corresponding to the main effect display device 9 is specified, and the timing is set as the timing of V sync corresponding to the sub effect display devices 11a to 11d. In this case, the display control unit 213 resets the V sink corresponding to the main effect display device 9 by resetting the timer. Alternatively, for example, the effect control CPU 86 outputs a command (reset instruction command) instructing the VDP 262 to reset the V sink of the main image display device 9. When the reset instruction command is input, the drawing control unit 206 in the VDP 262 receives the dot clock value (40 MHz), the number of dots for the frame period of the main effect display device 9, and the sub effect set in the system register 202. One frame period is newly set for the main effect display device 9 based on the number of dots for each frame period of the display devices 11a to 11d.

  When the V sync corresponding to the main effect display device 9 is reset, the timings of the V sync corresponding to the main effect display device 9 and the V sync corresponding to the sub effect display devices 11a to 11d coincide. That is, the start timing of the frame period of the main effect display device 9 specified by the V sync corresponding to the main effect display device 9 and the sub effect display device 11a specified by the V sync corresponding to the sub effect display devices 11a to 11d. The start timing of the frame period of ˜11d matches.

  FIG. 26 is a flowchart showing image data drawing processing in the VDP 262.

  As described above, in step S712 of FIG. 23, the effect control CPU 86 outputs a drawing command (drawing command) designating the drawing destination of the image data to the system register 202 in the VDP 262. Stored in the register 202. When this drawing command is stored, the image data drawing process shown in FIG. 26 is started.

  First, the drawing control unit 206 in the VDP 262 determines whether or not a V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d has been input since the start of drawing image data in the latest frame buffer. (Step S801). For example, the system register 202 is provided with a counter that counts the number of input times of the V blank interrupt signal corresponding to the sub-effect display devices 11a to 11d. The drawing control unit 206 resets the value of the counter every time drawing of image data to the frame buffer is started, and increments the value by 1 at the timing when the V blank interrupt signal is input. When the value of this counter reaches 2, the drawing control unit 206 receives a V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d from the start of drawing image data on the latest frame buffer. It is determined that it has been input.

  If the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d has not been input after the start of drawing the image data to the latest frame buffer (step S801; No), the image data drawing process Ends.

  On the other hand, when the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d is input after the start of drawing the image data to the latest frame buffer (step S801; Yes), the drawing control unit 206 determines whether the image data rendering destination is the buffer A (step S802). For example, based on a drawing command stored in the system register 202, it is determined whether or not the drawing destination of the image data is the buffer A.

  When the drawing destination of the image data is the buffer A (step S802; Yes), the drawing control unit 206 draws the main image data corresponding to the main effect display device 9 in the buffer A. Further, the drawing control unit 206 draws the sub image data corresponding to the sub effect display devices 11a to 11d in the buffer A, and draws the output image data Z generated from the sub image data (step S803).

  On the other hand, when the drawing destination of the image data is not the buffer A (step S802; No), the drawing control unit 206 draws the main image data corresponding to the main effect display device 9 in the buffer B. In addition, the drawing control unit 206 draws sub image data corresponding to the sub effect display devices 11a to 11d in the buffer B, and draws output image data Z generated from the sub image data (step S804).

  By performing the image data drawing process in this way, the image data drawing to the buffer A and the image data drawing to the buffer B are performed every cycle twice the frame cycle of the sub-effect display devices 11a to 11d. Are performed alternately.

  FIG. 27 is a flowchart showing image data output processing from the VDP 262 to the main effect display device 9 and the sub effect display devices 11a to 11d.

  The display control unit 213 in the VDP 262 determines whether it is the timing of the V sync corresponding to the sub-effect display devices 11a to 11d (step S851). As described above, the system register 202 includes the dot clock value that is the output cycle of image data, the number of dots for the frame cycle of the main effect display device 9, and the number of dots for the frame cycle of the sub-effect display devices 11a to 11d. Is set. For each of the sub-effect display devices 11a to 11d, the display control unit 213 sets the dot clock value corresponding to the number of dots of the corresponding sub-effect display devices 11a to 11d in the X-axis direction (horizontal direction) and the Y-axis direction (vertical direction). ) And the multiplication values are further added to calculate the frame periods of the sub-effect display devices 11a to 11d. Further, the display control unit 213 starts a timer (not shown) at the timing when the V sync is started in step S700 of FIG. Further, the display control unit 213 makes a frame corresponding to the sub-effect display devices 11a to 11d each time the time corresponding to the timer value becomes an integral multiple of the frame period corresponding to the sub-effect display devices 11a to 11d. The start timing of the cycle is specified, and the timing is set as the timing of the V sync corresponding to the sub effect display devices 11a to 11d.

  If it is not the timing of the V sync corresponding to the sub-effect display devices 11a to 11d (step S851; No), the image data output process ends.

  On the other hand, when it is the timing of V sync corresponding to the sub-effect display devices 11a to 11d (step S851; Yes), the display control unit 213 indicates that the swap setting information confirmed in step S723 in FIG. It is determined whether or not ON and buffer B are OFF, in other words, whether or not output of image data from buffer A is designated (step S852).

  When the swap setting information indicates that the buffer A is on and the buffer B is off (step S852; Yes), the display control unit 213 moves from the buffer A toward the main effect display device 9 and the sub effect display devices 11a to 11d. Image data is output (step S853). Specifically, the display control unit 213 outputs the main image data in the buffer A to the main display system output unit MK, and outputs the output image data Z composed of the sub image data in the buffer A as the sub display system output. Output to the unit SK.

  On the other hand, if the swap setting information indicates that the buffer A is on and the buffer B is not off (step S852; No), the display control unit 213 moves from the buffer B toward the main effect display device 9 and the sub effect display devices 11a to 11d. Image data is output (step S854). Specifically, the display control unit 213 outputs the main image data in the buffer B to the main display system output unit MK, and outputs the output image data Z composed of the sub image data in the buffer B as the sub display system output. Output to the unit SK.

  FIG. 28 is a timing chart for drawing and outputting image data. FIG. 28A shows output of image data to the sub-effect display devices 11a to 11d, V sink and V of the sub-effect display devices 11a to 11d. FIG. 28B is a timing chart showing blanks, and FIG. 28B is a timing chart showing output of image data to the main effect display device 9, V sync and V blank of the main effect display device 9, and FIG. FIG. 28D is a timing chart showing V blank waiting and swap setting by the effect control CPU 86 and drawing in the buffer by the effect control CPU 86 and the VDP 262. is there.

  The effect control CPU 86 sets the dot clock value, the number of dots for the frame period of the main effect display device 9, and the number of dots for each frame period of the sub effect display devices 11a to 11d in the system register 202. At this time, the main effect display device 9 is set so that the frame period of the main effect display device 9 is longer than the frame period of the sub effect display devices 11a to 11d and longer than the inherent frame period of the main effect display device 9. Sets the number of dots for the frame period. As a result, as shown in FIG. 28B, the V sink of the main effect display device 9 is changed from the initial timing indicated by the dotted line to the timing after setting indicated by the alternate long and short dash line.

  On the other hand, as shown in FIGS. 28A and 28B, the display control unit 213 in the VDP 262 uses the dot clock value set in the system register 202 and each frame period of the sub-effect display devices 11a to 11d. When the V sync that is the start timing of the frame period of the sub-effect display devices 11a to 11d is calculated based on the number of dots, the frame period of the main effect display device 9 is reset, and the V sync timing that is the start timing Is made to coincide with the timing of V sync which is the start timing of the frame period of the sub-effect display devices 11a to 11d.

  As shown in FIG. 28D, the effect control CPU 86 and the drawing control unit 206 in the VDP 262 have V blank interrupt signals corresponding to the sub effect display devices 11a to 11d from the CPU interface 201 in the VDP 262. Each time is input twice, the drawing of the image data in the buffer A and the drawing of the image data in the buffer B are alternately repeated. When the drawing of the image data is finished, the effect control CPU 86 and the drawing control unit 206 wait for the V blank, that is, wait for the input of the V blank interrupt signal corresponding to the next sub-effect display devices 11a to 11d. It becomes a state. However, when the switch check interrupt process, which is an interrupt process by a periodically generated timer interrupt, which is executed in preference to the drawing control, is performed, buffer A or buffer after the switch check interrupt process Image data is drawn on B.

  As shown in FIG. 28D, the effect control CPU 86 starts the first sub effect display devices 11a to 11d after the effect control CPU 86 and the VDP 262 start drawing the image data in the buffer A or the buffer B. When a V blank interrupt signal corresponding to is input, swap setting is performed at the timing when drawing of image data in the buffer A or buffer B is completed. Further, the effect control CPU 86 performs swap setting when a V blank interrupt signal corresponding to the sub effect display devices 11a to 11d is input while waiting for the V blank.

  Further, the display control unit 213 in the VDP 262 receives a V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d after the start of drawing of image data in the latest buffer A or buffer B. In addition, the swap setting is confirmed at the timing when the standby time has elapsed since the second input of the V blank interrupt signal, and the buffer A or the buffer B indicated by the swap setting at each of the subsequent two V sync timings. The process of outputting image data from is performed.

  As described above, according to the present embodiment, when the V blank interrupt signal from the CPU interface 201 is input, the effect control CPU 86 performs the drawing control of the image data to the buffer A or the buffer B, and the drawing control is performed. A buffer to which the image data is to be output after the V blank interrupt signal corresponding to the first sub-effect display devices 11a to 11d after the start is input and the drawing of the image data in the buffer A or the buffer B is completed. Swap setting for designating A or buffer B is performed. On the other hand, the display control unit 213 in the VDP 262 receives the V blank interruption signal corresponding to the second sub-effect display devices 11a to 11d after the start of the latest drawing control, and further displays the second sub-effect display. After the standby time has elapsed from the input of the V blank interrupt signal corresponding to the devices 11a to 11d, the swap setting is confirmed. Thereby, time delay from the swap setting by the production control CPU 86 to the confirmation of the swap setting by the display control unit 213 can be secured. For this reason, even if the switch check interrupt process, which is an interrupt process by a periodically generated timer interrupt, is performed in the effect control CPU 86 in preference to the drawing control, the image data is stored. The output buffer can be switched appropriately, and the swap setting by the display control unit 213 is not confirmed before the swap setting by the effect control CPU 86, and an error occurs in the buffer that outputs the image data. It is prevented.

  Further, according to the present embodiment, the effect control CPU 86 can perform the swap setting even when the V blank interrupt signal from the CPU interface 201 is input. For this reason, even when the swap setting is not performed after the drawing process is completed, the setting can be appropriately performed.

  Further, according to the present embodiment, the standby time from the input of the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d is set longer than the period required for the switch check interrupt process. Therefore, it is possible to confirm the swap setting by the display control unit 213 more reliably after the swap setting by the effect control CPU 86.

  In addition, according to the present embodiment, the display control unit 213 confirms the swap setting after the V blank interrupt signal corresponding to the second sub-effect display devices 11a to 11d after the start of the latest drawing control is input. On the other hand, the effect control CPU 86 performs the swap setting after the V blank interrupt signals corresponding to the first sub effect display devices 11a to 11d after the start of the drawing control are input. Thereby, even when the time required for drawing the image data is longer than the period of the V blank interrupt signal, the buffer for outputting the image data can be appropriately switched.

  In addition, according to the present embodiment, since common swap setting information is set in the main effect display device 9 and the sub effect display devices 11a to 11d, image data is output while synchronizing the effect display devices. Can be switched appropriately.

  Moreover, according to this embodiment, the display control part 213 performs the output process of the image data with respect to the main effect display apparatus 9 and the sub effect display apparatuses 11a-11d to the frame period of sub effect display apparatus 11a, 11b, 11c, 11d. Even when a plurality of effect display devices are provided, display control can be performed while synchronizing the display devices.

  As described above, the embodiments of the present invention have been described with reference to the drawings. However, specific configurations are not limited to these embodiments, and modifications and additions without departing from the gist of the present invention are included in the present invention. It is.

  For example, the effect control CPU 86 performs swap setting every time the V sink interrupt signal is input twice, and the display control unit 213 performs the second time every time the V sink interrupt signal is input twice. The swap setting may be confirmed after the standby time has elapsed from the input. In the above embodiment, the timing of swap setting by the effect control CPU 86 and the timing of confirmation of swap setting by the display control unit 213 are determined based on the V blank interrupt signal. The timing of the swap setting by the effect control CPU 86 and the timing of the swap setting confirmation by the display control unit 213 are determined based on the signal, and the buffer for outputting the image data can be appropriately switched as in the above-described embodiment. .

  For example, in the above embodiment, in the initial state, the inherent frame period of the sub-effect display devices 11a to 11d is longer than the inherent frame period of the main effect display device 9, and the frame period of the main effect display device 9 Is set to a period longer than the unique frame period of the sub-effect display devices 11a to 11d, and the reset process is performed so that the frame period of the effect display device 9 is synchronized with the unique frame period of the sub-effect display devices 11a to 11d. went. However, it is not limited to this.

  For example, the frame period of the main effect display device 9 is set to the same period as the unique frame period of the sub effect display devices 11a to 11d, and the frame period of the effect display device 9 is unique to the sub effect display devices 11a to 11d. You may perform a reset process so that it may synchronize with a frame period. Alternatively, both the frame period of the main effect display device 9 and the frame period of the sub effect display devices 11a to 11d are set to a period longer than the inherent frame period of the sub effect display devices 11a to 11d, and the sub effect display is performed. It is a period that is equal to or longer than the inherent frame period of the devices 11a to 11d and is equal to or shorter than the shorter one of the frame period of the set main effect display device 9 and the frame period of the sub effect display devices 11a to 11d. You may make it perform the reset process of both the frame period of the effect display apparatus 9, and the frame period of the sub effect display apparatuses 11a-11d.

  In the above embodiment, the effect control CPU 86 resets the V sink of the main image display device 9 every time the V sink interrupt signal corresponding to the sub effect display devices 11a to 11d from the CPU interface 201 is input. . However, the present invention is not limited to this, and the effect control CPU 86 performs the main image display device every time a predetermined period elapses after the V blank interrupt signals corresponding to the sub effect display devices 11a to 11d from the CPU interface 201 are input. Nine V sinks may be reset. Here, the predetermined period is a time difference between the input / output of the V sync interrupt signal corresponding to the sub effect display devices 11a to 11d and the input / output of the V blank interrupt signal corresponding to the sub effect display devices 11a to 11d. . If the V blank interrupt signal is input, the V sync of the main image display device 9 is immediately reset to wait for the elapse of the predetermined time, and the frame cycle start timing of the main effect display device 9 and the sub effect display device 11a. This is to prevent a time difference from occurring at the start timing of the frame period of ˜11d.

  Moreover, in the said embodiment, in view of the time required for drawing image data in the image drawing area being longer than one frame period of the sub-effect display devices 11a to 11d and shorter than two frame periods. The area and the image drawing area are switched every two times the frame period of the sub-effect display devices 11a to 11d. However, the present invention is not limited to this, and the switching period between the image display area and the image drawing area is an integral multiple of the frame period of the sub-effect display devices 11a to 11d according to the time required to draw the image data in the image drawing area. Should be set.

  In the above embodiment, switching between the buffer A and the buffer B serving as the image drawing area is performed every time the V blank interruption signal corresponding to the sub-effect display devices 11a to 11d is input to the drawing control unit 206 twice. Although it is performed, the sub-effect display devices 11a to 11d may be switched every time the V sync timing comes twice.

  In the above embodiment, it is assumed that the plurality of sub-effect display devices 11a to 11d all have the same resolution and the total number of pixels, but the plurality of sub-effect display devices 11a to 11d have different resolutions and It may be the total number of pixels. Further, when the plurality of sub-effect display devices 11a to 11d have different resolutions and total numbers of pixels, the sub-image data drawn in the storage areas of the sub-frame buffer are drawn with a common image size. Each sub image data is stored in the composite image storage area to generate output image data. After the output image data is separated as each sub image data by the signal separation board 220, each sub image data The data signal is enlarged or reduced according to the resolution and the total number of pixels of each sub-effect display device 11a to 11d, and the enlarged or reduced data signal is input to each sub-effect display device 11a to 11d. Image data may be displayed.

  In the above embodiment, the four sub-effect display devices 11a to 11d are mounted on the pachinko gaming machine 1, but the number of sub-effect display devices is not limited to four, but two or three. A sub-effect display device may be mounted, or five, six, or more sub-effect display devices may be mounted. Even when three sub-effect display devices are mounted, it is possible to cope with the problem by using one signal separation substrate 220 corresponding to the four sub-effect display devices 11a to 11d described above.

  For example, four storage areas of the subframe buffer are provided, sub image data A to C are stored in three storage areas of each storage area, and blank image data that is blank is stored in the remaining one storage area. Is stored. Then, in the order of the image data divided from the sub image data A, the image data divided from the sub image data C, the image data divided from the sub image data B, and the image data divided from the blank image data, Image data A to C and blank image data are stored in the composite image storage area, and output image data Z is generated. The output image data Z is output from the VDP 262 to the signal separation board 220 as one system data signal. Furthermore, when the output image data Z is separated into four systems and output by the signal separation board 220, the sub-effect display is provided from each of the three transmission circuits among the four transmission circuits 223a to 223d of the signal separation board 220. The sub image data A to C are transmitted to the apparatus, and the blank image data is transmitted from the transmission circuits 223a to 223d not connected to the sub effect display apparatus.

  Moreover, in the said embodiment, although the normal display which displays a two-dimensional image is illustrated as the main effect display apparatus 9 and each sub effect display apparatus 11a-11d, this invention is not limited to this. As the main effect display device 9 and the sub effect display devices 11a to 11d, autostereoscopic display devices capable of stereoscopic display such as a parallax barrier method and an integral image method may be used.

  Moreover, in the said embodiment, although each sub effect display apparatus 11a-11d smaller than the main effect display apparatus 9 is used, this invention is not limited to this, The main effect display apparatus 9 and sub The effect display devices 11a to 11d may be the same size, or may be sub-effect display devices 11a to 11d larger than the main effect display device 9.

  Moreover, in the said embodiment, the 1st drawing area and each 2nd drawing area are set to the main frame buffer, and the setting of each 2nd drawing area is also changed according to the movement of sub effect display apparatus 11a-11d. However, the setting of the drawing area that is changed according to such a display device is not limited to the main frame buffer, and may be in another mode. For example, in the virtual drawing space in the previous stage of drawing in the main frame buffer, the first drawing area and each second drawing area are set, and each second drawing area is set in accordance with the movement of each sub-effect display device 11a to 11d. After the primitive is drawn in these virtual drawing spaces, the primitives in the first drawing area and the second drawing area in the virtual drawing space are changed to the first drawing area and the second drawing in the main frame buffer. You may make it the aspect drawn in a drawing area. Further, after the primitive is drawn in the virtual drawing space, the primitives in the first drawing area and the second drawing area in the virtual drawing space are individually stored in the first drawing area of the main frame buffer and the storage area of the subframe buffer, respectively. You may make it the aspect drawn in.

  Further, in the above embodiment, in the VRAM area, areas having storage areas are used as subframe buffers. However, these storage areas are not used as subframe buffers, but are used as virtual drawing spaces for simply drawing image data. A composite image storage area for storing output image data to be output to the effect display devices 11a to 11d may be used as a frame buffer.

  Moreover, in the said embodiment, each sub effect display apparatuses 11a-11d are arrange | positioned at the four corners of the main effect display apparatus 9, and each sub effect display apparatus 11a-11d is moved, and each is displayed on the main effect display apparatus 9. Although the sub effect display devices 11a to 11d are superposed, the main effect display device 9 and the sub effect display devices 11a to 11d are overlapped when the main effect display device 9 is moved. An aspect may be sufficient.

  Moreover, in the said embodiment, arrangement | positioning of the up-down direction of each sub effect display apparatus 11a-11d is arranged in the state rotated by the clockwise or counterclockwise rotation with respect to the horizontal instead of the direction where the horizontal line of a display screen becomes horizontal. However, the sub effect display devices 11a to 11d may not be rotated.

  In the above embodiment, each of the sub image data A to D stored in the storage area of the subframe buffer is divided, and each of the divided image data is read in the reading direction (X-axis direction) in the composite image storage area. The output image data Z is generated by being sequentially arranged and stored in the composite image storage area. The output image data Z is output from the sub display system output unit SK of the VDP 262, and the output image data Z is signal-separated. After being separated as the sub image data A to D on the substrate 220, the sub effect display devices 11a to 11d are inputted. However, the present invention is not necessarily configured to have a composite image storage area. Well, for example, the sub-effect display devices 11a to 11d are directly connected to the sub-display system output unit SK of the VDP 262 without passing through the signal separation substrate 220. The sub image data A to D stored in the storage area of the frame buffer are directly transmitted from the sub display system output unit SK of the VDP 262 to the sub effect display devices 11a to 11d, and the sub effect display devices 11a to 11d are transmitted to the VDP 262. The sub image data A to D received directly from the display unit may be displayed on the display unit.

  In the above embodiment, the sub image data A to D drawn in the storage areas of the subframe buffer are reduced and copied to the second drawing areas of the main frame buffer, and effect processing is performed in the main frame buffer. The sub image data A to D of each second drawing area in the main frame buffer are enlarged and reproduced again in each storage area of the sub frame buffer. 9 and the sub-effect display devices 11a to 11d have the same resolution (display pixel density), the sub-image data A to D stored in the storage areas of the sub-frame buffer are stored in the main frame buffer. Each of the sub image data A to D of the second drawing area in the main frame buffer. , When they are re-replicated to each storage area of the sub-frame buffer, at the same magnification without enlargement or reduction may be carried out duplicate or re-duplicated image data.

  In the above-described embodiment, in order to notify the effect control CPU 86 of the change pattern indicating the change mode such as the change time, the type of reach effect, and the presence / absence of the pseudo-ream, one change pattern designation command is used when the change is started. In the example shown in FIG. 7, the variation pattern may be notified to the effect control CPU 86 by two or more commands. Specifically, in the case of notification by two commands, the CPU 56 uses the first command to indicate whether or not there is a pseudo-continuity, whether or not there is a slip effect, etc. before reaching reach (if not reaching, before so-called second stop. ) Command indicating the fluctuation time and fluctuation mode, and the second command has reached reach, such as the type of reach and presence / absence of re-lottery effect (if not reach, after so-called second stop) It is also possible to send a command indicating the fluctuation time or fluctuation mode. In this case, the effect control CPU 86 may perform effect control in variable display based on the variable time derived from the combination of two commands.

  The CPU 56 may notify the change time by each of the two commands, and the effect control CPU 86 may select a specific change mode to be executed at each timing. When two commands are sent, the two commands may be transmitted within the same timer interrupt. After the first command is transmitted, a predetermined period elapses (for example, the next timer interrupt is transmitted). The second command may be transmitted. Note that the variation mode indicated by each command is not limited to this example, and the order of transmission can be changed as appropriate. Thus, by notifying the variation pattern by two or more commands, the amount of data that must be stored as the variation pattern designation command can be reduced.

  Further, in the above embodiment, a pachinko gaming machine in which a game ball is paid out as a prize to the player, and the player launches the paid out game ball (which may be a rental ball) into the game area to play a game. 1 is illustrated, but the present invention is not limited to this. For example, a frequency that is a game value of a size specified by record information of a game recording medium such as a prepaid card or a membership card is used. Then, a game score for use in the game is given, and the game ball enclosed in the game machine is driven into the game area by using the assigned game score or the game score given by winning the game. The present invention can also be applied to a gaming machine in which a player plays a game.

  In the above embodiment, the pachinko gaming machine 1 is illustrated as a gaming machine, but the present invention is not limited to this, and even a slot machine that uses a medal as a gaming medium to play a game. Good. When the gaming machine is a slot machine, for example, when a bonus flag is set in the internal lottery, a bonus flag is displayed on each of the sub-effect display devices 11a to 11d and the main effect display device 9. It is only necessary to execute an suggestion effect that displays the effect images linked to each other.

  In addition, game machines other than these, for example, game media, are encapsulated inside the game machine, and the number of pachinko balls and medals lent out, and the number of pachinko balls and medals awarded in accordance with winnings are added. On the other hand, enclosed game machines where the number of pachinko balls and medals used in games are subtracted and stored, and values such as points and points lent out in response to loan requests without using pachinko balls and medals Alternatively, a gaming machine that stores all values such as points and points awarded in accordance with winnings as credits and can play a game using only the values stored as credits may be used. In this case, these points, points, and the like correspond to game media, and credits become game value.

  The program and data for realizing the present invention are not limited to a form distributed and provided by a detachable recording medium with respect to the computer device or the like included in the pachinko gaming machine 1; It is also possible to adopt a form that is distributed by pre-installing the storage device. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the program and data downloaded via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

1 ... Pachinko machine 3 ... Bump supply tray (top plate)
3a ... Upper plate part 4 ... Surplus ball storage plate (lower plate)
4a ... Lower plate part (protruding part)
5 ... Hitting ball operation handle (operation knob)
6 ... Game board 7 ... Game area 8, 8a, 8b ... Special symbol display 9 ... Main effect display device 9 '... First liquid crystal panel 10 ... Normal symbol display 11, 11a, 11b, 11c, 11d ... Sub effect display Device 11a ', 11b', 11c ', 11d' ... 2nd liquid crystal panel 13 ... Movable piece 14a, 14b ... Start port switch 15 ... Start winning device 15a, 15b ... Start port 16, 21, 21a ... Solenoid 18 ... Special design On-hold storage indicator 19 ... Full switch 20 ... Special variable winning ball device 23 ... Count switch 25L, 25R ... Decoration light emitting part 25a ... Decoration LED
25b ... Stage decoration LED
26 ... Out port 27, 27L, 27R, 27a, 27b ... Speaker 28L, 28R, 28H ... Light emitting part 28b, 28c ... Frame LED
29, 30 ... Normal winning opening 29a, 30a ... Winning opening switch 31 ... Main board 32 ... Gate 32a ... Gate switch 37 ... Dispensing control board 41 ... Normal symbol hold memory display 51 ... Prize ball LED
52… LED out of ball
54, 84 ROM
55, 85 ... RAM
56 ... CPU
57, 87 ... I / O ports 58, 260 ... Input circuit 59a, 59b, 59c, 59d ... Motor for movement 60 ... Link mechanism 78, 79 ... Output circuit 80 ... Production control board 81 ... Production control microcomputer 86 ... Production CPU for control
97 ... Ball dispensing device 101 ... Front frame 102 ... Glass door frame 103 ... Lower door frame 130a ... Big hit determination table 130b, 130c ... Small hit determination table 131a ... Big hit type determination table 132a, 132b ... Hit variation pattern type determination table 135a , 135b ... deviation variation pattern type determination table 137a, 137b ... hit variation pattern determination table 138a ... deviation variation pattern determination table 156 ... game control microcomputer 201 ... CPU interface (I / F)
202 ... System register 203 ... Attribute register 204 ... CG bus interface (I / F)
205 ... CGROM
206 ... Drawing controller 209 ... VRAM bus interface (I / F)
210 ... SDRAM (Synchronous DRAM)
211 ... Data transfer control unit 213 ... Display control unit 220 ... Signal separation substrate 221 ... Primary separation circuit 222a, 222b ... Secondary separation circuit 223a, 223b, 223c, 223d ... Transmission circuit 224a, 224b, 224c, 224d, 225 ... Liquid crystal Panel side receiving circuit 262 VDP
510a, 510b, 510c, 510d ... Lever switch 516 ... Operation button 516a ... Button switch 530 ... Skylight module 600 ... Operation lever MK ... Main display system output unit SK ... Sub display system output unit

Claims (1)

A game machine to perform the Yu skills,
A display device Update to display based images relating to pre Ki遊 technique in a predetermined frame period,
A plurality of image data storage means for temporarily storing image data of an image displayed on the display device;
And the effect control means for controlling the performance in the previous Ki遊 skills,
Display control means for performing display control of the display device according to control by the effect control means;
With
The display control means stores image data to output the image data of the plurality of image data storage means at a predetermined timing after outputting a signal synchronized with the frame period of the display device to the effect control means. Confirm storage location designation information for designating means, and switch the image data storage means for outputting the image data according to the content of the storage location designation information,
The effect control means executes a drawing process for storing the image data in the image data storage means in accordance with a signal synchronized with a frame period of the display device, and after the drawing process is finished , The gaming machine is characterized in that the storage location designation information is set prior to the timing .

Images