JP6205721B2 - Multilayer circuit board and electronic device - Google Patents

Description

  The present invention relates to a multilayer circuit board and an electronic device.

  A computer or the like is equipped with an electronic device in which a chip on which a semiconductor element is formed is mounted on a printed board. As a printed board used in an electronic device, a multilayer circuit board in which insulating layers and conductor layers on which wiring patterns are formed is alternately laminated is known. The insulating layer is formed by curing a composite material in which a glass cloth woven with glass fiber weave is impregnated with a resin in order to maintain the rigidity of the printed circuit board.

  Here, when an electrical signal is transmitted at high speed using a printed circuit board using a glass cloth as an insulating layer, the signal propagation time difference may occur due to the dielectric constant of the insulating layer affecting the signal transmission speed. Are known. For this reason, an electronic circuit that needs to synchronize a plurality of signals may cause inconvenience in signal processing when the arrival times of the signals are deviated. The signal propagation time difference is caused by a shift in signal propagation time in a plurality of wirings. The signal propagation time difference is generally considered to be about 1% to 3% of the signal delay time, although it varies depending on the material and wiring structure used for the insulating layer and the conductor layer. For this reason, the difference in signal propagation time becomes more serious as the transmission signal becomes faster and the time interval for sending the signal becomes narrower. For example, if the time required for signal propagation is about 700 picoseconds at a wiring length of 10 cm, a signal propagation time difference of 7 ps will occur if a 1% difference occurs in the signal propagation time between the two wires. become.

  For example, when signals are transmitted at a transmission rate of 20 Gbps (bps: bits per second), the signal interval is 50 picoseconds. It is known that the electronic circuit can tolerate a signal propagation time difference up to about 10% with respect to the signal interval. Therefore, in this case, signal delay can be allowed up to 5 picoseconds corresponding to a signal propagation time difference of 10%. When the signal transmission rate is made higher than 20 Gbps, the signal propagation time difference needs to be made smaller than 5 picoseconds. Thus, in order to realize high-speed signal transmission, it is necessary to reduce the signal propagation time difference in the printed circuit board.

  Here, when a pair of wirings are formed on the same insulating layer, it is known that the signal propagation time difference transmitted through each wiring is affected by the positional relationship between the wiring and the glass cloth. For this reason, in a conventional printed circuit board, a glass cloth is woven in a lattice shape to form an insulating layer, and a wiring pattern is formed so as to cross the glass cloth, thereby generating a signal generated depending on the position of the glass cloth and the wiring. The change in transmission speed is reduced.

  In this case, when the pair of wirings are formed so as to cross obliquely with the glass cloth, the signal transmission speed can be made substantially the same between the two wirings. Also, by arranging the wiring pattern diagonally and zigzag with respect to the glass cloth woven in a lattice shape, if the density of the glass cloth viewed from the wiring is made as uniform as possible, signal transmission between the two wirings The speed can be made substantially the same. Furthermore, the influence of the glass cloth is reduced by installing a plurality of wirings at intervals equal to the texture interval of the glass cloth.

US Published Patent No. 2006123371

However, if the wiring is formed obliquely with the glass cloth, a great deal of waste is generated in materials and space. In addition, the method of making the wiring interval equal to the weave interval of the glass cloth has an effect of reducing the signal propagation time difference between the two adjacent wires. In some cases, sufficient effects may not be obtained between interconnects or between interconnects and clocks.
This invention is made in view of such a situation, and it aims at reducing the signal propagation time difference in a printed circuit board.

According to one aspect of the embodiment, an insulating layer braided perpendicularly to a glass cloth woven with glass fibers and impregnated with a resin, and disposed adjacent to the insulating layer, is used for signal transmission of 20 Gbps or more. A multilayer circuit board comprising: a plurality of wirings, wherein a width of the wirings is 75% to 95% with respect to an interval between the weaves of the glass cloth arranged in parallel to the wirings Is provided.

  It becomes possible to suppress the difference in signal propagation time between the plurality of wirings to a predetermined value or less. The degree of freedom in layout can be increased, and signal processing in a semiconductor circuit or the like can be executed accurately.

FIG. 1 is a cross-sectional view showing an example of a wiring layout of a multilayer circuit board according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a result of simulating the relationship between the wiring width of the multilayer circuit board and the glass cloth weave interval according to the embodiment of the present invention. FIG. 3A is a cross-sectional view showing an example of a wiring structure used for simulation of the multilayer circuit board according to the embodiment of the present invention. FIG. 3B is a cross-sectional view showing an example of a wiring structure used for simulation of the multilayer circuit board according to the embodiment of the present invention. FIG. 4 shows an example of a wiring structure used for the simulation of the multilayer circuit board according to the embodiment of the present invention, where (a) is a plan view and (b) is a front view. FIG. 5 is a diagram showing a list of four wiring structures used for the simulation of the multilayer circuit board according to the embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a result of a simulation of the relationship between the wiring width of the multilayer circuit board according to the embodiment of the present invention and the weave interval of the glass cloth while changing the width of the glass cloth. FIG. 7 is a cross-sectional view showing an example of the microstrip line according to the embodiment of the present invention. FIG. 8A is a cross-sectional view showing an example of the manufacturing process of the microstrip line according to the embodiment of the present invention. (Part 1) FIG. 8B is a cross-sectional view showing an example of the manufacturing process of the microstrip line according to the embodiment of the present invention. (Part 2) FIG. 9 is a cross-sectional view showing an example of a multilayer circuit board having strip lines and an electronic device including the multilayer circuit board according to an embodiment of the present invention. FIG. 10 is a cross-sectional view showing an example of a side cross-sectional view of a multilayer circuit board having striplines according to an embodiment of the present invention.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

First, the principle of the embodiment will be described.
FIG. 1 shows a cross-sectional view of a multilayer circuit board as an example of a wiring layout. The multilayer circuit board 1 has a first insulating layer 2 on the lower side. The first insulating layer 2 is formed by impregnating a resin cloth 3 into a glass cloth 4, and a conductor layer 5 used as a ground layer is attached to the lower surface. A pair of parallel wirings 6 is formed on the upper surface of the first insulating layer 2. The wiring 6 is manufactured using a conductive material such as copper. Further, a second insulating layer 7 is formed on the first insulating layer 2 so as to cover the wiring 6. The second insulating layer 7 is formed by impregnating a glass cloth 4 with a resin 3, and a conductor layer 5 used as a ground layer is attached to the upper surface. The upper and lower conductor layers 5 and 8 are made of the same conductive material as the wiring 6, for example, copper. Such a multilayer circuit board 1 has a pair of wirings 6 as signal lines, and conductor layers 5 and 8 wider than the wirings 6 are provided above and below the wiring layers 6 via the insulating layers 2 and 7. Or it is a strip line used as a ground layer.

  Here, the glass cloth 4 of the first insulating layer 2 is formed by weaving glass fibers in two directions substantially orthogonal to each other. The thickness of the glass fiber and the interval between the weaves are manufactured to be substantially constant. The relative dielectric constant of the resin 3 of the insulating layers 2 and 7 is, for example, 2.95. The relative permittivity of the glass cloth 4 is, for example, 5.5, and the texture interval PG1 of the glass cloth 4 is 300 μm.

  The wiring 6 is designed with the type and shape of the conductive material so that signal transmission is possible at a speed exceeding 20 Gbps. Assuming that the width of the wiring 6 is WH1 and the texture interval of the glass cloth 4 is PG1, in this multilayer circuit board 1, the width WH1 of the wiring 6 is slightly smaller than the texture distance PG1 of the glass cloth 4. Specifically, the width WH1 of the wiring 6 has a size of 75% to 95% of the texture interval PG1 of the glass cloth 4.

  Such a range of the width WH1 of the wiring 6 is determined based on the result of simulation. FIG. 2 shows the result of simulating the relationship between the weaving interval PG1 of the glass cloth 4 and the wiring width ratio R1 of the width WH1 of the wiring 6 and the signal propagation time difference. The horizontal axis indicates the wiring width ratio R1 (= WH1 / PG1) of the weave interval PG1 of the glass cloth 4 and the width WH1 of the wiring 6, and the vertical axis indicates the signal propagation time difference for each 1 cm length of the wiring 6.

  The difference in signal propagation time is the time T2 required when a signal is transmitted through the wiring 6 in the wiring structure A2 shown in FIG. 3B from the time T1 required when the signal is transmitted through the wiring 6 in the wiring structure A1 shown in FIG. 3A. Calculated by subtracting. Here, in the wiring structure A1 shown in FIG. 3A, the center of the glass cloth 4 and the center of the wiring 6 coincide. In the wiring structure A2 shown in FIG. 3B, the center position of the two adjacent glass cloths 4 and the center of the wiring 6 coincide. That is, the wiring structure A2 is configured such that the position of the wiring 6 and the position of the glass cloth 4 are most shifted. Other conditions were the same in the two wiring structures A1 and A2. 3A and 3B, the conductor layers 5 and 8 are not shown.

  As shown in FIG. 2, the signal propagation time difference becomes a negative value when the wiring width ratio R1 is small, that is, when the wiring width WH1 is sufficiently narrower than the wiring width PG1 of the glass cloth 4. This is because the signal of the wiring structure A1 as a reference is easily affected by the glass cloth 4, whereas the signal of the wiring structure A2 has a large distance from the glass cloth 4 and is not easily affected. This is thought to be because the propagation time difference becomes larger on the minus side. Further, as the wiring width ratio R1 increases, the signal propagation time difference decreases, and when the wiring width ratio R1 is 0.85, the signal propagation time difference becomes zero. Then, the change in the signal propagation time difference converged to a predetermined value, for example, about 0.7 picosecond / cm when the wiring width ratio R1 was around 1.2.

  In this simulation result, the signal propagation time difference is the smallest when the wiring width ratio R1 is 0.85. If the wiring width ratio is in the range of 0.7 to 1.1, the signal propagation time difference can be kept within ± 0.5 picoseconds / cm.

  Subsequently, the relationship between the wiring width ratio R1 and the signal propagation time difference when the width of the glass cloth 4 was changed was simulated. The model used for the simulation here is schematically shown in FIG. 4A shows a plan view of the wiring structure, and FIG. 4B shows a front view of the wiring structure. In this wiring structure, the texture interval PG1 of the glass cloths 4 arranged perpendicular to the wiring 6 is set to 300 μm. Further, the weave interval PG1 of the glass cloth 4 arranged in parallel as the wiring 6 was set to 500 μm. When the width WG1 of the glass cloth 4 arranged parallel to the wiring 6 and the width WG2 of the glass cloth 4 arranged perpendicular to the wiring 6 are changed, signal propagation is performed while changing the wiring width ratio R1. The time difference was simulated.

  The simulation was performed on four models (wiring structures ST1 to ST4) shown in FIG. In the wiring structure ST1, the width WG1 of the glass cloth 4 parallel to the wiring 6 is 200 μm, and the width WG2 of the glass cloth 4 perpendicular to the wiring 6 is 200 μm. In the wiring structure ST2, the width WG1 of the glass cloth 4 parallel to the wiring 6 is 200 μm, and the width WG2 of the glass cloth 4 perpendicular to the wiring 6 is 400 μm. In the wiring structure ST3, the width WG1 of the glass cloth 4 parallel to the wiring 6 is 300 μm, and the width WG2 of the glass cloth 4 perpendicular to the wiring 6 is 200 μm. In the wiring structure ST4, the width WG1 of the glass cloth 4 parallel to the wiring 6 is 300 μm, and the width WG2 of the glass cloth 4 perpendicular to the wiring 6 is 400 μm.

FIG. 6 shows the result of simulation of the signal propagation time difference in each of the wiring structures ST1 to ST4 while changing the wiring width ratio R1. The horizontal and vertical axes are the same as in FIG.
In each of the four wiring structures ST1 to ST4, when the wiring width ratio R1 is small, the signal propagation time difference is negative, and as the wiring width ratio R1 increases, the signal propagation time difference approaches zero. As the wiring width ratio R1 increases, the signal propagation time difference increases to the plus side. However, when the wiring width ratio R1 exceeds 1.2, the increasing width tends to decrease and converge to a predetermined value. More specifically, in the region where the wiring width ratio R1 is small, the signal propagation time difference of the wiring structure ST1 is the largest on the negative side, and the negative value of the signal propagation time difference is in the order of the wiring structure ST2, the wiring structure ST3, and the wiring structure ST4. It is getting smaller. On the other hand, in the region where the wiring width ratio R1 is large, the signal propagation time difference of the wiring structure ST1 is the largest on the plus side, and the positive value of the signal propagation time difference is smaller in the order of the wiring structure ST2, the wiring structure ST3, and the wiring structure ST4. . In all the wiring structures ST1 to ST4, when the wiring width ratio R1 is 0.85, the signal propagation time difference is almost zero.

  According to the simulation results of FIG. 6, the lower limit value of the wiring width ratio R1 for setting the signal propagation time difference per 10 cm of the wiring 6 to 5 picoseconds or less in all the wiring structures ST1 to ST4 is as shown by the line L1. It was 0.75. In all the wiring structures ST1 to ST4, the upper limit value of the wiring width ratio R1 for reducing the signal propagation time difference per 10 cm of the wiring 6 to 5 picoseconds or less was 0.95 as shown by the line L2. Therefore, if the wiring width ratio R1 is set to 75% to 95%, the signal propagation time difference per 10 cm of the wiring 6 can be reduced to 5 picoseconds or less. That is, if the wiring 6 width WH1 is 75% to 95% of the wiring position PG1 of the glass cloth 4, the signal propagation time difference can be suppressed within ± 5 picoseconds.

  This is because the electric field is easily concentrated at the end of the wiring 6 and is susceptible to the effect of an effective change in the dielectric constant caused by the glass cloth 4, so that the width WH1 of the wiring 6 is slightly smaller than the texture interval GP1 of the glass cloth 4. This is because it is considered that the effect of the effective dielectric constant due to the glass cloth 4 at the end of the wiring 6 can be reduced by making it smaller. In other words, it is considered that the effective dielectric constant of one wiring 6 is substantially equal to the effective dielectric constant of one weave interval GP1 of the glass cloth 4. As a result, a change in signal transmission speed due to the positional relationship between the glass cloth 4 and the wiring 6 is suppressed.

Here, it is generally considered that an error in manufacturing accuracy of about 5% to 10% with respect to the designed wiring width occurs in the multilayer circuit board. For this reason, even if 255 μm corresponding to 85% of the texture interval PG1 of the glass cloth 4 is designed as the width WH1 of the wiring 6, if there is an error of 10% at the maximum, the width WH1 of the wiring 6 is 230 μm to 280 μm. Even in such a case, since the wiring width ratio R1 falls within the range of 75% to 95%, the signal propagation time difference time can be suppressed to a desired value, for example, 0.5 picosecond / cm.
When the signal transmission speed is 40 Gps, the signal propagation time difference allowed under the same conditions is 0.25 picoseconds / cm. However, if the glass cloth 4 having the smallest texture interval PG1 is used, the wiring 6 Even if there is a manufacturing error of the width WH1, the specification can be satisfied.

  Next, as an example, a microstrip line structure and a manufacturing method thereof will be described with reference to FIG. Here, this embodiment can also be applied to a coplanar structure or a microstrip structure other than the stripline structure.

  The microstrip line 30 has the first insulating layer 2. A conductor layer 5 used as a ground layer is attached to the lower surface of the first insulating layer 2. A pair of wirings 6 is formed on the upper surface of the first insulating layer 2. The weave interval PG1 of the glass cloth 4 of the first insulating layer 2 is constant, and the width WH1 of the pair of wirings 6 is 75% to 95% of the crease interval PG1 of the glass cloth 4.

  When manufacturing the microstrip line 30, first, as shown in FIG. 8A, the copper foils 31 </ b> A and 31 </ b> B are attached to both surfaces of the first insulating layer 2 one by one to form a double-sided copper-clad plate 32. . At this time, the upper copper foil 31 </ b> A covers the entire upper surface of the first insulating layer 2, and the lower copper foil 31 </ b> B covers the entire lower surface of the first insulating layer 2.

  Subsequently, a photoresist film (not shown) is formed on each surface of the copper foils 31A and 31B of the double-sided copper-clad plate 32 by coating. Further, the upper photoresist film is exposed and developed and patterned to form a resist pattern. As shown in FIG. 8B, in the photoresist pattern 33A, the resist film is partially left together with the pattern of the wiring 6 formed in a later step. On the other hand, the lower photoresist film 33B is not patterned.

  Thereafter, the upper copper foil 31A is wet-etched using the resist pattern 33A as a mask to form a pair of wirings 6. The wiring 6 is arranged in parallel with a predetermined interval, and is used as a signal line for high-speed differential transmission, for example. On the other hand, the lower copper foil 31B is not etched because it is covered by the photoresist film 33B. When the wet etching is finished, the photoresist pattern 33A left on the pair of wirings 6 and the photoresist film 33B protecting the copper foil 31B on the lower surface side are removed by ashing or chemical treatment. As a result, the wiring 6 is formed only on one surface of the first insulating layer 2, and the microstrip line 30 having the conductor layer 5 made of the lower copper foil 31B is formed.

  In the microstrip line 30, the width WH1 of the pair of wirings 6 is 75% to 95% of the fold interval PG1 of the glass cloth 4, so even when signals are transmitted to the pair of wirings 6 at a speed of 20 Gbps or more. The signal propagation time difference between the wirings 6 can be made within 0.5 picosecond / cm.

FIG. 9 illustrates a multilayer circuit board 40 having a stripline structure and an electronic device 50 having the multilayer circuit board 40.
The multilayer circuit board 40 has a configuration in which a plurality of insulating layers and conductor layers are alternately stacked. Specifically, the multilayer circuit board 40 includes a first insulating layer 2, a first conductor layer 41, a second insulating layer 7, a second conductor layer 42, a third insulating layer 43, a third insulating layer 2 from the bottom. The conductor layer 44, the fourth insulating layer 45, the fourth conductor layer 46, and the fifth insulating layer 47 are laminated in order. Further, a lowermost layer 48 made of a conductive material is formed on the lower surface of the first insulating layer 2, and an uppermost layer 49 made of a conductive material is formed on the upper surface of the fifth insulating layer 47.

  Each insulating layer 2, 7, 43, 45, 47 is formed by impregnating the glass cloth 4 with the resin 3, and the glass cloth 4 is knitted in two orthogonal directions. Furthermore, the widths WG1 and WG2 of the glass cloth 4 of the insulating layers 2, 7, 43, 45, and 47 and the weave interval PG1 are the same. Each of the conductor layers 41, 42, 44, 46 is formed, for example, by wet etching of a copper foil, and a wiring pattern is formed for each of the conductor layers 41, 42, 44, 46. In each conductor layer 41, 42, 44, 46, the wiring pattern used for signal transmission has a width WH1 of 75% to 95% of the wiring interval PG1 of the glass cloth 4.

  Each of the conductor layers 41, 42, 44, and 46 is electrically connected to the lowermost layer 48 or the uppermost layer 49 using a via hole 51 as necessary. The via hole 51 is formed by forming a through hole 52 at a predetermined position of the multilayer circuit board 40 and growing a conductive film 53 in the through hole 52 by a plating method.

  As shown in FIG. 9 and FIG. 10 showing an enlarged cross-sectional view of FIG. 9 from the side, the pair of wirings 6 of the first conductor layer 41 are electrically connected to the via hole 51. Further, the pair of wirings 6 forms a strip line by the first insulating layer 2 and the lowermost layer 48 below and the upper second insulating layer 7 and the second conductor layer 42. That is, the lowermost layer 48 and the second conductor layer 42 are formed wider than the width WH1 of the pair of wirings 6, and are used as a ground layer.

  For manufacturing the multilayer circuit board 40, for example, a batch lamination process is used. In the collective lamination process, the microstrip line 30 shown in FIG. 7, the uncured second insulating layer 7, and the copper foil are laminated from below. Subsequently, it is molded all at once by a heating type vacuum press. The uncured second insulating layer 7 is cured after heat melting, and the layers are integrated. Thereafter, the copper foil on the second insulating layer 7 is etched to form the second conductor layer 42.

  Further, a package substrate 64 is electrically connected to the electrodes 61 and 62 formed on the uppermost layer of the multilayer circuit substrate 49 via solder bumps 63. In the package substrate 64, a second layer 66 is formed on the lower first layer 65, and a third layer 67 is formed on the second layer 66. In the lower first layer 65, a conductive via 65B manufactured by plating is formed in an insulating layer 65A, and a solder bump 63 is bonded to an electrode 68 connected to the via 65B. In addition to the electrode 68, an electronic component 69 is mounted on the lower surface of the first layer 65.

  The second layer 66 includes a multilayer wiring board 66A, and plays a role of electrically connecting the two layers 65 and 67 through the plated through hole 66B. In the upper third layer 67, conductive vias 67B manufactured by plating are formed in an insulating layer 67A, and the semiconductor chip 71 is bonded to the vias 67B via solder bumps 70. The semiconductor chip 71 has a semiconductor element inside and is packaged with, for example, a resin.

  As described above, in this embodiment, the width WH1 of the wiring 6 used for high-frequency signal transmission is set to 75% to 95% of the texture interval PG1 of the glass cloth 4 of the insulating layers 2, 7, 43, 45, 47. Thus, the signal propagation time difference between the plurality of wirings 6 can be suppressed to within ± 10%. For example, when the signal transmission rate is 20 Gbps, the signal propagation time difference can be suppressed to 0.5 picosecond / cm or less. When such a wiring structure is applied to a stripline structure or a microstripline structure, a signal propagation time difference can be suppressed. Further, in the electronic device 50 having such a wiring structure, since the signal propagation time difference can be suppressed, signal processing in the semiconductor chip 71 and the like can be executed accurately.

  By setting the width WH1 of the wiring 6 to 75% to 95% of the weave interval PG1 of the glass cloth 4, the signal propagation time difference can be reduced without depending on the arrangement of the glass cloth 4 and the wiring 6, so that the wiring layout is easy. become. The multilayer circuit board 40 and the electronic device 50 having such a wiring structure can prevent a signal propagation time difference and perform accurate signal processing. Further, since the degree of freedom of layout is not easily limited, manufacturing is facilitated.

  Further, when the width WH1 of the wiring 6 used for signal transmission is set to 85% of the texture interval PG1 of the glass cloth 4 of the insulating layers 2, 7, 43, 45, 47, the difference in signal propagation time between the plurality of wirings 6 is minimized. can do. In this case, the multilayer circuit board 40 and the electronic device 50 can prevent a difference in signal propagation time, and can be easily manufactured because the degree of freedom of layout is hardly limited.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, and such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

DESCRIPTION OF SYMBOLS 1,40 Multilayer circuit board 2 1st insulating layer 4 Glass cloth 6 Wiring 7 2nd insulating layer 50 Electronic device 71 Semiconductor chip

Claims (6)

An insulating layer knitted perpendicular to a glass cloth woven with glass fibers and impregnated with resin;
A plurality of wirings arranged close to the insulating layer and used for signal transmission of 20 Gbps or more;
Including
The multilayer circuit board according to claim 1, wherein a width of the wiring has a length of 75% to 95% with respect to an interval between the weaves of the glass cloth arranged in parallel to the wiring.   2. The multilayer circuit board according to claim 1, wherein a width of the wiring is 85% of a distance between the weaves of the glass cloth.   The multilayer circuit according to claim 1, wherein the insulating layer is disposed with the wiring interposed therebetween, and a conductor layer wider than the wiring is formed on each of an upper surface and a lower surface of the insulating layer. substrate.   The multilayer circuit board according to any one of claims 1 to 3, wherein an interval between the weaves of the glass cloth is 200 µm to 400 µm. 5. The multilayer circuit board according to claim 1, wherein a wiring structure including the insulating layer and the wiring is a stripline structure or a microstripline structure. 6. The multilayer circuit board according to any one of claims 1 to 5,
A semiconductor chip electrically connected to the wiring of the multilayer circuit board and having a semiconductor element formed thereon;
An electronic device comprising:

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