JP6247314B2 - Computer system and computer system control method - Google Patents

Description

  The present invention relates to an information processing system including a semiconductor memory and a control method thereof. In particular, the present invention relates to a technique for realizing an information processing system that satisfies low power consumption and predetermined reliability.

  With the miniaturization of semiconductors, the performance of a computer system is improved, while the variation in transistor characteristics is increasing. This variation in characteristics particularly decreases the reliability of a storage device such as SRAM (Static Random Access Memory) and causes damage to retained data. Since data corruption can cause system down, compensation technology has become a major issue in recent years. The same applies to a storage device such as a DRAM (Dynamic Random Access Memory) as well as an SRAM. For example, in a DRAM, the memory holding time is reduced.

  For this reason, as a technique for maintaining the reliability of the storage device, Patent Document 1 discloses a technique for correcting errors in data stored by error correction coding (ECC) or data multiplexing. Further, in Patent Document 2, in order to cope with a difference in necessary threshold voltage due to deterioration of a memory chip, a parameter that determines an electrical characteristic of a signal used for writing or reading data with respect to the memory chip is changed and set to an appropriate value. Technology is disclosed.

Special table 2008-521160 JP2012-68825A

  As in Patent Document 1 and Patent Document 2, when errors are completely corrected for all data, the reliability maintenance cost increases. For example, when ECC is applied, power is consumed for encoding and correction processing. In addition, by increasing the voltage in the SRAM and increasing the frequency of the refresh rate in the DRAM, the operation margin can be expanded, but the power consumption also increases. As described above, a large amount of power cost is required to maintain the reliability of the storage device, and the reliability maintenance cost increases as the semiconductor becomes finer.

  In the future, the rise of applications such as learning / recognition processing using large-scale data is expected. Such an application requires a large capacity storage device to perform a large amount of calculations. For this reason, the increase in the reliability maintenance cost accompanying the increase in the capacity of the storage device becomes a particular problem.

  However, some applications, such as an application using learning / recognition processing, have a strong resistance to calculation result errors. For example, the correct calculation result in the recognition of a person has a certainty factor of 90%, but even if the certainty factor is 88% due to a data error, there is no problem as long as there is no change in the conclusion that this is Mr. A. However, in the current computer system that assumes that the storage device is highly reliable, all the instructions and data to the processor are handled in the same way, and therefore an error in the data of the storage device may lead to a failure of the entire computer system. There is.

  Therefore, in the computer system according to the embodiment of the present invention, data relating to control of the entire system, such as instruction data and pointers, and highly important data that leads to system down if an error occurs are highly reliable in the storage device. (Level at which error correction is possible). On the other hand, low-reliability data (such as input data such as images and text) and intermediate data for calculations that do not stop the entire system even if an error occurs. At a level where error correction is impossible). As a result, a fatal error of the computer system such as the stop of the entire system can be avoided while using most of the storage device in a state of low reliability (in other words, low power).

  Specifically, a computer system in an example of the embodiment includes a memory and first and second processors connected to the memory. The first processor accesses the memory in the first operation state, and stops accessing the memory in the second operation state in which the data error occurrence rate in the memory is higher than the first operation state. On the other hand, the second processor accesses the memory in the second operating state.

  Then, the first processor stores the work instruction content to the second processor in the memory in the first operation state, and the second processor stores the work instruction content stored in the memory in the second operation state. Read and execute the process. In addition, the first processor checks whether the second processor is operating in the first operating state, and if it is not operating, restarts the second processor.

  When the memory is an SRAM, the first and second operating states described above are determined by the operating voltage of the SRAM. In this case, the operating voltage in the second operating state is lower than the operating voltage in the first operating state.

  When the memory is a DRAM, the first and second operating states described above are determined by the refresh rate of the DRAM. In this case, the refresh rate in the second operating state is lower than the refresh rate in the first operating state.

  According to the present invention, it is possible to provide a computer system that reduces power consumption of a storage device while maintaining predetermined reliability.

It is a figure which shows the structural example of the processor provided with SRAM. It is a figure which shows the data which SRAM has. It is a figure explaining the parallel calculation processing of a processor. It is a figure which shows the data arrangement | positioning of the address area | region on SRAM which a worker uses. It is a figure which shows the data arrangement | positioning of the address area | region on SRAM which a worker uses. It is a figure which shows the data arrangement | positioning of the address area | region on SRAM which a worker uses. It is a figure which shows the operation | movement flowchart of the master in parallel calculation processing. It is a figure which shows the operation | movement flowchart of the worker in a parallel calculation process. It is a figure which shows the structural example of a computer system. It is a figure which shows the data which a memory holds. It is a process flowchart of the program for parameter adjustment of a computer system. It is a figure which shows the structural example of a computer system. It is a figure which shows the structural example of a memory. It is a figure which shows the data which the control unit of memory has. It is a figure which shows the data which the high reliability area | region of the memory | storage unit of a memory holds. It is a figure which shows the data which the low power area | region of the memory | storage unit of a memory holds. It is a figure which shows the operation | movement flowchart of a computer system.

  In the first embodiment, an example of a processor in which the power consumption of the SRAM is reduced will be described.

  FIG. 1 is a block diagram illustrating a configuration of a processor 10 including an SRAM. The processor 10 is a multi-core processor having a plurality of processor cores, and includes a CPU 110, a CPU 120, a bus 130, an input / output unit 140, an SRAM 150, a timer 160, and a voltage / frequency control unit 170.

  The CPU 110 is an arithmetic core that serves as a master in the master-worker parallel processing, and the CPU 120 is an arithmetic core that serves as a worker. The CPU 120 includes an instruction cache 121 and a load / store unit 122.

  The instruction cache 121 is a cache memory that stores instruction data, and is configured to be able to operate with high reliability even in a low-voltage operation, such as a large memory cell transistor size or a large number of transistors. The load / store unit 122 is a unit that performs processing for writing the data of the CPU 120 to the SRAM 150 and processing for reading the data of the SRAM 150 from the CPU 120.

  The bus 130 is a unit that connects modules existing in the processor 10. The input / output unit 140 is a unit that connects the processor 10 and an external system. The SRAM 150 is a shared memory in which data used for calculation by the CPU 110 (master) and the CPU 120 (worker) is stored. For example, the data shown in FIG. 2 is stored.

  The timer 160 is a timer that counts time, and based on the control information 111 including the low voltage set value information 201 and the voltage change interval information 202 received from the CPU 110, a control including a voltage change instruction to the voltage / frequency control unit 170. Information 161 is output, and interrupt information 162 including information indicating completion of voltage change is output to the CPU 110.

  The voltage / frequency control unit 170 is a unit that changes the operating voltage and operating frequency of the processor 10. In this embodiment, the voltage of the CPU 110 and the CPU 120 is commonly controlled by the voltage / frequency control unit 170, but independent control may be performed by different voltage / frequency control units.

  FIG. 2 is an example of data stored in the SRAM 150. The low voltage set value information 201 is information on an operating voltage in a low voltage state and an operating frequency at which the CPU 110 and the CPU 120 can operate at the operating voltage. The voltage change interval information 202 is time interval information for changing the operating voltage of the processor 10. The address offset information 203 is address offset information of a storage area on the SRAM 150 that the CPU 110 assigns to the CPU 120.

  The task management information 204 is task management information given to the CPU 120 by the CPU 110, and is information indicating which worker (CPU 120) is processing which task and how many tasks are completed as a whole. The task queue 205 is a queue of tasks that the CPU 110 gives to the CPU 120. The worker (CPU 120) receives and processes tasks from the task queue 205 until there are no more tasks in the task queue 205.

  The task calculation result information 206 is information on the calculation result of the task processed by the CPU 120 (worker), and is information for the CPU 110 (master) to acquire the calculation result, such as arrangement address information of the calculation result. The master work data 207 is data generated by the CPU 110 (master) during the processing. The worker work data 208 is data generated by the CPU 120 (worker) during the processing.

  The input data 209 is input data to be calculated, for example, image data to be machine learning teacher data. The survival confirmation information 210 is information for confirming the worker's survival status. The target error number 211 is a target value for the number of error data that the processor 10 counts in a predetermined process during program execution. The allowable error number 212 is a threshold that the application can tolerate in the number of error data counted by the processor 10 in the processing of a predetermined part during program execution.

  FIG. 3 is a time chart illustrating an example of parallel processing executed by the CPU 110 (master) and the CPU 120 (worker) in the processor 10. First, the CPU 110 (master) performs processing 301 up to the time before performing parallel processing in a standard voltage state. Thereafter, in a process 302, a task queue creation process and a worker activation process 321 are performed. The CPU 120 (worker) performs worker activation processing 311 and notifies the master of completion. The master that has confirmed the completion of all worker activations sets the low voltage set value information 201 and the voltage change interval information 202 in the timer 160, and performs the sleep process 303.

  The timer 160 outputs an operation voltage and an operation frequency setting value change instruction (control information 161) to the voltage / frequency control unit 170 based on the low voltage setting value information 201. The voltage / frequency control unit 170 changes the operating voltage and the operating frequency based on the setting value change instruction from the timer 160, and puts the processor 10 into a low voltage state. The worker acquires a task from the task queue 205 and performs task processing 312 using the input data 209. When the processing of the acquired task is completed, the worker writes the storage address of the task calculation result to the SRAM 150 as the task calculation result information 206, and acquires and processes a new task from the task queue 205. The worker repeats this until there are no more tasks in the task queue 205.

  The timer 160 outputs a setting value change instruction (control information 161) to the standard voltage to the voltage / frequency control unit 170 after a predetermined time based on the voltage change interval information 202, and after the voltage change, the interrupt information 162 is sent to the master. Output. The master that has received the interrupt information 162 performs management processing 304 for confirming the progress status of the task and the survival status of the worker. Here, when a worker (worker 2) accesses the SRAM 150 in a low voltage state and an accident 313 that stops due to corruption of pointer data or the like has occurred, the master executes the restart process 322 of the worker 2 To do. In the restart process 322, the master changes the offset value of the address area on the SRAM 150 used by the worker to be restarted. As a result, the restarted worker (worker 2) accesses an address area different from the previous one, so that it is possible to avoid stopping due to the same cause as the accident 313.

  The survival status can be confirmed by periodically counting up the data of the survival confirmation information 210 on the SRAM 150 and observing the data by the master. If all the tasks are not completed in the management process 304, the master outputs the control information 111 to the timer 160 and performs the sleep process 303 as in the process 302. When all the tasks are completed in the management process 304, the task end notification 323 is notified to the worker, and the post-processing 305 is performed.

  Thus, when the master accesses the SRAM 150, the data held by the master can be correctly held by always setting the SRAM 150 voltage to the standard voltage state. Further, the task queue 205, task calculation result information 206, and survival confirmation information 210 are held in triplicate on the SRAM 150, and data is highly reliable (data can be completely restored by correction processing) even in a low voltage state. It can be accessed. On the other hand, when the worker accesses the SRAM 150, the power consumption of the SRAM 150 can be reduced by setting the voltage of the SRAM 150 to a low voltage state.

  Next, means for changing the data arrangement of the address area on the SRAM 150 used by the CPU 120 (worker) that is restarted by the CPU 110 (master) will be described with reference to FIGS. 4, 5, and 6. 4, 5, and 6 are diagrams showing the data arrangement of the address area used by the worker. The master secures an address area that the worker uses for work when starting the worker larger than the size that is actually allocated, sets an offset value and an index value of the address area on the SRAM 150 to the worker, and allocates an address area that can be used by the worker . The offset value is the physical start address of the address area assigned to the worker, and the index value is the logical start address in the address area assigned to the worker.

  As shown in FIG. 4, for example, the master allocates an address area 401 to the worker 1, assigns an address area 410 to the worker 1 by setting the address 411 as an offset value (start address), and the remaining address area 451. Is a margin area. Similarly, the address area 402 is allocated to the worker 2, and the address area 420 is assigned by setting the address 421 as an offset value. The initial value of the index value is set as zero. Information regarding the address offset of the worker possessed by the master is stored in the SRAM 150 as address offset information 203, and the offset value and index value possessed by the worker are stored in the load / store unit 122 of the worker.

  Here, when restarting the worker 2, as shown in FIG. 5, the master changes the offset value of the worker 2 to the address 422 and restarts. Thereby, since the data arrangement of the worker 2 is changed, an event in which the worker 2 stops many times due to the same cause can be avoided.

  If the worker 2 repeatedly stops even after changing the offset value, the master changes the index value of the worker 2 as shown in FIG. The load / store unit 122 of the worker 2 changes the data arrangement by ring-shifting the address where the data is arranged in the address area 420 according to the changed index value. FIG. 4 shows an example in which the offset value of the worker 2 is set to the address 422 and the address conversion is performed so that the address 422 becomes the logical start address of the worker 2 in accordance with the change of the index value.

  By changing the data arrangement in this way, it is possible to prevent the restarted worker from repeatedly stopping due to the same cause as the previous stop.

  Next, parallel processing executed by the processor 10 will be described with reference to FIGS. 7 and 8. FIG. 7 is a flowchart of processing performed by the CPU 110 (master) of the processor 10. First, the master executes task queue 205 creation processing (step S701). Here, the information in the task queue 205 is written with high reliability by triple or the like. Thus, the worker can acquire accurate information from the task queue 205 even when the SRAM 150 is in a low voltage state. Since the information in the task queue 205 is very small compared to the whole, the power loss caused by the triple operation is very small. Thereafter, worker activation processing (step S702) is performed, low voltage set value information 201 and voltage change interval information 202 are set in the timer 160 as voltage change processing (step S703), and the process proceeds to sleep processing (step S704). When the master receives the interrupt information 162 from the timer 160 (step S705), the master cancels the sleep process, moves to step S706, and performs worker survival confirmation and worker restart processing. Thereafter, the task management information 204 is referred to in step S707 to check the progress of the task processing status. If all the tasks in the task queue 205 have been processed, the task end notification 323 is sent to all the CPUs 120 (workers). Is transferred to step S710, and if all the tasks in the task queue 205 have not been processed, branch processing (step S708) of shifting to S703 is performed.

  In step S710, it is checked whether the calculation result of the task processed by the worker satisfies a predetermined format. For example, in the K-means clustering algorithm which is a kind of unsupervised learning, the number of the cluster to which each element of the input data belongs is always smaller than the number K of clusters. In this way, it is checked whether the calculation result of the worker satisfies a value range that can be taken as the calculation result. As a result, when the master uses the calculation result of the worker as the element number of the array, it is possible to avoid a fatal error that causes the system to stop such as array overflow. A calculation result that does not satisfy the predetermined format is discarded.

  In step S711, the master performs a process of adjusting reliability so that the number of calculation results that do not satisfy the predetermined format approaches the target error number 211. The reliability is adjusted by changing the voltage value of the low voltage set value information 201. When the number of discarded data is larger than the target error number 211, the voltage value is set to a higher value in order to improve the reliability of the SRAM 150. When the number of discarded data is smaller than the target error number 211, the voltage value is set to a lower value in order to improve the power efficiency of the SRAM 150. In step S711, when the number of calculation results that do not satisfy the predetermined format is equal to or greater than the allowable error number 212, all of the worker calculation results are discarded, and the process proceeds to step S703 to retry the calculation. Process. The computer system including the processor 10 has an API (Application Programming Interface) that allows the user to easily set the low voltage set value information 201, the target error number 211, and the allowable error number 212. Note that if the number of errors is not particularly finely adjusted to maintain accuracy, the computer system including the processor 10 can omit step S711.

  FIG. 8 is a flowchart of processing performed by the CPU 120 (worker) activated by the CPU 110 (master) in S702 of FIG. The activated worker confirms the task progress status in the task queue 205 in step S801, and proceeds to step S820 if all tasks are completed as step S802, and to S810 if unprocessed tasks remain. Transition. In S820, the process waits until the task end notification 323 is received from the master, and the worker ends the process. In S810, the task is acquired from the task queue 205, and the acquired task identification number and its own worker identification number are written in the task management information 204 so that it can be understood which worker has acquired which task. The task acquired as step S811 is processed. The calculation result of the task processed in step S812 is output to the SRAM 150, and the task identification number that has been processed and its worker identification number are written to the task management information 204 so that it can be seen that the processing of the acquired task has been completed. Include. Here, the data of the task management information 204 is written with high reliability by triple or the like. In the flow from S801 to S820, the worker updates the survival confirmation information 210 at a predetermined interval.

  With the above configuration and processing, it is possible to realize the low-power processor 10 that avoids the entire system from being stopped without completely correcting the failure bit in the SRAM.

  Next, means for setting the low voltage set value information 201 and the target error number 211 of the processor 10 will be described with reference to FIGS. 9, 10, and 11. In the reliability adjustment process of step S711 shown in FIG. 7, it is necessary to set the target error number 211 in the program. When a computer system including the processor 10 is provided to the user, it may be difficult for the user to set parameters such as the target error number 211 in consideration of the application program. In such a case, the user can set an optimum parameter without being aware of the application program by executing the parameter adjustment program 1003. The parameter adjustment program 1003 executes the application program on the processor 10 using the test data for parameter adjustment prepared by the user and the accuracy target value information of the calculation result set in advance, thereby improving the accuracy of the calculation result. The low voltage set value information 201 in which the power is the lowest within the range satisfying the target value is acquired, and the target error number 211 is acquired.

  FIG. 9 is a diagram illustrating a configuration example of the computer system 1 including the processor 10. The memory 20 is a memory composed of a DRAM or the like. Information shown in FIG. 10 is stored in the memory 20. The input / output unit 30 is a unit that connects the external system and the computer system 1. The bus 40 is a bus that connects the components of the computer system 1.

  FIG. 10 is an example of data stored in the memory 20. The application program 1001 is an application program that is a parameter adjustment target. Test data 1002 is input test data for adjusting the parameters of the low voltage set value information 201 and the target error number 211. The parameter adjustment program 1003 is a program for searching for the optimum parameter of the application program 1001. The accuracy target value information 1004 is reference information that defines allowable accuracy degradation.

  A method for acquiring the setting values of the low voltage setting value information 201 and the target error number 211 without the user being aware of the application program will be described using the flowchart of the parameter adjustment program 1003 in FIG. First, the computer system 1 performs correct reference data generation (step S1101). The correct reference data is a calculation result at the time of high-reliability calculation obtained by executing the low voltage set value information 201 of the processor 10 as a standard voltage value (that is, executing all processes at the standard voltage). It is data used for comparison with the calculation result at the time of high efficiency calculation including operation.

  In step S1102, the parameter of the low voltage set value information 201 is set to a value smaller by the voltage value update width information 1005. That is, here, the voltage value update width information 1005 is set to a value smaller than the standard voltage. Next, in step S1103, the application program 1001 is executed to obtain a calculation result at the time of high efficiency calculation including low voltage operation. In step S1104, the result is compared with the correct answer reference data, and the calculation accuracy deteriorates at the time of high efficiency calculation. A calculation accuracy deterioration value indicating the degree is acquired.

  In step S1105, the calculated accuracy deterioration value and accuracy target value information 1004 are compared. If the target calculation accuracy is satisfied, the process proceeds to step S1102, and the value of the low voltage set value information 201 is further converted to a voltage value. The update width information 1005 is set to a small value. If the target calculation accuracy is not satisfied in the process of step S1105 in the Nth trial, the low voltage setting value information 201 in the N-1th trial is obtained as the low voltage setting value information 201 in the application program 1001. Further, in step S1110, an average value of the number of discarded data counted in step S710 (data integrity check) in the N-1th trial is obtained as the target error number 211.

  With the above configuration and processing, the user can acquire the set values of the low voltage set value information 201 and the target error number 211 without being aware of the application program, and reduce power consumption while satisfying the required calculation accuracy. The computer system 1 can be realized. Here, an example in which the low voltage set value information 201 is gradually decreased from the standard voltage, that is, an example in which an optimum parameter is obtained by gradually changing from a high voltage value to a low voltage value is shown. It is also possible to obtain optimum parameters by changing to a higher voltage value.

  In the second embodiment, an example of a computer system 3 in which the power consumption of the DRAM is reduced will be described.

  FIG. 12 is a configuration example of the computer system 3 in this embodiment. The computer system 3 includes a processor 1810, a processor 1820, a bus 40, an input / output unit 30, and a DRAM 1830. The same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.

  The processor 1810 and the processor 1820 are processors configured by a CPU or the like. The computer system 3 is a computer system that performs the calculation of the master-worker configuration as in the first embodiment. The processor 1810 serves as a master and the processor 1820 serves as a worker. The memory 1830 is a memory according to the present invention, and is composed of a storage device such as a DRAM that requires refreshing to prevent data volatilization.

  The memory 1830 includes an input / output unit 1910, a control unit 1920, a bus 1940, and a storage unit 1930 as shown in FIG. A bus 1940 is a bus for connecting components in the memory 1830. The input / output unit 1910 is a unit that connects the bus 40 and the inside of the memory 1830, and performs processing related to the communication protocol.

  The control unit 1920 is a control unit of the memory 1830, and performs data writing and reading processing to the storage unit 1930, ECC processing associated therewith, and further refresh processing. The control unit 1920 has a storage unit 1921.

  As shown in FIG. 14, the storage unit 1921 has first refresh rate information 2001 and second refresh rate information 2002. The first refresh rate information 2001 is the refresh rate of the high reliability area 1931 of the storage unit 1930, and the second refresh rate information 2002 is the refresh rate of the low power area 1932. The first refresh rate information 2001 and the second refresh rate information 2002 are set from the processor 1810 (master). The higher the refresh rate, the more frequently refreshing is performed, so the reliability of the storage unit is improved but the power consumption is also increased. For this reason, the refresh rate (first refresh rate information 2001) of the low power region 1932 is set lower than the refresh rate (second refresh rate information 2002) of the high reliability region 1931.

  The storage unit 1930 is a storage device composed of an array of DRAMs, and has a high reliability area 1931 and a low power area 1932. The high-reliability area 1931 is an address area that operates so that the number of failed bits of data held is within a range that can be correctly corrected by the ECC executed by the control unit 1920. The low power area 1932 is an address area that operates so that the number of failed bits of data held is outside the range that can be correctly corrected by the ECC executed by the control unit 1920. That is, the data written in the low power region 1932 is output to the bus 40 while having an error at the time of reading.

  Data included in the high reliability region 1931 is shown in FIG. In FIG. 15, the same data as in FIG. Rate change interval information 2102 is information on an interval for changing the refresh rate. Data included in the low power region 1932 is shown in FIG. In FIG. 16, the same data as in FIG. The high reliability area 1931 is an area accessed by both the master and the worker, and stores data for controlling the computer system. On the other hand, the low-reliability area 1932 is an area accessed by a worker, and stores input data such as images and text, intermediate data for calculation, and the like.

  Next, a processing flow of the computer system 3 will be described with reference to an operation flowchart of the computer system 3 shown in FIG. In FIG. 17, the same elements as those of FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In parallel processing, the master performs task queue creation processing (step S701), performs worker activation processing (step S702), and sleeps for a predetermined time (step S704). In the task queue creation process in this embodiment, the master stores the created task queue in the high reliability area 1931. Thereafter, in step S705, the state transits to an active state based on reception of interrupt information and an internal timer, worker survival confirmation and restart processing (step S706) are performed, and task progress confirmation (step S707) is performed. If all the tasks are not completed, the process proceeds to step S704. If all the tasks are completed, a data soundness check is performed on the obtained result (step S710). In step S2311, reliability adjustment processing is performed by the same means as in step S711 in the first embodiment. However, in the computer system 1 in the first embodiment, the data reliability (that is, the number of failed bits in the data or the failure bit rate) is adjusted by changing the voltage. However, in the computer system 3 in the present embodiment, the data reliability is improved. The difference is that the adjustment is performed by changing the refresh rate of the DRAM (step S2311). That is, the computer system 3 performs the reliability adjustment by changing the second refresh rate information 2002 that determines the refresh rate of the low power region 1932. When the number of discarded data is larger than the target error number 211, the refresh rate is set to a higher value in order to improve the reliability of the DRAM 1932. When the number of discarded data is smaller than the target error number 211, the refresh rate is set to a lower value in order to improve the power efficiency of the DRAM 1932.

  Also in the present embodiment, the worker activated by the processing of S702 executes the series of processing of FIG. 8, but the processing is executed on the input data 208 stored in the low-reliability area 1932, and the worker as the processing result is executed. The point that the work data 209 is stored in the low reliability area is different from the first embodiment.

  With the above configuration and processing, it is possible to realize a low-power computer system 3 that avoids the entire system from being stopped without completely correcting the failure bit in the DRAM. In a system using a large-capacity DRAM, most of the power consumed by the DRAM is for refreshing. Therefore, the computer system in this embodiment can greatly reduce the power of the DRAM.

Claims (10)

A memory that transitions between a first operating state and a second operating state ;
Wherein said access to the memory of the first operating state, set to the data error rate in the memory is shifted to a higher second operating state than said first operation state, access to the memory A first processor to stop;
Computer system and a second processor to access the memory of the second operating state. A computer system according to claim 1, wherein
In the first operation state , the first processor stores work instruction contents for the second processor in the memory,
In the second operation state , the second processor reads out work instruction contents from the memory and executes processing. A computer system according to claim 2, wherein
The computer system according to claim 2, wherein the second operation state is a state in which an uncorrectable data error of 1 bit or more occurs in the memory. A computer system according to claim 2, wherein
A computer system, wherein the second operation state is determined based on a result of executing processing using a test pattern as input data. A computer system according to claim 2, wherein
In the second processor, the first storage area of the memory is allocated as a usable storage area,
The first processor checks whether the second processor is operating, and if not, allocates a second storage area to the second processor instead of the first storage area A computer system, wherein the second processor is restarted. A computer system according to claim 2, wherein
The first processor checks whether a processing result of the second processor satisfies a predetermined condition, and re-executes an operation instructed to the second processor if the predetermined result is not satisfied. Computer system. A computer system according to claim 2, wherein
The memory is SRAM (Static Random Access Memory),
The computer system characterized in that the first and second operating states are determined by an operating voltage of the memory, and the operating voltage in the second operating state is lower than the operating voltage in the first operating state. A control method for a computer system comprising a first and a second processor and a memory that transitions between a first operating state and a second operating state ,
Said first processor, said access to the memory of the first operating state, set to the data error rate in the memory is shifted to a higher second operating state than the first operating state , Stop accessing the memory,
The second processor accesses to the memory of the second operating state, the control method of the computer system. A control method for a computer system according to claim 8 , comprising:
In the first operation state , the first processor stores work instruction contents for the second processor in the memory,
Said second processor, said in a second operating state, performs the process by reading the work instruction contents from the memory, the control method of the computer system. A control method for a computer system according to claim 9 , comprising:
The memory is SRAM (Static Random Access Memory),
The computer system characterized in that the first and second operation states are determined by an operation voltage of the memory, and the operation voltage in the second operation state is lower than the operation voltage in the first operation state. Control method.

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