JP6246518B2 - Transistor - Google Patents

Description

  The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a manufacturing method thereof.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor device such as a transistor, a power device, an integrated circuit including a power device, a power supply circuit, or a power conversion circuit, a semiconductor circuit, and an arithmetic device are one embodiment of the semiconductor device. In addition, a memory device, an imaging device, an electro-optical device, a display device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface is known. The transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image display device (also simply referred to as a display device). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor has attracted attention as another material.

  In addition, semiconductor devices manufactured using silicon are widely distributed as semiconductor devices for high withstand voltage. However, the performance of semiconductor devices using silicon is approaching its limit, and it has become difficult to achieve higher performance.

  In addition, since silicon has a small band gap, a semiconductor device for high withstand voltage using the silicon has a limited operating range at a high temperature. For this reason, in recent years, development of semiconductor devices using SiC or GaN having a wide band gap has been promoted.

  In addition, it is disclosed that an oxide semiconductor is used for a semiconductor device used for high power (Patent Documents 1 and 2).

JP 2011-91382 A JP 2011-172217 A

  A transistor applied to a semiconductor device for high power is desired to pass a large current. Moreover, it is desired that normal operation is possible even at high temperatures. It is also desirable to have a high drain current.

  In order to reduce power consumption of a semiconductor device including a transistor, it is desirable to control the threshold voltage of the transistor to an appropriate value.

  An object of one embodiment of the present invention is to provide a semiconductor device capable of flowing a large current. Another object is to provide a semiconductor device that can operate at high temperature. Another object is to provide a semiconductor device that operates stably with a high driving voltage. Another object is to provide a semiconductor device in which threshold voltage can be easily controlled. Another object is to provide a semiconductor device with reduced power consumption. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with favorable characteristics. Another object is to provide a novel semiconductor device.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  According to one embodiment of the present invention, a semiconductor layer, a source electrode and a drain electrode which are electrically connected to the semiconductor layer and are separated from each other in a region overlapping with the semiconductor layer, a first gate electrode and a second electrode provided with the semiconductor layer interposed therebetween A semiconductor device having a first gate insulating layer between the semiconductor layer and the first gate electrode, and a second gate insulating layer between the semiconductor layer and the second gate electrode. is there. The first gate electrode is provided so as to overlap with part of the source electrode, the semiconductor layer, and part of the drain electrode. The second gate electrode overlaps with part of the semiconductor layer, and the end of the source electrode on the drain electrode side and the end of the second gate electrode on the source electrode side are separated from each other when viewed from the upper surface side. Further, the end of the drain electrode on the source electrode side and the end of the second gate electrode on the drain electrode side are separated from each other when viewed from the upper surface side.

  In the above, it is preferable that the distance between the second gate electrode and the drain electrode as viewed from the upper surface side is larger than the distance between the second gate electrode and the source electrode.

  The semiconductor layer preferably has an island shape, the drain electrode has an annular shape having an opening overlapping the semiconductor layer, and the source electrode is preferably provided inside the opening.

  Alternatively, the semiconductor layer preferably has an island shape, the source electrode has an annular shape having an opening overlapping with the semiconductor layer, and the drain electrode is preferably provided inside the opening.

  The semiconductor layer preferably contains an oxide semiconductor.

  At this time, the semiconductor device further includes a first oxide layer between the semiconductor layer and the second gate insulating layer, and a second oxide layer between the semiconductor layer and the first gate insulating layer. Is preferred. In particular, the first oxide layer and the second oxide layer preferably include one or more metal elements that are the same as those of the semiconductor layer.

  According to one embodiment of the present invention, a semiconductor device capable of flowing a large current can be provided. Alternatively, a semiconductor device capable of high temperature operation can be provided. Alternatively, a semiconductor device that operates stably with a high driving voltage can be provided. Alternatively, a semiconductor device in which the threshold voltage can be easily controlled can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a highly reliable semiconductor device can be provided.

4 illustrates a configuration example of a semiconductor device according to an embodiment. The structural model used for calculation based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. The calculation result of the transistor characteristic based on Embodiment. 4 illustrates a configuration example of a semiconductor device according to an embodiment. 4 illustrates a configuration example of a semiconductor device according to an embodiment. 8A to 8D illustrate an example of a method for manufacturing a semiconductor device according to an embodiment. 4 illustrates a configuration example of a semiconductor device according to an embodiment. 4 illustrates a configuration example of a semiconductor device according to an embodiment. 4 illustrates a configuration example of a semiconductor device according to an embodiment. The structural example of the power converter circuit based on Embodiment. The structural example of the power converter circuit based on Embodiment. 3 shows a configuration example of a power supply circuit according to an embodiment. 3 shows a configuration example of a power supply circuit according to an embodiment. 4 illustrates a configuration example of a buffer circuit according to an embodiment. FIG. 10 is a circuit diagram illustrating a memory device according to Embodiment; 10A and 10B each illustrate a structure of a display panel according to Embodiment; An electronic device according to an embodiment. An electronic device according to an embodiment.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

  In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

  A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

(Embodiment 1)
In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention will be described with reference to drawings. Here, a transistor is described as an example of a semiconductor device.

  A semiconductor device according to one embodiment of the present invention has a structure including two gate electrodes, a first gate electrode and a second gate electrode, with a semiconductor layer in which a channel is formed interposed therebetween, and By providing a region that does not overlap with one of the gate electrodes, the control of the threshold voltage of the transistor and the improvement of the field effect mobility and the drain current can be realized at the same time.

  More specifically, for example, the following configuration can be adopted.

[Configuration example]
FIG. 1 is a schematic cross-sectional view in the channel length direction for describing the positional relationship between typical components in a configuration example of a transistor of one embodiment of the present invention.

  In the transistor illustrated in FIG. 1A, the semiconductor layer 102, the first electrode 103a and the second electrode 103b that are electrically connected to the semiconductor layer 102, and the semiconductor layer 102 overlap with the insulating layer 104, respectively. 1 gate electrode 105a and a second gate electrode 105b which is provided to face the first gate electrode 105a with the semiconductor layer 102 interposed therebetween and overlaps with part of the semiconductor layer 102 with the insulating layer 106 interposed therebetween. .

  Note that although the first gate electrode 105a is shown above the second gate electrode 105b in FIG. 1A, the upper and lower positional relationship is not limited.

  The semiconductor layer 102 can include a semiconductor such as silicon in a region where a channel is formed, but preferably includes a semiconductor having a larger band gap than silicon. Preferably, the semiconductor layer 102 includes an oxide semiconductor.

  For example, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). More preferably, an oxide represented by an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) is included.

  By applying an oxide semiconductor having a larger band gap than silicon to the semiconductor layer 102 in which a channel is formed, variation in electric characteristics of the transistor can be extremely small even at high temperatures. Therefore, by using an oxide semiconductor for the semiconductor layer 102, a transistor capable of stable operation at high temperature can be realized.

  Further, by using an oxide semiconductor for the semiconductor layer 102, resistance to hot carrier deterioration can be increased, and a high drain breakdown voltage can be applied to the transistor. Therefore, a transistor that operates stably at a high driving voltage can be realized.

  Here, hot carrier deterioration means that electrons accelerated at high speed are injected into the gate insulating layer in the vicinity of the drain in the channel to become a fixed charge, or a trap level is formed at the gate insulating layer interface. Transistor characteristic deterioration such as threshold voltage fluctuation and gate leakage occurs, and causes of hot carrier deterioration include channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). .

  Since silicon has a narrow band gap, electrons are likely to be generated in an avalanche due to avalanche breakdown, and the number of electrons accelerated faster as the barrier of the gate insulating layer is exceeded. However, since the oxide semiconductor described in this embodiment has a wide band gap, avalanche breakdown is less likely to occur and resistance to hot carrier deterioration is higher than that of silicon.

  Thus, it can be said that the transistor has a high drain breakdown voltage. Therefore, it is suitable for a power device such as an insulated gate field effect transistor (IGFET: Insulated-Gate Field-Effect Transistor).

  The first electrode 103a functions as a source electrode of the transistor. In addition, the second electrode 103b functions as a drain electrode of the transistor.

  Here, the first gate electrode 105a is provided so as to overlap the semiconductor layer 102 from the end portion of the first electrode 103a to the end portion of the second electrode 103b.

  On the other hand, the second gate electrode 105b is provided between the end portion of the first electrode 103a and the end portion of the second electrode 103b so as not to overlap with any of the first electrode 103a and the second electrode 103b. Is provided. In other words, a region (also referred to as an offset region) that does not overlap with the second gate electrode 105 b is provided on both the first electrode 103 a side and the second electrode 103 b side of the semiconductor layer 102.

  Here, as shown in FIG. 1A, the interval between the first electrode 103a and the second electrode 103b is referred to as a channel length L. In addition, the distance between the first electrode 103a and the second gate electrode 105b when viewed from the upper surface side at least in a region overlapping with the semiconductor layer 102 is referred to as an offset length Loff1, and the second electrode 103b and the second electrode 103b The distance from the gate electrode 105b is referred to as an offset length Loff2.

  The ratio of the offset length Loff1 to the channel length L (that is, Loff1 / L) may be 0 or more and 0.95 or less, preferably 0 or more and 0.5 or less, and more preferably 0 or more and 0.25 or less. The ratio of the offset length Loff2 to the channel length L (ie, Loff2 / L) is 0 or more and 0.95 or less, preferably 0.5 or more and 0.95 or less, more preferably 0.75 or more and 0.95 or less. That's fine. Actually, it is assumed that the variation includes a variation of plus or minus 10%.

  The first gate electrode 105a can be supplied with a potential for controlling the on state of the transistor. For example, a potential for turning on the transistor or a potential for turning off the transistor is supplied. By applying such a potential, the switching operation of the transistor can be realized.

  A potential for controlling the threshold voltage of the transistor can be applied to the second gate electrode 105b. Preferably, a potential lower than the potential applied to the first electrode 103a functioning as the source electrode is applied. By applying such a potential, the threshold voltage of the transistor can be positively shifted. In particular, normally-off transistor characteristics can be obtained by applying an appropriate potential to the second gate electrode 105b.

  By disposing the second gate electrode 105b for applying such a potential offset from both the first electrode 103a functioning as a source electrode and the second electrode 103b functioning as a drain electrode, an offset region is formed. In the case where it is not provided, that is, compared with the case where it is provided so as to overlap with the first electrode 103a and the second electrode 103b, not only the shift amount of the threshold voltage is made equal, but also the field effect mobility of the transistor. And the source-drain current in the on state (also referred to as on-current and drain current) can be increased.

  Note that the second gate electrode 105b may be provided so as not to overlap with at least the first electrode 103a and the second electrode 103b. Therefore, even when one or both of the offset lengths Loff1 and Loff2 are 0, the second gate electrode 105b overlaps with the first electrode 103a and the second electrode 103b as compared with the case where the transistor is provided. The field effect mobility can be improved and the drain current can be increased.

  When the potential applied to the second gate electrode 105b is constant, the shift amount of the threshold voltage increases as the width of the second gate electrode 105b in the channel length direction increases. On the other hand, the smaller the width of the second gate electrode 105b in the channel length direction, the higher the field-effect mobility and the on-current can be increased. The width of the second gate electrode 105b in the channel length direction with respect to the channel length L is preferably as small as possible from the viewpoint of on-state current and field-effect mobility, but a shift in driving voltage of a transistor or a desired threshold voltage What is necessary is just to set suitably in consideration of quantity.

  Here, a potential higher than that applied to the first electrode 103a functioning as the source electrode can be applied to the second gate electrode 105b. By applying such a potential, the threshold voltage of the transistor can be negatively shifted.

  Alternatively, a potential for controlling the on state of the transistor can be applied to the second gate electrode 105b. For example, it is preferable to apply the same potential as that input to the first gate electrode 105a. At this time, the second gate electrode 105b may be electrically connected to the first gate electrode 105a with a wiring, a plug, or the like (not shown). With such a structure, a wiring for supplying a potential to the first gate electrode 105a and the second gate electrode 105b can be shared, and the circuit structure can be simplified.

  Note that the potential for controlling the on state of the transistor input to the second gate electrode 105b is not limited to the above, and the potential input to the first gate electrode 105a is considered in consideration of the thickness of the insulating layer 106, electrical characteristics, and the like. May be a higher potential or a lower potential. In addition, a signal whose potential rise or fall timing is shifted with respect to a signal (a signal whose potential level changes with time) input to the first gate electrode 105a may be input to the second gate electrode 105b. .

  By applying such a potential to the second gate electrode 105b, a channel region formed in the semiconductor layer 102 is expanded, the field-effect mobility of the transistor can be improved, and the on-state current can be increased.

  In the transistor illustrated in FIG. 1B, the second gate electrode 105b is disposed so that the offset length Loff2 is larger than the offset length Loff1 as compared with the transistor illustrated in FIG. ing.

  Thus, when the width in the channel length direction of the second gate electrode 105b is constant, the distance (offset length Loff2) between the second gate electrode 105b and the second electrode 103b when viewed from the upper surface side is as follows. A larger value can improve the field-effect mobility of the transistor and increase the on-state current. In particular, as the distance (offset length Loff1) between the second gate electrode 105b and the first electrode 103a when viewed from the upper surface side is closer to 0, the increase in on-state current becomes more significant.

In addition, as illustrated in FIG. 1C, the second gate electrode 105b may be divided into a plurality of portions in the channel length direction and separated from each other. Here, for convenience, the distance between the second gate electrodes 105b ₁ and 105b ₂ divided into two is referred to as an offset length Loff3.

At this time, the second gate electrode 105b ₁ and the second gate electrode 105b ₂ which is divided into two are both to be located between the first electrode 103a and the second electrode 103b when viewed from the top side It is preferable to arrange.

  Note that although the example in which the second gate electrode 105b is divided into two is shown here, a configuration in which the second gate electrode 105b is divided into three or more is also possible. In that case also, it is preferable that the second gate electrode divided into a plurality of portions be disposed so as to be positioned between the first electrode 103a and the second electrode 103b when viewed from the upper surface side. Such a structure in which the second gate electrode 105b is divided into a plurality of parts can be referred to as a multi-gate structure.

  In this manner, by dividing the second gate electrode 105b into a plurality of portions and having a plurality of offset regions in which the semiconductor layer 102 and the second gate electrode 105b do not overlap with each other in the channel length direction, the field effect transfer of the transistor is performed. And the on-current can be increased.

Further, as shown in FIG. 1D, one or more of the plurality of second gate electrodes divided into a plurality may be arranged at a position farther from the semiconductor layer 102 than the others. In FIG. 1D, among the second gate electrodes 105b ₁ , 105b ₂ , and 105b ₃ divided into _three , the second gate electrode 105b ₂ is arranged at a position farther from the semiconductor layer 102 than the others. Shows the case. Note that, for the sake of clarity, description of a channel length, an offset length, and the like is omitted in FIG.

The second gate electrode 105 b ₂ is disposed so as to overlap with part of the semiconductor layer 102 with the insulating layer 106, the insulating layer 108, and the insulating layer 109 interposed therebetween.

At this time, a potential different from the others may be supplied to the second gate electrode arranged at a position farther from the semiconductor layer 102 than others. For example, in the structure illustrated in FIG. 1D, a potential lower than the potential applied to the first electrode 103a is applied to the second gate electrodes 105b ₁ and 105b ₃ , and the second gate electrode 105b ₂ is supplied with a potential lower than that. A low potential can also be applied.

  The above is the description of this configuration example.

  As described above, the transistor of one embodiment of the present invention can impart normally-off electrical characteristics by applying an appropriate potential to the second gate electrode. Further, by using an oxide semiconductor for the semiconductor layer, leakage current in an off state (also referred to as off-state current) can be extremely small. Therefore, power consumption of a semiconductor device including the transistor of one embodiment of the present invention can be reduced.

  In addition, since the transistor of one embodiment of the present invention has a higher drain breakdown voltage than that in the case where silicon is used for a semiconductor layer, the transistor can be preferably used for a device that requires a high drain breakdown voltage. Further, the transistor of one embodiment of the present invention can easily control a threshold voltage, and can flow a high drain current even when the threshold voltage is shifted to have a normally-off characteristic. Therefore, it can be suitably used for a device that is required to be driven with high efficiency and low power consumption. For example, it can be suitably used for a power supply circuit, a power conversion circuit such as a DCDC converter or an inverter, a transmission circuit or reception circuit related to signal transmission / reception, a power reception circuit that receives power.

  In addition, by using a semiconductor material having a wider band gap than silicon for the semiconductor layer, stable operation can be performed even at high temperatures. In particular, the transistor of one embodiment of the present invention can flow a large current, and self-heating during driving may be remarkable. In a semiconductor device for high power, the usage environment may become high due to heat generated from other elements. However, the transistor of one embodiment of the present invention can maintain stable electrical characteristics even in such a high temperature environment, and can improve reliability in a high temperature environment of a semiconductor device to which the transistor is applied.

  In addition, since the transistor of one embodiment of the present invention can achieve high drain breakdown voltage and high field-effect mobility, the channel length and the channel width can be reduced, and the area occupied by the element can be reduced. Therefore, it can be suitably used for devices that require high integration and element miniaturization. For example, in an image display device including a plurality of pixels, high definition of the pixels is possible. Further, it can be suitably used for an IC such as a memory device or an arithmetic unit for which high integration is desired.

[Verification by simulation]
Below, the result of having verified about the influence which the difference in arrangement | positioning of each gate electrode has on the electrical property of a transistor is shown.

[Calculation model]
First, a transistor model used in the calculation is shown in FIGS. For the calculation, device simulation software Sentaurus (manufactured by synopsys) was used.

  The transistor illustrated in FIG. 2A includes a first gate insulating layer (GI1) over a semiconductor layer (OS), and a first gate electrode (GE1) over the first gate insulating layer (GI1). Have. On the semiconductor layer (OS), a source electrode (Source) and a drain electrode (Drain) are spaced apart. A region (n +) with a high donor density is formed in a region overlapping with the source electrode (Source) and the drain electrode (Drain) of the semiconductor layer (OS). A second gate insulating layer (GI2) is disposed below the semiconductor layer (OS), and the second gate insulating layer (GI2) overlaps with part of the semiconductor layer (OS) below the second gate insulating layer (GI2). A gate electrode (GE2) is disposed. That is, the second gate electrode (GE2) is provided so as not to overlap with the source electrode (Source) and the drain electrode (Drain).

  Here, the distance between the source electrode (Source) and the drain electrode (Drain) is defined as a channel length L. The distance between the source electrode (Source) and the second gate electrode (GE2) when viewed from the upper surface side is the offset length Loff1, and the distance between the drain electrode (Drain) and the second gate electrode (GE2) is The offset length is Loff2. In addition, the overlap length Lov is a length where the second gate electrode (GE2) and the semiconductor layer (OS) overlap in a region between the source electrode (Source) and the drain electrode (Drain).

  In this calculation model, the calculation was performed assuming an oxide semiconductor as a semiconductor used for the semiconductor layer.

  Table 1 shows the conditions used for the calculation.

  In addition, in the transistor illustrated in FIG. 2B, the second gate electrode (GE2) includes a source electrode (Source), a drain electrode (Drain), and a semiconductor layer between them as compared with FIG. (OS) is different in that it is arranged so as to be superimposed on the whole. Here, the length Lov at which the second gate electrode (GE2) and the semiconductor layer (OS) overlap is equal to the channel length L.

  The transistor illustrated in FIG. 2C is different from that in FIG. 2A in that the second gate electrode (GE2) is not included.

[Dependence of overlap length of second gate electrode]
In the model shown in FIG. 2A, first, the overlap length Lov between the second gate electrode (GE2) and the semiconductor layer (OS) (that is, the width of the second gate electrode (GE2) in the channel length direction). The transistor characteristics were calculated while changing. Here, conditions were used in which the position of the second gate electrode (GE2) was fixed at an intermediate position between the source electrode (Source) and the drain electrode (Drain). That is, the offset length Loff1 between the second gate electrode (GE2) and the source electrode (Source) and the offset length Loff2 between the second gate electrode (GE2) and the drain electrode (Drain) when viewed from the upper surface side. Matching conditions were used. Further, the calculation was performed by changing the overlap length Lov by L / 20 in a range from L / 20 to L with reference to the channel length L. Further, a model in which the second gate electrode (GE2) is provided so as to overlap with the source electrode and the drain electrode (FIG. 2B), and a model in which the second gate electrode (GE2) is not disposed (FIG. 2C). ) Was also calculated.

  In the calculation, the channel length L was 10 μm, and the calculation was performed under two conditions of 0.1 V and 3.0 V as the source-drain voltage (hereinafter referred to as the drain voltage Vd).

  FIG. 3A shows the relationship between the source-drain current (hereinafter referred to as the drain current Id) and the gate-source voltage (hereinafter referred to as the gate voltage Vg) when the drain voltage Vd is 0.1 V. It is the calculation result of (it is also called Vg-Id characteristic). FIG. 3B shows the relationship of the field effect mobility with respect to the gate voltage Vg estimated from the Vg-Id characteristics of FIG. 4A and 4B are similarly calculated results when the drain voltage Vd is set to 3.0V. In the figure, the model (FIG. 2B) in which the second gate electrode (GE2) is provided so as to overlap with the source electrode and the drain electrode is shown by a one-dot chain line, and the second gate electrode (GE2) is arranged. The models that are not used (FIG. 2C) are indicated by broken lines.

  Note that the Id-Vg characteristics and field-effect mobility shown in FIGS. 3 and 4 are almost the same between the Lov = L condition and the second gate electrode (GE2). Therefore, they are displayed in an overlapping manner.

  Here, FIG. 3 shows the result of the condition where the drain voltage is sufficiently small, and corresponds to the electrical characteristics of the transistor in the linear region. On the other hand, FIG. 4 shows the result of the condition where the drain voltage is sufficiently high, and corresponds to the electrical characteristics of the transistor in the saturation region.

  FIG. 5 shows the relationship of various characteristics of the transistor with respect to each Lov condition calculated for each condition of the drain voltage Vd. FIG. 5A shows the threshold voltage value for each Lov condition. FIG. 5B shows the maximum value of field effect mobility under each Lov condition. FIG. 5C shows the drain current value for each Lov condition. Here, the drain current Id indicates the drain current Id when the gate voltage Vg is 1.5 V higher than the threshold voltage in order to facilitate comparison under each condition. Further, in FIG. 5D, in order to facilitate comparison between conditions of different drain voltages Vd, the drain current Id under the condition that the second gate electrode (GE2) is arranged as a whole is 100%. The ratio of the drain current Id in each Lov condition is shown.

  From FIG. 3 to FIG. 5, it was confirmed that the threshold voltage can be shifted more positively as the overlap length Lov between the second gate electrode (GE2) and the semiconductor layer (OS) is larger. More specifically, the threshold voltage changes abruptly with respect to the condition in which the second gate electrode (GE2) is not disposed even under the condition that Lov is the smallest (Lov = L × 1/20). There was a tendency for the rate to rise gradually as Lov increased.

  It was also confirmed that the field effect mobility and the drain current Id tend to increase as Lov decreases. It was confirmed that both the field-effect mobility and the drain current Id are more markedly changed with respect to Lov when the drain voltage Vd is large (in the saturation region). The value of the drain current Id under the condition that Lov is the smallest (Lov = L × 1/20) is 0.1V (linear region) as compared with the case where the second gate electrode (GE2) is arranged as a whole. It was confirmed that the current ratio was improved about 1.4 times under the condition of 1.3 and 2.3 times under the condition of the drain voltage of 3.0 V (saturation region).

  As described above, by providing a region (offset region) where the second gate electrode (GE2) and the semiconductor layer (OS) do not overlap on both the source side and the drain side, the second gate electrode (GE2) is provided as the source. It was confirmed that the field-effect mobility and the drain current can be improved as compared with the case where the entire structure is arranged from the electrode to the drain electrode.

  Further, even when the width (Lov) in the channel length direction of the second gate electrode (GE2) is sufficiently small with respect to the channel length L, the second gate electrode (GE2) is extended from the source electrode to the drain electrode. The threshold voltage can be shifted as in the case of the entire arrangement. Further, it was confirmed that the field effect mobility and the drain current Id can be increased as the width (Lov) in the channel length direction of the second gate electrode (GE2) is smaller than the channel length L.

[Position dependence of second gate electrode]
Subsequently, the transistor when the width (Lov) in the channel length direction of the second gate electrode (GE2) is fixed and the position is changed from the source electrode (Source) side to the drain electrode (Drain) side. The influence on the electrical characteristics of the Specifically, the overlap length Lov between the second gate electrode (GE2) and the semiconductor layer (OS) is fixed to L / 20, and the offset length between the source electrode (Source) and the second gate electrode (GE2). The calculation was performed by changing Loff1 from 0 to L × 19/20 by L / 20. Here, the condition that Loff1 is 0 means that the source-side end portion of the second gate electrode (GE2) and the drain-side end portion of the source electrode (Source) coincide with each other when viewed from the upper surface side. Similarly, the condition that Loff1 is L × 19/20 is when the end on the drain side of the second gate electrode (GE2) matches the end on the source side of the drain electrode (Drain) when viewed from the upper surface side. Means.

  6 and 7 show the relationship between the Ig-Vd characteristics when the drain voltage Vd is 0.1 V and 3.0 V, respectively, and the field effect mobility with respect to the gate voltage Vg. FIG. 8 shows the relationship between various characteristics of the transistor for each Loff1 condition calculated for each drain voltage Vd. 8A shows the threshold voltage value for each Loff1 condition, FIG. 8B shows the maximum field effect mobility for each Loff1 condition, and FIG. 8C shows each Loff1. The value of the drain current Id with respect to the conditions is shown. FIG. 8D shows the ratio of the drain current Id under each Loff1 condition when the drain current Id under the condition where the second gate electrode (GE2) is disposed as a whole is 100%.

  6 to 8, it was confirmed that the threshold voltage value was substantially constant even when the magnitude of Loff1, that is, the position of the second gate electrode (GE2) was changed.

  Further, the field effect mobility is almost constant regardless of the magnitude of Loff1 when the drain voltage Vd is small (in the linear region), whereas it is Loff1 when the drain voltage Vd is large (in the saturation region). It was confirmed that the value rose sharply toward 0.

  Further, the drain current Id is almost constant regardless of the magnitude of Loff1 when the drain voltage Vd is small (in the linear region), whereas Loff1 is large under the condition where the drain voltage Vd is large (in the saturation region). It was confirmed that the smaller the value, the higher the rate.

  From the above results, it was confirmed that the field effect mobility and the drain current Id can be further improved by arranging the second gate electrode (GE2) close to the source side. It was confirmed that the drain voltage Vd is large and becomes more prominent in the case of driving in the saturation region.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, a more specific structure example of a semiconductor device of one embodiment of the present invention and an example of a manufacturing method thereof will be described with reference to drawings. Here, a transistor is described as an example of a semiconductor device. In addition, description may be abbreviate | omitted about the part which overlaps with the above.

[Configuration example]
FIG. 9A is a schematic top view of the transistor 100 in this structural example. 9B and 9C are schematic cross-sectional views taken along section lines AB and CD in FIG. 9A, respectively. Note that some components are not illustrated in FIG. 9A for clarity.

  The transistor 100 is provided over a substrate 101 and has an island-shaped semiconductor layer 102, a first electrode 103 a and a second electrode 103 b that are electrically connected to the semiconductor layer 102, and a first electrode that overlaps the semiconductor layer 102. The first gate electrode 105a and the second gate electrode 105b, the insulating layer 104 between the first gate electrode 105a and the semiconductor layer 102, and the insulating layer 106 between the second gate electrode 105b and the semiconductor layer 102. Have. An insulating layer 107 is provided to cover the insulating layer 106, the first electrode 103a, the second electrode 103b, the first gate electrode 105a, and the like.

  The first electrode 103 a functions as a source electrode of the transistor 100. In addition, the second electrode 103 b functions as a drain electrode of the transistor 100.

  Here, as illustrated in FIGS. 9A and 9B, the distance between the first electrode 103 a and the second electrode 103 b in a portion overlapping with the semiconductor layer 102 is a channel length L of the transistor 100.

  A first gate electrode 105 a is provided so as to cover the semiconductor layer 102 in a region sandwiched between the first electrode 103 a and the second electrode 103 b. The first gate electrode 105a is provided so as to overlap with part of the first electrode 103a and part of the second electrode 103b.

  On the other hand, the second gate electrode 105b is provided so as to overlap with part of the semiconductor layer 102 in a region between the first electrode 103a and the second electrode 103b.

  Here, as shown in FIGS. 9A and 9B, in the region overlapping with the semiconductor layer 102, from the end of the first electrode 103 a to the end of the second gate electrode 105 b when viewed from the upper surface side. The distance is the offset length Loff1, and the distance from the end of the second electrode 103b to the end of the second gate electrode 105b is the offset length Loff2. The offset lengths Loff1 and Loff2 are both above, and the second gate electrode 105b is arranged so that the sum of Loff1 and Loff2 is smaller than the channel length L.

  An insulating layer 108 is provided in contact with the side surface of the second gate electrode 105b. In addition, it is preferable that the top surfaces of the second gate electrode 105b and the insulating layer 108 are flattened and the heights thereof coincide with each other. By flattening at least the lower portion of the semiconductor layer 102, the uniformity of the thickness and film quality of the semiconductor layer 102 can be increased, and the stability and variation in the electrical characteristics of the transistor can be improved.

  The insulating layer 108 preferably includes a film that releases oxygen by heating. For example, a structure including an insulating film having an oxygen excess region may be used. As the insulating film having an oxygen-excess region, for example, an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used. In such an oxide insulating film, part of oxygen is released by heating.

  Since the transistor 100 has a structure in which the second gate electrode 105b does not cover the entire semiconductor layer 102, oxygen released from the insulating layer 108 due to heat treatment in the manufacturing process of the transistor is interposed through the insulating layer 106 in the semiconductor layer 102. The oxygen vacancies in the semiconductor layer 102 can be compensated and the oxygen vacancies in the semiconductor layer 102 can be reduced.

  Here, as illustrated in FIG. 9C, the semiconductor layer 102 is surrounded by the first gate electrode 105 a and the second gate electrode 105 b in the cross section of the transistor 100 in the channel width direction. Further, the first gate electrode 105 a is provided so as to cover not only the upper surface of the semiconductor layer 102 but also an end portion in the channel width direction. With such a structure, since the electric field from the first gate electrode 105a is applied not only in the vertical direction but also in the horizontal direction with respect to the semiconductor layer 102, the region where the channel of the semiconductor layer 102 is formed is enlarged. The on-state current of the transistor 100 can be further increased.

[About each component]
Hereinafter, each component of the transistor 100 will be described.

[Semiconductor layer]
In the case where an oxide semiconductor is used for the semiconductor layer 102, an oxide semiconductor containing at least one of indium and zinc is preferably used. Typically, an In—Ga—Zn-based metal oxide or the like can be given. It is preferable to use an oxide semiconductor with a wider band gap and lower carrier density than silicon because leakage current in an off state can be suppressed.

  As the semiconductor layer 102, an oxide semiconductor film may be used as a single layer, or oxide semiconductor films having different compositions may be stacked.

  For example, a structure in which two layers of oxide semiconductor films are stacked and a material whose lower energy of the conduction band is higher than that of a lower oxide semiconductor film is used for the oxide semiconductor film close to the first gate electrode 105a side. Alternatively, a structure in which three or more oxide semiconductor films are stacked is used, and a material having lower energy in the lower end of its conduction band is used for the oxide semiconductor film provided inside. With such a structure, a channel is mainly formed in the oxide semiconductor film having the lowest energy at the lower end of the conduction band.

  In the case where an In-M-Zn oxide is used for the oxide semiconductor film, the energy at the lower end of the conduction band may be decreased as the ratio of the In atomic ratio to the M atomic ratio in the film increases. it can. Moreover, the stability of the crystal structure increases as the proportion of Zn increases. Further, as the proportion of M is larger, release of oxygen from the oxide semiconductor film can be suppressed.

  By providing an oxide semiconductor film that includes the same constituent elements in contact with the oxide semiconductor film that is mainly formed with a channel and serves as a main current path, generation of these interface states is suppressed, and the electrical characteristics of the transistor Reliability is improved. Further, when a material having a large atomic ratio of M is used for an oxide semiconductor film which is provided in contact with an oxide semiconductor film in which a channel is mainly formed, the oxide semiconductor in which a channel is mainly formed Oxygen vacancies in the film can be reduced.

  Note that a preferable embodiment of an oxide semiconductor that can be applied to the semiconductor layer 102 and a formation method thereof will be described in detail in later embodiments.

  In addition to silicon, a semiconductor having a larger band gap than silicon such as silicon carbide, gallium nitride, or diamond can be used as a semiconductor other than an oxide semiconductor. An oxide semiconductor is preferably used from the viewpoints of ease of manufacture, stability of electrical characteristics, and the like.

  Hereinafter, a case where an oxide semiconductor is used for the semiconductor layer 102 is described unless otherwise specified.

〔substrate〕
There is no particular limitation on the material of the substrate 101, but a material having heat resistance enough to withstand the heat applied to the process is used. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, a yttria stabilized zirconia (YSZ) substrate, or the like may be used as the substrate 101. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used.

  In addition, a substrate in which a semiconductor element is provided over various semiconductor substrates or SOI substrates may be used as the substrate 101. In that case, the transistor 100 is formed over the substrate 101 with an interlayer insulating layer interposed therebetween. At this time, at least one of electrodes such as the first gate electrode 105a, the second gate electrode 105b, the first electrode 103a, and the second electrode 103b of the transistor 100 is formed by the connection electrode embedded in the interlayer insulating layer. However, it may be configured to be electrically connected to the semiconductor element. By providing the transistor 100 over the semiconductor element with an interlayer insulating layer interposed therebetween, the occupied area can be reduced as compared with the case where they are formed over the same plane.

[Gate electrode]
The first gate electrode 105a and the second gate electrode 105b are formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-described metal as a component, or a combination of the above-described metals. It can be formed by using an alloy or the like. Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used. The gate electrode 105 may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film is stacked on the titanium film, and a titanium film is further formed thereon is there. Alternatively, an alloy film in which one or a plurality of metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum, or a nitride film thereof may be used.

  The first gate electrode 105a and the second gate electrode 105b are formed using indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive material such as indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal can be used.

  In addition, an In—Ga—Zn-based oxynitride semiconductor film or an In—Sn-based oxynitride semiconductor is provided between the first gate electrode 105 a and the insulating layer 104 or between the second gate electrode 105 b and the insulating layer 106. Film, In—Ga-based oxynitride semiconductor film, In—Zn-based oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, ZnN, etc.), etc. May be. These films have a work function of 5 eV, preferably 5.5 eV or more, and have a value larger than the electron affinity of the oxide semiconductor, so that the threshold voltage of a transistor including the oxide semiconductor is shifted to plus. Therefore, a switching element having a so-called normally-off characteristic can be realized. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of the semiconductor layer 102, specifically, 7 atomic% or more is used.

[Gate insulation layer]
The insulating layer 104 and the insulating layer 106 function as a gate insulating layer.

  For the insulating layer 104 and the insulating layer 106, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn-based metal oxide, silicon nitride, or the like may be used. Provided.

As the insulating layer 104 and the insulating layer 106, hafnium silicate (HfSiO _x ), hafnium silicate added with nitrogen (HfSi _x O _y N _z ), or hafnium aluminate added with nitrogen (HfAl _x O _y N _z ) Alternatively, a high-k material such as hafnium oxide or yttrium oxide may be used.

  Note that when a specific material is used for the gate insulating layer, the threshold voltage can be increased by trapping electrons in the gate insulating layer under specific conditions. For example, a material having a high electron capture level, such as hafnium oxide, aluminum oxide, or tantalum oxide, is used for a part of the gate insulating layer, such as a stacked film of silicon oxide and hafnium oxide. The temperature of the gate electrode is higher than the potential of the source electrode or the drain electrode at a temperature higher than the temperature or storage temperature, or 125 ° C. to 450 ° C., typically 150 ° C. to 300 ° C. By maintaining for 1 second or more, typically 1 minute or more, electrons move from the semiconductor layer toward the gate electrode, and some of them are captured by the electron capture level.

  As described above, the threshold voltage of the transistor that captures an amount of electrons necessary for the electron capture level is shifted to the positive side. The amount of electrons captured can be controlled by controlling the voltage of the gate electrode, and the threshold voltage can be controlled accordingly. Further, the process for trapping electrons may be performed in the manufacturing process of the transistor.

  For example, after the formation of the wiring metal connected to the source or drain electrode of the transistor, after the completion of the previous process (wafer processing), after the wafer dicing process, after packaging, etc. You should do it. In any case, it is preferable that the film is not subsequently exposed to a temperature of 125 ° C. or higher for 1 hour or longer.

[First electrode, second electrode]
The first electrode 103a and the second electrode 103b are each made of a single metal made of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component. Used as a layered structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, a two layer structure in which an aluminum film is stacked on a titanium film, a two layer structure in which an aluminum film is stacked on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film Two-layer structure to stack, two-layer structure to stack a copper film on a titanium film, two-layer structure to stack a copper film on a tungsten film, a titanium film or a titanium nitride film, and an overlay on the titanium film or titanium nitride film A three-layer structure in which an aluminum film or a copper film is stacked and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper layer stacked on the molybdenum film or the molybdenum nitride film There is a three-layer structure in which films are stacked and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[Insulating layer]
The insulating layer 106 and the insulating layer 108 may have a function of supplying oxygen to the semiconductor layer 102 and a function of preventing impurities contained in the substrate 101 from diffusing.

The insulating layer 106 and the insulating layer 108 are preferably formed using an oxide insulating film containing more oxygen than that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of the stoichiometric composition. An oxide insulating film containing more oxygen than that in the stoichiometric composition is desorbed in terms of oxygen atoms by thermal desorption gas spectroscopy (TDS) analysis. The oxide insulating film has an amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more.

  By using such an insulating film for the insulating layer 106 and the insulating layer 108, oxygen can be supplied to the semiconductor layer 102 by heat treatment or the like in the manufacturing process, so that oxygen vacancies in the semiconductor layer 102 can be reduced.

  The insulating layer 107 can be formed using a material that does not easily transmit oxygen. Moreover, it is preferable to give the property of being hard to permeate hydrogen or water. Examples of the material that can be used for the insulating layer 107 and hardly transmit oxygen include silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and oxide. An insulating material such as hafnium nitride can be used. In particular, the above materials are materials that do not allow oxygen, hydrogen, and water to pass therethrough. By using such a material for the insulating layer 107, diffusion of oxygen released from the insulating layer 106 and the insulating layer 108 to the outside and entry of hydrogen, water, and the like from the outside into the semiconductor layer 102 and the like can be suppressed at the same time. be able to.

  Note that a layer that releases oxygen similar to the insulating layer 106 may be provided below the insulating layer 107. In the case where a structure such as a wiring is provided above the insulating layer 107, an insulating layer functioning as a planarization layer may be provided over the insulating layer 107.

  The above is the description of each component.

[Modification]
Hereinafter, a structural example of a transistor having a part of the structure different from that of the transistor 100 will be described. In addition, description is abbreviate | omitted about the part which overlaps with the above, and a difference is demonstrated in detail. Further, even when the positions and shapes of the constituent elements are different, the same reference numerals may be attached and the description may be omitted if the functions are the same.

[Modification 1]
FIG. 10A is a schematic cross-sectional view of a transistor exemplified below. Note that FIG. 9A can be used for a schematic top view. The transistor illustrated in FIG. 10A is different from the transistor 100 in that the shape of the insulating layer 104 is different. Specifically, a part of the insulating layer 104 is in contact with the insulating layer 106 and covers the top surfaces of the first electrode 103a and the second electrode 103b.

  With such a structure, the insulating layer 104 can function as an etching stopper when the gate electrode 105a is processed, and unintended thinning of the first electrode 103a and the second electrode 103b in the etching process is suppressed. it can.

[Modification 2]
In the semiconductor device of one embodiment of the present invention, at least one of the metal elements included in the oxide semiconductor layer is included as a component between the oxide semiconductor layer and the insulating layer overlapping with the oxide semiconductor layer. It is preferable to have an oxide layer included as Accordingly, formation of trap levels at the interface between the oxide semiconductor layer and the insulating layer overlapping with the oxide semiconductor layer can be suppressed.

  In other words, according to one embodiment of the present invention, an oxide layer in which at least a top surface and / or a bottom surface of a channel formation region of the oxide semiconductor layer functions as a barrier film for preventing formation of an interface state of the oxide semiconductor layer. It is preferable to have a configuration in contact. With such a structure, generation of oxygen vacancies that cause carriers to be generated in the oxide semiconductor and the interface and the introduction of impurities can be suppressed, so that the oxide semiconductor layer is highly purified and intrinsic. be able to. High purity intrinsic refers to making an oxide semiconductor layer intrinsic or substantially intrinsic. Therefore, a change in electrical characteristics of the transistor including the oxide semiconductor layer can be suppressed and a highly reliable semiconductor device can be provided.

Note that in this specification and the like, the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁷ / cm ^3, less than 1 × 10 ¹⁵ / cm ³ , or less than 1 × 10 ¹³ / cm ³ when it is substantially intrinsic. It is. By making the oxide semiconductor layer highly purified and intrinsic, stable electrical characteristics can be imparted to the transistor.

  More specifically, for example, the following configuration can be adopted.

  FIG. 10B is a schematic cross-sectional view of a transistor exemplified below. Note that FIG. 9A can be used for a schematic top view. The transistor illustrated in FIG. 10B is different in that it mainly includes a first oxide layer 121 and a second oxide layer 122.

  The first oxide layer 121 is provided between the insulating layer 106 and the semiconductor layer 102.

  The second oxide layer 122 is provided between the semiconductor layer 102 and the insulating layer 104. More specifically, the upper surface of the second oxide layer 122 is provided in contact with the lower surfaces of the first electrode 103 a and the second electrode 103 b and the lower surface of the insulating layer 104.

  The first oxide layer 121 and the second oxide layer 122 each include an oxide containing one or more metal elements that are the same as those of the semiconductor layer 102.

  Note that the boundary between the semiconductor layer 102 and the first oxide layer 121 and the boundary between the semiconductor layer 102 and the second oxide layer 122 may be unclear.

  For example, the first oxide layer 121 and the second oxide layer 122 include In or Ga, and are typically In—Ga based oxide, In—Zn based oxide, or In—M—Zn based. A material which is an oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) and whose energy at the lower end of the conduction band is closer to a vacuum level than the semiconductor layer 102 is used. Typically, the difference between the energy at the lower end of the conduction band of the first oxide layer 121 or the second oxide layer 122 and the energy at the lower end of the conduction band of the semiconductor layer 102 is 0.05 eV or more, 0 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less is preferable.

  The first oxide layer 121 and the second oxide layer 122 which are provided so as to sandwich the semiconductor layer 102 are formed using an oxide having a higher Ga content which functions as a stabilizer than the semiconductor layer 102. Release of oxygen from the layer 102 can be suppressed.

  For example, when an In—Ga—Zn-based oxide with an atomic ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 is used as the semiconductor layer 102, the first oxide layer 121 or the first oxide layer 121 As the two oxide layers 122, for example, In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: 6: 4, 1: 6: 8, 1: 6: 10. Alternatively, an In—Ga—Zn-based oxide with an atomic ratio of 1: 9: 6 or the like can be used. Note that the atomic ratios of the semiconductor layer 102, the first oxide layer 121, and the second oxide layer 122 each include a variation of plus or minus 20% of the above atomic ratio as an error. For the first oxide layer 121 and the second oxide layer 122, materials having the same composition may be used, or materials having different compositions may be used.

In the case where an In-M-Zn-based oxide is used for the semiconductor layer 102, a target used for forming a semiconductor film to be the semiconductor layer 102 has an atomic ratio of metal elements contained in the target of In: When M: Zn = x ₁ : y ₁ : z ₁ , the value of x ₁ / y ₁ is 1/3 or more and 6 or less, preferably 1 or more and 6 or less, and z ₁ / y ₁ is 1/3. It is preferable to use an oxide having an atomic ratio of 6 or more, preferably 1 or more and 6 or less. Note that by setting z ₁ / y ₁ to 6 or less, a CAAC-OS film described later can be easily formed. Typical examples of the atomic ratio of the target metal element include In: M: Zn = 1: 1: 1, 3: 1: 2.

In addition, in the case where an In-M-Zn-based oxide is used for the first oxide layer 121 and the second oxide layer 122, the oxide to be the first oxide layer 121 and the second oxide layer 122 The target used for forming the film is x ₂ / y ₂ <x ₁ when the atomic ratio of the metal elements contained in the target is In: M: Zn = x ₂ : y ₂ : z _2. / Y ₁ and an oxide having an atomic ratio of z ₂ / y ₂ of 1/3 to 6 and preferably 1 to 6 is preferably used. Note that by setting z ₂ / y ₂ to 6 or less, a CAAC-OS film described later can be easily formed. Typical examples of the atomic ratio of the target metal element include In: M: Zn = 1: 3: 4, 1: 3: 6, and 1: 3: 8.

  In addition, when the first oxide layer 121 and the second oxide layer 122 are formed using a material whose energy at the lower end of the conduction band is close to a vacuum level as compared with the semiconductor layer 102, a channel is mainly formed in the semiconductor layer 102. The semiconductor layer 102 is formed as a main current path. In this manner, by sandwiching the semiconductor layer 102 in which a channel is formed between the first oxide layer 121 and the second oxide layer 122 containing the same metal element, generation of these interface states is suppressed. This improves the reliability of the electrical characteristics of the transistor.

  Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, variation, and the like) of the transistor. In addition, in order to obtain necessary semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, and number of metal elements and oxygen atoms of the semiconductor layer 102, the first oxide layer 121, and the second oxide layer 122 It is preferable to make the ratio, interatomic distance, density, etc. appropriate.

  Here, the semiconductor layer 102 is preferably formed to be thicker than at least the first oxide layer 121. The thicker the semiconductor layer 102, the higher the on-state current of the transistor. The first oxide layer 121 may have a thickness that does not lose the effect of suppressing the generation of the interface state of the semiconductor layer 102. For example, the thickness of the semiconductor layer 102 is more than 1 time, preferably 2 times or more, more preferably 4 times or more, more preferably 6 times or more with respect to the thickness of the first oxide layer 121. That's fine. Note that this is not limited to the case where it is not necessary to increase the on-state current of the transistor, and the thickness of the first oxide layer 121 may be greater than or equal to the thickness of the semiconductor layer 102.

  Similarly to the first oxide layer 121, the second oxide layer 122 may have a thickness that does not lose the effect of suppressing the generation of the interface state of the semiconductor layer 102. For example, the thickness may be equal to or less than that of the first oxide layer 121. If the second oxide layer 122 is thick, the electric field generated by the first gate electrode 105a may not easily reach the semiconductor layer 102. Therefore, the second oxide layer 122 is preferably formed thin. For example, the thickness may be smaller than the thickness of the semiconductor layer 102. Note that the thickness of the second oxide layer 122 is not limited to this, and may be set as appropriate depending on the voltage for driving the transistor in consideration of the withstand voltage of the insulating layer 104 and the like.

  Here, for example, when the semiconductor layer 102 is in contact with an insulating layer having a different constituent element (eg, an insulating layer including a silicon oxide film), an interface state is formed at the interface, and the interface state forms a channel. Sometimes. In such a case, a second transistor having a different threshold voltage appears, and the apparent threshold voltage of the transistor may fluctuate. However, since the transistor having this structure includes the first oxide layer 121 containing one or more metal elements included in the semiconductor layer 102, the interface between the first oxide layer 121 and the semiconductor layer 102 is included. It becomes difficult to form interface states. Therefore, by providing the first oxide layer 121, variation or fluctuation in electrical characteristics such as threshold voltage of the transistor can be reduced.

  In addition, when a channel is formed at the interface between the insulating layer 104 and the semiconductor layer 102, interface scattering occurs at the interface, and the field-effect mobility of the transistor is reduced. However, since the transistor having this structure includes the second oxide layer 122 containing one or more metal elements included in the semiconductor layer 102, the interface between the semiconductor layer 102 and the second oxide layer 122 is used. Then, carrier scattering hardly occurs, and the field-effect mobility of the transistor can be increased.

[Modification 3]
FIG. 10C is a schematic cross-sectional view of a transistor exemplified below. Note that FIG. 9A can be used for a schematic top view. The transistor illustrated in FIG. 10C is different from the transistor described in Modification 2 mainly in that the shape of the second oxide layer 122 is different.

  The lower surface of the second oxide layer 122 is provided in contact with the upper surfaces of the first electrode 103a and the second electrode 103b. Further, the first electrode 103 a and the second electrode 103 b are provided in contact with the upper surface of the semiconductor layer 102 in a region where the first electrode 103 a and the second electrode 103 b are not provided.

  In the structure illustrated in FIG. 10C, processing is performed using the same photomask so that the top surface shapes of the second oxide layer 122 and the insulating layer 104 substantially match the top surface shape of the first gate electrode 105a. Has been.

  Note that in this specification and the like, “the upper surface shape is approximately the same” means that at least a part of the contour overlaps between the stacked layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof by the same mask pattern is included. However, strictly speaking, the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

  With such a structure, the contact area between the first electrode 103a and the second electrode 103b and the semiconductor layer 102 in which the channel is formed can be increased, and the contact resistance can be reduced. it can. As a result, the on-state current of the transistor can be increased.

  The above is the description of the modified example.

[Example of production method]
An example of a method for manufacturing the transistor 100 illustrated in FIGS. 9A to 9C is described below with reference to drawings. FIG. 11 is a schematic cross-sectional view at each stage in the manufacturing process of the transistor 100.

[Formation of Second Gate Electrode]
First, a conductive film is formed over the substrate 101. Thereafter, a resist mask is formed over the conductive film by using a photolithography method or the like, unnecessary portions of the conductive film are removed by etching, and then the resist mask is removed to form the second gate electrode 105b. Can do.

  The conductive film can be formed by, for example, a sputtering method, an evaporation method, a CVD (Chemical Vapor Deposition) method, or the like.

  Note that an insulating layer functioning as a barrier layer may be formed over the substrate 101 before the conductive film is formed.

  As light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing them can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  Subsequently, an insulating film is formed. The insulating film is preferably formed thicker than the second gate electrode 105a. Subsequently, the insulating layer 108 is formed by performing a planarization process on the insulating film using a CMP (Chemical Mechanical Polishing) method or the like so that the upper surface of the second gate electrode 105b is exposed. Yes (FIG. 11A).

  The insulating film to be the insulating layer 108 can be formed by a sputtering method, a CVD method, an MBE (Molecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, or the like.

  In order to make the insulating layer 108 contain excessive oxygen, for example, an insulating film to be the insulating layer 108 may be formed in an oxygen atmosphere. Or oxygen may be introduce | transduced into the insulating film after film-forming, and oxygen may be contained excessively, and both means may be combined.

  For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  For the treatment for introducing oxygen, a gas containing oxygen can be used. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the treatment for introducing oxygen, a dilution gas such as a rare gas may be included in the gas containing oxygen.

  Note that although the method for forming the second gate electrode 105b first is described here, an insulating film to be the insulating layer 108 may be formed first. In that case, the insulating film is formed over the substrate 101, a resist mask is formed by a photolithography method or the like, an unnecessary portion of the insulating film is removed by etching, and the second gate electrode 105b is provided. A recess is formed in the surface. After that, a conductive film is formed so as to fill the concave portion, and planarization treatment is performed so that the upper surface of the insulating film is exposed, whereby the insulating layer 108 and the second gate electrode 105b can be formed.

(Formation of insulating layer)
Subsequently, the insulating layer 106 is formed. The insulating layer 106 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like.

  The insulating layer 106 preferably contains excess oxygen by a method similar to that of the insulating layer 108.

[Formation of semiconductor layer]
Subsequently, a semiconductor film is formed over the insulating layer 106. Thereafter, a resist mask is formed over the semiconductor film by using a photolithography method or the like, and unnecessary portions of the semiconductor film are removed by etching. After that, by removing the resist mask, the island-shaped semiconductor layer 102 can be formed (FIG. 11B).

  The semiconductor film can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. Alternatively, a thin film forming technique using a liquid material such as a sol-gel method, a spray method, or a mist method can also be used. The semiconductor film is preferably formed by a sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In particular, the DC sputtering method is preferably used because dust generated during film formation can be reduced and the film thickness distribution can be uniform.

  Heat treatment may be performed after the semiconductor film is formed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, oxygen is supplied from the insulating layer 108 or the insulating layer 106 to the semiconductor film (or the semiconductor layer 102), so that oxygen vacancies in the oxide semiconductor included in the semiconductor layer 102 can be reduced. Note that the heat treatment may be performed immediately after the semiconductor film is formed, or may be performed in a step after the semiconductor film is processed to form the island-shaped semiconductor layer 102.

  Further, an organic resin film having a function of improving adhesion between a film to be processed (here, a semiconductor film) and the resist film may be formed before forming a resist film to be a resist mask. In addition, the organic resin film can be formed so as to cover a step in the lower layer by, for example, a spin coating method, and variation in the thickness of the resist mask provided on the upper layer of the organic resin film can be reduced. In particular, when fine processing is performed, a material that functions as an antireflection film for light used for exposure is preferably used as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed or after the resist mask is removed.

  As a mask for etching the semiconductor film, a hard mask made of an inorganic film or a metal film may be used. For example, an inorganic film or a metal film is formed over the semiconductor film, and the inorganic film or the metal film is etched using an resist mask to be processed into an island shape to form a hard mask. After that, the semiconductor film may be etched using the hard mask as a mask, and the island-like semiconductor film may be formed by removing the hard mask. In particular, in the case of performing fine processing, by using a hard mask, reduction in pattern width due to resist side etching can be suppressed, and the semiconductor film can be processed into a stable shape. Can be reduced.

[Formation of first electrode and second electrode]
Subsequently, a conductive film is formed over the insulating layer 106 and the semiconductor layer 102. After that, a resist mask is formed over the conductive film using a photolithography method or the like, and unnecessary portions of the conductive film are removed by etching. After that, the resist mask is removed, whereby the first electrode 103a and the second electrode 103b can be formed (FIG. 11C).

  The conductive film can be formed by, for example, a sputtering method, a vapor deposition method, a CVD method, or the like.

  Here, when the conductive film is etched, a part of the upper portion of the semiconductor layer 102 is etched, and a portion which does not overlap with the first electrode 103a and the second electrode 103b may be thinned. Therefore, it is preferable that the thickness of the semiconductor film to be the semiconductor layer 102 be formed thick in advance in consideration of the etching depth.

[Formation of gate insulating layer and first gate electrode]
Subsequently, an insulating film is formed over the semiconductor layer 102, the first electrode 103 a, the second electrode 103 b, and the insulating layer 106. Further, a conductive film is formed over the insulating film.

  The insulating film is an insulating film that later becomes the insulating layer 104. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved.

  The conductive film is a conductive film that later becomes the first gate electrode 105a. The conductive film can be formed by, for example, a sputtering method, a vapor deposition method, a CVD method, or the like.

  Subsequently, a resist mask is formed over the conductive film by using a photolithography method or the like. Thereafter, unnecessary portions of the conductive film and the insulating film are sequentially removed by etching. After that, the resist mask is removed, whereby the first gate electrode 105a and the insulating layer 104 can be formed (FIG. 11D).

  Note that after the conductive film is etched to form the first gate electrode 105a, the resist mask may be removed, and the insulating layer 104 may be processed using the first gate electrode 105a as a hard mask.

(Formation of insulating layer)
Subsequently, an insulating layer 107 is formed over the first electrode 103a, the second electrode 103b, the first gate electrode 105a, the insulating layer 104, and the insulating layer 106 (FIG. 11E).

  The insulating layer 107 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. In particular, the insulating layer 107 is preferably formed by a CVD method, preferably a plasma CVD method, because the coverage can be improved.

  Through the above steps, the transistor 100 can be formed.

[Heat treatment]
Heat treatment may be performed after the insulating layer 107 is formed. By the heat treatment, oxygen can be supplied from the insulating layer 106, the insulating layer 108, and the insulating layer 107 to the semiconductor layer 102, so that oxygen vacancies in the semiconductor layer 102 can be reduced. At this time, oxygen released from the insulating layer 106, the insulating layer 108, and the semiconductor layer 102 is effectively confined inside the insulating layer 107, and release of the oxygen to the outside is suppressed. Therefore, the amount of oxygen released from the insulating layer 106 and the insulating layer 108 and supplied to the semiconductor layer 102 can be increased, and oxygen vacancies in the semiconductor layer 102 can be effectively reduced.

  The above is the description of the method for manufacturing the transistor 100.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, an example of a transistor whose structure is partly different from that of the transistor illustrated in Embodiment 2 will be described. In addition, description is abbreviate | omitted about the part which overlaps with the above, and a difference is demonstrated in detail. Further, even when the positions and shapes of the constituent elements are different, the same reference numerals may be attached and the description may be omitted if the functions are the same.

[Configuration example 1]
FIG. 12A is a schematic top view of the transistor 200 shown in this structural example. FIG. 12B is a schematic cross-sectional view taken along a cutting line EF in FIG.

  The transistor 200 is different from the transistor 100 described in Embodiment 1 in terms of the semiconductor layer 102, the first electrode 103a, the second electrode 103b, the insulating layer 104, the first gate electrode 105a, and the second gate electrode 105b. Are different mainly in that the top surface shape is different and the wiring 111 a and the wiring 111 b provided on the insulating layer 107 are newly provided.

  The island-shaped semiconductor layer 102 has a circular upper surface shape. The second electrode 103 b has an annular top surface shape having an opening in a region overlapping with the semiconductor layer 102. The first electrode 103a is provided so as to be located inside the opening of the second electrode 103b. The second gate electrode 105b has an annular top surface shape so as to overlap with part of the semiconductor layer 102 in a region sandwiched between the first electrode 103a and the second electrode 103b when viewed from above. A part of the second electrode 103b is drawn outside the second electrode 103b when viewed from above. The first gate electrode 105a has a circular top surface shape so as to overlap with part of the first electrode 103a, part of the second electrode 103b, and the semiconductor layer 102, and part of the first gate electrode 105a is a top surface. As viewed from the outside of the second electrode 103b. In addition, an opening is formed in a region where the first gate electrode 105a overlaps with the first electrode 103a. The first electrode 103a is electrically connected to the wiring 111a through an opening in the insulating layer 107 provided at a position overlapping with the opening in the first gate electrode 105a. The second electrode 103b is electrically connected to the wiring 111b through an opening in the insulating layer 107 provided thereabove.

  In this manner, by providing the second electrode 103b so as to surround the first electrode 103a, the channel width with respect to the occupied area of the transistor 200 can be increased as compared with the case where they are arranged in parallel. Therefore, a larger drain current can be obtained. Such a configuration can be suitably applied to a power device for high power.

  Further, the upper surface shape of the semiconductor layer 102 and the first electrode 103a is circular, and the upper surface shape of the second electrode 103b is an annular shape surrounding them, so that the channel length L is constant over the circumferential direction. It becomes possible. Note that the top surface shape of the semiconductor layer 102 is not limited thereto, and may be a polygon including a square or a rectangle, an ellipse, or a polygon with rounded corners. At this time, these shapes and arrangement methods may be set as appropriate so that the distance (channel length L) between the first electrode 103a and the second electrode 103b is constant.

  Note that, here, the first electrode 103a functioning as a source electrode is arranged on the inner side, and the second electrode 103b functioning as a drain electrode is arranged on the outer side. However, by changing the potential input to these, Each function may be exchanged.

[Configuration example 2]
FIG. 13A is a schematic top view of the transistor 210 shown in this structural example. FIG. 13B is a schematic cross-sectional view taken along the cutting line GH in FIG.

  In the transistor 210, the first gate electrode 105 a is located below the semiconductor layer 102 (on the substrate 101 side), and the second gate electrode 105 b is formed from the semiconductor layer 102 compared to the transistor 200 in the above structure example 1. Is mainly different in that the wiring 111c is newly provided on the insulating layer 107.

  The first gate electrode 105 a is provided closer to the substrate 101 than the semiconductor layer 102 with the insulating layer 106 interposed therebetween. The first gate electrode 105a has a circular upper surface shape with a larger radius than the semiconductor layer 102, and overlaps with part of the first electrode 103a, the semiconductor layer 102, and the second electrode 103b. Is provided.

  The second gate electrode 105b is provided on the insulating layer 104 and has an annular upper surface shape. The second gate electrode 105b is provided between the first electrode 103a and the second electrode 103b so as not to overlap with each other when viewed from above.

  The second gate electrode 105b is electrically connected to the wiring 111c through an opening in the insulating layer 107 provided thereabove.

  Here, as illustrated in FIG. 13B, a structure in which the top surface of the semiconductor layer 102 not covered with the second gate electrode 105 b is covered with an insulating layer 104 is preferable. By leaving the insulating layer 104 over the semiconductor layer 102, damage to the semiconductor layer 102 in the step of forming the insulating layer 107 can be suppressed.

  In the region of the semiconductor layer 102 that is not covered with the second gate electrode 105b, oxygen released from the insulating layer 107 by heat treatment in the manufacturing process is transferred to the channel formation region of the semiconductor layer 102 through the insulating layer 104. It becomes possible to supply. Accordingly, oxygen vacancies in the semiconductor layer 102 are reduced, and the reliability of the transistor 210 can be improved.

[Configuration example 3]
FIG. 14A is a schematic top view of the transistor 220 shown in this structural example. FIG. 14B is a schematic cross-sectional view taken along section line I-J in FIG.

  The transistor 220 is different from the transistor 200 in the above configuration example 1 in that the top surfaces of the first electrode 103a, the second electrode 103b, and the second gate electrode 105b are different, and the wirings 111a and 111b are provided. The main difference is that it does not.

  The first electrode 103 a is provided so that a part of the first electrode 103 a extends over the end portion of the semiconductor layer 102 as viewed from above. The second electrode 103b is provided over the semiconductor layer 102 so that the distance from the first electrode 103a is substantially constant. Further, part of the end portion of the semiconductor layer 102 has a region which does not overlap with the first electrode 103a and the second electrode 103b.

  In addition, the second gate electrode 105b has an upper surface shape such that the distance from the first electrode 103a and the distance from the second electrode 103b are substantially constant at least in a region overlapping with the semiconductor layer 102. ing. In addition, part of the second gate electrode 105 b extends over the end portion of the semiconductor layer 102 and is extracted to the outside.

  In this manner, by adopting a structure in which the wiring 111a, the wiring 111b, and the like are not provided, the process can be simplified. Furthermore, since the connection part of wiring or an electrode can be reduced, the influence of the contact resistance in the said connection part can be reduced. In particular, when a large current is passed, the connection portion becomes high temperature due to contact resistance, and there is a risk of disconnection in the worst case. Therefore, it is preferable to reduce the number of wires in this way.

  In addition, as illustrated in FIG. 14B, the first gate electrode 105a covers the end portion of the semiconductor layer 102 that is not covered with the first electrode 103a and the second electrode 103b. . Therefore, since the electric field from the first gate electrode 105a is applied not only in the vertical direction but also in the horizontal direction to the semiconductor layer 102 in the region, the region in which the channel of the semiconductor layer 102 is formed is expanded, The on-current can be further increased.

  Note that, here, the first electrode 103a functioning as a source electrode is arranged on the inner side, and the second electrode 103b functioning as a drain electrode is arranged on the outer side. However, by changing the potential input to these, Each function may be exchanged.

  The above is the description of each configuration example.

  Each of the transistors exemplified in this embodiment has a structure in which the channel width with respect to the occupied area of the transistor can be increased. Therefore, a larger drain current can be obtained, and it can be suitably used for a semiconductor device for high power.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, an oxide semiconductor that can be favorably used for the semiconductor layer of the semiconductor device of one embodiment of the present invention will be described.

  An oxide semiconductor has a large energy gap of 3.0 eV or more. In a transistor to which an oxide semiconductor film obtained by processing an oxide semiconductor under appropriate conditions and sufficiently reducing its carrier density is applied, The leakage current (off-state current) between the source and the drain in the off state can be made extremely low as compared with a conventional transistor using silicon.

  An applicable oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. In addition, as a stabilizer for reducing variation in electrical characteristics of a transistor using the oxide semiconductor, gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr), titanium (Ti) , Scandium (Sc), yttrium (Y), or a lanthanoid (for example, cerium (Ce), neodymium (Nd), gadolinium (Gd)), or a plurality of types are preferably included.

  For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg oxide In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn- Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In-Ti-Zn oxide In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd -Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn Oxide, In—Yb—Zn oxide, In—Lu—Zn oxide, In—Sn—Ga—Zn oxide, In—Hf—Ga—Zn oxide, In—Al—Ga— A Zn-based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide can be used.

  Here, the In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co, or the above-described element as a stabilizer. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

  For example, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 3: 2, In: Ga: Zn = 1: 3: 4, In: Ga: Zn = 1: 3: 6, An In—Ga—Zn-based oxide with an atomic ratio of In: Ga: Zn = 3: 1: 2 or In: Ga: Zn = 2: 1: 3 or an oxide in the vicinity of the composition may be used.

  When the oxide semiconductor film contains a large amount of hydrogen, the oxide semiconductor film is bonded to the oxide semiconductor, so that part of the hydrogen becomes a donor and an electron which is a carrier is generated. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the oxide semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film so that impurities are contained as little as possible. preferable.

  Note that oxygen may be reduced from the oxide semiconductor film at the same time due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to add oxygen that has been simultaneously reduced by dehydration treatment (dehydrogenation treatment) to the oxide semiconductor film or supply oxygen to fill oxygen vacancies in the oxide semiconductor film. . In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film may be referred to as oxygenation treatment or peroxygenation treatment.

As described above, the oxide semiconductor film is made i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and filling oxygen vacancies by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be obtained. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

As described above, a transistor including an i-type or substantially i-type oxide semiconductor film can realize extremely excellent off-state current characteristics. For example, the drain current when the transistor including an oxide semiconductor film is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 at room temperature (about 25 ° C.). × 10 ⁻²⁴ A or lower, or 1 × 10 ⁻¹⁵ A or lower, preferably 1 × 10 ⁻¹⁸ A or lower, more preferably 1 × 10 ⁻²¹ A or lower at 85 ° C. Note that an off state of a transistor means a state where a gate voltage is sufficiently lower than a threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold voltage, the transistor is turned off.

  Hereinafter, the structure of the oxide semiconductor film is described.

  An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

  First, the CAAC-OS film is described.

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

  When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

  When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

  On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

  From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most crystal parts included in the CAAC-OS film fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. Note that a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a planar TEM image, a crystal region that is 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

  From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

  Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

  In the CAAC-OS film, the distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the ratio of the crystal part in which the region near the upper surface is c-axis aligned than the region near the formation surface May be higher. In addition, in the case where an impurity is added to the CAAC-OS film, the region to which the impurity is added may be changed, and a region having a different ratio of partially c-axis aligned crystal parts may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

  The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

  The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

  A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

  In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

  Next, a microcrystalline oxide semiconductor film is described.

  In the microcrystalline oxide semiconductor film, there is a case where a crystal part cannot be clearly confirmed in an observation image using a TEM. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in an observation image using a TEM.

  The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus that uses X-rays having a beam diameter larger than that of a crystal part, a peak indicating a crystal plane is not detected by analysis using the out-of-plane method. . Further, when electron beam diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is obtained. Is observed. On the other hand, when nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter (for example, 1 nm to 30 nm) that is close to the crystal part or smaller than the crystal part. Spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

  The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

  Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 5)
In this embodiment, as an example of a semiconductor device of one embodiment of the present invention, a structural example of a power conversion circuit such as an inverter or a converter including the transistor described in the above embodiment will be described.

[DCDC converter]
A DCDC converter 501 illustrated in FIG. 15A is a step-down DCDC converter that uses a chopper circuit as an example. The DCDC converter 501 includes a capacitor 502, a transistor 503, a control circuit 504, a diode 505, a coil 506, and a capacitor 507.

  The DCDC converter 501 operates by the switching operation of the transistor 503 by the control circuit 504. The DCDC converter 501 can output the input voltage V1 applied to the input terminals IN1 and IN2 to the load 508 as V2 stepped down from the output terminals OUT1 and OUT2. The semiconductor device described in the above embodiment can be applied to the transistor 503 included in the DCDC converter 501. Therefore, a large output current can be allowed to flow through the switching operation, and an off current can be reduced. Therefore, it is possible to realize a DCDC converter that can reduce power consumption and operate at high speed.

  Although FIG. 15A shows a step-down DCDC converter using a chopper circuit as an example of a non-insulated power conversion circuit, a step-up DCDC converter using a chopper circuit and a chopper circuit are also used. The semiconductor device described in the above embodiment can also be applied to a transistor included in a step-up / step-down DCDC converter. Therefore, a large output current can be allowed to flow through the switching operation, and an off current can be reduced. Therefore, it is possible to realize a DCDC converter that can reduce power consumption and operate at high speed.

  Next, a DCDC converter 511 illustrated in FIG. 15B illustrates a circuit configuration example of a flyback converter which is an insulating power conversion circuit as an example. The DCDC converter 511 includes a capacitor 512, a transistor 513, a control circuit 514, a transformer 515 including a primary coil and a secondary coil, a diode 516, and a capacitor 517.

  The DCDC converter 511 illustrated in FIG. 15B operates by switching operation of the transistor 513 by the control circuit 514. The DCDC converter 511 can output the input voltage V1 applied to the input terminals IN1 and IN2 to the load 518 as V2 boosted or stepped down from the output terminals OUT1 and OUT2. The semiconductor device described in the above embodiment can be applied to the transistor 513 included in the DCDC converter 511. Therefore, a large output current can be allowed to flow through the switching operation, and an off current can be reduced. Therefore, it is possible to realize a DCDC converter that can reduce power consumption and operate at high speed.

  Note that the semiconductor device described in any of the above embodiments can be applied to a transistor included in a forward type DCDC converter.

[Inverter]
An inverter 601 illustrated in FIG. 16 is a full-bridge inverter as an example. The inverter 601 includes a transistor 602, a transistor 603, a transistor 604, a transistor 605, and a control circuit 606.

  The inverter 601 illustrated in FIG. 16 operates by switching operation of the transistors 602 to 605 by the control circuit 606. The DC voltage V1 applied to the input terminals IN1 and IN2 can be output as the AC voltage V2 from the output terminals OUT1 and OUT2. The semiconductor device described in the above embodiment can be applied to the transistors 602 to 605 included in the inverter 601. Therefore, a large output current can be flowed by the switching operation, and the off-current can be reduced. Therefore, power consumption can be reduced and an inverter capable of high-speed operation can be obtained.

  In the case where the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIGS. 15 and 16, the source electrode (first electrode) is provided on the low potential side, and the drain electrode (second electrode) is provided on the high potential side. It is configured to be electrically connected. Further, the potential of the first gate electrode is controlled by the control circuit, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). That's fine.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 6)
In this embodiment, as an example of a semiconductor device of one embodiment of the present invention, a structural example of a power supply circuit including the transistor described in the above embodiment will be described.

  FIG. 17 illustrates an example of a structure of the power supply circuit 400 according to one embodiment of the present invention. A power supply circuit 400 illustrated in FIG. 17 includes a control circuit 413, a power switch 401, a power switch 402, and a voltage adjustment unit 403.

  The power supply circuit 400 is supplied with a voltage from the power supply 416, and the power switch 401 and the power switch 402 have a function of controlling the input of the voltage to the voltage adjustment unit 403.

  When the voltage output from the power source 416 is an AC voltage, as shown in FIG. 17, the power switch 401 that controls the input of the first potential to the voltage adjustment unit 403 and the second to the voltage adjustment unit 403 A power switch 402 that controls input of a potential is provided in the power supply circuit 400. When the voltage output from the power supply 416 is a DC voltage, as shown in FIG. 17, the power switch 401 that controls the input of the first potential to the voltage adjustment unit 403 and the second potential to the voltage adjustment unit 403 The power switch 402 for controlling the input may be provided in the power supply circuit 400, or the power switch 402 for controlling the input of the second potential to the voltage adjusting unit 403 is not provided with the second potential as the ground potential. In addition, a power switch 401 that controls input of the first potential to the voltage adjustment unit 403 may be provided in the power supply circuit 400.

  In one embodiment of the present invention, a transistor with high withstand voltage is used as the power switch 401 and the power switch 402. For example, the transistor described in the above embodiment can be used as the transistor.

  By using the oxide semiconductor film having the above crystal structure as the power switch 401 and the power switch 402, a high output current can flow and the withstand voltage can be increased.

  By using the field effect transistor using the semiconductor material for the active layer for the power switch 401 or the power switch 402, the power switch 401 or the power switch is more effective than the field effect transistor using silicon carbide or gallium nitride for the active layer. The switching of 402 can be performed at high speed, so that power loss caused by switching can be reduced.

  When a voltage is input from the power source 416 via the power switch 401 and the power switch 402, the voltage adjustment unit 403 has a function of adjusting the voltage. Specifically, the voltage adjustment in the voltage adjustment unit 403 is any one or more of converting an AC voltage into a DC voltage, changing a voltage level, and smoothing a voltage level. including.

  The voltage adjusted by the voltage adjustment unit 403 is supplied to the load 417 and the control circuit 413.

  In addition, the power supply circuit 400 illustrated in FIG. 17 includes the power storage device 404, the auxiliary power supply 405, the voltage generation circuit 406, the transistors 407 to 410, the capacitor 414, and the capacitor 415.

  The power storage device 404 has a function of temporarily storing the power supplied from the voltage adjustment unit 403. Specifically, the power storage device 404 includes a power storage unit such as a capacitor or a secondary battery that can store electric power using the voltage supplied from the voltage adjustment unit 403.

  The auxiliary power source 405 has a function of supplementing power required for operation of the control circuit 413 when power that can be output from the power storage device 404 is insufficient. As the auxiliary power source 405, a primary battery or the like can be used.

  The voltage generation circuit 406 has a function of generating a voltage for controlling switching of the power switch 401 and the power switch 402 by using a voltage output from the power storage device 404 or the auxiliary power supply 405. Specifically, the voltage generation circuit 406 has a function of generating a voltage for turning on the power switch 401 and the power switch 402, and a function of generating a voltage for turning off the power switch 401 and the power switch 402. .

  The wireless signal input circuit 411 has a function of controlling the power switch 401 and the power switch 402 in accordance with switching of the transistors 407 to 410.

  Specifically, the wireless signal input circuit 411 includes an input unit that converts a command superimposed on a wireless signal for controlling the operation state of the power switch 401 and the power switch 402, which is supplied from the outside, into an electrical signal, and the electrical signal. And a signal processing unit that generates a signal for controlling switching of the transistors 407 to 410 according to the instruction.

  The transistors 407 to 410 perform switching according to the signal generated in the wireless signal input circuit 411. Specifically, when the transistor 408 and the transistor 410 are on, a voltage for turning on the power switch 401 and the power switch 402 generated by the voltage generation circuit 406 is supplied to the power switch 401 and the power switch 402. . Further, when the transistor 408 and the transistor 410 are off, the state where the power switch 401 and the power switch 402 are supplied with the voltage for turning on the power switch 401 and the power switch 402 is maintained. When the transistor 407 and the transistor 409 are on, the voltage generated by the voltage generation circuit 406 for turning off the power switch 401 and the power switch 402 is supplied to the power switch 401 and the power switch 402. Further, when the transistor 408 and the transistor 410 are off, the state in which the voltage for turning off the power switch 401 and the power switch 402 is applied to the power switch 401 and the power switch 402 is maintained.

  In one embodiment of the present invention, a transistor with extremely small off-state current is used as the transistors 407 to 410 in order to maintain the state where the voltage is applied to the power switch 401 and the power switch 402. With the above structure, the operation state of the power switch 401 and the power switch 402 can be maintained even when the voltage generation circuit 406 stops generating the voltage for determining the operation state of the power switch 401 and the power switch 402. Therefore, power consumption in the voltage generation circuit 406 can be reduced, and thus power consumption in the power supply circuit 400 can be reduced.

  Note that the transistor 407 to the transistor 410 may be provided with a back gate, and the threshold voltage of the transistor 407 to the transistor 410 may be controlled by applying a potential to the back gate.

  A transistor in which a wide gap semiconductor whose band gap is twice or more that of silicon is used for an active layer is preferably used for the transistors 407 to 410 because the off-state current is extremely small. For example, an oxide semiconductor can be used as the wide gap semiconductor.

  Note that an oxide semiconductor (purified OS) purified by reducing impurities such as moisture or hydrogen serving as an electron donor (donor) and reducing oxygen vacancies is an i-type (intrinsic semiconductor) or Close to i-type. Therefore, the off-state current of the transistor can be reduced by using an oxide semiconductor film which is highly purified by reducing the concentration of impurities such as moisture or hydrogen and reducing oxygen vacancies. Therefore, by using a transistor including a highly purified oxide semiconductor film for the transistors 407 to 410, power consumption in the voltage generation circuit 406 is reduced and an effect of reducing power consumption in the power supply circuit 400 is increased. be able to.

Specifically, it can be proved by various experiments that the off-state current of a transistor in which a highly purified oxide semiconductor is used for a channel formation region is small. For example, even in an element having a channel width of 1 × 106 μm and a channel length of 10 μm, the off-current is the measurement limit of the semiconductor parameter analyzer when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V. The following characteristics can be obtained, that is, 1 × 10 ⁻¹³ A or less. In this case, it can be seen that the off-current obtained by normalizing the off-current with the channel width of the transistor is 100 zA / μm or less. In addition, off-state current was measured using a circuit in which a capacitor and a transistor were connected and charge flowing into or out of the capacitor was controlled by the transistor. In this measurement, a highly purified oxide semiconductor film of the transistor was used for a channel formation region, and the off-state current of the transistor was measured from the change in the amount of charge per unit time of the capacitor. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has significantly lower off-state current than a transistor using crystalline silicon.

  Further, among oxide semiconductors, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, or the like is different from silicon carbide or gallium nitride in that a transistor with excellent electrical characteristics is manufactured by a sputtering method or a wet method. This has the advantage of being excellent in mass productivity. Unlike silicon carbide or gallium nitride, the oxide semiconductor In—Ga—Zn-based oxide can be formed even at room temperature; therefore, it can be formed over a glass substrate or over an integrated circuit using silicon. A transistor with excellent electrical characteristics can be manufactured. In addition, it is possible to cope with an increase in the size of the substrate.

  The capacitor 414 has a function of holding voltage applied to the power switch 401 when the transistor 407 and the transistor 408 are off. The capacitor 415 has a function of holding voltage applied to the power switch 402 when the transistor 409 and the transistor 410 are off. One of the pair of electrodes of the capacitor elements 414 and 415 is connected to the wireless signal input circuit 411. Note that the capacitor elements 414 and 415 are not necessarily provided as shown in FIG.

  When the power switch 401 and the power switch 402 are on, the voltage is supplied from the power source 416 to the voltage adjustment unit 403. Power is stored in the power storage device 404 by the voltage.

  When the power switch 401 and the power switch 402 are off, the supply of voltage from the power source 416 to the voltage adjustment unit 403 is stopped. Thus, power is not supplied to the power storage device 404; however, in one embodiment of the present invention, as described above, the control circuit 413 is operated using power stored in the power storage device 404 or the auxiliary power supply 405. Can be made. That is, in the power supply circuit 400 according to one embodiment of the present invention, supply of voltage to the voltage adjustment unit 403 can be stopped while the operation state of the power switch 401 and the power switch 402 is controlled by the control circuit 413. Then, by stopping the supply of voltage to the voltage adjustment unit 403, when the voltage is not supplied to the load 417, electric power is prevented from being consumed due to charge / discharge of the capacity of the voltage adjustment unit 403. Accordingly, power consumption of the power supply circuit 400 can be reduced.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIGS. 17 and 18, the source electrode (first electrode) is provided on the low potential side, and the drain electrode (second electrode) is provided on the high potential side. It is configured to be electrically connected. Further, the potential of the first gate electrode is controlled by the control circuit, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). That's fine.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, a structure of a buffer circuit including the transistor of one embodiment of the present invention will be described.

  The transistor of one embodiment of the present invention can be applied to a buffer circuit for supplying voltage to the gate of the power switch.

  FIG. 19A illustrates a circuit including the buffer circuit 701 of one embodiment of the present invention.

  A drive circuit 702 and a power switch 721 are electrically connected to the buffer circuit 701. The buffer circuit 701 is given a positive potential from the power source 715 and a negative potential from the power source 716.

  The drive circuit 702 is a circuit that outputs a signal for controlling the on / off operation of the power switch 721. A signal output from the drive circuit 702 is input to the gate of the power switch 721 via the buffer circuit 701.

  As the power switch 721, the transistor exemplified in the above embodiment can be used, or a power transistor using silicon, silicon carbide, gallium nitride, or the like as a semiconductor can be used. Hereinafter, a case where the power switch 721 is an n-channel transistor will be described. However, a p-channel transistor may be used.

  The buffer circuit 701 includes a transistor 711, a transistor 712, and an inverter 713.

  In the transistor 711, one of a source and a drain is electrically connected to the high potential output terminal of the power source 715, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor 712 and the gate of the power switch 721. The gate is electrically connected to the output terminal of the inverter 713. The other of the source and the drain of the transistor 712 is electrically connected to the low potential output terminal of the power supply 716. An output portion of the driver circuit 702 is electrically connected to an input terminal of the inverter 713 and a gate of the transistor 712.

  A high level potential or a low level potential is output from the driver circuit 702. Here, the high level potential is a potential at which at least the transistor 712 is turned on, and the low level potential is a potential at least at the transistor 712.

  When a high level potential is input from the driver circuit 702, a low level potential is input to the gate of the transistor 711 through the inverter 713, so that the transistor 711 is turned off. At the same time, a high-level potential is input to the gate of the transistor 712, so that the transistor 712 is turned on. Therefore, a negative potential is input from the power source 716 to the gate of the power switch 721, and the power switch 721 is turned off.

  On the other hand, when a low-level potential is input from the driver circuit 702, a high-level potential is input to the gate of the transistor 711 through the inverter 713, and the transistor 711 is turned on. At the same time, a low-level potential is input to the gate of the transistor 712, so that the transistor 712 is turned off. Therefore, a positive potential is input from the power source 715 to the gate of the power switch 721, and the power switch 721 is turned on.

  In this manner, the driving circuit 702 outputs a pulse signal having a high level potential or a low level potential, whereby the power switch 721 can be controlled to be turned on / off. As a control method for controlling the power switch 721, a control method such as a pulse width modulation (PWM) method or a pulse frequency modulation (PFM) method can be used.

  Here, the transistor illustrated in the above embodiment can be used as the transistor 711 and the transistor 712. Therefore, the power switch 721 can be driven at a high potential. Furthermore, since stable operation is possible at high temperatures, the operation of the power switch can be controlled stably even in a high temperature environment, and the power switch 721 can be arranged near the power switch 721 that generates more heat. In addition, a large output current can be caused to flow by the switching operation of the transistors 711 and 712, and the off-state current can be reduced. Accordingly, power consumption can be reduced, and a buffer capable of high-speed operation can be obtained.

  Note that although a power supply 716 that outputs a negative potential is provided in FIG. 19, a ground potential (or a reference potential) may be input to the other of the source and the drain of the transistor 712 without providing the power supply 716. .

  Alternatively, the inverter 713 may be electrically connected to the transistor 712 instead of the transistor 711. In that case, in the above operation, the buffer circuit 701 outputs a potential inverted from the above.

  Here, in place of the power switch 721, a bipolar power transistor, an insulated gate bipolar transistor (IGBT), a thyristor, a gate turn-off thyristor (GTO), a triac, or a MESFET (Metal Semiconductor Transistor Effect Transistor). A power device can also be used.

  At this time, the output signal of the driving circuit 702 is not limited to the above, and a signal suitable for controlling the driving of each element may be used.

  FIG. 19B shows a case where an IGBT 722 is provided instead of the power switch 721.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by the control circuit, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). That's fine.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, a transistor including an oxide semiconductor which is one embodiment of the present invention is used, the memory content can be retained even in a state where power is not supplied, and the number of writings is not limited (memory) An example of the apparatus will be described with reference to the drawings.

  FIG. 20 shows a circuit diagram of the semiconductor device.

  A semiconductor device illustrated in FIG. 20 includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. Note that as the transistor 3300, the transistor described in the above embodiment can be used.

  Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material is the oxide described in the above embodiment. It can be a semiconductor. A transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor has low off-state current.

  The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 3300 has low off-state current, stored data can be held for a long time by using the transistor 3300. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

  In FIG. 20, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to a gate electrode of the transistor 3300. The other of the gate electrode of the transistor 3200 and the source or drain electrode of the transistor 3300 is electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Connected.

  In the semiconductor device illustrated in FIG. 20, by using the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read as follows.

  Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, predetermined charge is supplied to the gate electrode of the transistor 3200 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, whereby the charge given to the gate electrode of the transistor 3200 is held (held).

  Since the off-state current of the transistor 3300 is extremely small, the charge of the gate electrode of the transistor 3200 is held for a long time.

  Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the amount of charge held in the gate electrode of the transistor 3200 is increased. The second wiring 3002 has different potentials. In general, when the transistor 3200 is an n-channel transistor, the apparent threshold Vth_H in the case where a high level charge is applied to the gate electrode of the transistor 3200 is the case where the low level charge is applied to the gate electrode of the transistor 3200 This is because it becomes lower than the apparent threshold value Vth_L. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for turning on the transistor 3200. Therefore, when the potential of the fifth wiring 3005 is set to a potential V0 between Vth_H and Vth_L, the charge given to the gate electrode of the transistor 3200 can be determined. For example, in the case where a high-level charge is applied in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 is V0 (> Vth_H). In the case where the low-level charge is supplied, the transistor 3200 remains in the “off state” even when the potential of the fifth wiring 3005 is V0 (<Vth_L). Therefore, the stored information can be read by determining the potential of the second wiring 3002.

  Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 3200 is turned off regardless of the state of the gate electrode, that is, a potential lower than Vth_H may be supplied to the fifth wiring 3005. Alternatively, a potential that turns on the transistor 3200 regardless of the state of the gate electrode, that is, a potential higher than Vth_L may be supplied to the fifth wiring 3005.

  In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

  In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 20, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 9)
In this embodiment, structural examples of the display panel of one embodiment of the present invention will be described.

[Configuration example]
FIG. 21A is a top view of a display panel of one embodiment of the present invention, and FIG. 21B can be used when a liquid crystal element is applied to a pixel of the display panel of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 21C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display panel of one embodiment of the present invention.

  The transistor provided in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

  An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 901, a first scan line driver circuit 902, a second scan line driver circuit 903, and a signal line driver circuit 904 are provided over a substrate 900 of the display device. In the pixel portion 901, a plurality of signal lines are extended from the signal line driver circuit 904, and a plurality of scan lines are extended from the first scan line driver circuit 902 and the second scan line driver circuit 903. Has been placed. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 900 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

  In FIG. 21A, the first scan line driver circuit 902, the second scan line driver circuit 903, and the signal line driver circuit 904 are formed over the same substrate 900 as the pixel portion 901. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 900, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where the driver circuit is provided over the same substrate 900, the number of connections between the wirings can be reduced, and reliability or yield can be improved.

[LCD panel]
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit which can be applied to a pixel of a VA liquid crystal display panel is shown.

  This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

  The gate wiring 912 of the transistor 916 and the gate wiring 913 of the transistor 917 are separated so that different gate signals can be given. On the other hand, the source or drain electrode layer 914 functioning as a data line is used in common for the transistor 916 and the transistor 917. As the transistor 916 and the transistor 917, the transistor described in the above embodiment can be used as appropriate. Thereby, a highly reliable liquid crystal display panel can be provided.

  The shapes of the first pixel electrode layer electrically connected to the transistor 916 and the second pixel electrode layer electrically connected to the transistor 917 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

  A gate electrode of the transistor 916 is connected to the gate wiring 912, and a gate electrode of the transistor 917 is connected to the gate wiring 913. By supplying different gate signals to the gate wiring 912 and the gate wiring 913, the operation timings of the transistor 916 and the transistor 917 are made different so that the alignment of the liquid crystal can be controlled.

  Further, a storage capacitor may be formed using the capacitor wiring 910, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

  The multi-domain structure includes a first liquid crystal element 918 and a second liquid crystal element 919 in one pixel. The first liquid crystal element 918 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 919 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

  Note that the pixel circuit illustrated in FIG. 21B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

[Organic EL panel]
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display panel using an organic EL element is shown.

  In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

  FIG. 21C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. In addition, digital time grayscale driving can be applied to the pixel circuit.

  An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

  The pixel 920 includes a switching transistor 921, a driving transistor 922, a light emitting element 924, and a capacitor 923. The switching transistor 921 has a gate electrode layer connected to the scanning line 926, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 925, and a second electrode (the source electrode layer and the drain electrode layer). Is connected to the gate electrode layer of the driving transistor 922. In the driving transistor 922, the gate electrode layer is connected to the power supply line 927 through the capacitor 923, the first electrode is connected to the power supply line 927, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 924. It is connected. The second electrode of the light emitting element 924 corresponds to the common electrode 928. The common electrode 928 is electrically connected to a common potential line formed over the same substrate.

  The transistor described in the above embodiment can be used as appropriate as the switching transistor 921 and the driving transistor 922. Thereby, an organic EL display panel with high reliability can be provided.

  The potential of the second electrode (common electrode 928) of the light emitting element 924 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential set to the power supply line 927. For example, GND, 0 V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 924, and the potential difference is applied to the light emitting element 924, thereby causing the light emitting element 924 to emit light. Note that the forward voltage of the light-emitting element 924 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

  Note that the capacitor 923 can be omitted by substituting the gate capacitance of the driving transistor 922. As for the gate capacitance of the driving transistor 922, a capacitance may be formed between the channel formation region and the gate electrode layer.

  Next, signals input to the driving transistor 922 are described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 922 to be sufficiently turned on or off is input to the driving transistor 922. Note that a voltage higher than the voltage of the power supply line 927 is applied to the gate electrode layer of the driving transistor 922 in order to operate the driving transistor 922 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 922 to the power supply line voltage is applied to the signal line 925.

  When analog grayscale driving is performed, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 922 to the forward voltage of the light emitting element 924 is applied to the gate electrode layer of the driving transistor 922. Note that a video signal is input so that the driving transistor 922 operates in a saturation region, and a current is supplied to the light-emitting element 924. In addition, the potential of the power supply line 927 is set higher than the gate potential of the driving transistor 922 in order to operate the driving transistor 922 in the saturation region. By making the video signal analog, current corresponding to the video signal can be supplied to the light emitting element 924 to perform analog gradation driving.

  Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 21, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 10)
A semiconductor device (including a power conversion circuit, a power supply circuit, a buffer circuit, and the like) according to one embodiment of the present invention is suitable for controlling supply of power to a device, and particularly suitable for a device that requires large power. Can be used. For example, it can be suitably used for a device including a driving unit whose driving is controlled by electric power such as a motor, or a device for controlling heating or cooling by electric power.

  As an electronic device that can use the semiconductor device according to one embodiment of the present invention, a display device, a personal computer, an image reproducing device including a recording medium (typically, a recording medium such as a DVD: Digital Versatile Disc, A device having a display capable of displaying the image). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a video camera, a digital still camera, a goggle type display (head Mount display), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automatic teller machines (ATMs), vending machines, microwave ovens, etc. Air conditioner such as equipment, electric rice cooker, electric washing machine, electric fan, dryer, air conditioner, elevator equipment such as elevator and escalator, electric refrigerator, electric freezer, electric refrigerator-freezer, electric sewing machine, electric tool, semiconductor test equipment, etc. Is mentioned. The semiconductor device according to one embodiment of the present invention may be used for a moving body that is propelled by an electric motor using electric power. Examples of the moving body include automobiles (motorcycles, ordinary automobiles of three or more wheels), motorbikes including electric assist bicycles, airplanes, ships, and railway vehicles. It can also be used to control the driving of industrial robots used in all fields such as food, home appliances, mobile bodies, steel, semiconductor equipment, civil engineering, architecture, and construction.

  Hereinafter, a specific example of the electronic device is illustrated in FIG.

  FIG. 22A illustrates a microwave oven 1400, which includes a housing 1401, a processing chamber 1402 for placing an object to be processed, a display portion 1403, an input device 1404 such as an operation panel, and the inside of the housing 1401. And an irradiation unit 1405 for supplying an electromagnetic wave generated from the high-frequency generator installed in the processing chamber 1402.

  The semiconductor device according to one embodiment of the present invention can be used for, for example, a power supply circuit that controls supply of electric power to a high-frequency generator.

  FIG. 22B illustrates a washing machine 1410, which includes a housing 1411, an opening / closing portion 1412 that opens and closes an entrance of a laundry tub provided in the housing 1411, an input device 1413 such as an operation panel, And a water supply port 1414.

  The semiconductor device according to one embodiment of the present invention can be used, for example, in a circuit that controls supply of electric power to a motor that controls rotation of a washing tub.

  FIG. 22C illustrates an example of an electric refrigerator-freezer. An electronic device illustrated in FIG. 22C includes a housing 1451, a refrigerator door 1452, and a freezer door 1453.

  An electronic device illustrated in FIG. 22C includes a semiconductor device that is one embodiment of the present invention inside a housing 1451. With the above structure, for example, supply of power supply voltage to the semiconductor device in the housing 1451 can be controlled in accordance with the temperature inside the housing 1451 or in accordance with opening and closing of the refrigerator door 1452 and the freezer door 1453. .

  FIG. 22D illustrates an example of an air conditioner. The electronic device illustrated in FIG. 22D includes an indoor unit 1460 and an outdoor unit 1464.

  The indoor unit 1460 includes a housing 1461 and an air outlet 1462.

  An electronic device illustrated in FIG. 22D includes a semiconductor device that is one embodiment of the present invention inside a housing 1461. With the above structure, for example, supply of power supply voltage to the semiconductor device in the housing 1461 can be controlled in accordance with a signal from a remote controller or in accordance with indoor temperature or humidity.

  The semiconductor device of one embodiment of the present invention can also be used for a circuit that controls supply of electric power to a motor that controls rotation of a fan included in the outdoor unit 1464.

  Note that FIG. 22D illustrates a separate type air conditioner including an indoor unit and an outdoor unit. However, the air conditioner includes the functions of the indoor unit and the outdoor unit in one housing. There may be.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 11)
In this embodiment, structural examples of electronic devices to which the semiconductor device of one embodiment of the present invention is applied will be described.

  FIG. 23 is an external view of an electronic device including the semiconductor device of one embodiment of the present invention.

  Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (a mobile phone or a mobile phone). Large-sized game machines such as portable game machines, portable information terminals, sound reproduction apparatuses, and pachinko machines.

  FIG. 23A illustrates a portable information terminal, which includes a main body 1001, a housing 1002, display portions 1003a and 1003b, and the like. The display portion 1003b is a touch panel, and screen operations and character input can be performed by touching a keyboard button 1004 displayed on the display portion 1003b. Of course, the display unit 1003a may be configured as a touch panel. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in the above embodiment as a switching element and applying it to the display portions 1003a and 1003b, a highly reliable portable information terminal can be obtained.

  A portable information terminal illustrated in FIG. 23A has a function of displaying various information (a still image, a moving image, a text image, and the like), a function of displaying a calendar, a date, a time, or the like on a display portion, and a display on the display portion. It is possible to have a function of operating or editing the processed information, a function of controlling processing by various software (programs), and the like. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

  In addition, the portable information terminal illustrated in FIG. 23A may be configured to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

  FIG. 23B shows a portable music player. A main body 1021 is provided with a display portion 1023, a fixing portion 1022 to be attached to the ear, a speaker, operation buttons 1024, an external memory slot 1025, and the like. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in the above embodiment as a switching element and applying it to the display portion 1023, a portable music player with higher reliability can be obtained.

  Furthermore, if the portable music player shown in FIG. 23B has an antenna, a microphone function, and a wireless function and is linked to a mobile phone, a wireless hands-free conversation is possible while driving a passenger car or the like.

  FIG. 23C illustrates a mobile phone, which includes two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone 1034, a pointing device 1036, a camera lens 1037, an external connection terminal 1038, and the like. The housing 1030 is provided with a solar battery cell 1040 for charging the mobile phone, an external memory slot 1041, and the like. The antenna is incorporated in the housing 1031. By applying the transistor described in the above embodiment to the display panel 1032, a highly reliable mobile phone can be obtained.

  The display panel 1032 includes a touch panel. A plurality of operation keys 1035 displayed as images is illustrated by dashed lines in FIG. Note that a booster circuit for boosting the voltage output from the solar battery cell 1040 to a voltage required for each circuit is also mounted.

  For example, the transistor described in the above embodiment can also be used as a power transistor used in a power supply circuit such as a booster circuit.

  In the display panel 1032, the display direction can be appropriately changed depending on a usage pattern. In addition, since the camera lens 1037 is provided on the same surface as the display panel 1032, a videophone can be used. The speaker 1033 and the microphone 1034 can be used for videophone calls, recording and playing sound, and the like as well as voice calls. Further, the housing 1030 and the housing 1031 can be slid to be in an overlapped state from the deployed state as illustrated in FIG. 23C, and thus can be reduced in size to be portable.

  The external connection terminal 1038 can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with a personal computer are possible. In addition, a recording medium can be inserted into the external memory slot 1041 so that a larger amount of data can be stored and moved.

  In addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

  FIG. 23D illustrates an example of a television set. In the television device 1050, a display portion 1053 is incorporated in a housing 1051. An image can be displayed on the display portion 1053. In addition, a CPU is incorporated in a stand 1055 that supports the housing 1051. By applying the transistor described in the above embodiment to the display portion 1053 and the CPU, the television set 1050 with high reliability can be provided.

  The television device 1050 can be operated with an operation switch provided in the housing 1051 or a separate remote controller. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

  Note that the television set 1050 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

  In addition, the television device 1050 includes an external connection terminal 1054, a storage medium playback / recording unit 1052, and an external memory slot. The external connection terminal 1054 can be connected to various types of cables such as a USB cable, and data communication with a personal computer or the like is possible. The storage medium playback / recording unit 1052 can insert a disk-shaped recording medium, read data stored in the recording medium, and write data to the recording medium. In addition, an image, a video, or the like stored in the external memory 1056 inserted into the external memory slot can be displayed on the display portion 1053.

  Further, in the case where the off-leakage current of the transistor described in the above embodiment is extremely small, by applying the transistor to the external memory 1056 or the CPU, the highly reliable television device 1050 whose power consumption is sufficiently reduced is described. can do.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

100 transistor 101 substrate 102 semiconductor layer 103a electrode 103b electrode 104 insulating layer 105 gate electrode 105a gate electrode 105b gate electrode 106 insulating layer 107 insulating layer 108 insulating layer 109 insulating layer 111a wiring 111b wiring 111c wiring 121 oxide layer 122 oxide layer 200 Transistor 210 Transistor 220 Transistor 400 Power supply circuit 401 Power switch 402 Power switch 403 Voltage adjustment unit 404 Power storage device 405 Auxiliary power supply 406 Voltage generation circuit 407 Transistor 408 Transistor 409 Transistor 410 Transistor 411 Wireless signal input circuit 413 Control circuit 414 Capacitance element 415 Capacitance element 416 Power supply 417 Load 501 DCDC converter 502 Capacitance element 503 Transistor 504 Control circuit 05 diode 506 coil 507 capacitive element 508 load 511 DCDC converter 512 capacitive element 513 transistor 514 control circuit 515 transformer 516 diode 517 capacitive element 518 load 601 inverter 602 transistor 603 transistor 604 transistor 605 transistor 606 control circuit 701 buffer circuit 702 drive circuit 711 Transistor 712 Transistor 713 Inverter 715 Power supply 716 Power supply 721 Power switch 722 IGBT
900 Substrate 901 Pixel portion 902 Scan line driver circuit 903 Scan line driver circuit 904 Signal line driver circuit 910 Capacitive wiring 912 Gate wiring 913 Gate wiring 914 Drain electrode layer 916 Transistor 917 Transistor 918 Liquid crystal element 919 Liquid crystal element 920 Pixel 921 Switching transistor 922 Driving transistor 923 Capacitor element 924 Light emitting element 925 Signal line 926 Scan line 927 Power line 928 Common electrode 1001 Main body 1002 Case 1003a Display unit 1003b Display unit 1004 Keyboard button 1021 Main unit 1022 Fixed unit 1023 Display unit 1024 Operation button 1025 External memory slot 1030 Case 1031 Case 1032 Display panel 1033 Speaker 1034 Microphone 1035 Operation key 1036 Pointing Vise 1037 Camera lens 1038 External connection terminal 1040 Solar cell 1041 External memory slot 1050 Television device 1051 Case 1052 Storage medium playback recording unit 1053 Display unit 1054 External connection terminal 1055 Stand 1056 External memory 1400 Microwave oven 1401 Case 1402 Processing Room 1403 Display unit 1404 Input device 1405 Irradiation unit 1410 Washing machine 1411 Case 1412 Opening / closing unit 1413 Input device 1414 Water supply port 1451 Case 1452 Refrigeration room door 1453 Freezer compartment door 1460 Indoor unit 1461 Case 1462 Blower port 1464 Outdoor unit 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitance element

Claims (5)

An oxide semiconductor layer;
A first gate electrode and a second gate electrode positioned above and below the oxide semiconductor layer;
A first gate insulating layer between the oxide semiconductor layer and the first gate electrode;
A second gate insulating layer between the oxide semiconductor layer and the second gate electrode;
A transistor which have a, a source electrode and a drain electrode in contact with the oxide semiconductor layer,
The oxide semiconductor layer includes a first region that overlaps the source electrode, a second region that overlaps the drain electrode, and the source electrode and the second region between the first region and the second region. A third region that does not overlap the drain electrode;
The third region includes a fourth region overlapping with the second gate electrode, a fifth region between the first region and the fourth region, the second region, and the second region. A sixth region between the four regions, and
All of the third region overlaps the first gate electrode;
The channel length direction of the length of the first gate electrode, rather long than the channel length direction of the length of the second gate electrode,
The first gate electrode is located above the second gate electrode through the second gate insulating layer, the oxide semiconductor layer, and the first gate insulating layer,
The first gate electrode has a function of controlling a switching operation of the transistor;
The transistor, wherein the second gate electrode has a function of controlling a threshold voltage of the transistor . An oxide semiconductor layer;
A first gate electrode and a second gate electrode positioned above and below the oxide semiconductor layer;
A first gate insulating layer between the oxide semiconductor layer and the first gate electrode;
A second gate insulating layer between the oxide semiconductor layer and the second gate electrode;
A transistor having a source electrode and a drain electrode in contact with the oxide semiconductor layer,
The oxide semiconductor layer includes a first region that overlaps the source electrode, a second region that overlaps the drain electrode, and the source electrode and the second region between the first region and the second region. A third region that does not overlap the drain electrode;
The third region includes a fourth region overlapping with the second gate electrode, a fifth region between the first region and the fourth region, the second region, and the second region. A sixth region between the four regions, and
All of the third region overlaps the first gate electrode;
The length of the first gate electrode in the channel length direction is longer than the length of the second gate electrode in the channel length direction,
The first gate electrode is located above the second gate electrode through the second gate insulating layer, the oxide semiconductor layer, and the first gate insulating layer,
The material of the first gate insulating layer is the same as the material of the second gate insulating layer,
The transistor is characterized in that the thickness of the first gate insulating layer is smaller than the thickness of the second gate insulating layer. In claim 1 or claim 2 ,
The length in the channel length direction of the sixth region, the transistor according to claim longer than the length in the channel length direction of the fifth region. In any one of Claim 1 thru | or 3 ,
One of the source electrode and the drain electrode has an annular top surface shape having an opening overlapping the oxide semiconductor layer,
The other of the source electrode and the drain electrode, a transistor, characterized in that provided inside the opening. In any one of claims 1 to 4,
A first oxide layer between the oxide semiconductor layer and the first gate insulating layer;
A second oxide layer between the oxide semiconductor layer and the second gate insulating layer;
The first oxide layer and said second oxide layer, a transistor and having the oxide semiconductor layer of one or more of the same metal element as the metal element included in the.