JP6245087B2 - Reverse blocking IGBT and manufacturing method thereof - Google Patents

Description

  The present invention relates to a reverse blocking IGBT having a forward reverse high breakdown voltage and a high avalanche resistance and a method for manufacturing the reverse blocking IGBT.

  The power device is mounted on the power conversion device as a device having the main function. As such a power device, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET) and the like are known. Among these, IGBTs, which are bipolar devices, are frequently used in high-voltage power conversion circuits because they can easily obtain a low on-voltage even in a high breakdown voltage device due to conductivity modulation and have a small conduction loss.

  Among these power conversion circuits, an AC-AC direct converter has recently attracted attention. A matrix converter that is a typical AC-AC direct converter requires a plurality of bidirectional switching devices capable of current control in forward and reverse directions. When a normal IGBT is used as the bidirectional switching device, a reverse voltage blocking diode connected in series with the IGBT is required. However, as shown in the equivalent circuit diagram of the bidirectional switching device using two reverse blocking IGBTs in FIG. 25, there is an advantage that the series connection diode can be omitted by using the reverse blocking IGBT (Reverse Blocking IGBT). is there. Furthermore, there are also merits that lead to a reduction in the size, weight, efficiency and cost of the mounted circuit.

  The structure of such a conventional reverse blocking IGBT will be described below with reference to FIGS. FIG. 14 is an enlarged cross-sectional view inside the broken line frame of FIG.

The semiconductor chip 200 that is a reverse blocking IGBT uses an n-type silicon semiconductor substrate as the drift layer 1. One main surface is a front surface 300 and the other main surface is a back surface 400. On the surface 300 side of the drift layer 1, an active region 21 through which a main current flows, a termination region 22 surrounding this region, and a p-type isolation region 7 are provided. The p-type isolation region 7 is a region that penetrates the drift layer 1 from the surface 300 side along the cut surface of the semiconductor chip 200 and reaches the collector layer 13 on the back surface 400 side. The surface of the active region 21 has an emitter electrode 10, a gate runner 8a, a gate pad electrode (not shown), and the like, and the termination region 22 is provided with a field limiting ring (FLR) 25 that relaxes a high electric field, a field plate 11, and the like. It is done. A p-type collector layer 13 is provided on the entire surface on the back surface 400 side, and a collector electrode 14 is deposited on the main surface so as to be in contact with the collector layer 13. On the surface 300 side of the active region 21, a p-type base region 3, an n ⁺ -type emitter region 4 provided on the surface layer of the p-type base region 3, the emitter region 4, the surface of the drift layer 1, A MOS structure having a polysilicon gate electrode 8b deposited via a gate insulating film 9 on the surface of the p-type base region 3 sandwiched between them is provided. Preferably, the surface layer of the p-type base region 3 has a p ⁺ -type contact region 5 adjacent to the n ⁺ -type emitter region 4 in the creeping direction. The emitter electrode 10 is in contact so as to short-circuit the surfaces of the n ⁺ -type emitter region 4 and the p ⁺ -type contact region 5.

  The polysilicon gate electrode 8b and the polysilicon gate runner 8a are connected outside the figure and are connected to a gate pad electrode (not shown) for inputting / outputting a gate signal to / from the outside. The polysilicon gate runner 8a is disposed between the active region 21 and the termination region 22, and is a region for transmitting a gate electric signal between the polysilicon gate electrode 8b and the gate pad electrode. A p-type region 6 (not shown) is provided in each of the substrate surface layers under the polysilicon gate runner 8a and the gate pad electrode.

  FIG. 18 shows a planar pattern of the p-type region 6 directly under the gate runner and directly under the gate pad electrode in Patent Document 1. Here, Patent Document 1 is an example of a reverse conducting IGBT, but the p-type region 6 immediately below the gate runner and the gate pad electrode has the same planar arrangement in the above-described reverse blocking IGBT. These p-type regions 6 are necessary for the high avalanche breakdown resistance of the MOSFET and the wide reverse-bias safe operating area (RBSOA) of the conventional IGBT.

The reverse conducting IGBT is a device in which an IGBT and a FWD (free wheeling diode) are integrated in the same semiconductor substrate. In this case, the p-type region 6 is an anode region of the diode. In this reverse conducting IGBT, the p-type low resistance (high impurity concentration) p-type region 6 arranged so as to surround the outer periphery of the active region 21 increases the reverse recovery loss of the diode formed on the same semiconductor substrate. There is a drawback. Further, with respect to the p-type region 6 portion immediately below the gate pad electrode, as shown in the plan view of FIG. 19, the p-type region 6 portion immediately below the gate runner is ion-implanted and thermally diffused into a slit-shaped or stripe-shaped selective region. The structure is connected to FIG. 20 is a sectional view taken along line A1-A2 of FIG. FIG. 20 additionally shows a gate pad electrode 50 and an anode electrode 60 which are formed on the substrate surface in the p-type region 6 and are omitted in FIG. The impurity concentration of the striped p-type region 6 shown in FIG. 19 is formed by expanding the region by thermal diffusion from the selectively provided ion implantation region. Therefore, ions are implanted into the entire region shown in FIG. The dose amount is smaller and the impurity concentration is lower than that of the p-type region 6 formed in this manner. The reason for this is that if the dose and impurity concentration of the striped p-type region 6 in FIG. 19 are lower than the dose and impurity concentration of the conventional entire p-type region 6 portion of FIG. This is because the carrier injection from the anode formed of the striped p-type region 6 on the outer periphery of the diode is reduced, and the reverse recovery current of the diode is reduced, which is preferable. Reference numeral 51 denotes a drift layer, reference numeral 53 denotes an n-type buffer layer, reference numeral 54 denotes a p ⁺ collector layer, reference numeral 55 denotes an n ⁺ cathode region, and reference numeral 56 denotes an insulating film.

Patent Document 2 relating to a MOSFET or IGBT discloses a structure that suppresses the protrusion of the high impurity concentration p-type region 5a immediately below the gate pad electrode 80 of the MOSFET into the active region 21. As shown in FIG. 21 and FIG. 22, which is a cross-sectional view taken along line B 1 -B 2, in Patent Document 2, the p-type region 53 and the p-type region 5 a having a high impurity concentration are replaced with the p-type base region 43 in the active region 21. This shows a structure formed simultaneously with the p-type contact region 5b provided on the surface. In that case, in order to form the p-type region 53 immediately below the gate pad electrode 80 and the p-type region 5a having a high impurity concentration by self-alignment, the polysilicon electrode 8a is formed like the polysilicon gate electrode 8b in the active region. It needs to be formed so as to be divided without covering the entire region directly under the gate pad electrode. 22, reference numeral 41 denotes an n-type drift layer, reference numeral 42 denotes an n ⁺ source region, reference numeral 43 denotes a p-type base region, reference numeral 8b denotes a polysilicon gate electrode, reference numeral 9 denotes a gate insulating film, reference numeral 14 denotes a drain electrode, reference numeral 16 Is a drain region, numeral 17 is an interlayer insulating film, and numeral 25 is a field limiting ring.

  In the low breakdown voltage MOSFET (not shown) described in Patent Document 3, the low resistance (high impurity concentration) p-type region 5a is not formed in order to simplify the manufacturing process. This low breakdown voltage MOSFET will be described with reference to FIG. By adopting a structure in which the p-type base region 43 and the polysilicon gate electrode 8b deposited on the region 43 through the gate insulating film 9 are formed in a comb shape, a gate signal extraction portion (gate pad electrode) Therefore, the high impurity concentration p-type region 5a is not formed. Here, in Patent Document 3, the p-type base region 43 separated as described above is formed (at the same depth) at the same time so that it can serve as both the FLR 25 and the p-type region 6 immediately below the gate runner 8a.

JP 2010-186805 A JP 2008-85188 A Japanese Patent No. 3391715

  In the reverse blocking IGBT 200 shown in FIG. 13, the IGBT unit cell in the active region 21 is formed with a planar gate structure. An enlarged view of the vicinity of the gate runner 8a within the broken line frame is shown in FIG. The p-well 6 below the gate runner 8a has the same impurity profile as the field limiting ring 25 (hereinafter abbreviated as FLR 25) in the termination region 22. That is, they are formed simultaneously. Although not shown in FIG. 13, the p-well 6 immediately below the gate pad electrode also has the same impurity profile as described above.

However, the reverse breakdown voltage (reverse breakdown voltage) of the reverse blocking IGBT is not determined simply by the breakdown voltage of the reverse-biased collector junction 13a. As shown in FIG. 23, an open base of a pnp transistor having the p-type base region 3 or p-type region 6 on the surface side as an emitter, the n ⁻ -type drift layer 1 as a base, and the p-type collector layer 13 as a collector. Influenced by the withstand pressure. That is, the reverse breakdown voltage of the reverse blocking IGBT is smaller than the breakdown breakdown voltage of the collector junction 13a due to the influence of the amplification action of the pnp transistor. For example, the reverse blocking IGBT shown in FIG. 13 has the p-type region 6 immediately below each of the gate runner 8a and the gate pad even when the electric field relaxation structure in the termination structure 22 is appropriately designed. The portion is more easily reverse breakdown than the portion having the p-type base in the active region 21, and determines the reverse breakdown voltage. The reason is the dose of the p-well 6 immediately below the gate runner 8a is than the dose of the p-type base region 3 in the active region 21, 10 times or more greater, since further the junction is deep, correspondingly, n ^- -type drift layer This is because the thickness of 1 is reduced and the amplification factor of the parasitic pnp transistor is increased as described above.

  In a general reverse blocking IGBT, the total area of the gate runner 8a and the p-well 6 immediately below the gate pad is narrower than the area of the active region 21, so that when the energy at the time of reverse voltage application is concentrated in the narrow region, the avalanche resistance There is a problem that the reverse double resistance is reduced.

  The present invention has been made in view of the above, and an object of the present invention is to provide a reverse blocking IGBT capable of obtaining a higher reverse breakdown voltage and higher avalanche resistance and reverse recovery resistance than a conventional reverse blocking IGBT and a manufacturing method thereof. .

  In order to achieve the above object, the present invention provides a second conductivity type base region and a first layer selectively provided on the surface layer of the second conductivity type base region on one surface side of the first conductivity type semiconductor substrate serving as a drift layer. A conductive type emitter region, an active region mainly comprising a MOS gate structure comprising a gate electrode in contact with a surface of the second conductive type base region sandwiched between the emitter region and the surface of the drift layer via a gate oxide film; A termination region having an electric field relaxation structure including a field limiting ring surrounding the outer periphery of the active region, a second conductivity type collector layer on the other surface side, and the drift layer from the one surface side on the outer periphery of the termination region A second conductivity type isolation region that is in contact with the second conductivity type collector layer, and a second conductivity type well between the active region and the termination region on the one surface side. A reverse blocking IGBT in which the depth and the amount of impurities from the surface of the one surface are equal to or greater than the depth and the amount of impurities of the second conductivity type base region and less than the depth and the amount of impurities of the field limiting ring; To do.

  Further, the present invention provides a second conductivity type base region on one surface side of the first conductivity type semiconductor substrate serving as a drift layer, a trench reaching the drift region through the second conductivity type base region, and a gate oxide film in the trench An active region having a MOS gate structure as a main region selectively formed on the surface of the base region and having a first conductivity type emitter region in contact with the trench gate oxide film, and the active region A termination region having an electric field relaxation structure including a field limiting ring that surrounds the outer periphery of the second region, a second conductivity type collector layer on the other surface side, and a second outer periphery of the termination region that penetrates the drift layer from the one surface side. A second conductivity type isolation region in contact with the conductivity type collector layer; and a second conductivity type well between the active region and the termination region on the one surface side. The reverse blocking IGBT in which the depth and the amount of impurities from the surface on the one surface side are equal to or greater than the depth and the amount of impurities of the second conductivity type base region and less than the depth and the amount of impurities of the field limiting ring And

  The second conductivity type well is preferably 1/10 or less of the impurity amount of the field limiting ring.

  It is also preferable to have a gate runner on the surface of the second conductivity type well via an oxide film.

  The gate runner is preferably a polysilicon layer.

  More preferably, the polysilicon layer is a doped polysilicon layer.

  Manufacturing of reverse blocking IGBT in which a plurality of ion implantation regions are evenly arranged in the second conductivity type well, and the plurality of ion implantation regions are overlapped with each other by thermal diffusion after ion implantation. A method is desirable.

  It is more preferable to use a reverse blocking IGBT manufacturing method in which the ion implantation is performed simultaneously with ion implantation for forming the field limiting ring.

  The gist of the present invention is that the dose amount of the p-well just below the gate runner and the gate pad connecting the active region and the termination region is 1/10 or less of the dose amount of the FRL in the termination region, and the IGBT unit cell in the active region In other words, the dose is equal to or greater than the dose of the p-type base region, and the depth thereof is FLR or less and the reverse blocking IGBT is greater than the p-type base region.

  According to the present invention, it is possible to provide a reverse blocking IGBT and a method for manufacturing the same that can provide a higher reverse breakdown voltage and higher avalanche resistance and reverse recovery resistance than conventional reverse blocking IGBTs.

It is sectional drawing of the periphery part of the reverse blocking IGBT concerning Example 1 of this invention. It is an expanded sectional view of the gate runner part vicinity shown with the broken-line frame of FIG. FIG. 2 is a relationship diagram between a reverse breakdown voltage and a drift layer thickness using a dose amount of a p-well immediately below the gate runner portion of the reverse blocking IGBT of FIG. 1 as a parameter. FIG. 3 is a plan view showing a mask layout when forming a p-well region of the reverse blocking IGBT according to the first embodiment shown in FIG. 1; FIG. 5 is a cross-sectional view taken along line C1-C2 of FIG. 4 after the thermal diffusion of the reverse blocking IGBT according to the first embodiment illustrated in FIG. It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 2 of this invention (the 1). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 2 of this invention (the 2). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 2 of this invention (the 3). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 3 of this invention (the 1). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 3 of this invention (the 2). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 3 of this invention (the 3). It is sectional drawing which shows the manufacturing process of the p well area | region 18 of reverse blocking IGBT concerning Example 3 of this invention (the 4). It is sectional drawing of the periphery part of the conventional reverse blocking IGBT. It is an expanded sectional view of the gate runner part vicinity shown with the broken-line frame of FIG. It is sectional drawing of the semiconductor substrate shown in order of a manufacturing process in order to demonstrate the manufacturing method of the conventional reverse block IGBT (the 1). It is sectional drawing of the semiconductor substrate shown in order of a manufacturing process in order to demonstrate the manufacturing method of the conventional reverse block IGBT (the 2). It is sectional drawing of the semiconductor substrate shown in order of a manufacturing process in order to demonstrate the manufacturing method of the conventional reverse block IGBT (the 3). 10 is a plan view showing a pattern of a p-type region immediately below a gate runner and a p-type region immediately below a gate pad of a reverse conducting IGBT described in Patent Document 1. FIG. 10 is a plan view showing an improved pattern of a p-type region directly under a gate runner and a p-type region directly under a gate pad of a reverse conducting IGBT described in Patent Document 1. FIG. It is A1-A2 sectional view taken on the line of FIG. 10 is a plan view showing a planar pattern of an emitter electrode and a gate pad electrode of a reverse blocking IGBT described in Patent Document 2. FIG. It is B1-B2 sectional view taken on the line of FIG. It is explanatory drawing of the reverse pressure | voltage resistance of reverse blocking IGBT. It is an expanded sectional view of the gate runner part vicinity of reverse blocking IGBT of a trench gate structure. It is an equivalent circuit diagram of a bidirectional switching device using two reverse blocking IGBTs.

  Hereinafter, embodiments of the reverse blocking IGBT of the present invention and the manufacturing method thereof will be described in detail with reference to the drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and overlapping descriptions are omitted as much as possible. In addition, the accompanying drawings used in the following description are not drawn with an accurate scale and dimensional ratio for easy understanding and understanding. Moreover, this invention is not limited to description of embodiment described below, unless the summary is exceeded.

  A semiconductor chip 100 made of a reverse blocking IGBT according to the present invention has a emitter-side surface 30 and a collector-side back surface 40 with a drift layer 1 made of an n-type silicon semiconductor substrate as the center, as shown in the cross-sectional view of the main part of FIG. Have The surface 30 side includes an active region 21 through which a main current flows, a termination region 22 surrounding this region, and a p-type isolation region 7. The surface of the active region 21 is covered with an emitter electrode 10 and a gate pad electrode (not shown), and the termination region 22 is provided with an FLR 25 that relaxes a high electric field, a field plate 11 and the like. The p-type isolation region 7 is a region that penetrates the drift layer 1 and reaches the collector layer 13 on the back surface 40 side along the cut surface of the semiconductor chip 100 from the front surface 30 side. A p-type collector layer 13 is provided on the entire back surface 40 side, and a collector electrode 14 is in contact therewith.

A p-well 18 (p-type region), which is a feature of the present invention, is provided between the FLR 25 and the active region 21. The reverse blocking IGBT of the present invention is formed so that the diffusion profile of the p-well 18 has the characteristics described later. Further, on the surface 30 side of the active region 21, a p-type base region 3, an n ⁺ -type emitter region 4 provided in the surface layer of the region 3 and the surfaces of the emitter region 4 and the drift layer 1 are selectively provided. A MOS structure comprising a polysilicon gate electrode 8b deposited via a gate insulating film 9 is provided on the surface of the p-type base region 3 sandwiched between the two. It is preferable that the surface of the p-type base region 3 has a p ⁺ -type contact region 5 adjacent to the n ⁺ -type emitter region 4 in the creeping direction. An emitter electrode 10 is in common contact so as to short-circuit the surfaces of the n ⁺ -type emitter region 4 and the p ⁺ -type contact region 5, and further covers the polysilicon gate electrode 8 b via an interlayer insulating film 17. The p-type base region 3 at the outermost periphery of the active region 21 partially overlaps with the p-well 18. A gate runner 8a serving as a gate electrode wiring via an oxide film and a gate electrode 8b connected to the gate runner 8a outside the figure are simultaneously formed on the p-well 18 by polysilicon. The p-well 18 has a depth equal to or greater than that of the p-type base region 3, is shallower than the FLR 25, and has an impurity amount reduced from that of the conventional p-well (p-type region 6). This is a feature of reverse blocking IGBT.

  The dose amount of the p well 18 is equal to or more than that of the p-type base region 3 and is 1/10 or less of the dose amount of the FLR 25. Thus, in order to make the dose amount of the FLR 25 1/10 or less, the ion implantation region for forming the P well 18 is 1/10 or less of the ion implantation region of the conventional p well (p-type region 6). It is assumed that the area is selected so as to have an area of. However, the above-mentioned 1/10 or less so that the p-well region 18 which is made continuous by thermal diffusion by heat-treating the selective ion implantation region has the same planar area as the conventional p-well (p-type region 6). It is a feature of the manufacturing method of the reverse blocking IGBT of the present invention that the ion-implanted regions having the same area are uniformly distributed. Incidentally, evenly distributing and arranging the ion implantation regions is described in Patent Document 1 described above, but only the P-type region under the gate pad electrode. In the reverse blocking IGBT of the present invention, in order not to reduce the reverse breakdown voltage, unlike the above-mentioned Patent Document 1, ion implantation regions are distributed evenly in both the P-type region under the gate pad electrode and under the gate runner. The dose amount in this region is made smaller than that in the conventional P-type region, the impurity concentration is reduced, and the depth is made shallower.

  FIG. 2 is an enlarged cross-sectional view of the vicinity of the gate runner in the broken line frame of the reverse blocking IGBT according to the present invention (FIG. 1). Although the unit cell in the active region 21 in FIG. 2 is shown as a planar gate structure, it may be a trench gate structure as shown in FIG.

The reverse blocking IGBT of the present invention (FIG. 1) and FIG. 2 which is an enlarged cross-sectional view in the vicinity of the gate runner, the room temperature reverse breakdown voltage and the thickness of the drift layer using the dose amount of the p well 18 (p type region 6) as parameters. The result of examining the relationship is shown in FIG. The impurity concentration n of the drift layer 1 is n = 1.22 × 10 ¹⁴ cm ⁻³ . The carrier lifetime (τ) is adjusted spatially and uniformly by electron beam irradiation, the electron lifetime is 0.35 μs, and the hole lifetime is 1/3 thereof. The width of the p well 18 is 48 μm, and the width of the half cell connected to the p well 18 is 12.5 μm. The dose amount of the p-type base region 3 is 2.5 × 10 ¹³ cm ⁻² , and the dose amount of the FLR 25 (p-type region 6 in FIG. 14) is 2.5 × 10 ¹⁵ cm ⁻² .

3 shows a case where the dose of the p-well 18 is equivalent to that of the p-type base region 3 (that is, 2.5 × 10 ¹³ cm ⁻² ), and a dose of FLR 25 (p-type region 6 in FIG. 14). The relationship diagram of room temperature reverse withstand voltage and drift layer 1 thickness in the case where four parameters of 1% (2.5 × 10 ¹⁵ cm ⁻² ), 10%, and 100% are used is shown. From FIG. 3, when the dose amount of the p-well 18 is 100% which is the same as the dose amount of the FLR 25 (in the case of the p-type region 6 in FIG. 14), the reverse breakdown voltage of the gate runner portion and the gate pad portion is It can be seen that the reverse breakdown voltage (reverse breakdown voltage when the dose of the p-well 18 is equivalent to that of the p-type base region 3) is about 50V lower. In that case, the reverse withstand voltage is determined by the gate pad part or the gate runner part having a low withstand voltage. Generally, the area of these high electric field strength portions (gate pad portion and gate runner portion) is much smaller than the area of the active region. For this reason, electric field concentration due to a high electric field is likely to occur locally in a narrow area. As a result, the reverse breakdown voltage of the element is lowered, and reverse avalanche energy and reverse recovery energy in the diode mode of the reverse blocking IGBT are localized. (Concentrate) weakens the overall tolerance.

  In the p-well 18 of the reverse blocking IGBT of the present invention, by reducing the area of the ion implantation region for forming the p-well 18, the dose amount (total impurity amount) is reduced to the conventional p-well (p-type region 6). Therefore, as described with reference to FIG. 23, the amplification factor of the bipolar transistor that determines the reverse breakdown voltage is reduced, and as a result, the reverse breakdown voltage is improved. For example, if the dose amount (total impurity amount) of the p-well 18 is set to 1/10 or less of the FLR 25, the reverse of the p-well junction immediately below the gate runner / gate pad and the p-type base region junction of the active region from FIG. The difference in breakdown voltage can be suppressed to about 40 V or less. As a result, even if a reverse breakdown occurs immediately under the gate runner or gate pad, the breakdown voltage of those portions is improved due to a temperature rise or the like, and eventually the entire active region is broken. Therefore, the reverse avalanche resistance and the reverse recovery resistance in the diode mode can be improved.

  The p-well 18 shown in FIG. 2 has a dose (total amount of impurities) in the same manufacturing process as the conventional p-well (p-type region 6) shown in FIG. It can form by reducing.

  First, the manufacturing process up to the formation of FLR 25 is the same as the manufacturing process of FLR 25 of the conventional reverse blocking IGBT (FIG. 13), and will be described below with reference to FIG.

An oxide film is formed by thermal oxidation on the surface of an n-type FZ-Si wafer having a resistivity of 28 to 35 Ωcm. An isolation region opening is formed by pattern etching of the oxide film through a photolithography process. Thereafter, the photoresist is removed and the wafer is washed. A thin screen oxide film is formed in the isolation region opening by thermal oxidation. Using the oxide film as a mask, boron ions of 5 × 10 ¹⁵ cm ⁻² are implanted into the isolation region opening with an ion implantation energy of 45 KeV. The thickness of the oxide film needs to be a thickness that masks implantation of boron ions other than the opening into the Si wafer. A p-type isolation region 7 is formed by adding a thermal diffusion process similar to the conventional one to the boron ions implanted. The atmosphere for thermal diffusion is Ar or N ₂ containing oxygen. The diffusion temperature is 1250 to 1350 ° C. The diffusion time depends on the wafer thickness necessary for the design breakdown voltage, that is, the final depth of the p-type isolation region 7. In the case of a withstand voltage 700V class element, about 140 hours are required. At that time, the depth of the p-type isolation region 7 is 120 μm or more. Thereafter, the oxide film and screen oxide film on the wafer surface used as a mask are removed.

As shown in FIG. 15, in the conventional reverse blocking IGBT manufacturing process, an initial thermal oxide film 19 having a thickness of about 0.8 μm is formed again on the wafer surface by thermal oxidation, and the initial oxide film 19 is formed by a photolithography process. Patterning is performed to form an opening 20a for FLR 25 and an opening 20b for forming a p-well (p-type region 6). After removing the photoresist mask 20, a screen oxide film is formed by thermal oxidation with a thickness of about 30 to 80 nm. As shown in FIG. 16, boron ions are implanted into the entire surface of the wafer. The implantation energy is 30 to 60 KeV, and the dose is 1 to 2.5 × 10 ¹⁵ cm ⁻² .

  As shown in FIG. 17, the temperature is 1050 to 1150 ° C., the thermal diffusion time is 200 to 250 minutes, the drive-in is performed in an inert atmosphere, and the FLR 25 and the p well (p-type region 6) with a junction depth of 8 to 9 μm are used. ) Was formed.

  On the other hand, in the reverse blocking IGBT of the present invention, the pattern in the conventional p-well opening 20b shown at the right end of FIG. 15 is formed into a plurality of evenly arranged slits as shown in the plan view of FIG. Let it be the opening 20c. When all the openings are opened as in the prior art, all of the ion implantation dose is implanted into the opening. In that case, when the process is completed, a p-well (p-type region 6) (opening 20b) having the same profile as that of FLR 25 (opening 20a) is formed as in the prior art. However, when the pattern in the conventional p-well opening 20b is a plurality of evenly arranged slit-like openings 20c as shown in FIG. 4 as in the first embodiment according to the present invention, specifically, 4, if slit openings of A = 2 μm are arranged at an interval of B = 8 μm in the orthogonal direction, this slit-like opening is equivalent to the opening of a conventional p-well (p-type region 6). The area is about 8% of 20a. That is, if the dose is the same as that of the FLR 25 as in the conventional example, the dose of the p-well 18 of the present invention is 8% of that of the conventional p-well (p-type region 6).

  The width of the p-well (p-type region 6) immediately below the gate runner of the conventional reverse blocking IGBT is several tens of μm or more. For example, in FIG. 14, since the width of the p-well (p-type region 6) is 48 μm, a slit opening 20c of 2 μm × 2 μm square is formed in the p-well 6 having the width of 48 μm as shown in FIG. If a plurality of photoresist patterns are formed in the arrangement, the p-well 18 of the reverse blocking IGBT of the present invention can be obtained. As described above, the slit-like opening 20c according to the present invention is formed in the p-well region immediately below the gate runner and the gate pad, and is ion-implanted to form the p-well region 18.

  Further, in order to provide a large current turn-off capability as a reverse blocking IGBT, the opening area and the opening are set so that boron ions implanted from a plurality of slit-like openings are connected to each other by thermal diffusion and become a continuous region. It is necessary to set the interval. FIG. 5 shows a cross-sectional view after thermal diffusion along the line C1-C2 in FIG. In this way, the selectively implanted ion implantation regions become connected regions, that is, continuous p-well 18 regions, and the junction depth is also the conventional p-well (p-type region 6). ) It becomes shallower.

When the depth of the p-well 18 is shallow, when the RBSOA of the element is damaged due to carrier concentration on the gate runner when turning off with a large current and high voltage, as shown in FIG. The creeping dimensions of the p-type base region 3 and the p ⁺ contact region 5 may be increased. As a result, the area into which the turn-off current flows under the termination increases, so that current concentration is mitigated, dynamic avalanche and local overheating can be suppressed, and RBSOA can be recovered.

  In Example 2, a different manufacturing method for forming the impurity profile of the p-well 18 described in Example 1 will be described.

Similarly to FIGS. 15 and 16, an initial thermal oxide film 19 of 0.8 μm is formed on the surface of the wafer, and the initial oxide film 19 is patterned by a photolithography process, and an opening 20a for FLR 25, a p-well (p-type) Region 6) A forming opening 20b is formed. After removing the photoresist mask 20, a screen oxide film is formed by thermal oxidation with a thickness of about 30 to 80 nm. Boron ions are implanted into the entire wafer surface. The implantation energy is 45 to 75 KeV, and the dose is 1 to 2.5 × 10 ¹⁴ cm ^{−2, which} is 1/10 of the dose of the conventional p-well (p-type region 6) (FIG. 6).

As shown in FIG. 7, a photolithography process is performed, and a p-well 18 to be formed is covered with a resist mask 20c and masked. Thereafter, boron ions are implanted. The implantation conditions are an energy of 45 to 75 KeV and a dose of 1 to 2.5 × 10 ¹⁵ cm ⁻² .

  As shown in FIG. 8, FLR 25 and p-well 18 are formed at the same time in the same process as in FIG. That is, at a temperature of 1050 to 1150 ° C., a thermal diffusion time of 200 to 250 minutes, drive-in in an inert atmosphere, and FLR 25 and p-well 18 are formed.

  By providing the resist mask 20c in the region of the p well 18 as described above, only the dose amount of the p well 18 can be selectively reduced. Also in this case, since the continuous p-well 18 shallower than the conventional p-well (p-type region 6) can be produced, the reverse breakdown voltage is improved as in the first embodiment, and the reverse avalanche resistance or diode mode is used. Can improve reverse recovery tolerance.

  In Example 3 according to the present invention, a further different manufacturing method for forming the profile of the p-well 18 described in Example 1 will be described.

  As shown in FIG. 9, the same steps as those in FIG. 15 described in the first embodiment are performed. However, the resist mask 20 in the photolithography process is formed so as to cover the p well 18 to be formed later.

  A p-well 18 is formed through the steps of FIGS.

  As shown in FIG. 10, in order to remove the oxide film 19 in the active region 21, a photolithography process is performed using a resist mask 20 that covers the active region 21. A p well 18 forming opening 20b to be formed later is formed. The oxide film 19 is removed by wet etching. Thereafter, the resist mask 20 is removed by ashing. Clean the wafer.

As shown in FIG. 11, the screen oxide film is thermally oxidized by about 30 to 80 nm. Photolithography is performed with the resist mask 20. A p well 18 forming opening 20b to be formed later is formed. Boron ions are implanted into the entire wafer surface. The implantation conditions are such that the energy is 45 to 75 KeV, and the dose is 1 to 2.5 × 10 ¹⁴ cm ⁻² or less, which is 1/10 of the dose of FLR25.

  As shown in FIG. 12, drive-in is performed with the same thermal history as in the subsequent manufacturing process of the conventional reverse blocking IGBT, and the p-well 18 is formed.

  According to the reverse blocking IGBT of the third embodiment of the present invention, the dose amount of the gate runner having a small area with respect to the active region 21 and the p-type region (p well 18) immediately below the gate pad is reduced, which is related to the reverse breakdown voltage. Since the current amplification factor of the pnp transistor is reduced, the reverse breakdown voltage is improved. The reverse breakdown voltage difference between the junction of the p-well just below the gate runner and the gate pad and the p-type base region junction in the active region is reduced, and even if reverse breakdown occurs first below the gate runner, It tends to yield the entire active region. Further, the reverse avalanche resistance and the reverse recovery resistance in the diode mode are improved.

1: Drift layer 3: p-type base region 4: n ⁺ emitter region 5: p ⁺ base contact layer 6: gate runner and gate pad p-type region 7: p-type isolation region 8a: gate runner polysilicon electrode 8b: poly Silicon gate electrode 9: Gate oxide film 10: Emitter electrode 11: Polysilicon field plate 12: Metal field plate 13: Collector layer 13a: Collector junction 13b: Collector junction end 14: Collector electrode 17: Interlayer insulating film 18: Gate runner P-well 19 under the gate pad: initial oxide film 20: photoresist 20a: FLR opening 20b: p-well opening 20c: photoresist on the p-well opening 21: active region 22: termination region 23: gate Runner and gate pad oxide film 25: field limit Ting ring 30: Front side 40: Back side 100: Reverse blocking IGBT

Claims (8)

A second conductivity type base region, a first conductivity type emitter region selectively provided on a surface layer of the second conductivity type base region on one surface side of the first conductivity type semiconductor substrate serving as a drift layer, the emitter region and the drift An active region having a MOS gate structure as a main region, the gate electrode being in contact with the surface of the second conductivity type base region sandwiched by the surface of the layer via a gate oxide film;
A termination region having an electric field relaxation structure including a field limiting ring surrounding the outer periphery of the active region;
A second conductivity type collector layer on the other side,
A second conductivity type isolation region that is on the outer periphery of the termination region and is in contact with the second conductivity type collector layer through the drift layer from the one surface side;
A second conductivity type well between the active region on the one surface side and the termination region,
The depth and the amount of impurities from the one surface side surface of the second conductivity type well are not less than the depth and the amount of impurities of the second conductivity type base region, and less than the depth and the amount of impurities of the field limiting ring. A reverse-blocking IGBT characterized by being. A first conductive type semiconductor substrate serving as a drift layer has a second conductive type base region, a trench penetrating the second conductive type base region and reaching the drift region, and a gate in contact with the inside of the trench through a gate oxide film An active region mainly composed of a MOS gate structure comprising a first conductivity type emitter region selectively formed on the surface of the electrode and the base region and in contact with the trench gate oxide film;
A termination region having an electric field relaxation structure including a field limiting ring surrounding the outer periphery of the active region;
A second conductivity type collector layer on the other side,
A second conductivity type isolation region that is on the outer periphery of the termination region and is in contact with the second conductivity type collector layer through the drift layer from the one surface side;
A second conductivity type well between the active region on the one surface side and the termination region,
The depth and the amount of impurities from the one surface side surface of the second conductivity type well are not less than the depth and the amount of impurities of the second conductivity type base region, and less than the depth and the amount of impurities of the field limiting ring. A reverse-blocking IGBT characterized by being. 3. The reverse blocking IGBT according to claim 1, wherein the second conductivity type well is 1/10 or less of the impurity amount of the field limiting ring. The reverse blocking IGBT according to claim 1, further comprising a gate runner on the surface of the second conductivity type well via an oxide film. 5. The reverse blocking IGBT according to claim 4, wherein the gate runner is a polysilicon layer. 6. The reverse blocking IGBT according to claim 5, wherein the polysilicon layer is a doped polysilicon layer. A plurality of ion implantation regions are equally arranged in the second conductivity type well, and the second conductivity type well is formed by overlapping the plurality of ion implantation regions by thermal diffusion after ion implantation. A method for manufacturing the reverse blocking IGBT according to claim 1. 8. The method of manufacturing a reverse blocking IGBT according to claim 7, wherein the ion implantation is performed simultaneously with ion implantation for forming the field limiting ring.

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