JP6135293B2 - Clock generation apparatus and clock generation method - Google Patents

Description

  The present invention relates to a clock generation device and a clock generation method.

The radio base station currently employs an FDD (Frequency Division Duplex) scheme, but the adoption of a TDD (Time Division Duplex) scheme is also being studied for cell miniaturization. In the TDD scheme, the mutual timing between radio base stations is an important issue compared to the FDD scheme. In order to solve this problem, time synchronization using a protocol called PTP (Precision Time Protocol) defined by IEEE 1588 or GPS (Global Positioning System) is used. PTP (Precision Time Protocol) is a standard that defines a method for synchronizing devices on a network.

  In a radio base station, a PTP ordinary clock or GPS receiver is mounted on a synchronization card between base stations, a clock synchronized with this is generated, and a clock is supplied to the radio unit, thereby synchronizing between radio base stations. Is realized.

  FIG. 1 is a diagram showing a configuration example of an inter-base station synchronization card and a clock card in a conventional radio base station. In the example of FIG. 1, the radio base station includes an inter-base station synchronization card and two clock cards (clock card # 1, clock card # 2).

  In the wireless base station, a communication clock is supplied from the clock card to the wireless card that performs data processing. The clock card has a redundant configuration for stable supply of a communication clock. That is, a plurality of clock cards are mounted on the radio base station. Each clock card is equipped with a highly stable reference frequency oscillator (hereinafter also referred to as an oscillator).

  Also, a highly stable reference frequency oscillator is mounted on an inter-base station synchronization card for generating a synchronization clock based on an external master clock (for example, a PTP master or a GPS antenna).

JP-A-4-291533

  A highly stable reference frequency oscillator is used for accuracy assurance in a radio base station. Since highly stable reference frequency oscillators are expensive, it is necessary to reduce the number of them used. Furthermore, it is required to reduce the accuracy by reducing the number of highly stable reference frequency oscillators used.

  It is an object of the technology disclosed herein to reduce the number of highly stable reference frequency oscillators without degrading accuracy in a clock generator.

  The disclosed technology employs the following means in order to solve the above-described problems.

That is, the first aspect is
A clock generator connected to a first device having a first oscillator for generating a clock signal and a second device having a second oscillator for generating a clock signal,
A selector that selects one of the clock signal generated by the first oscillator and the clock signal generated by the second oscillator;
The internal clock is included, accumulated data based on the clock signal is stored, the clock signal selected by the selection unit and the accumulated data are used to synchronize the internal clock with the external master clock, and the clock signal based on the internal clock is An output clock section;
When a switching signal instructing switching of the clock signal selected by the selection unit is received, the selection unit is instructed to switch the clock signal to be selected, and the clock unit is instructed to delete the accumulated data. A control unit,
The selection unit switches a clock signal to be selected based on an instruction from the control unit,
When receiving an instruction to delete the accumulated data, the clock unit deletes the accumulated data, and synchronizes the internal clock with the external master clock using the clock signal switched by the selection unit, A clock generator that outputs a clock signal based on an internal clock.

  An aspect of the disclosure may be realized by executing a program by an information processing device. That is, the disclosed configuration can be specified as a program for causing the information processing apparatus to execute the processing executed by each unit in the above-described aspect, or a computer-readable recording medium on which the program is recorded. Further, the disclosed configuration may be specified by a method in which the information processing apparatus executes the process executed by each of the above-described units.

  According to the disclosed technique, the number of highly stable reference frequency oscillators can be reduced in the clock generator without degrading accuracy.

FIG. 1 is a diagram showing a configuration example of an inter-base station synchronization card and a clock card in a conventional radio base station. FIG. 2 is a diagram illustrating a configuration example of a radio base station. FIG. 3 is a diagram illustrating a configuration example of an inter-base station synchronization card and a clock card of a radio base station. FIG. 4 is a diagram illustrating an example of an operation flow for switching the clock signal supplied to the PTP device. FIG. 5 is a diagram illustrating an example (1) of the operation sequence. FIG. 6 is a diagram illustrating an example (2) of the operation sequence. FIG. 7 is a diagram illustrating an example of an operation flow of phase adjustment.

  Hereinafter, embodiments will be described with reference to the drawings. The configuration of the embodiment is an exemplification, and the disclosed configuration is not limited to the specific configuration of the disclosed embodiment. In implementing the disclosed configuration, a specific configuration according to the embodiment may be appropriately employed.

Embodiment
(Configuration example)
FIG. 2 is a diagram illustrating a configuration example of a radio base station. The radio base station 10 includes an inter-base station synchronization card 100, a clock card A200, a clock card B300, a control card 400, a radio card 500, a switch card 600, and a station interface card 700. The radio base station 10 transmits and receives packets to and from the PTP master of the LTE station.

  The inter-base station synchronization card 100 synchronizes the internal clock with the clock of the PTP master based on the PTP packet from the PTP master. The inter-base station synchronization card 100 generates a clock signal based on the internal clock, and outputs the generated clock signal to the clock card A200 and the clock card B300.

The clock card A200 generates a communication clock signal based on the clock signal from the inter-base station synchronization card 100 and outputs it to the wireless card. Clock card B300 has the same configuration as the clock card A200, is used as an emergency clock card, such as when the clock card A200 fails.

  The control card 400 controls the clock card A200 and the clock card B300. Wireless card 500 performs baseband signal processing on transmission signals and reception signals with wireless terminals. The wireless card 500 receives a communication clock signal from the clock card. Switch card 600 switches between wireless cards. The station interface card 700 includes an L2SW (Layer 2 Switch). The L2SW extracts the PTP packet from the PTP master and transmits it to the inter-base station synchronization card 100.

  FIG. 3 is a diagram illustrating a configuration example of an inter-base station synchronization card and a clock card of a radio base station. In the example of FIG. 3, the radio base station includes an inter-base station synchronization card 100, a clock card A200, and a clock card B300. A PTP master 1100 and a GPS antenna 1200 are connected to the inter-base station synchronization card 100. Either one of the PTP master 1100 and the GPS antenna 1200 may be omitted.

  The inter-base station synchronization card 100 includes a PTP device 102, a clock selection unit 112, a signal change monitoring unit 114, a switching state transition control unit 116, a synchronization state monitoring control unit 118, and a PTP device communication unit 120. The inter-base station synchronization card 100 further includes a GbEPHY 130, a GPS 140, a CPU 150, and a memory 160.

The PTP device 102 receives a clock signal having a predetermined frequency from the clock selection unit 112. The predetermined frequency is, for example, 10 MHz or 5 MHz. The PTP device 102 corrects drift and offset of the clock signal ( internal clock) received from the clock selection unit 112 with respect to the clock of the PTP master 1100. The PTP device 102 outputs a 1 PPS (1 Pulse Per Second) signal, a 10 MHz clock signal, a ToD (Time of Day), and the like. The 1PPS signal is a pulse signal every second. ToD (Time of Day) is time information. The PTP device 102 is an example of a clock unit.

  The PTP device 102 generates a 1PPS signal or the like based on internal accumulated data, an input clock signal, and a signal from the PTP master 1100 or the like. The accumulated data inside the PTP device 102 is data obtained by an input clock signal. The input clock signal depends on the oscillator that generates the input clock signal. Therefore, the accumulated data depends on the oscillator that generates the input clock signal. Accordingly, when the accumulated data inside the PTP device 102 obtained before the change of the oscillator that generates the input clock signal is used, the 1PPS signal or the like is generated after the change of the oscillator that generates the input clock signal. The operation is not guaranteed. Therefore, when the oscillator that generates the clock signal input to the PTP device 102 is changed, the accumulated data in the PTP device 102 is required to be reset.

The clock selection unit 112 switches the clock signal output to the PTP device 102 between normal (active) and emergency (standby). The clock signal input to the clock selection unit 112 is a clock signal generated by the high stability reference frequency oscillator 202 of the clock card A 200 and a clock signal generated by the high stability reference frequency oscillator 302 of the clock card B 300. . The clock selection unit 112 normally outputs the clock signal generated by the high stability reference frequency oscillator 202 of the clock card A 200 to the PTP device 102. The switching of the clock signal is performed by an instruction from the switching state transition control unit 116, for example. The clock selection unit 112 is an example of a selection unit.

  The signal change monitoring unit 114 monitors the switching signal and notifies the switching state transition control unit 116 if there is a change.

  The switching state transition control unit 116 controls switching transition by a trigger (notification) from the signal change monitoring unit 114.

  The synchronization state monitoring control unit 118 reads the state of the PTP device 102 and operates the PTP device 102 via the PTP device communication unit 120.

  The PTP device communication unit 120 performs communication unique to the PTP device 102 with the PTP device 102. Communication by the PTP device communication unit 112 is, for example, low-speed serial communication such as I2C.

  The GbEPHY 130 receives a PTP packet from the PTP master 300. The GbEPHY 130 transmits a PTP packet to the PTP device 102. The GbEPHY 130 receives a PTP packet for the PTP master 300 from the PTP device 102. The GbEPHY 130 transmits the PTP packet to the PTP master 1100.

  The GPS module 140 generates a 1PPS signal and ToD from the GPS signal received by the GPS antenna, and outputs it to the PTP device 102. The GPS clock is an example of an external master clock.

  The CPU 150 controls the inter-base station synchronization card 100. The CPU 150 loads a program recorded on the recording medium into the work area of the memory 160 and executes the program, and the peripheral device or the like is controlled through execution of the program, thereby realizing a function that meets a predetermined purpose. A DSP (Digital Signal Processor) may be used instead of the CPU 150.

  The memory 160 stores programs and data used by the CPU 150. The memory 160 includes, for example, a RAM (Random Access Memory) and a ROM (Read Only Memory).

  The inter-base station synchronization card 100 only needs to include at least one of the GbEPHY 130 and the GPS module 140.

  The clock selection unit 112, the signal change monitoring unit 114, the switching state transition control unit 116, the synchronization state monitoring control unit 118, and the PTP device communication unit 120 are realized using, for example, an FPGA (Field Programmable Gate Array).

  The signal change monitoring unit 114, the switching state transition control unit 116, the synchronization state monitoring control unit 118, and the PTP device communication unit 120 may operate as one control unit.

  The clock card A200 includes a highly stable reference frequency oscillator 202, a DPLL 204, a selector 206, an APLL 208, a phase difference detection unit 210, and an abnormal time switching unit 212.

  The clock card B300 includes a highly stable reference frequency oscillator 302, a DPLL 304, a selector 306, an APLL 308, a phase difference detection unit 310, and an abnormal time switching unit 312.

  Clock signals generated by the clock card A200 and the clock card B300 are output to a wireless card or the like.

  The clock card A200 and the clock card B300 have the same function. Here, it is assumed that the clock card A200 is a clock card used in a normal time, and the clock card B300 is a card used in an emergency. Here, the clock card A200 will be mainly described.

  The highly stable reference frequency oscillator 202 generates a signal (clock signal) having a predetermined frequency. The predetermined frequency is, for example, 5 MHz or 10 MHz. A signal generated by the highly stable reference frequency oscillator 202 is output to the DPLL 204 and the clock selection unit 112 of the inter-base station synchronization card 100.

A DPLL (Digital Phase Locked Loop) 204 is a digital phase synchronization circuit. D
The PLL 204 adjusts the frequency of a signal to be output, for example, in units of 1 PPM according to an instruction from the phase difference detection unit 210 based on a signal from the highly stable reference frequency oscillator 202 or the PTP device 102. The DPLL 204 outputs a 3.84 MHz signal (communication clock signal) to the selector 206.

  The selector 206 selects and outputs one signal from two input signals. The selector 206 receives a signal from the DPLL 204 and a signal from the clock card B300. In the selector 206, the signal from the DPLL 204 is normally selected. Further, the selector 306 of the clock card B300 normally selects a signal from the clock card A200.

  An APLL (Analog Phase Locked Loop) 208 is an analog phase synchronization circuit. The APLL 208 outputs a clock signal synchronized with the clock signal input from the selector 206. The signal (communication clock signal) output from the APLL 208 is input to the wireless card.

  The phase difference detection unit 210 has a register for storing the self phase, and detects whether the self phase is delayed or advanced by comparing the external 1PPS and ToD with the self-phase 1PPS and ToD. The phase difference detection unit 210 adjusts the synchronization phase of the DPLL 204 based on the phase difference.

  When receiving an abnormality notification from the abnormality detection unit 314 of the clock card B300, the abnormality time switching unit 212 transmits a switching signal to the signal change monitoring unit 114 of the inter-base station synchronization card 100.

  The abnormality detection unit 214 monitors the state of the clock card A200 and detects an abnormality of the clock card A200. When detecting an abnormality of the clock card A200 when the clock card A200 is operating as a clock card that is normally used, the abnormality detection unit 214 notifies the abnormality switching unit 312 of the clock card B300 of an abnormality.

  When receiving an abnormality notification from the abnormality detection unit 214 of the clock card A200, the abnormality time switching unit 312 of the clock card B300 transmits a switching signal to the signal change monitoring unit 114 of the inter-base station synchronization card 100.

  A plurality of components may be integrated and operate as one component. One component may be divided into a plurality of components to operate. Furthermore, a plurality of components may operate as another plurality of components.

  Each unit of the inter-base station synchronization card 100, the clock card A200, and the clock card B300 can be realized as a hardware component, a software component, or a combination thereof.

  A hardware component is a hardware circuit, for example, an FPGA (Field Programmable Gate Array), an application specific integrated circuit (ASIC), a gate array, a combination of logic gates, an analog circuit, or the like. .

  The software component is a component that realizes predetermined processing as software. The components of software are not a concept that limits the language, development environment, etc. for realizing software.

(Time synchronization)
The synchronization of the clock (internal clock) of the PTP device 102 of the inter-base station synchronization card 100 with the clock of the PTP master 1100 will be described.

  The PTP master 1100 transmits a Sync Message to the PTP device 102 of the inter-base station synchronization card 100 at time T1 in the PTP master 1100. The inter-base station synchronization card 100 receives the Sync Message from the PTP master 1100 at the time T2 in the PTP device 102. Also, the PTP device 102 receives the Sync Message transmission time T1 from the PTP master 1100 from the PTP master 1100 using a Sync Follow up Message.

Also, the PTP device 102 transmits a Delay Request Message to the PTP master 1100 at time T3 in the PTP device 102. The PTP master 1100
A Delay Request Message from the PTP device 102 is received at time T4 in the PTP master 1100. In addition, the PTP device 102 receives the Delay Request Message reception time T4 in the PTP master 1100 from the PTP master 1100 using a Delay Response Message.

The (one-way) path delay Td between the PTP master 1100 and the PTP device 102 is calculated as Td = ((T2−T1) + (T4−T3)) / 2. Using the path delay Td,
The time difference Tms between the PTP master 1100 and the PTP device 102 is calculated as Tms = Td− (T2−T1) = (T4−T3) −Td. The time difference Tms is calculated by the PTP device 102.

The time difference Tms is calculated continuously (for example, every predetermined time) by the PTP device 102 and accumulated in the PTP device 102. The PTP device 102 calculates an average value of the time difference Tms. The time difference Tms accumulated in the PTP device 102 and the average value of the time difference Tms are examples of accumulated data. The accumulated data is stored in the PTP device 102. The internal clock of the PTP device 102 is corrected using the average value of the time difference Tms. The PTP device 102 outputs a clock signal based on the internal clock to the clock card A200 and the clock card B300. The time difference Tms depends on a clock signal (a clock signal generated by a highly stable reference frequency oscillator) input to the PTP device 102. Therefore, although the clock signal input to the PTP device 102 is changed, the accuracy of the clock signal output from the PTP device 102 corrected using the average value of the accumulated time difference Tms is not guaranteed. .

  When synchronizing the clock (internal clock) of the PTP device 102 with the GPS clock, the PTP device 102 calculates the time difference between the GPS clock and the clock of the PTP device 102. The time difference is continuously calculated and accumulated in the PTP device 102. The internal clock of the PTP device 102 is corrected using the average value of the time difference. The time difference also depends on the clock signal input to the PTP device 102. Therefore, although the clock signal input to the PTP device 102 is changed, the accuracy of the clock signal output from the PTP device 102 corrected using the average value of the accumulated time differences is not guaranteed.

(Operation example)
FIG. 4 is a diagram illustrating an example of an operation flow for switching the clock signal supplied to the PTP device of the present embodiment.

  When an abnormality is detected in the clock card A200, the abnormality switching unit 312 of the clock card B300 is notified (S101). When the abnormality switching unit 312 of the clock card B300 recognizes the abnormality of the clock card A200, it transmits a switching signal to the inter-base station synchronization card 100 (S102). The switching signal is a signal that instructs switching of the clock card and resetting of the PTP device 102. In addition, the abnormal time switching unit 312 instructs the clock card A200 and the clock card B300 to switch to the self-running mode (holdover mode) (S103). The free-running mode is a mode in which each clock card outputs a communication clock signal without depending on the clock signal from the inter-base station synchronization card 100. Each clock card switches the communication clock signal output to the wireless card or the like from the communication clock signal of the clock card A200 to the communication clock signal of the clock card B300 (S104).

  When the inter-base station synchronization card 100 receives the switching signal, it resets the PTP device 102 (S105). Further, the inter-base station synchronization card 100 changes the clock signal input to the PTP device 102 from the clock signal of the clock card A200 to the clock signal of the clock card B300 (S106).

  Further, the inter-base station synchronization card 100 deletes the accumulated data of the PTP device 102. The PTP device 102 of the inter-base station synchronization card 100 performs resynchronization processing with the external master clock. When the PTP device 102 is synchronized again, the inter-base station synchronization card 100 instructs each clock card to switch from the self-running mode to the subordinate mode (S107). Each clock card switches from the free-running mode to the subordinate mode, and receives a clock signal from the PTP device 102. As a result, each clock card again outputs a communication clock signal based on the clock signal of the PTP device 102 toward the wireless card or the like.

  Next, the operation of switching the clock signal supplied to the PTP device of this embodiment will be described in detail using an operation sequence.

  5 and 6 are diagrams illustrating an example of an operation sequence according to the present embodiment. “A” to “N” in FIG. 5 are connected to “A” to “N” in FIG. 6, respectively.

The abnormality detection unit 214 of the clock card A200 monitors the state of the clock card A200. The abnormality detection unit 214 detects an abnormality of the clock card A200 (SQ1001).
Then, an abnormality notification is transmitted to the abnormality time switching unit 312 of the clock card B300 (SQ1002). The abnormality of the clock card A200 is, for example, a failure of the highly stable reference frequency oscillator 202. For example, the abnormality detection unit 214 detects a failure of the high stability reference frequency oscillator 202 by detecting a break of the clock signal of the high stability reference frequency oscillator 202.

  Upon receiving an abnormality notification of the clock card A200 from the abnormality detection unit 214 of the clock card A200, the abnormality time switching unit 312 transmits a switching signal to the signal change monitoring unit 114 of the inter-base station synchronization card 100 (SQ1003). The switching signal is a signal that instructs switching of the clock card and resetting of the PTP device 102. The abnormal time switching unit 312 may transmit a switching signal to the signal change monitoring unit 114 of the inter-base station synchronization card 100, for example, when the clock card A200 stops due to inspection, inspection, repair, etc. of the clock card A200. .

  The abnormal time switching unit 312 instructs the phase difference detection unit 210 of the clock card A200 to switch to the self-running mode (self-running synchronous mode) (SQ1004). The clock card A200 is not affected by the clock signal from the PTP device 102 by switching to the self-running mode. In addition, the abnormal time switching unit 312 instructs the phase difference detection unit 310 of the clock card B300 to switch to the self-running mode (self-running synchronous mode) (SQ1005). The clock card B300 is not affected by the clock signal from the PTP device 102 by switching to the self-running mode. Each clock card can supply a communication clock signal whose accuracy is guaranteed for a predetermined time in the self-running mode without receiving a signal from the clock signal from the PTP device 102.

  In addition, the abnormality time switching unit 312 instructs the selector 206 of the clock card A200 to select a signal from the clock card B300 (SQ1006). By selecting a signal from the clock card B300, a communication clock signal generated by the clock card B300 from the clock card A200 is output to the wireless card 400. The abnormal time switching unit 312 instructs the selector 306 of the clock card B300 to select a signal from the DPLL 304 of the clock card B300 (SQ1007). By selecting a signal from the DPLL 304 of the clock card B300, a communication clock signal generated by the clock card B300 from the clock card B300 is output to the wireless card 400.

  On the other hand, when the signal change monitoring unit 114 of the inter-base station synchronization card 100 receives the switching signal from the abnormal time switching unit 312, it notifies the switching state transition control unit 116 that the switching signal has been received (SQ 1008).

  When receiving the notification from the signal change monitoring unit 114, the switching state transition control unit 116 transmits a reset request to the synchronization state monitoring control unit 118 (SQ1009). The reset request is a request for resetting the PTP device 102. Moreover, the switching state transition control unit 116 transmits a clock selection request for requesting to change the clock signal to be selected to the clock selection unit 112 (SQ1010). When receiving the clock selection request from the switching state transition control unit 116, the clock selection unit 112 switches the clock signal input to the PTP clock from the clock signal of the clock card A200 to the clock signal of the clock card B300. The clock signal of the clock card A200 is generated by the high stability reference frequency oscillator 202. The clock signal of the clock card B300 is generated by the highly stable reference frequency oscillator 302.

When receiving the reset request from the switching state transition control unit 116, the synchronization state monitoring control unit 118 instructs the PTP device communication unit 120 to reset the PTP device 102 (SQ1011).

  When receiving the instruction from the synchronization state monitoring control unit 118, the PTP device communication unit 120 transmits a reset instruction to the PTP device 102 (SQ1012).

  When receiving the reset instruction, the PTP device 102 performs reset processing of the PTP device 102. In the reset process, the PTP device 102 deletes accumulated data used for generating a clock signal. When the reset process is completed, the PTP device 102 performs another synchronization process (resynchronization process) with the PTP master 1100 or the GPS module 140 via the GbEPHY 130. In the resynchronization process, for example, the PTP device 102 repeatedly transmits and receives PTP packets to and from the PTP master 1100, and performs an average value process and the like. When the resynchronization process ends, the PTP device enters a synchronized state. The PTP device 102 uses accumulated data accumulated when the clock signal generated by the high stability reference frequency oscillator 202 is used, when the clock signal generated by the high stability reference frequency oscillator 302 is used. do not do. Therefore, the PTP device 102 can output a clock signal with guaranteed accuracy.

  The synchronization state monitoring control unit 118 reads the state of the PTP device 102 via the PTP device communication unit 120. The synchronization state monitoring control unit 118 confirms that the reset process and the resynchronization process of the PTP device 102 are completed and the PTP device 102 is in the synchronized state again. The control unit 116 is notified (SQ1013). The synchronization state monitoring control unit 118 may end the reset process when a predetermined time has elapsed since the start of the reset process.

  When receiving the notification from the PTP device communication unit 120, the switching state transition control unit 116 instructs the phase difference detection unit 210 to switch from the self-running mode to the subordinate mode (SQ1014). The clock card A200 receives the 10 MHz signal (clock signal) from the PTP device 102 by switching to the subordinate mode.

  The phase difference detection unit 210 detects whether the self-phase is delayed or advanced by comparing the external 1PPS and ToD with the self-phase 1PPS and ToD. The phase difference detection unit 210 adjusts the synchronization phase of the DPLL 204 in order to eliminate the phase difference. By the phase adjustment, the phase difference between the phase of the external signal and the self phase is gradually eliminated. The phase adjustment will be described in detail later.

  In addition, when receiving the notification from the PTP device communication unit 120, the switching state transition control unit 116 instructs the phase difference detection unit 310 to switch from the self-running mode to the subordinate mode (SQ1015). The clock card B300 receives the 10 MHz signal from the PTP device 102 by switching to the subordinate mode.

  The phase difference detection unit 310 detects whether the self-phase is delayed or advanced by comparing the external 1PPS and ToD with the self-phase 1PPS and ToD. The phase difference detection unit 310 adjusts the synchronization phase of the DPLL 204 in order to eliminate the phase difference. By the phase adjustment, the phase difference between the phase of the external signal and the self phase is gradually eliminated.

  FIG. 7 is a diagram illustrating an example of an operation flow of phase adjustment.

  The phase difference detection unit 210 compares the 1PPS and ToD from the PTP device 102, which is the reference clock signal, with the self-phase 1PPS and ToD (S201).

  The phase difference detection unit 210 determines whether there is a phase difference between the phase of the reference clock signal and the self phase (S202). If there is no phase difference (S202; YES), the process ends. If there is a phase difference (S202; NO), the process proceeds to step S203.

  The phase difference detection unit 210 determines whether or not the self phase is advanced with respect to the phase of the reference clock signal (S203). If the self phase is delayed with respect to the phase of the reference clock signal (S203; YES), the process proceeds to step S204. If the self phase is advanced with respect to the phase of the reference clock signal (S202; NO), the process proceeds to step S205.

  In step S204, the phase difference detection unit 210 sets the frequency of the DPLL 204 to + 1PPM (parts per million). Thereafter, the process returns to step S201.

  In step S205, the phase difference detection unit 210 sets the frequency of the DPLL 204 to -1PPM. Thereafter, the process returns to step S201.

  By doing so, the phase difference is gradually eliminated between the phase of the reference clock and the self phase.

  The phase difference detection unit 310 of the clock card B300 is the same as the phase difference detection unit 210 of the clock card A200.

(Operation and effect of the embodiment)
The PTP device 102 of the inter-base station synchronization card 100 in the radio base station 10 receives a clock signal generated by the high stability reference frequency oscillator 202 of the clock card A200 or the high stability reference frequency oscillator 302 of the clock card B300. The inter-base station synchronization card 100 does not have a highly stable reference frequency oscillator. The PTP device 102 deletes accumulated data inside the PTP device 102 when the input clock signal is switched. The PTP device 102 synchronizes the internal clock with the external master clock using the switched clock signal. When the clock signal input to the PTP device 102 is switched, the accumulated data inside the PTP device 102 is deleted. Thereby, after switching, the PTP device 102 can synchronize the internal clock of the PTP device 102 with the external master clock without being affected by the accumulated data before switching. That is, the inter-base station synchronization card 100 can output a clock signal with guaranteed accuracy even after switching the clock supplied to the PTP device 102.

  While each clock card is operating in the free-running mode, the PTP device 102 deletes accumulated data and performs resynchronization processing. As a result, the inter-base station synchronization card 100 can switch the clock signal supplied to the PTP device 102 without affecting the supply of the communication clock signal from the clock card.

  Since the inter-base station synchronization card 100 does not have a highly stable reference frequency oscillator, the number of highly stable reference frequency oscillators in the radio base station 10 can be reduced as compared with the prior art. Further, since the inter-base station synchronization card 100 does not have a highly stable reference frequency oscillator, the mounting area can be reduced by removing the highly stable reference frequency oscillator as compared with the prior art.

10 radio base stations
100 Inter-base station synchronization card
102 PTP device
112 Clock selector
114 Signal change monitoring unit
116 State transition control unit for switching
118 Synchronous state monitoring control unit
120 PTP device communication unit
130 GbEPHY
140 GPS module
150 CPU
160 memory
200 Clock card A
202 Highly stable reference frequency oscillator
204 DPLL
206 Selector
208 APLL
210 Phase difference detector
212 Abnormal switching unit
214 Anomaly detector
300 Clock card B
302 Highly stable reference frequency oscillator
304 DPLL
306 Selector
308 APLL
310 Phase difference detector
312 Abnormal switching unit
314 Abnormality detection unit
400 control card
500 wireless card
600 switch card
700 station interface card 1100 PTP master 1200 GPS antenna

Claims (2)

A clock generator connected to a first device having a first oscillator for generating a clock signal and a second device having a second oscillator for generating a clock signal,
A selector that selects one of the clock signal generated by the first oscillator and the clock signal generated by the second oscillator as an internal clock ;
Storing the accumulated data to an external master clock based on the time difference between the path delay between the internal clock, the accumulated data using the external master clock to synchronize the internal clock, wherein the clock signal synchronized first An oscillator and a clock unit for outputting to the second oscillator ;
When a switching signal instructing switching of the clock signal selected by the selection unit is received, the selection unit is instructed to switch the clock signal to be selected, and the clock unit is instructed to delete the accumulated data. A control unit,
The selection unit switches a clock signal to be selected based on an instruction from the control unit,
Said clock unit, when receiving an instruction to remove the accumulated data, the delete cumulative data, said to synchronize the clock signal is switched before Kigaibu master clock by the selection unit, a clock signal obtained by the synchronization Is generated to the first oscillator and the second oscillator . In a clock generator connected to a first device having a first oscillator for generating a clock signal and a second device having a second oscillator for generating a clock signal,
The clock generator
Selecting one of the clock signal generated by the first oscillator and the clock signal generated by the second oscillator as an internal clock ;
Storing the accumulated data to an external master clock based on the time difference between the path delay between the internal clock, the accumulated data using the external master clock to synchronize the internal clock, wherein the clock signal synchronized first Output to the oscillator and the second oscillator ;
When receiving the switch signal for instructing to switch the clock signal to be selected, switch the clock signal for selecting, to remove the accumulated data, to synchronize the clock signal is switched before Kigaibu master clock, then the synchronization A clock generation method for outputting a clock signal to the first oscillator and the second oscillator .

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