JP6124513B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6124513B2 JP6124513B2 JP2012113837A JP2012113837A JP6124513B2 JP 6124513 B2 JP6124513 B2 JP 6124513B2 JP 2012113837 A JP2012113837 A JP 2012113837A JP 2012113837 A JP2012113837 A JP 2012113837A JP 6124513 B2 JP6124513 B2 JP 6124513B2
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Description
[第1の実施の形態に係る半導体装置の構造]
まず、第1の実施の形態に係る半導体装置の構造について説明する。図1は、第1の実施の形態に係る半導体装置を例示する断面図である。図1を参照するに、半導体装置10は、大略すると、第1絶縁層21と、配線層22と、第2絶縁層23と、配線層24と、第3絶縁層25と、配線層26と、第4絶縁層27と、配線層28と、ソルダーレジスト層29と、受動素子40と、接着層50と、半導体チップ60とを有する。
次に、第1の実施の形態に係る半導体装置の製造方法について説明する。図2〜図4は、第1の実施の形態に係る半導体装置の製造工程を例示する図である。なお、図2〜図4において、Cは最終的にダイサー等により切断する位置(以下、「切断位置C」とする)を示している。
次に、第1の実施の形態に係る半導体装置の応用例として、POP構造の半導体装置について説明する。図5は、POP構造の半導体装置を例示する断面図である。図5を参照するに、半導体装置10Aは、半導体装置10に他の半導体装置70を搭載したPOP構造の半導体装置である。なお、図5において、半導体装置10は、図1等とは上下が反転した状態で描かれている。
第1の実施の形態の変形例1では、高さの異なる受動素子を搭載する例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する。
21 第1絶縁層
21x、29x 開口部
22、24、26、28 配線層
22A、120、130 金属箔
23 第2絶縁層
23x、25x、25y、25z、27x ビアホール
23y 半導体チップ収容部
25 第3絶縁層
27 第4絶縁層
29 ソルダーレジスト層
40、40B 受動素子
41、41B 電極
50 接着層
60 半導体チップ
61 電極パッド
80 接合部
90 外部接続端子
100 支持体
100x 凹部
110 絶縁層
Claims (9)
- 最外層である第1絶縁層と、
前記第1絶縁層の一方の面に形成され、前記第1絶縁層に形成された複数の開口部内に各々露出する第1電極パッドを含む配線層と、
前記第1絶縁層の一方の面に前記配線層を覆うように形成された第2絶縁層と、
前記第2絶縁層を貫通するように設けられた半導体チップ収容部と、
回路形成面を前記第1絶縁層と反対側に向けて、前記半導体チップ収容部に収容された半導体チップと、
前記第2絶縁層の一方の面、並びに前記半導体チップの前記回路形成面及び側面を被覆する第3絶縁層と、
少なくとも側面の一部が前記第2絶縁層に接し前記第1絶縁層に埋設されている埋設部と、前記第1絶縁層の他方の面から突出している突出部とを備えた受動素子と、を有し、
前記埋設部に位置する前記受動素子の電極の端面は前記第2絶縁層又は前記第3絶縁層により被覆され、
前記埋設部に位置する前記受動素子の電極の端面を露出するビアホール内に充填されたビア配線と、前記第2絶縁層又は前記第3絶縁層の一方の面に配置され前記ビア配線と一体的に形成された配線パターンと、を備えた他の配線層が設けられ、
前記第1電極パッドは、接合部を介して他の半導体装置と電気的に接続され、
前記第1絶縁層の他方の面からの前記突出部の突出量は、前記第1絶縁層の他方の面と前記他の半導体装置の対向面との間隔未満とされている半導体装置。 - 前記第2絶縁層は、前記第1絶縁層と前記受動素子の側面との間に充填されている請求項1記載の半導体装置。
- 前記埋設部は、前記第1絶縁層を含む複数の絶縁層に埋設されている請求項1又は2記載の半導体装置。
- 前記半導体チップ収容部は、前記第3絶縁層側に開口されていると共に、前記配線層の一部である半導体チップ搭載部によって底面が形成された凹部である請求項1乃至3の何れか一項記載の半導体装置。
- 前記第1絶縁層には前記第1電極パッドの各々と電気的に接続された複数の第2ビア配線が形成され、
前記複数の第2ビア配線は、前記受動素子と前記第1電極パッドとを電気的に接続する経路の一部をなすビア配線を含む請求項1乃至4の何れか一項記載の半導体装置。 - 前記複数の第2ビア配線は、前記半導体チップと前記第1電極パッドとを電気的に接続する経路の一部をなすビア配線を含む請求項5記載の半導体装置。
- 支持体上に第1絶縁層及び金属箔を順次積層する工程と、
前記金属箔をパターニングして配線層を形成する工程と、
前記第1絶縁層を貫通し底面が前記支持体内に達する凹部を形成する工程と、
前記凹部内に受動素子を挿入する工程と、
前記第1絶縁層の一方の面に、前記受動素子の少なくとも一部及び前記配線層を被覆する第2絶縁層を形成する工程と、
前記第2絶縁層に、半導体チップを収容する半導体チップ収容部を形成する工程と、
回路形成面を前記第1絶縁層と反対側に向けて、前記半導体チップ収容部に半導体チップを収容する工程と、
前記第2絶縁層上に、前記半導体チップの前記回路形成面を被覆する第3絶縁層を形成する工程と、
前記受動素子の端面を被覆する絶縁層にビア配線を形成し、前記受動素子の電極を、直接、前記ビア配線を介して、前記受動素子の端面を被覆する絶縁層の一方の面に形成された配線パターンと電気的に接続する工程と、
前記支持体を除去して、前記受動素子の一部を前記第1絶縁層の他方の面から突出させる工程と、を有する半導体装置の製造方法。 - 前記配線層を形成する工程では、前記金属箔をパターニングして半導体チップ搭載部を含む配線層を形成し、
前記半導体チップ収容部を形成する工程では、前記半導体チップ搭載部をエッチングストッパとして前記半導体チップ搭載部上の前記第2絶縁層をエッチングによって除去し、前記半導体チップ搭載部によって底面が形成された凹部である前記半導体チップ収容部を形成する請求項7記載の半導体装置の製造方法。 - 前記配線層を形成する工程では、前記金属箔をパターニングして前記半導体チップ搭載部及び第1電極パッドとなる部分を含む配線層を形成し、
前記支持体を除去した後、前記第1絶縁層に開口部を形成し、前記開口部内に前記配線層の一部を露出させて前記第1電極パッドを形成する請求項8記載の半導体装置の製造方法。
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KR101462770B1 (ko) * | 2013-04-09 | 2014-11-20 | 삼성전기주식회사 | 인쇄회로기판과 그의 제조방법 및 그 인쇄회로기판을 포함하는 반도체 패키지 |
US9209154B2 (en) | 2013-12-04 | 2015-12-08 | Bridge Semiconductor Corporation | Semiconductor package with package-on-package stacking capability and method of manufacturing the same |
US9257396B2 (en) * | 2014-05-22 | 2016-02-09 | Invensas Corporation | Compact semiconductor package and related methods |
DE102014118462A1 (de) | 2014-12-11 | 2016-06-16 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Semiflexible Leiterplatte mit eingebetteter Komponente |
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US9865437B2 (en) | 2014-12-30 | 2018-01-09 | Applied Materials, Inc. | High conductance process kit |
JP2016139648A (ja) * | 2015-01-26 | 2016-08-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
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US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
CN111199935A (zh) | 2018-11-20 | 2020-05-26 | 奥特斯奥地利科技与系统技术有限公司 | 电子封装件和生产电子封装件的方法 |
US20240332104A1 (en) * | 2023-03-28 | 2024-10-03 | At&S Austria Technologie & Systemtechnik Ag | Component Carrier With Reinforcement Layer Structure and Manufacturing Method Using Two Temporary Carriers |
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US7935892B2 (en) * | 2005-04-14 | 2011-05-03 | Panasonic Corporation | Electronic circuit device and method for manufacturing same |
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JP4423285B2 (ja) | 2006-12-19 | 2010-03-03 | 新光電気工業株式会社 | 電子部品内蔵基板および電子部品内蔵基板の製造方法 |
WO2008120755A1 (ja) * | 2007-03-30 | 2008-10-09 | Nec Corporation | 機能素子内蔵回路基板及びその製造方法、並びに電子機器 |
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JP5078021B2 (ja) * | 2008-03-14 | 2012-11-21 | 住友ベークライト株式会社 | 光導波路モジュール、光導波路モジュールの製造方法 |
JP4489821B2 (ja) * | 2008-07-02 | 2010-06-23 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US8963016B2 (en) * | 2008-10-31 | 2015-02-24 | Taiyo Yuden Co., Ltd. | Printed wiring board and method for manufacturing same |
JP5589302B2 (ja) * | 2008-11-12 | 2014-09-17 | 富士通株式会社 | 部品内蔵基板及びその製造方法 |
JP5147678B2 (ja) * | 2008-12-24 | 2013-02-20 | 新光電気工業株式会社 | 微細配線パッケージの製造方法 |
KR101058621B1 (ko) * | 2009-07-23 | 2011-08-22 | 삼성전기주식회사 | 반도체 패키지 및 이의 제조 방법 |
US8742561B2 (en) * | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
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US20120139095A1 (en) * | 2010-12-03 | 2012-06-07 | Manusharow Mathew J | Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same |
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