JP6107698B2 - Switching element driving device - Google Patents

Description

  The present invention relates to a switching element driving device including a level shift circuit.

  For example, when driving two power semiconductor elements of an upper arm and a lower arm that are half-bridge connected, a high-side drive circuit that drives the power semiconductor element of the upper arm, and a low-side drive circuit that drives the power semiconductor element of the lower arm And a driving circuit. At this time, the high-side drive circuit needs a level shift circuit for level-shifting a low-voltage input signal and transmitting it to the high-side driver connected to the gate of the power semiconductor element.

  Such a level shift circuit is described in Patent Document 1, for example. In Patent Document 1, when the reference potential of the high-side floating power supply rises by turning on the first switch element of the level shift circuit, the main terminal of the first switch element is connected via a pull-up resistor. An emphasis circuit is provided to minimize the mask time during which no signal is transmitted due to the current flowing through the parasitic capacitance. The emphasis circuit includes a second switch element that is turned on in response to an increase in the reference potential of the floating power supply. The second switch element is connected in parallel with the pull-up resistor of the first switch element. For this reason, when the second switch element is turned on, the parallel resistance of the on-resistance of the second switch element and the pull-up resistor is connected to the parasitic capacitance of the first switch element. As a result, the time constant due to the parasitic capacitance and the parallel resistance becomes shorter than the time constant due to the parasitic capacitance and the pull-up resistance, and the mask time depending on the time constant can be shortened.

JP 2006-270382 A

  However, in Patent Document 1, when a surge occurs in the power supply of the high-side drive circuit, a displacement current corresponding to the fluctuation of the power supply potential due to the surge flows through the pull-up resistor. Therefore, there is a problem that the potential input to the signal level detection circuit changes according to the displacement current, and as a result, the signal transmission time changes.

  The present invention has been made in view of the above points, and provides a switching element driving device including a level shift circuit capable of suppressing a change in signal transmission time even when a power surge occurs. For the purpose.

In order to achieve the above-described object, a switching element driving apparatus according to the present invention includes:
An input switching element (NHVLS) that is turned on and off according to a control input signal;
On the upstream side of the input switching element, a resistor (RLS) connected in series to the input switching element;
A first power source (VOM) for generating a first voltage (VB) applied to a series circuit of a resistor and an input switching element;
One of a first operation mode for outputting a drive signal for turning on an output switching element (QH), which will be described later, and a second operation mode for stopping output of the drive signal in accordance with the potential after the voltage drop due to the resistor A driver (3) that can be switched to
An output switching element (QH) that is turned on and off according to a drive signal;
A second power source (VHIGH) that is applied to the output switching element and generates a second voltage (VH) that is higher than the first voltage;
A displacement current circuit (2) through which a current (IPP2, INN2) corresponding to a displacement current (ICPLS) flowing in the series circuit flows when a surge occurs in the first voltage;
By connecting the displacement current circuit between the resistance in the series circuit and the input switching element, the displacement current (ICPLS) is configured to flow between the displacement current circuit and the input switching element, bypassing the resistance. It is characterized by that.

  In the configuration described above, a level shift circuit is configured by a series circuit of an input switching element (NHVLS) and a resistor (RLS). When a surge occurs in the first voltage (VB), a displacement current that charges and discharges the parasitic capacitance (CPLS) of the input switching element (NHVLS) flows. When this displacement current flows through the resistor (RLS), the resistance Since the potential change time after the voltage drop due to (RLS) fluctuates, the signal transmission time changes.

  Therefore, in the present invention, when a surge occurs in the first voltage (VB), a displacement current circuit (IPP2, INN2) corresponding to a displacement current (ICPLS) flowing in the series circuit flows due to the surge ( 2), and the displacement current circuit (2) was connected between the resistor (RLS) and the input switching element (NHVLS) in the series circuit. As a result, the displacement current (ICPLS) that charges and discharges the parasitic capacitance (CPLS) of the input switching element (NHVLS) bypasses the resistance (RLS), and the displacement current circuit (2) and the input switching element (NHVLS) It begins to flow between. Therefore, even when a displacement current (ICPLS) occurs, it is possible to suppress the influence on the potential after the voltage drop due to the resistance (RLS), and it is possible to reduce a change in signal transmission time.

  The reference numerals in the parentheses merely show an example of a correspondence relationship with a specific configuration in an embodiment described later in order to facilitate understanding of the present invention, and are intended to limit the scope of the present invention. Not intended.

  Further, the technical features described in the claims of the claims other than the features described above will become apparent from the description of embodiments and the accompanying drawings described later.

1 is a configuration diagram illustrating an overall configuration of a switching element driving apparatus 1 according to an embodiment. It is explanatory drawing for demonstrating the problem which may occur when the surge which raises power supply potential VB generate | occur | produces when the input switching element NHVLS is turned on by the pulse signal according to the falling edge of a control input signal. It is explanatory drawing for demonstrating the problem which may occur when the surge which raises power supply potential VB generate | occur | produces when the input switching element NHVLS is turned on by the pulse signal according to the rising edge of a control input signal, and is turned off after that. . It is explanatory drawing for demonstrating the problem which may occur when the surge which reduces the power supply potential VB generate | occur | produces when the input switching element NHVLS is turned on by the pulse signal according to the falling edge of a control input signal. FIG. 6 is an explanatory diagram for explaining a problem that may occur when a surge that lowers the power supply potential VB occurs when the input switching element NHVLS is turned on by a pulse signal corresponding to the rising edge of the control input signal and then turned off. is there. It is explanatory drawing for demonstrating the effect of the current detection circuit when the surge which raises power supply potential VB generate | occur | produces. It is explanatory drawing for demonstrating the effect of the current detection circuit when the surge which reduces the power supply potential VB generate | occur | produces. It is an equivalent circuit diagram which shows the equivalent circuit at the time of charge of an input switching element and a 2nd switching element. It is a graph which shows the voltage characteristic of parasitic capacitance. It is the block diagram which showed the structure of the switching element drive device by a 1st modification. It is the block diagram which showed the structure of the switching element drive device by the 2nd modification. It is the block diagram which showed the structure of the switching element drive device by the 3rd modification.

  Hereinafter, a switching element driving device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an overall configuration of a switching element driving apparatus 1 according to the present embodiment.

  In FIG. 1, power semiconductor elements QH and QL as switching elements are made of, for example, IGBTs or MOSFETs and are half-bridge connected. The switching element driving apparatus 1 includes a high side driving circuit that drives the high side power semiconductor element QH connected to the upper arm, and a low side driving circuit that drives the low side power semiconductor element QL connected to the lower arm. The high-side power semiconductor element QH and the low-side power semiconductor element QL are alternately driven on and off by the high-side drive signal VGH and the low-side drive signal VGL output from the high-side drive circuit and the low-side drive circuit. The magnitude of the drive current for the load 5 connected between the high-side power semiconductor element QH and the low-side power semiconductor element QL is controlled by the ratio between the on and off times.

  The high-side power semiconductor element QH is connected to a high-potential power supply VHIGH that generates a potential VH higher than the power supply VOM that supplies power to the high-side drive circuit. Further, in order to stabilize the high potential VH generated by the high potential power supply VHIGH, an electric field capacitor EC is connected in parallel to the high potential power supply VHIGH. Thereby, a sufficiently high drive current can be supplied to the load 5. In FIG. 1, the resistance ESR indicates the internal resistance of the electric field capacitor EC.

  The high-side driver 3 of the high-side drive circuit operates using the potential difference between the power supply potential VB supplied from the power supply VOM via the diode BSD and the floating potential VSS as an operating voltage. The high-side drive circuit includes a bootstrap capacitor CBS, and is configured such that the potential difference between the power supply potential VB and the floating potential VSS is substantially constant regardless of changes in the floating potential VSS. That is, the power supply line of the floating potential VSS is connected between the high-side power semiconductor element QH and the low-side power semiconductor element QL, and the floating potential VSS is changed according to the on / off states of the power semiconductor elements QH and QL. Change. Specifically, when the high side power semiconductor element QH is off and the low side power semiconductor element QL is on, the floating potential VSS is approximately 0V. On the other hand, when the high-side power semiconductor element QH is on and the low-side power semiconductor element QL is off, the floating potential VSS is substantially the high potential VH generated by the high potential power supply VHIGH. In this way, even if the floating potential VSS changes, the potential difference between the power supply potential VB and the floating potential VSS is kept almost constant, so that it is not necessary to make each element constituting the high-side driver 3 have a high breakdown voltage. Become.

  Hereinafter, the configuration of the high-side drive circuit will be described in detail with reference to FIG. Note that the low-side drive circuit is composed of only the low-side driver 4 because there is no need for level shift. The low side driver 4 is supplied with a control input signal for turning on and off the low side power semiconductor element QL directly from a control circuit (not shown).

  The high side drive circuit detects an edge (rising edge and falling edge) of a control input signal for turning on the high side power semiconductor element QH from the control circuit, and outputs an extremely short pulse signal ( (Not shown). When the pulse signal output from the edge detection circuit is applied to the gate terminal of the input switching element NHVLS, the input switching element NHVLS is turned on. Thus, since the level change of the control input signal is detected and the input switching element NHVLS is turned on for an extremely short time, the power consumption can be reduced.

  The input switching element NHVLS is configured by, for example, an N-channel high voltage MOSFET. The drain terminal of the input switching element NHVLS is connected to the power supply potential VB of the high side drive circuit via the pull-up resistor RLS. The source terminal of the input switching element NHVLS is connected to the ground via the constant current circuit 6. The pull-up resistor RLS, the input switching element NHVLS, and the constant current circuit 6 constitute a level shift circuit. Note that the input switching element NHVLS has a parasitic capacitance CPLS.

  A branch line branched from a connection line between the pull-up resistor RLS and the input switching element NHVLS is connected to the input terminal of the inverter INV. Therefore, when the input switching element NHVLS is off, the input potential VIN to the inverter INV is higher than the threshold potential, and the output potential VOUT of the inverter INV is at a low level. When the input switching element NHVLS is turned on and the input potential VIN to the inverter INV (the potential after the voltage drop of the pull-up resistor RLS) falls below the threshold potential, the output potential VOUT of the inverter INV changes to a high level.

  The high side driver 3 has a flip-flop circuit function, and every time the inverter INV outputs a high level output potential VOUT, the high side drive signal VGH output to the high side power semiconductor element QH is turned on → off → on → Turn off and invert.

  The above is the configuration of a known high-side drive circuit for the high-side power semiconductor element QH. Here, problems that may occur in such a known high-side drive circuit will be described with reference to FIGS.

  First, with reference to FIG. 2, a case will be described in which a surge that raises the power supply potential VB occurs when the input switching element NHVLS is turned on by a pulse signal corresponding to the falling edge of the control input signal.

  As shown in FIG. 2, when the signal level input to the gate terminal of the input switching element NHVLS changes from the low level to the high level, the input switching element NHVLS is turned on. Then, the current IRLS starts to flow through the pull-up resistor RLS and the input switching element NHVLS toward a constant current defined by the constant current circuit 6 connected between the source terminal of the input switching element NHVLS and the ground. The current IRLS increases from 0, but as the current IRLS increases, the input potential VIN of the inverter INV decreases from the power supply potential VB. When the input potential VIN drops below the threshold potential of the inverter INV, the output potential VOUT of the inverter INV changes from the low level to the high level.

The relationship between the input potential VIN and the current IRLS flowing through the pull-up resistor RLS at this time can be expressed by the following Equation 1.
(Equation 1) VB-VIN = IRLS / RLS
However, when the power supply potential VB fluctuates due to a surge while the current IRLS is increasing, and this is a surge that increases the power supply potential VB, the pull-up resistor RLS has an input switching function as shown in FIG. A displacement current ICPLS that charges the parasitic capacitance CPLS of the element NHVLS flows. As described above, when the displacement current ICPLS flows in the pull-up resistor RLS in addition to the current IRLS, the input potential VIN, which is the potential after the voltage drop by the pull-up resistor RLS, is changed as shown in FIG. Compared to the case where the ICPLS does not flow, it falls in a shorter time. As a result, the time until the input potential VIN falls below the threshold voltage of the inverter INV is shortened, and the signal transmission time (time from the signal change of the control input signal to the output change of the inverter INV) in the high-side drive circuit is shorter than usual. Will also be shorter.

  Note that a surge that fluctuates the power supply potential VB may occur in a situation as described below. For example, when the temperature is low, the internal resistance ESR of the electric field capacitor EC is relatively high. In such a situation, when the high side power semiconductor element QH is turned on or off, a surge may occur in the power supply line of the high side power semiconductor element QH. Thus, when a surge occurs in the power supply line of the high-side power semiconductor element QH, the surge may propagate to the power supply potential VB via the floating potential VSS.

  Next, with reference to FIG. 3, a case will be described in which a surge that raises the power supply potential VB occurs when the input switching element NHVLS is turned on and then turned off by a pulse signal corresponding to the rising edge of the control input signal. .

  As shown in FIG. 3, when the pulse signal from the edge detection circuit ends and the signal level input to the gate terminal of the input switching element NHVLS changes from the high level to the low level, the input switching element NHVLS is turned off. Then, the current IRLS flowing through the pull-up resistor RLS starts to decrease. As the current IRLS decreases, the input potential VIN of the inverter INV increases from a potential that is substantially close to the ground potential toward the power supply potential VB. When the input potential VIN exceeds the threshold potential of the inverter INV, the output potential VOUT of the inverter INV changes from the high level to the low level.

  However, when a surge that raises the power supply potential VB occurs while the current IRLS is decreasing, as shown in FIG. 3, the pull-up resistor RLS has a displacement current that charges the parasitic capacitance CPLS of the input switching element NHVLS. ICPLS will flow. The displacement current ICPLS acts in a direction that cancels the decrease in the current IRLS, so that the rising of the input potential VIN of the inverter INV is delayed as compared with the case where the displacement current ICPLS does not flow. As a result, the time until the input potential VIN exceeds the threshold voltage of the inverter INV becomes longer, and the signal transmission time becomes longer than usual.

  Next, with reference to FIG. 4, a case will be described in which a surge that lowers the power supply potential VB occurs when the input switching element NHVLS is turned on by a pulse signal corresponding to the falling edge of the control input signal.

  Immediately after the input switching element NHVLS is turned on, if a surge that lowers the power supply potential VB occurs while the current IRLS is increasing, as shown in FIG. 4, the pull-up resistor RLS has an input switching element NHVLS. Displacement current ICPLS discharged from the parasitic capacitance CPLS of the current flows. The displacement current ICPLS acts in a direction that cancels the increase in the current IRLS, so that the falling of the input potential VIN of the inverter INV is delayed as compared with the case where the displacement current ICPLS does not flow. As a result, the time until the input potential VIN falls below the threshold voltage of the inverter INV becomes longer, and the signal transmission time becomes longer than usual.

  Finally, referring to FIG. 5, a case where a surge that lowers the power supply potential VB occurs when the input switching element NHVLS is turned on and then turned off by a pulse signal corresponding to the rising edge of the control input signal will be described. To do.

  Immediately after the input switching element NHVLS is turned off, if a surge that lowers the power supply potential VB occurs while the current IRLS is decreasing, as shown in FIG. 5, the pull-up resistor RLS has the input switching element NHVLS A displacement current ICPLS discharged from the parasitic capacitance CPLS flows. Since the displacement current ICPLS acts in a direction to increase the decrease in the current IRLS, the rising of the input potential VIN of the inverter INV is faster than when the displacement current ICPLS does not flow. As a result, the time until the input potential VIN exceeds the threshold voltage of the inverter INV is shortened, and the signal transmission time is shorter than usual.

  As described above, the signal transmission time in the level shift circuit may change when the power supply potential VB is affected by the surge. Therefore, it is necessary to set a dead time so that the high-side power semiconductor element QH and the low-side power semiconductor element QL are not turned on at the same time. This dead time is further considered in consideration of a change in signal transmission time of the level shift circuit. It becomes necessary to set a long time. However, the longer the dead time is set, the worse the controllability of the load 5 is.

  Therefore, in the present embodiment, as shown in FIG. 1, when the power supply potential VB fluctuates due to a surge, a displacement current circuit 2 through which a current corresponding to the above-described displacement current ICPLS flows is provided. The pull-up resistor RLS and the input switching element NHVLS were connected. By adopting such a configuration, it is possible to cause a current corresponding to the displacement current ICPLS to flow between the displacement current circuit 2 and the input switching element NHVLS. Therefore, even when a displacement current ICPLS is generated due to a surge, the displacement current ICPLS can be suppressed from flowing through the pull-up resistor RLS. As a result, the influence on the rise and fall times of the input potential VIN of the inverter INV due to the occurrence of a surge can be suppressed, and the change in signal transmission time can be reduced.

  Hereinafter, the displacement current circuit 2 will be described in detail.

  As shown in FIG. 1, the displacement current circuit 2 includes a first switching element NHVP configured to have the same characteristics as the input switching element NHVLS. For example, when the input switching element NHVLS is configured by an N-channel high breakdown voltage MOSFET, the first switching element NHVP is also configured by an N-channel high breakdown voltage MOSFET having the same material and the same element size. Therefore, the first switching element NHVP has the same parasitic capacitance CPP as the parasitic capacitance CPLS of the input switching element NHVLS. Note that the gate terminal of the first switching element NHVP is connected to the ground, and the first switching element NHVP is always kept off.

  The drain terminal of the first switching element NHVP is connected to one end of the first resistor RP1. The first resistor RP1 has the same resistance value as the pull-up resistor RLS. The other end of the first resistor RP1 is connected to the power supply potential VB of the high side drive circuit via the transistor PP1. The transistor PP1 is made of a P-channel MOSFET, has a body diode DPP, and forms a current mirror circuit with the transistor PP2. Therefore, when a current flows through the transistor PP1, the same current as that flows through the transistor PP2. The resistor RP2 is a pull-up resistor for the gate voltages of the transistors PP1 and PP2. The drain terminal of the transistor PP2 is connected to a connection line between the pull-up resistor RLS and the input switching element NHVLS.

  Further, the displacement current circuit 2 includes a second switching element NHVN, and the second switching element NHVN is configured to have the same characteristics as the input switching element NHVLS, like the first switching element NHVP. ing. Therefore, the second switching element NHVN also has the same parasitic capacitance CPN as the parasitic capacitance CPLS of the input switching element NHVLS. The gate terminal of the second switching element NHVN is also connected to the ground, and the second switching element NHVN is always kept off.

  The drain terminal of the second switching element NHVN is connected to one end of the second resistor RN1. The second resistor RN1 has the same resistance value as that of the pull-up resistor RLS. The other end of the second resistor RN1 is connected to the floating potential VSS via the transistor NN1. The transistor NN1 is composed of an N-channel MOSFET, has a body diode DPN, and forms a current mirror circuit with the transistor NN2. Accordingly, when a current flows through the transistor NN1, the same current as that flows through the transistor NN2. The resistor RN2 is a pull-down resistor for the gate voltages of the transistors NN1 and NN2. The drain terminal of the transistor NN2 is connected to a connection line between the pull-up resistor RLS and the input switching element NHVLS.

  The operation and effect of the displacement current circuit 2 configured as described above will be described with reference to FIGS. FIG. 6 is an explanatory diagram for explaining the operation and effect of the displacement current circuit 2 when a surge that raises the power supply potential VB occurs. First, a case where a surge for increasing the power supply potential VB has occurred will be described with reference to FIG.

  When a surge that raises the power supply potential VB occurs, as shown in FIG. 6, a displacement current ICPP that charges the parasitic capacitance CPP of the first switching element NHVP flows. As described above, the parasitic capacitance CPP of the first switching element NHVP is equal to the parasitic capacitance CPLS of the input switching element NHVLS. The first resistor RP1 has the same resistance value as the pull-up resistor RLS. Therefore, the displacement current ICPP is substantially equal to the displacement current ICPLS that charges the parasitic capacitance CPLS of the input switching element NHVLS described with reference to FIGS.

  Since the displacement current ICPP flows through one transistor PP1 constituting the current mirror circuit, the same displacement current IPP2 also flows through the other transistor PP2. Since the drain terminal of the transistor PP2 is connected to the connection line between the pull-up resistor RLS and the input switching element NHVLS, the displacement current IPP2 flows from the transistor PP2 toward the input switching element NHVLS. Then, the parasitic capacitance CPLS of the input switching element NHVLS is charged by the displacement current IPP2. Since the displacement current IPP2 is substantially equal to the displacement current ICPLS, the displacement current substantially bypasses the pull-up resistor RLS. As a result, even if a surge that raises the power supply potential VB occurs, it is possible to suppress displacement current due to the surge from flowing through the pull-up resistor RLS.

  At the same time, a displacement current ICPN that charges the parasitic capacitance CPN of the second switching element NHVN flows from the floating potential VSS toward the second switching element NHVN. When the displacement current ICPN flows, the current mirror circuit constituted by the transistors NN1 and NN2 is turned off, and the displacement current ICPN flows through the body diode DPN of the transistor NN1. Thereby, the parasitic capacitance CPN of the second switching element NHVN is charged so as to be in the same charging state as the parasitic capacitance CPLS of the input switching element NHVLS.

  The parasitic capacitance CPLS of the input switching element NHVLS is charged by the displacement current from the power supply potential VB, and the parasitic capacitance CPN of the second switching element NHVN is charged by the displacement current ICPN from the floating potential VSS. As described above, the reason why the parasitic capacitance CPN of the second switching element NHVN and the parasitic capacitance CPLS of the input switching element NHVLS are in substantially the same charged state regardless of the connection destination is shown in FIGS. It explains using.

FIG. 8 shows an equivalent circuit during charging of the input switching element NHVLS and the second switching element NHVN. In FIG. 8, the displacement currents charging the respective parasitic capacitances CPLS and CPN are generated due to the surges of the power supply potential VB and the floating potential VSS, and the forward voltage of the body diode of the transistor NN1 is considered to be almost constant. Each displacement current can be obtained as a solution of the differential equation of Equation 2 below.

However, the definition of each symbol is as follows.
VCPN: voltage VCPLS applied to the parasitic capacitance CPN of the second switching element NHVN: voltage ICPN applied to the parasitic capacitance CPLS of the input switching element NHVLS: current ICPLS flowing in the parasitic capacitance CPN of the second switching element NHVN: input Current flowing in parasitic capacitance CPLS of switching element NHVLS

Further, the power supply potential VB and the floating potential VSS are defined as follows.
VB = VB0 + ΔVBB
VSS = VSS0 + ΔVSS
VB0, VSS0: Potential ΔVBB, ΔVSS: No potential change due to surge

  Here, the bootstrap capacitor CBS keeps the potential difference between the power supply potential VB and the floating potential VSS constant even when a surge occurs. Therefore, the change amount ΔVBB of the power supply potential VB is equal to the change amount ΔVSS of the floating potential VSS. The second resistor RN1 and the pull-up resistor RLS are configured to have the same resistance value. Furthermore, as shown in FIG. 9, the parasitic capacitance has voltage dependency, but the power supply potential VB and the floating potential VSS (for example, 200 V or more) when the floating potential VSS is high depend on the voltage. Without, it becomes almost constant. Therefore, when there is no surge, the parasitic capacitance CPN (VSS0) of the second switching element NHVN is equal to the parasitic capacitance CPLS (VB0) of the input switching element NHVLS. When these are applied to the differential equation, the conclusion that the displacement current ICPN (t) = ICPLS (t) is derived. Thus, since the displacement currents are equal, the charged states of the parasitic capacitors CPN and CPLS charged by the displacement currents are also equal.

  Next, a case where a surge that lowers the power supply potential VB occurs will be described with reference to FIG.

  When a surge that lowers the power supply potential VB occurs, as shown in FIG. 7, the displacement current ICPP due to the discharge from the parasitic capacitance CPP of the first switching element NHVP and the parasitic capacitance CPN of the second switching element NHVN Displacement current ICPN due to discharge flows. As described above, the parasitic capacitance CPN of the second switching element NHVN is equal to the parasitic capacitance CPLS of the input switching element NHVLS. The second resistor RN1 has the same resistance value as the pull-up resistor RLS. Therefore, the displacement current ICPN becomes substantially equal to the displacement current ICPLS discharged from the parasitic capacitance CPLS of the input switching element NHVLS described with reference to FIGS.

  Since the displacement current ICPN flows through one transistor NN1 constituting the current mirror circuit, the same displacement current INN2 also flows through the other transistor NN2. Since the drain terminal of the transistor NN2 is connected to the connection line between the pull-up resistor RLS and the input switching element NHVLS, the displacement current INN2 flows from the input switching element NHVLS toward the transistor NN2. Then, the displacement current INN2 discharges the parasitic capacitance CPLS of the input switching element NHVLS. In this case, since the displacement current INN2 is substantially equal to the displacement current ICPLS, the displacement current substantially bypasses the pull-up resistor RLS. As a result, even when a surge that lowers the power supply potential VB occurs, it is possible to suppress the displacement current due to the surge from flowing through the pull-up resistor RLS.

  At the same time, a displacement current ICPP due to the discharge from the parasitic capacitance CPP of the first switching element NHVP flows. However, at this time, the current mirror circuit constituted by the transistors PP1 and PP2 is OFF, and the displacement current ICPP flows through the body diode DPP of the transistor PP1. Thereby, the parasitic capacitance CPP of the first switching element NHVP is discharged so as to be in the same charge state as the parasitic capacitance CPLS of the input switching element NHVLS.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. .

  For example, in the above-described embodiment, the transistors constituting the current mirror circuit are MOSFETs. However, as shown in FIG. 10, the current mirror circuit may be constituted using bipolar transistors. However, in the case of a bipolar transistor, since there is no body diode between the collector and the emitter, it is necessary to connect the diodes DP1 and DN1 in parallel to the transistors QP1 and QN1. Even when such a circuit configuration is employed, the same operational effects as those of the above-described embodiment can be obtained.

  Further, as shown in FIG. 11, in the high side drive circuit, two systems of a system for turning on the high side power semiconductor element QH and a system for turning off may be provided. In this case, a pulse signal for turning on the high-side power semiconductor element QH is given to the first input switching element NHVLS1, and a pulse signal for turning off the high-side power semiconductor element QH to the second input switching element NHVLS2. Is given. The first and second switching elements NHVP and NHVN are preferably shared with the first and second input switching elements NHVLS1 and NHVLS2, and only the current mirror circuit has two systems. As a result, the circuit configuration can be simplified.

  Further, as shown in FIG. 12, a delay circuit for delaying the operation of the level shift circuit may be provided. That is, there is some delay time for the displacement current circuit 2 to operate in order to cancel the displacement current flowing through the pull-up resistor RLS of the level shift circuit. Therefore, as a delay circuit, a capacitor CLS is connected in parallel with the pull-up resistor RLS to delay the operation of the level shift circuit. As a result, the timing at which the currents IPP2 and INN2 corresponding to the displacement current flow through the displacement current circuit 2 and the timing at which the displacement current ICPLS flows through the series circuit of the pull-up resistor RLS and the input switching element NHVLS can be made closer. Therefore, the displacement current circuit 2 can cancel the displacement current flowing through the pull-up resistor RLS with higher accuracy.

DESCRIPTION OF SYMBOLS 1 Switching element drive device 2 Displacement current circuit 3 High side driver 4 Low side driver 5 Load NHVLS Input switching element RLS Pull-up resistance INV Inverter QH High side power semiconductor element

Claims (7)

An input switching element (NHVLS) that is turned on and off according to a control input signal;
On the upstream side of the input switching element, a resistor (RLS) connected in series to the input switching element;
A first power supply (VOM) for generating a first voltage (VB) applied to a series circuit of the resistor and the input switching element;
A first operation mode for outputting a drive signal for turning on an output switching element (QH), which will be described later, and a second operation mode for stopping the output of the drive signal in accordance with the potential after the voltage drop by the resistor. A driver (3) that can be switched to one of the following:
An output switching element (QH) that is turned on and off according to the drive signal;
A second power source (VHIGH) applied to the output switching element to generate a second voltage (VH) higher than the first voltage;
A displacement current circuit (2) through which a current (IPP2, INN2) corresponding to a displacement current (ICPLS) flowing in the series circuit flows when a surge occurs in the first voltage;
By connecting the displacement current circuit between the resistance and the input switching element in the series circuit, the displacement current bypasses the resistance and is between the displacement current circuit and the input switching element. The switching element driving device is configured to flow at In the displacement current circuit, when the first voltage increases due to the surge, and thereby the displacement current that charges the parasitic capacitance (CPLS) of the input switching element flows, a current corresponding to the displacement current ( IPP2) has a first circuit through which a current corresponding to the displacement current flows from the first circuit to the input switching element, thereby charging the parasitic capacitance of the input switching element,
The displacement current circuit further has a current corresponding to the displacement current when the first voltage is lowered by the surge, and the displacement current discharged from the parasitic capacitance of the input switching element flows. INN2) has a second circuit, and when a current corresponding to the displacement current flows from the input switching element to the second circuit, the parasitic capacitance of the input switching element is discharged. The switching element driving device according to claim 1. The first circuit includes:
A first switching element (NHVP) configured to have the same characteristics as the input switching element and maintained in an off state at all times;
A first resistor (RP1) connected in series with the first switching element and having the same resistance value as the resistor;
A current (ICPP) flowing through a first series circuit of the first resistor and the first switching element and a first current mirror circuit that generates the same current (IPP2);
The first voltage is applied to the first series circuit of the first resistor and the first switching element, and the surge that increases the first voltage causes the first series circuit to When a current (ICPP) for charging a parasitic capacitance (CPP) of the first switching element flows, a current (IPP2) generated by the first current mirror circuit is caused to flow to the input switching element. The switching element driving device according to claim 2. The second circuit includes:
A second switching element (NHVN) that is configured to have the same characteristics as the input switching element and that is always maintained in an off state;
A second resistor (RN1) connected in series with the second switching element and having the same resistance value as the resistor;
A current (ICPN) that flows through a second series circuit of the second resistor and the second switching element, and a second current mirror circuit that flows the same current (INN2),
When a surge that reduces the first voltage occurs and a current (ICPN) discharged from the parasitic capacitance (CPN) of the second switching element flows in the second series circuit, the second 4. The switching element driving device according to claim 2, wherein the current mirror circuit passes a current (INN2) corresponding to a displacement current discharged from the parasitic capacitance (CPLS) of the input switching element.   In order to match the timing at which a current corresponding to a displacement current flows in the displacement current circuit and the timing at which a displacement current flows in a series circuit of the resistor and the input switching element, a series circuit of the resistor and the input switching element 5. The switching element driving device according to claim 1, further comprising a delay circuit that delays a timing at which the displacement current flows.   6. The switching element driving device according to claim 5, wherein the delay circuit includes a capacitor (CLS) connected in parallel to the resistor.   Two series circuits of the resistor and the input switching element are provided, one series circuit is used to switch the driver to the first operation mode, and the other series circuit connects the driver to the second mode. 7. The switching element driving device according to claim 1, wherein the switching element driving device is used to switch to the operation mode.

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