JP6106951B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A nitride semiconductor such as GaN, AlN, InN, or a mixed crystal material thereof has a wide band gap, and is used as a high-power electronic device or a short-wavelength light-emitting device. For example, GaN, which is a nitride semiconductor, has a band gap of 3.4 eV, which is larger than the Si band gap of 1.1 eV and the GaAs band gap of 1.4 eV.

  As such a high-power electronic device, there is a field effect transistor (FET), in particular, a high electron mobility transistor (HEMT). HEMTs using such nitride semiconductors are used in high power / high efficiency amplifiers, high power switching devices, and the like. For example, in a HEMT using AlGaN as an electron supply layer and GaN as a traveling layer, piezopolarization and spontaneous polarization occur in AlGaN due to strain due to a difference in lattice constant between AlGaN and GaN, and a high concentration of 2DEG (Two-Dimensional Electron Gas: Two-dimensional electron gas) is generated. For this reason, the operation | movement in a high voltage is possible and it can use for the high voltage | pressure-resistant electric power device in a highly efficient switching element, an electric vehicle use, etc.

  By the way, in HEMT using a nitride semiconductor, it is calculated | required that it is normally off from viewpoints, such as fail safe. However, in a HEMT using a nitride semiconductor, a large number of electrons are present in 2DEG, so that even when no voltage is applied to the gate electrode, normally-on current tends to flow. For this reason, there is a method of forming a p-type semiconductor layer on the electron supply layer in the region where the gate electrode is formed in order to make the HEMT using such a nitride semiconductor normally off. Specifically, a GaN layer is formed as an electron transit layer, an AlGaN layer is formed as an electron supply layer, and a p-GaN layer is formed on the AlGaN layer, thereby eliminating 2DEG directly under the p-GaN layer, It is a way to turn off Mary.

JP 2002-359256 A

Yasuhiro Uemoto, Masahiro Hikita, Hiroaki Ueno, Hisayoshi Matsuo, Hidetoshi Ishida, Manabu Yanagihara, Tetsuzo Ueda, Tsuyoshi Tanaka, and Daisuke Ueda, "Gate Injection Transistor (GIT) -A Normally-off AlGaN / GaN Power Transistor Using Conductivity Modulation", IEEE TRANSACTIONS ON ELECTRON DEVICES, 54, 3393 (2007). H. Marchand, XH Wu, JP Ibbetson, PT Fini, P. Kozodoy, S. Keller, JS Speck, SP DenBaars, and UK Mishra, "Microstructure of GaN laterally overgrown by metalorganic chemical vapor deposition", Appl. Phys. Lett. 73, 747 (1998). Tsvetanka S. Zheleva, Ok-Hyun Nam, Michael D. Bremser, and Robert F. Davis, "Dislocation density reduction via lateral epitaxy in selectively grown GaN structures", Appl. Phys. Lett. 71, 2472 (1997).

  By the way, when a p-type layer such as a p-GaN layer is formed, generally, Mg is doped as an impurity element to be p-type. However, since the activation rate of Mg is as low as about 1%, the hole concentration is low. It is difficult to form a high p-GaN. Further, when the concentration of Mg, which is an impurity element that becomes a p-type, is increased, Mg diffuses to the interface between the electron transit layer and the electron supply layer, 2DEG disappears more than necessary, and the on-resistance is reduced. May be higher.

  In addition, as a method for setting the energy level at the AlGaN / GaN hetero interface above the Fermi level, a method for increasing the thickness of the p-GaN layer, a method for reducing the AlGaN layer as the electron supply layer, There is a method of reducing the composition ratio. However, when the p-GaN layer is formed thick, the distance between the gate electrode formed on the p-GaN layer and the AlGaN / GaN hetero interface serving as a channel becomes long, and pinch-off defects are likely to occur. Problems arise. Further, in the method of thinning the AlGaN layer that is the electron supply layer and the method of reducing the Al composition ratio, the concentration of 2DEG between the gate and the drain is lowered, and the on-resistance is increased.

  Therefore, in a semiconductor device using a nitride semiconductor, there is a need for a semiconductor device having a low on-resistance that is normally off even when the p-type layer is thin and a method for manufacturing the semiconductor device.

According to one aspect of the present embodiment, a buffer layer formed on a substrate, a growth control layer having an opening in a predetermined region formed of an insulating material on the buffer layer, and the growth A first semiconductor layer formed on a region where the opening of the control layer and the growth control layer is formed; a second semiconductor layer formed on the first semiconductor layer; And a third semiconductor layer of a first conductivity type formed in a region immediately above the opening of the growth control layer on the second semiconductor layer, wherein the first conductivity type is p The buffer layer is made of a material containing AlN, the first semiconductor layer is made of a material containing GaN, and the second semiconductor layer is a material containing AlGaN. It is formed by the third semiconductor layer, including the GaN Is formed of a material, the p-type and comprising Mg as an impurity element and is doped, the growth controlling layer the opening to become the first formed on a region of the semiconductor layer and the second of The density of threading dislocations occurring in the semiconductor layer is higher than the density of threading dislocations occurring in the first semiconductor layer and the second semiconductor layer formed on the growth control layer. Features.
According to another aspect of the present embodiment, a buffer layer formed on a substrate and a growth control layer having an opening in a predetermined region formed of an insulating material on the buffer layer. A first semiconductor layer formed on the growth control layer and a region where the opening of the growth control layer is formed, and a second semiconductor formed on the first semiconductor layer And a p-type third semiconductor layer formed in a region immediately above the opening of the growth control layer on the second semiconductor layer, and the buffer layer is made of AlN. The first semiconductor layer is formed of a material containing GaN, the second semiconductor layer is formed of a material containing AlGaN, and the third semiconductor layer is formed of a material containing AlGaN. the impurity element which serves as a p-type is doped The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region to be the opening of the growth control layer is formed on the growth control layer. Further, the density is higher than the density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer .

Further, according to another aspect of the present embodiment, a step of forming a buffer layer on the substrate, and a growth control layer having an opening in a predetermined region by an insulator material on the buffer layer. Forming a first semiconductor layer on the growth control layer and a region where the opening of the growth control layer is formed, and forming a second semiconductor layer on the first semiconductor layer. Forming a semiconductor layer; and forming a third semiconductor layer of the first conductivity type in a region immediately above the opening of the growth control layer on the second semiconductor layer. The first conductivity type is p-type, the buffer layer is made of a material containing AlN, and the first semiconductor layer is made of a material containing GaN, The second semiconductor layer is made of a material containing AlGaN. It said third semiconductor layer is formed of a material containing GaN, Mg as an impurity element which serves as the p-type is characterized in that it is doped.
Further, according to another aspect of the present embodiment, a step of forming a buffer layer on the substrate, and a growth control layer having an opening in a predetermined region by an insulator material on the buffer layer. Forming a first semiconductor layer on the growth control layer and a region where the opening of the growth control layer is formed, and forming a second semiconductor layer on the first semiconductor layer. Forming a semiconductor layer, and forming a third semiconductor layer doped with a p-type impurity element in a region immediately above the opening of the growth control layer on the second semiconductor layer a step of, have a, the buffer layer is formed of a material containing AlN, the first semiconductor layer is formed of a material containing GaN, the second semiconductor layer, AlGaN JP that you have been formed of a material containing To.

  According to the disclosed semiconductor device and semiconductor device manufacturing method, the p-type layer is normally off even when the p-type layer is thin, and the on-resistance can be lowered.

Explanatory diagram of threading dislocations generated in semiconductor devices TEM image of nitride laminate (1) TEM image of nitride stack (2) Concentration distribution diagram in the depth direction in the nitride laminate obtained by SIMS (1) Concentration distribution diagram in the depth direction in the nitride laminate obtained by SIMS (2) Structure diagram of the semiconductor device in the first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Structure diagram of semiconductor device according to second embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Explanatory drawing of the semiconductor device in 3rd Embodiment Circuit diagram of the PFC circuit in the third embodiment Circuit diagram of power supply device according to third embodiment Structure diagram of high-power amplifier according to third embodiment

  Modes for carrying out the invention will be described below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
When a p-type layer is formed in a HEMT using a nitride semiconductor, the diffusion amount and diffusion depth of impurity elements such as Mg that become p-type depend on the crystal state in the electron supply layer and the electron transit layer. This has been obtained as a finding by the inventors' research.

This will be specifically described based on a HEMT that is a semiconductor device using the nitride semiconductor having the structure shown in FIG. This semiconductor device is formed by laminating a buffer layer 921, an electron transit layer 923 made of GaN, and an electron supply layer 924 made of AlGaN on a substrate 910 made of silicon or the like. A p-type layer 925 made of -GaN is formed. Further, on the electron supply layer 924, the source electrode 942 and drain electrode 943 are formed on the p-type layer 925, the gate electrode 941 is formed so as to cover the whole SiO ₂ or the like A protective film 950 is formed of the insulator. In such a HEMT, in the electron transit layer 923, 2DEG 923a is generated in the vicinity of the interface between the electron supply layer 924 and the electron transit layer.

  The buffer layer 921, the electron transit layer 923, the electron supply layer 924, and the p-type layer 925 are formed by epitaxial growth on the substrate 910. At this time, in the electron transit layer 923, the electron supply layer 924, and the like, Threading dislocations 920 are generated. The threading dislocation 920 generated in the electron transit layer 923 and the electron supply layer 924 is generated due to a difference in lattice constant or a thermal expansion coefficient between silicon or the like forming the substrate 910 and GaN or the like. . That is, an internal stress is generated in the electron transit layer 923 and the like due to a difference in lattice constant and a coefficient of thermal expansion between silicon forming the substrate 910 and GaN, etc. In order to relieve the internal stress thus generated. Many threading dislocations are generated in the electron transit layer 923 and the like.

  In addition, although the p-type layer 925 is doped with Mg as an impurity element, Mg tends to diffuse along threading dislocations 920 as will be described later, and is generated in the electron transit layer 923 due to the diffusion of Mg. A part or all of the 2DEG 923a is lost. As described above, a part or all of the 2DEG 923a in the electron transit layer 923 disappears, and the on-resistance becomes high. In general, the p-type layer 925 is formed by forming a p-GaN film or the like on the entire surface of the electron supply layer 924, and then leaving the p-GaN film or the like only in a region where the gate electrode 941 is formed. The p-GaN film and the like are removed. Since Mg contained in the p-type layer 925 is considered to diffuse when a film such as p-GaN is formed by MOVPE (Metal-Organic Vapor Phase Epitaxy), the Mg in the region where the p-type layer 925 is formed. In some cases, 2DEG 923a may disappear not only directly below but also on the entire surface.

(Mg diffusion in threading dislocations)
Next, Mg diffusion in threading dislocation will be described. As shown in FIGS. 2 and 3, nitride stacks having different threading dislocation densities in the electron transit layer 923, the electron supply layer 924, and the like are produced, and the diffusion of Mg contained in the p-GaN film 925a is performed. I examined the situation. Specifically, by forming a buffer layer 921, an electron transit layer 923, an electron supply layer 924, and a p-GaN film 925a by MOVPE, and adjusting the conditions of the buffer layer 921, the threading dislocations in the electron transit layer 923, etc. Nitride laminates having different densities were produced. Among the nitride stacks thus manufactured, the nitride stack shown in FIG. 2 has a threading dislocation density of 7 × 10 ⁹ cm ⁻² , and the nitride stack shown in FIG. 3 has a threading dislocation density. Is 3 × 10 ⁹ cm ⁻² . 2 and 3 show TEM (Transmission Electron Microscope) images of the respective nitride laminates.

Next, FIG. 4 and FIG. 5 show the results of composition analysis in the depth direction by SIMS (Secondary Ion Mass Spectrometry) on the fabricated nitride stack shown in FIG. 2 and FIG. FIG. 4 shows the result of SIMS analysis of the nitride stack having a threading dislocation density of 7 × 10 ⁹ cm ⁻² shown in FIG. 2, and FIG. 5 shows the threading dislocation density of 3 × 10 ⁹ shown in FIG. It is the result of having analyzed by SIMS about the nitride laminated body which is cm ^<-2 >. As shown in FIG. 4, in the nitride laminate having a threading dislocation density of 7 × 10 ⁹ cm ⁻² , Mg is diffused deeply and in the vicinity of the interface between the electron supply layer 924 and the electron transit layer 923. The density of Mg in was 2 × 10 ¹⁷ cm ⁻³ . On the other hand, as shown in FIG. 5, in the nitride laminate having a threading dislocation density of 3 × 10 ⁹ cm ⁻² , Mg does not diffuse so deeply, and the electron supply layer 924 and the electron transit The density of Mg in the vicinity of the interface with the layer 923 was 2 × 10 ¹⁶ cm ⁻³ .

  As described above, in the electron supply layer 924 and the electron transit layer 923, when a large number of threading dislocations are generated, Mg diffuses deeply, and a large amount of Mg is diffused. The amount of diffusion is small. That is, it has been found that when the density of threading dislocations in the electron supply layer 924 and the electron transit layer 923 increases, the amount of Mg diffused in the electron supply layer 924 and the electron transit layer 923 increases. The present embodiment has been made based on the knowledge thus obtained.

(Semiconductor device)
Next, the semiconductor device according to the first embodiment will be described with reference to FIG. The semiconductor device in the present embodiment is a HEMT formed of a nitride semiconductor material. Specifically, a buffer layer 21, a lower semiconductor layer 22, a growth control layer 30, an electron transit layer 23, and an electron supply layer 24 are formed on the substrate 10. A p-type layer 25 is formed in a predetermined region on the electricity supply layer 24, and a gate electrode 41 is formed on the p-type layer 25. Further, a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 24, and a protective film 50 is formed so as to cover the whole. Further, the growth control layer 30 is formed in a region other than directly below the gate electrode 41, and an opening 31 is formed immediately below the gate electrode 41. In the present embodiment, the electron transit layer 23 is a first semiconductor layer, the electron supply layer 24 is a second semiconductor layer, the p-type layer 25 is a third semiconductor layer, and the lower semiconductor layer. The layer 22 is assumed to be a fourth semiconductor layer.

  The substrate 10 is made of sapphire, SiC, GaN, Si, or the like. The buffer layer 21 is formed of AlN or the like, the lower semiconductor layer 22 is formed of GaN or the like, and the electron transit layer 23 is formed of GaN or the like which is the same material as the lower semiconductor layer 22, The electron supply layer 24 is made of AlGaN or the like. Thereby, in the electron transit layer 23, 2DEG 23 a is formed in the vicinity of the interface between the electron transit layer 23 and the electron supply layer 24. A spacer layer (not shown) may be formed between the electron transit layer 23 and the electron supply layer 24. The p-type layer 25 is made of p-GaN and doped with Mg as an impurity element.

In the lower semiconductor layer 22 formed on the buffer layer 21, threading dislocations 20 are generated on the entire surface, and the growth control layer is formed on the lower semiconductor layer 22 on which the threading dislocations 20 are generated on the entire surface. 30 is formed. The growth control layer 30 is formed of an amorphous insulator material such as SiO ₂ , SiN, or Al ₂ O ₃ , and is formed so that the opening 31 is located immediately below the gate electrode 41. That is, the growth control layer 30 is formed in a region other than directly under the gate electrode 41.

  By forming such a growth control layer 30, in the electron transit layer 23, the region above the opening 31 of the growth control layer 30 without generating threading dislocations 20 in the region above the growth control layer 30. Threading dislocations 20 can be generated. That is, in the region above the opening 31 of the growth control layer 30, the electron transit layer 23 is formed on the lower semiconductor layer 22 where the threading dislocations 20 are generated. , Threading dislocations 20 are generated. However, in the region above the growth control layer 30 formed of amorphous material, the electron transit layer 23 is formed by new crystal growth, so that the threading dislocation 20 does not occur. For this reason, Mg doped as an impurity element diffuses greatly in the region immediately below the gate electrode 41 where the threading dislocation 20 is generated when the p-type layer 25 is formed, and the threading dislocation 20 is generated. Almost no diffusion occurs in a region that is not directly under the gate electrode 41. As a result, the 2DEG 23a in the region directly under the gate electrode 41 can be eliminated without reducing the 2DEG 23a in the region not directly under the gate electrode 41. Note that the growth control layer 30 formed in this way is generally sometimes referred to as ELO (Epitaxial Lateral Overgrowth).

  As described above, in the semiconductor device according to the present embodiment, the threading dislocations 20 are generated in the electron transit layer 23 and the like immediately below the gate electrode 41, so that Mg diffuses and the 2DEG 23 a immediately below the gate electrode 41 disappears. be able to. On the other hand, almost no threading dislocations 20 are generated in the electron transit layer 23 or the like that is not directly under the gate electrode 41, so that Mg hardly diffuses and the 2DEG 23 a in this region hardly disappears. Therefore, immediately after the gate electrode 41, 2DEG 23a disappears due to diffusion of Mg, which is an impurity element contained in the p-type layer 25, so that the p-type layer 25 is normally turned off without increasing the thickness thereof. In addition, the on-resistance is not increased.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 7A, nitride semiconductor layers such as a buffer layer 21 and a lower semiconductor layer 22 are formed on the substrate 10 by the MOVPE method. These nitride semiconductor layers are formed by epitaxial growth by MOVPE, but may be formed by a method other than MOVPE, for example, a molecular beam epitaxy (MBE) method. The substrate 10 is a silicon substrate, the buffer layer 21 is made of AlN having a thickness of 0.1 μm, and the lower semiconductor layer 22 is made of i-Gan. Note that threading dislocations 20 are generated in the lower semiconductor layer 22 formed by epitaxial growth on the buffer layer 21.

Next, as illustrated in FIG. 7B, an insulator film 30 a for forming the growth control layer 30 is formed on the lower semiconductor layer 22. The insulator film 30a is formed by depositing SiO ₂ by sputtering with a thickness of about 100 nm. The insulator film 30a may be formed by a film formation method other than sputtering, for example, a film formation method such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or vacuum deposition. The insulator film 30a is preferably amorphous.

  Next, as shown in FIG. 7C, the growth control layer 30 is formed by removing a part of the insulator film 30 a and forming the opening 31. Specifically, a photoresist is applied to the surface of the insulator film 30a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the opening 31 is formed. Thereafter, the growth control layer 30 is formed by removing the insulating film 30a in a region where the resist pattern is not formed by dry etching such as RIE (Reactive Ion Etching). The opening 31 formed in this way is formed to have substantially the same size as a gate electrode 41 and the like which will be described later. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 8A, the p for forming the electron transit layer 23, the electron supply layer 24, and the p-type layer 25 on the exposed lower semiconductor layer 22 and growth control layer 30. The mold film 25a is formed by epitaxial growth using MOVPE. Specifically, the electron transit layer 23 is formed of i-GaN having a thickness of 1 to 3 μm, the electron supply layer 24 is formed of n-AlGaN having a thickness of 30 nm, and a p-type film. 25a is formed of p-GaN having a thickness of 50 nm. A spacer layer (not shown) made of i-AlGaN having a thickness of 5 nm may be formed between the electron transit layer 23 and the electron supply layer 24.

Thus, by forming the electron transit layer 23, the electron supply layer 24, and the p-type film 25a by epitaxial growth, threading dislocations 20 generated in the lower semiconductor layer 22 are formed on the exposed lower semiconductor layer 22. Taken over. Therefore, threading dislocations 20 are generated on the exposed lower semiconductor layer 22, that is, in the electron transit layer 23, the electron supply layer 24, and the p-type film 25 a that crystal grows in the opening 31 in the growth control layer 30. . On the other hand, since the growth control layer 30 is amorphous in the electron transit layer 23, the electron supply layer 24, and the p-type film 25a formed on the growth control layer 30, the threading dislocations 20 generated in the lower semiconductor layer 22 are inherited. It will never be. Therefore, threading dislocations 20 hardly occur in the electron transit layer 23, the electron supply layer 24, and the p-type film 25a formed on the growth control layer 30. Therefore, in the electron transit layer 23, the electron supply layer 24, and the p-type film 25a, the density of threading dislocations 20 generated immediately above the opening 31 is the density of threading dislocations 20 generated immediately above the growth control layer 30. Higher than. 2 to 5, in the electron transit layer 23 and the electron supply layer 24, the density of threading dislocations 20 generated immediately above the opening 31 is 5 × 10 ⁹ cm ⁻² or more, The density of threading dislocations 20 generated immediately above the control layer 30 is preferably less than 5 × 10 ⁹ cm ⁻² .

In this embodiment, when forming AlN, GaN, and AlGaN by MOVPE, as source gases, trimethylaluminum (TMA) as an Al source, trimethylgallium (TMG) as a Ga source, and ammonia as an N source A gas such as (NH ₃ ) is used. The AlN, GaN, and AlGaN layers, which are nitride semiconductor layers, can be formed by supplying the above-described source gas mixed at a predetermined ratio according to the composition of the nitride semiconductor layer to be formed. . In the semiconductor device in this embodiment, when the nitride semiconductor layer is formed by MOVPE, the flow rate of ammonia gas is 100 ccm to 10 LM, and the pressure inside the device during film formation is 50 Torr to 300 Torr. The temperature is 1000 ° C to 1200 ° C.

In addition, the n-AlGaN serving as the electron supply layer 24 is doped with Si as an n-type impurity element. Specifically, when the electron supply layer 24 is formed, Si can be doped into the electron supply layer 24 by adding SiH ₄ gas to the source gas at a predetermined flow rate. The concentration of Si doped in the n-AlGaN formed in this way is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , for example, about 5 × 10 ¹⁸ cm ⁻³ .

Further, the p-GaN forming the p-type film 25a is doped with Mg as an impurity element to be p-type, and the concentration of the doped Mg is 1 × 10 ¹⁹ cm ⁻³ to 1 ×. 10 ²⁰ cm ⁻³ , for example, about 1 × 10 ¹⁹ cm ⁻³ .

  As described above, in the electron transit layer 23 and the electron supply layer 24, when the p-type film 25a is formed, Mg is more concentrated in a region where the threading dislocations 20 have a higher density than in a region where the threading dislocations 20 have a lower density. Spread. In other words, Mg is not directly under the gate electrode 41 with a low density of threading dislocations 20 and the electron supply layer 24, and the electron transit layer 23 and the electron supply directly under the gate electrode 41 with a high density of threading dislocations 20. A large amount diffuses into the layer 24. Therefore, a large amount of 2DEG 23a disappears immediately below the gate electrode 41 in which a large amount of Mg is diffused. Therefore, even if the p-type film 25a for forming the p-type layer 25 is thin, it is easily normally off. be able to.

  Thereafter, although not shown, an element isolation region may be formed. Specifically, a photoresist is applied on the p-type film 25a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a portion where an element isolation region is formed. Thereafter, the nitride semiconductor in the region where the resist pattern is not formed is removed by dry etching using a chlorine-based gas, or Ar is ion-implanted in the region where the resist pattern is not formed. An isolation region is formed. Incidentally, after the element isolation region is formed, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 8B, the p-type layer 25 is formed by processing the p-type film 25a. Specifically, a photoresist is applied on the p-type film 25a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) in a region where the p-type layer 25 is formed. Thereafter, dry etching such as RIE using a chlorine-based gas as an etching gas is performed to remove the p-type film 25a in the region where the resist pattern is not formed, and the surface of the electron supply layer 24 is exposed. Thereby, the p-type layer 25 is formed of p-GaN. The p-type layer 25 formed in this way is formed to have substantially the same size as a gate electrode 41 described later. Further, thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 8C, the source electrode 42 and the drain electrode 43 are formed on the electron transit layer 24. Specifically, a photoresist is applied on the electron transit layer 24 and the p-type layer 25, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. After that, a metal film for forming the source electrode 42 and the drain electrode 43 is formed by vacuum deposition and immersed in an organic solvent, so that the metal film formed on the resist pattern is lifted off together with the resist pattern. Remove with. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, an ohmic contact is established in the source electrode 42 and the drain electrode 43 by performing heat treatment in a nitrogen atmosphere at a temperature between 400 ° C. and 1000 ° C., for example, a temperature of 550 ° C. In addition, as a metal film for forming the source electrode 42 and the drain electrode 43, for example, a laminated metal film in which Ta with a thickness of 20 nm and Al with a thickness of 200 nm are laminated may be used.

  Next, as shown in FIG. 9A, the gate electrode 41 is formed on the p-type layer 25. Specifically, a photoresist is applied on the electron transit layer 24 and the p-type layer 25, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the gate electrode 41 is formed. The resist pattern is formed. Thereafter, a metal film for forming the gate electrode 41 is formed by vacuum deposition, and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal film. As the metal film for forming the gate electrode 41, for example, a laminated metal film in which Ni with a thickness of 30 nm and Au with a thickness of 400 nm are laminated may be used.

  Next, as shown in FIG. 9B, a protective film 50 is formed. Specifically, the protective film 50 is formed by forming a SiN film on the exposed electron supply layer 24 or the like by plasma CVD or the like. Thereafter, although not shown, wirings in the gate electrode 41, the source electrode 42, and the drain electrode 43 are formed.

  Thus, the semiconductor device in this embodiment can be manufactured.

[Second Embodiment]
Next, a second embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 10, unlike the first embodiment, the growth control layer 30 is formed on the buffer layer 21 without forming the lower semiconductor layer. It is what has been. Specifically, a buffer layer 21, a growth control layer 30, an electron transit layer 23, and an electron supply layer 24 are formed on the substrate 10. A p-type layer 25 is formed in a predetermined region on the electricity supply layer 24, and a gate electrode 41 is formed on the p-type layer 25. Further, a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 24, and a protective film 50 is formed so as to cover the whole. In the present embodiment, the electron transit layer 23 is a first semiconductor layer, the electron supply layer 24 is a second semiconductor layer, and the p-type layer 25 is a third semiconductor layer. .

The growth control layer 30 is formed of an amorphous insulator material such as SiO ₂ , SiN, or Al ₂ O ₃ , and is formed so that the opening 31 is located immediately below the gate electrode 41. That is, the growth control layer 30 is formed in a region other than directly under the gate electrode 41.

  By forming the growth control layer 30 as described above, in the electron transit layer 23 and the like, the threading dislocation 20 is not generated in the region above the growth control layer 30, and the region above the opening 31 of the growth control layer 30. The threading dislocation 20 can be generated in the region. That is, in the region above the opening 31 of the growth control layer 30, the electron transit layer 23 and the like are formed on the buffer layer 21 by epitaxial growth, so that threading dislocations 20 are generated as in the first embodiment. To do. However, in the region above the growth control layer 30 formed of amorphous material, the electron transit layer 23 is formed by new crystal growth, so that the threading dislocation 20 does not occur. For this reason, Mg doped as an impurity element diffuses greatly in the region immediately below the gate electrode 41 where the threading dislocation 20 is generated when the p-type layer 25 is formed, and the threading dislocation 20 is generated. Almost no diffusion occurs in a region that is not directly under the gate electrode 41. As a result, the 2DEG 23a in the region directly under the gate electrode 41 can be eliminated without reducing the 2DEG 23a in the region not directly under the gate electrode 41.

  As described above, in the semiconductor device according to the present embodiment, the threading dislocations 20 are generated in the electron transit layer 23 and the like immediately below the gate electrode 41, so that Mg diffuses and the 2DEG 23 a immediately below the gate electrode 41 disappears. be able to. On the other hand, almost no threading dislocations 20 are generated in the electron transit layer 23 or the like that is not directly under the gate electrode 41, so that Mg hardly diffuses and the 2DEG 23 a in this region hardly disappears. Therefore, immediately after the gate electrode 41, 2DEG 23a disappears due to diffusion of Mg, which is an impurity element contained in the p-type layer 25, so that the p-type layer 25 is normally turned off without increasing the thickness thereof. In addition, the on-resistance is not increased.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 11A, a nitride semiconductor layer such as the buffer layer 21 is formed on the substrate 10 by the MOVPE method. The nitride semiconductor layer is formed by epitaxial growth by MOVPE, but may be formed by a method other than MOVPE, for example, a molecular beam epitaxy method. A silicon substrate is used as the substrate 10, and the buffer layer 21 is made of AlN having a thickness of 0.1 μm.

Next, as illustrated in FIG. 11B, an insulator film 30 a for forming the growth control layer 30 is formed on the buffer layer 21. The insulator film 30a is formed by depositing SiO ₂ by sputtering with a thickness of about 100 nm. The insulator film 30a may be formed by a film formation method other than sputtering, for example, a film formation method such as ALD, CVD, or vacuum deposition, and the formed insulator film 30a is amorphous. Is preferred.

  Next, as shown in FIG. 11C, the growth control layer 30 is formed by removing a part of the insulator film 30 a and forming the opening 31. Specifically, a photoresist is applied to the surface of the insulator film 30a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the opening 31 is formed. Thereafter, the growth control layer 30 is formed by removing the insulator film 30a in the region where the resist pattern is not formed by dry etching such as RIE. The opening 31 formed in this way is formed to have substantially the same size as a gate electrode 41 and the like which will be described later. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 12A, the p-type for forming the electron transit layer 23, the electron supply layer 24, and the p-type layer 25 on the exposed buffer layer 21 and growth control layer 30. The film 25a is formed by epitaxial growth using MOVPE. Specifically, the electron transit layer 23 is formed of i-GaN having a thickness of 1 to 3 μm, the electron supply layer 24 is formed of n-AlGaN having a thickness of 30 nm, and a p-type film. 25a is formed of p-GaN having a thickness of 50 nm. A spacer layer (not shown) made of i-AlGaN having a thickness of 5 nm may be formed between the electron transit layer 23 and the electron supply layer 24.

Thus, by forming the electron transit layer 23, the electron supply layer 24, and the p-type film 25a by epitaxial growth, the electron transit layer 23, the electron supply layer 24, p, which grows crystals on the exposed buffer layer 21, are formed. In the mold film 25a, threading dislocations 20 are generated. On the other hand, the electron travel layer 23, the electron supply layer 24, and the p-type film 25a formed on the growth control layer 30 are formed on the growth control layer 30 because the growth control layer 30 is amorphous. The threading dislocation 20 hardly occurs in the layer 23, the electron supply layer 24, and the p-type film 25a. Therefore, in the electron transit layer 23, the electron supply layer 24, and the p-type film 25, the density of threading dislocations 20 generated immediately above the opening 31 is the density of threading dislocations 20 generated immediately above the growth control layer 30. Higher than. 2 to 5, in the electron transit layer 23 and the electron supply layer 24, the density of threading dislocations 20 generated immediately above the opening 31 is 5 × 10 ⁹ cm ⁻² or more, The density of threading dislocations 20 generated immediately above the control layer 30 is preferably less than 5 × 10 ⁹ cm ⁻² .

In this embodiment, when forming AlN, GaN, and AlGaN by MOVPE, as source gases, trimethylaluminum (TMA) as an Al source, trimethylgallium (TMG) as a Ga source, and ammonia as an N source A gas such as (NH ₃ ) is used. The AlN, GaN, and AlGaN layers, which are nitride semiconductor layers, can be formed by supplying the above-described source gas mixed at a predetermined ratio according to the composition of the nitride semiconductor layer to be formed. . In the semiconductor device in this embodiment, when the nitride semiconductor layer is formed by MOVPE, the flow rate of ammonia gas is 100 ccm to 10 LM, and the pressure inside the device during film formation is 50 Torr to 300 Torr. The temperature is 1000 ° C to 1200 ° C.

In addition, the n-AlGaN serving as the electron supply layer 24 is doped with Si as an n-type impurity element. Specifically, when the electron supply layer 24 is formed, Si can be doped into the electron supply layer 24 by adding SiH ₄ gas to the source gas at a predetermined flow rate. The concentration of Si doped in the n-AlGaN formed in this way is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , for example, about 5 × 10 ¹⁸ cm ⁻³ .

Further, the p-GaN forming the p-type film 25a is doped with Mg as an impurity element to be p-type, and the concentration of the doped Mg is 1 × 10 ¹⁹ cm ⁻³ to 1 ×. 10 ²⁰ cm ⁻³ , for example, about 1 × 10 ¹⁹ cm ⁻³ .

  As described above, in the electron transit layer 23 and the electron supply layer 24, when the p-type film 25a is formed, Mg is more concentrated in a region where the threading dislocations 20 have a higher density than in a region where the threading dislocations 20 have a lower density. Spread. In other words, Mg is not directly under the gate electrode 41 with a low density of threading dislocations 20 and the electron supply layer 24, and the electron transit layer 23 and the electron supply directly under the gate electrode 41 with a high density of threading dislocations 20. A large amount diffuses into the layer 24. Therefore, a large amount of 2DEG 23a disappears immediately below the gate electrode 41 in which a large amount of Mg is diffused. Therefore, even if the p-type film 25a for forming the p-type layer 25 is thin, it is easily normally off. be able to.

  Thereafter, although not shown, an element isolation region may be formed. Specifically, a photoresist is applied on the p-type film 25a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a portion where an element isolation region is formed. Thereafter, the nitride semiconductor in the region where the resist pattern is not formed is removed by dry etching using a chlorine-based gas, or Ar is ion-implanted in the region where the resist pattern is not formed. An isolation region is formed. Incidentally, after the element isolation region is formed, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 12B, the p-type layer 25 is formed by processing the p-type film 25a. Specifically, a photoresist is applied on the p-type film 25a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) in a region where the p-type layer 25 is formed. Thereafter, dry etching such as RIE using a chlorine-based gas as an etching gas is performed to remove the p-type film 25a in the region where the resist pattern is not formed, and the surface of the electron supply layer 24 is exposed. Thereby, the p-type layer 25 is formed of p-GaN. The p-type layer 25 formed in this way is formed to have substantially the same size as a gate electrode 41 described later. Further, thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 12C, the source electrode 42 and the drain electrode 43 are formed on the electron transit layer 24. Specifically, a photoresist is applied on the electron transit layer 24 and the p-type layer 25, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. After that, a metal film for forming the source electrode 42 and the drain electrode 43 is formed by vacuum deposition and immersed in an organic solvent, so that the metal film formed on the resist pattern is lifted off together with the resist pattern. To remove. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, an ohmic contact is established in the source electrode 42 and the drain electrode 43 by performing heat treatment in a nitrogen atmosphere at a temperature between 400 ° C. and 1000 ° C., for example, a temperature of 550 ° C. In addition, as a metal film for forming the source electrode 42 and the drain electrode 43, for example, a laminated metal film in which Ta with a thickness of 20 nm and Al with a thickness of 200 nm are laminated may be used.

  Next, as illustrated in FIG. 13A, the gate electrode 41 is formed on the p-type layer 25. Specifically, a photoresist is applied on the electron transit layer 24 and the p-type layer 25, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the gate electrode 41 is formed. The resist pattern is formed. Thereafter, a metal film for forming the gate electrode 41 is formed by vacuum deposition, and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal film. As the metal film for forming the gate electrode 41, for example, a laminated metal film in which Ni with a thickness of 30 nm and Au with a thickness of 400 nm are laminated may be used.

  Next, as shown in FIG. 13B, a protective film 50 is formed. Specifically, the protective film 50 is formed by forming a SiN film on the exposed electron supply layer 24 or the like by plasma CVD or the like. Thereafter, although not shown, wirings in the gate electrode 41, the source electrode 42, and the drain electrode 43 are formed.

  Thus, the semiconductor device in this embodiment can be manufactured. The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

(Semiconductor device)
The semiconductor device according to the present embodiment is a discrete package of the semiconductor device according to the first or second embodiment. The semiconductor device thus discretely packaged will be described with reference to FIG. FIG. 14 schematically shows the inside of a discrete packaged semiconductor device, and the arrangement of electrodes and the like are different from those shown in the first or second embodiment. .

  First, the semiconductor device manufactured in the first or second embodiment is cut by dicing or the like to form a HEMT semiconductor chip 410 made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device in the first or second embodiment.

  Next, the gate electrode 411 is connected to the gate lead 421 by a bonding wire 431, the source electrode 412 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are formed of a metal material such as Al. In the present embodiment, the gate electrode 411 is a kind of gate electrode pad and is connected to the gate electrode 41 of the semiconductor device in the first or second embodiment. The source electrode 412 is a kind of source electrode pad and is connected to the source electrode 42 of the semiconductor device in the first or second embodiment. The drain electrode 413 is a kind of drain electrode pad and is connected to the drain electrode 43 of the semiconductor device according to the first or second embodiment.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this way, a HEMT discrete packaged semiconductor device using a GaN-based semiconductor material can be manufactured.

(PFC circuit, power supply and high frequency amplifier)
Next, a PFC circuit, a power supply device, and a high frequency amplifier in this embodiment will be described. The PFC circuit, the power supply device, and the high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier that use the semiconductor device in the first or second embodiment.

(PFC circuit)
Next, a PFC (Power Factor Correction) circuit according to the present embodiment will be described. The PFC circuit in the present embodiment has the semiconductor device in the first or second embodiment.

  Based on FIG. 15, the PFC circuit in the present embodiment will be described. The PFC circuit 450 in this embodiment includes a switch element (transistor) 451, a diode 452, a choke coil 453, capacitors 454 and 455, a diode bridge 456, and an AC power supply (not shown). As the switch element 451, the HEMT which is the semiconductor device in the first or second embodiment is used.

  In the PFC circuit 450, the drain electrode of the switch element 451, the anode terminal of the diode 452, and one terminal of the choke coil 453 are connected. The source electrode of the switch element 451 is connected to one terminal of the capacitor 454 and one terminal of the capacitor 455, and the other terminal of the capacitor 454 is connected to the other terminal of the choke coil 453. The other terminal of the capacitor 455 and the cathode terminal of the diode 452 are connected, and an AC power supply (not shown) is connected between both terminals of the capacitor 454 via a diode bridge 456. In such a PFC circuit 450, direct current (DC) is output from between both terminals of the capacitor 455.

(Power supply)
Next, the power supply device according to the present embodiment will be described. The power supply device in the present embodiment is a power supply device having a HEMT that is the semiconductor device in the first or second embodiment.

  A power supply device according to the present embodiment will be described with reference to FIG. The power supply device in the present embodiment has a structure including the PFC circuit 450 in the present embodiment described above.

  The power supply device in this embodiment includes a high-voltage primary circuit 461 and a low-voltage secondary circuit 462, and a transformer 463 disposed between the primary circuit 461 and the secondary circuit 462. Yes.

  The primary circuit 461 includes the PFC circuit 450 in the present embodiment described above and an inverter circuit connected between both terminals of the capacitor 455 of the PFC circuit 450, for example, a full bridge inverter circuit 460. The full bridge inverter circuit 460 includes a plurality (here, four) of switch elements 464a, 464b, 464c, and 464d. The secondary side circuit 462 includes a plurality (three in this case) of switch elements 465a, 465b, and 465c. An AC power supply 457 is connected to the diode bridge 456.

  In the present embodiment, the HEMT that is the semiconductor device in the first to fifth embodiments is used in the switch element 451 of the PFC circuit 450 in the primary circuit 461. Further, the HEMT that is the semiconductor device in the first or second embodiment is used for the switch elements 464a, 464b, 464c, and 464d in the full bridge inverter circuit 460. On the other hand, the switch elements 465a, 465b, and 465c of the secondary circuit 462 are normal MIS FETs using silicon.

(High frequency amplifier)
Next, the high frequency amplifier in the present embodiment will be described. The high-frequency amplifier in the present embodiment has a structure in which the HEMT that is the semiconductor device in the first or second embodiment is used.

  Based on FIG. 17, the high frequency amplifier in this Embodiment is demonstrated. The high frequency amplifier in this embodiment includes a digital predistortion circuit 471, mixers 472a and 472b, a power amplifier 473, and a directional coupler 474.

  The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal, and includes the HEMT that is the semiconductor device according to the first or second embodiment. The directional coupler 474 performs monitoring of input signals and output signals. In FIG. 17, for example, by switching the switch, the output-side signal can be mixed with the AC signal by the mixer 472b and sent to the digital predistortion circuit 471.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A buffer layer formed on the substrate;
A growth control layer having an opening in a predetermined region formed of an insulating material on the buffer layer;
A first semiconductor layer formed on the growth control layer and a region where the opening of the growth control layer is formed;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed in a region immediately above the opening of the growth control layer on the second semiconductor layer;
A semiconductor device comprising:
(Appendix 2)
Supplementary note 1 including a fourth semiconductor layer formed of a material including a material forming the first semiconductor layer between the buffer layer and the growth control layer. A semiconductor device according to 1.
(Appendix 3)
The first conductivity type is p-type,
The third semiconductor layer is formed of a material containing GaN;
The semiconductor device according to appendix 1 or 2, wherein Mg is doped as the p-type impurity element.
(Appendix 4)
The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region to be the opening of the growth control layer is:
The appendix 1 to 3, wherein the density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the growth control layer is higher. Semiconductor device.
(Appendix 5)
The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region serving as the opening of the growth control layer is 5 × 10 ⁹ cm ⁻² or more. There,
Note that the density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the growth control layer is less than 5 × 10 ⁹ cm ^−2. The semiconductor device according to any one of 1 to 3.
(Appendix 6)
6. The semiconductor device according to any one of appendices 1 to 5, wherein the growth control layer is formed of one or more of SiO ₂ , SiN, and Al ₂ O ₃ .
(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the growth control layer is amorphous.
(Appendix 8)
The semiconductor device according to any one of appendices 1 to 7, wherein the first semiconductor layer is formed of a material containing GaN.
(Appendix 9)
9. The semiconductor device according to any one of appendices 1 to 8, wherein the second semiconductor layer is formed of a material containing AlGaN.
(Appendix 10)
10. The semiconductor device according to any one of appendices 1 to 9, wherein the second semiconductor layer is a second conductivity type, and the second conductivity type is an n-type.
(Appendix 11)
A gate electrode formed on the third semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
11. The semiconductor device according to any one of appendices 1 to 10, wherein:
(Appendix 12)
The semiconductor device according to any one of appendices 1 to 11, wherein the semiconductor device is a HEMT.
(Appendix 13)
Forming a buffer layer on the substrate;
Forming a growth control layer having an opening in a predetermined region with an insulating material on the buffer layer;
Forming a first semiconductor layer on the growth control layer and a region where the opening of the growth control layer is formed;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer of the first conductivity type on the second semiconductor layer in a region immediately above the opening of the growth control layer;
A method for manufacturing a semiconductor device, comprising:
(Appendix 14)
After the step of forming the buffer layer and before the step of forming the growth control layer,
14. The method of manufacturing a semiconductor device according to appendix 13, wherein a fourth semiconductor layer is formed on the buffer layer with a material including a material forming the first semiconductor layer.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to appendix 13 or 14, wherein the first semiconductor layer and the second semiconductor layer are formed by MOVPE.
(Appendix 16)
The step of forming the growth control layer includes:
Forming an insulator film by any one of sputtering, ALD, CVD, and vacuum deposition;
Forming the opening by partially removing a predetermined region of the formed insulator film; and
The method of manufacturing a semiconductor device according to any one of appendices 13 to 15, wherein
(Appendix 17)
The first conductivity type is p-type,
17. The method for manufacturing a semiconductor device according to any one of appendices 13 to 16, wherein the third semiconductor layer is a material containing GaN and doped with Mg.
(Appendix 18)
A PFC circuit comprising the semiconductor device according to any one of appendices 1 to 12.
(Appendix 19)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 12.
(Appendix 20)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 12.

10 Substrate 21 Buffer layer 22 Lower semiconductor layer (fourth semiconductor layer)
23 Electron travel layer (first semiconductor layer)
23a 2DEG
24 Electron supply layer (second semiconductor layer)
25 p-type layer (third semiconductor layer)
30 Growth Control Layer 31 Opening 41 Gate Electrode 42 Source Electrode 43 Drain Electrode 50 Protective Film

Claims (8)

A buffer layer formed on the substrate;
A growth control layer having an opening in a predetermined region formed of an insulating material on the buffer layer;
A first semiconductor layer formed on the growth control layer and a region where the opening of the growth control layer is formed;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed in a region immediately above the opening of the growth control layer on the second semiconductor layer;
Have
The first conductivity type is p-type,
The buffer layer is made of a material containing AlN,
The first semiconductor layer is made of a material containing GaN,
The second semiconductor layer is made of a material containing AlGaN,
The third semiconductor layer is formed of a material containing GaN;
Mg is doped as the p-type impurity element ,
The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region to be the opening of the growth control layer is formed on the growth control layer. A semiconductor device, wherein the density of threading dislocations occurring in the first semiconductor layer and the second semiconductor layer is higher . A buffer layer formed on the substrate;
A growth control layer having an opening in a predetermined region formed of an insulating material on the buffer layer;
A first semiconductor layer formed on the growth control layer and a region where the opening of the growth control layer is formed;
A second semiconductor layer formed on the first semiconductor layer;
A p-type third semiconductor layer formed in a region immediately above the opening of the growth control layer on the second semiconductor layer;
Have
The buffer layer is made of a material containing AlN,
The first semiconductor layer is made of a material containing GaN,
The second semiconductor layer is made of a material containing AlGaN,
The third semiconductor layer is doped with a p-type impurity element ,
The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region to be the opening of the growth control layer is formed on the growth control layer. A semiconductor device, wherein the density of threading dislocations occurring in the first semiconductor layer and the second semiconductor layer is higher .   The semiconductor device according to claim 1, wherein the substrate is made of a material containing any of sapphire, SiC, GaN, or Si. The fourth semiconductor layer formed of a material including a material forming the first semiconductor layer is provided between the buffer layer and the growth control layer. The semiconductor device according to any one of 1 to 3 . The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the region serving as the opening of the growth control layer is 5 × 10 ⁹ cm ⁻² or more. There,
The density of threading dislocations generated in the first semiconductor layer and the second semiconductor layer formed on the growth control layer is less than 5 × 10 ⁹ cm ^−2. Item 5. The semiconductor device according to any one of Items 1 to 4 . 6. The semiconductor device according to claim 1, wherein the growth control layer is formed of a material including one or more of SiO ₂ , SiN, and Al ₂ O _3. . Forming a buffer layer on the substrate;
Forming a growth control layer having an opening in a predetermined region with an insulating material on the buffer layer;
Forming a first semiconductor layer on the growth control layer and a region where the opening of the growth control layer is formed;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer of the first conductivity type on the second semiconductor layer in a region immediately above the opening of the growth control layer;
Have
The first conductivity type is p-type,
The buffer layer is made of a material containing AlN,
The first semiconductor layer is made of a material containing GaN,
The second semiconductor layer is made of a material containing AlGaN,
The third semiconductor layer is formed of a material containing GaN;
A method for manufacturing a semiconductor device, characterized in that Mg is doped as the impurity element to be p-type. Forming a buffer layer on the substrate;
Forming a growth control layer having an opening in a predetermined region with an insulating material on the buffer layer;
Forming a first semiconductor layer on the growth control layer and a region where the opening of the growth control layer is formed;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer doped with a p-type impurity element in a region immediately above the opening of the growth control layer on the second semiconductor layer;
I have a,
The buffer layer is made of a material containing AlN,
The first semiconductor layer is made of a material containing GaN,
Said second semiconductor layer, a method of manufacturing a semiconductor device which is characterized that you have been formed of a material containing AlGaN.