JP6183145B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  A nitride semiconductor has characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies have been conducted on applying nitride semiconductors to high breakdown voltage and high output semiconductor devices using these characteristics. For example, the band gap of GaN, which is a kind of nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV). For this reason, GaN has a high breakdown electric field strength and is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT, an AlGaN / GaN-HEMT using GaN as a channel layer and AlGaN as a carrier supply layer has attracted attention. In AlGaN / GaN-HEMT, strain is generated in AlGaN due to the difference in lattice constant between GaN and AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated by this strain and the spontaneous polarization of AlGaN. Therefore, AlGaN / GaN-HEMT is expected as a high-efficiency switch element, a high voltage power device for electric vehicles, and the like.

  However, it is extremely difficult to manufacture a GaN substrate with good crystallinity. For this reason, conventionally, a GaN layer, an AlGaN layer, and the like are mainly formed by heteroepitaxial growth above the Si substrate, sapphire substrate, and SiC substrate. In particular, a Si substrate having a large diameter and high quality is easily available at low cost. For this reason, research on a structure in which a channel layer and a carrier supply layer are grown above the Si substrate has been actively conducted.

  However, in a conventional GaN-based HEMT using a Si substrate, it is difficult to suppress the leakage current flowing between the source and the drain. Such a leakage current may cause a decrease in operating efficiency and a decrease in reliability.

JP 2005-527988 gazette JP 2011-100772 A JP 2011-119715 A JP 2012-9630 A Japanese Patent No. 4681684

  An object of the present invention is to provide a compound semiconductor device capable of suppressing a leakage current flowing between a source and a drain, and a manufacturing method thereof.

One aspect of the compound semiconductor device includes a first AlGaN layer having a first Al composition and a second AlGaN layer having a second Al composition that is thinner than the first AlGaN layer and higher than the first Al composition. A superlattice buffer layer; a channel layer formed above the superlattice buffer layer; a carrier supply layer formed above the channel layer; and a gate electrode, a source electrode, and a drain electrode formed above the carrier supply layer. And are provided. Further, a fourth AlGaN layer having a fourth Al composition thicker than the second AlGaN layer, the fourth AlGaN layer, and the channel layer between the superlattice buffer layer and the channel layer . A fifth AlGaN layer having a fifth Al composition that is thicker than the second AlGaN layer and thinner than the fourth AlGaN layer is provided therebetween. The first Al composition is 0 or more and less than 1, the second Al composition and the fifth Al composition are more than 0 and 1 or less, and the fourth Al composition is more than the first Al composition. Higher than the second Al composition and the fifth Al composition.

In one aspect of the manufacturing method of the compound semiconductor device, the first AlGaN layer having the first Al composition and the second AlGaN having the second Al composition that is thinner than the first AlGaN layer and higher than the first Al composition. Forming a channel layer above the superlattice buffer layer, forming a carrier supply layer above the channel layer, forming a gate electrode, a source electrode and a drain electrode above the carrier supply layer, and forming the superlattice buffer layer A fourth AlGaN layer having a fourth Al composition thicker than the second AlGaN layer is formed between the first AlGaN layer and the channel layer, and the fourth AlGaN layer is formed between the fourth AlGaN layer and the channel layer . A fifth AlGaN layer having a fifth Al composition that is thicker than the second AlGaN layer and thinner than the fourth AlGaN layer is formed. The first Al composition is 0 or more and less than 1, the second Al composition and the fifth Al composition are more than 0 and 1 or less, and the fourth Al composition is more than the first Al composition. Higher than the second Al composition and the fifth Al composition.

  According to the above compound semiconductor device and the like, since an appropriate AlGaN layer is provided between the superlattice buffer layer and the channel layer, a leakage current flowing between the source and the drain can be suppressed.

It is sectional drawing which shows the structure of the compound semiconductor device which concerns on a 1st reference example . It is a figure which shows the outline of the band structure of a 1st reference example . It is sectional drawing which shows the structure of the compound semiconductor device which concerns on a 2nd reference example . It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on a 2nd reference example to process order. FIG. 4B is a cross-sectional view illustrating the manufacturing method of the compound semiconductor device in the order of steps, following FIG. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is a figure which shows the outline of the band structure of 1st Embodiment. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the discrete package which concerns on 3rd Embodiment. It is a connection diagram which shows the PFC circuit which concerns on 4th Embodiment. It is a connection diagram which shows the power supply device which concerns on 5th Embodiment. It is a connection diagram which shows the amplifier which concerns on 6th Embodiment.

  The inventors of the present application have examined the cause of the difficulty in suppressing the leakage current flowing between the source and the drain in a conventional GaN-based HEMT using a Si substrate. As a result, it was found that a leak current flows under the channel layer. Based on this finding, the inventors of the present invention have conducted further diligent studies. As a result, by providing a layer under the channel layer that can raise the potential below the channel layer, the above leakage current can be reduced. It was found that it can be suppressed.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First reference example )
First, a first reference example will be described. The first reference example is an example of a GaN-based HEMT. FIG. 1 is a cross-sectional view showing the structure of a compound semiconductor device according to a first reference example .

In the first reference example , as shown in FIG. 1A, above the superlattice buffer layer 101 of the first AlGaN layer 101a having the first Al composition and the second AlGaN layer 101b having the second Al composition. A channel layer 102 is formed on the channel layer 102, and a carrier supply layer 103 is formed above the channel layer 102. A gate electrode 104, a source electrode 105, and a drain electrode 106 are formed above the carrier supply layer 103. The second AlGaN layer 101b is thinner than the first AlGaN layer 101a, and the second Al composition is higher than the first Al composition. A third AlGaN layer having a third Al composition is formed between the superlattice buffer layer 101 and the channel layer 102. The third AlGaN layer 107 is thicker than the second AlGaN layer 101b, and the third Al composition is higher than the first Al composition. The first Al composition is 0 or more and less than 1, and the second Al composition and the third Al composition are more than 0 and 1 or less. That is, the first AlGaN layer 101a may be a GaN layer, and the second AlGaN layer 101b and the third AlGaN layer 107 may be AlN layers. For example, the first Al composition and the second Al composition are within a range in which two-dimensional electron gas is not generated near the interface between the first AlGaN layer 101a and the second AlGaN layer 101b.

FIG. 2A shows an outline of the band structure of the channel layer 102, the third AlGaN layer 107, the first AlGaN layer 101a, and the second AlGaN layer 101b of the first reference example . As shown in FIG. 2A, since the third AlGaN layer 107 is thicker than the second AlGaN layer 101b, the thickness of the third AlGaN layer 107 is equal to the thickness of the second AlGaN layer 101b. Thus, the potential below the channel layer 102 is raised higher. Therefore, it is difficult for current to flow under the channel layer 102.

FIG. 2B shows the result of the simulation regarding the first reference example . In this simulation, the first AlGaN layer 101a is an Al _0.2 Ga _0.8 N layer having a thickness of 20 nm, the second AlGaN layer 101b is an AlN layer having a thickness of 1.5 nm, and the third AlGaN layer 107 is It was assumed that the AlN layer had a thickness of 2.5 nm. Then, the relationship between the drain voltage and the drain current when a gate voltage of −5 V was applied to the gate electrode 104 (off state) was obtained. For reference, the same relationship between the drain voltage and the drain current was obtained when the third AlGaN layer 107 was an AlN layer having a thickness of 1.5 nm. As shown in FIG. 2B, in the first reference example , a result that the drain current at the off time is significantly reduced as compared with the reference example was obtained. This indicates that there is an effect in greatly reducing the leakage current.

  The layer located closest to the channel layer 102 in the superlattice buffer layer 101 may be the first AlGaN layer 101a as shown in FIG. 1A, and the first AlGaN layer 101a as shown in FIG. Two AlGaN layers 101b may be used.

The thicker the third AlGaN layer 107, the higher the potential of the lower portion of the channel layer 102 is raised. However, when the thickness of the third AlGaN layer 107 is larger than a certain threshold value, 2 near the surface of the superlattice buffer layer 101. Dimensional electron gas can be generated. For this reason, it is preferable that the third AlGaN layer 107 be within a range in which such a two-dimensional electron gas is not generated. In order to suppress the generation of such a two-dimensional electron gas, acceptor impurities are contained in the first AlGaN layer 101a closest to the third AlGaN layer 107a. Is also preferable. The acceptor impurity is, for example, Fe, Mg, or C. With such a configuration, the breakdown voltage in the direction parallel to the surface of the superlattice buffer layer 101 is further improved, and the leakage current can be further suppressed. The concentration of the acceptor impurity is preferably, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and more preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. preferable. If the concentration of the acceptor impurity is 1 × 10 ¹⁷ cm ⁻³ or more, the effect of suppressing the generation of the two-dimensional electron gas is particularly remarkable. Further, if the concentration of the acceptor impurity is more than 1 × 10 ²¹ cm ⁻³ , warping is likely to occur, and if the concentration of the acceptor impurity is 1 × 10 ¹⁹ cm ⁻³ or less, the warping is extremely difficult to occur.

(Second reference example )
Next, a second reference example will be described. The second reference example is an example of a GaN-based HEMT. FIG. 3 is a cross-sectional view showing the structure of the compound semiconductor device according to the second reference example .

In the second reference example , as shown in FIG. 3, the initial layer 209 is formed on the substrate 208, the buffer layer 210 is formed on the initial layer 209, and the superlattice buffer layer 201 of the AlGaN layer 201a and the AlN layer 201b. Is formed on the buffer layer 210. An AlN layer 207 is formed on the superlattice buffer layer 201, a channel layer 202 is formed on the AlN layer 207, and a carrier supply layer 203 is formed on the channel layer 202. The substrate 208 is, for example, a Si substrate. The initial layer 209 is an AlN layer having a thickness of about 200 nm, for example. The buffer layer 210 is, for example, an Al _0.4 Ga _0.6 N layer. The Al composition of the AlGaN layer 201a is 0 or more and less than 1, preferably 0 or more and 0.5 or less. The AlGaN layer 201a is, for example, an Al _0.2 Ga _0.8 N layer having a thickness of 20 nm. The thickness of the AlN layer 201b is, for example, 1.5 nm. The thickness of the AlN layer 207 is, for example, 2.5 nm. The superlattice buffer layer 201 includes about 80 AlGaN layers 201a and AlN layers 201b. The AlN layer 201b is in direct contact with the buffer layer 210, and the AlGaN layer 201a is in direct contact with the AlN layer 207. The channel layer 202 is, for example, an i-GaN layer having a thickness of about 1 μm and not intentionally doped with impurities. The carrier supply layer 203 is an n-type n-Al _0.2 Ga _0.8 N layer having a thickness of about 20 nm, for example. The carrier supply layer 203 is doped with, for example, Si as an n-type impurity at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . The AlGaN layer 201a is an example of a first AlGaN layer, the AlN layer 201b is an example of a second AlGaN layer, and the AlN layer 207 is an example of a third AlGaN layer. The thickness of the AlN layer 201b is preferably 2.0 nm or less in order to avoid a decrease in breakdown voltage due to generation of residual electrons in the superlattice buffer layer 201. In order to sufficiently relax the lattice strain, the thickness of the AlN layer 201b is preferably 0.8 nm or more.

  In the superlattice buffer layer 201, the composition and thickness of each AlGaN layer 201a are substantially equal to each other, and the composition and thickness of each AlN layer 201b are substantially equal to each other. The composition of the AlN layer 207 is substantially equal to the composition of the AlN layer 201b.

  An element isolation region 211 that defines an element region is formed in the stacked body of the channel layer 202 and the carrier supply layer 203. A source electrode 205 and a drain electrode 206 are formed on the carrier supply layer 203 in the element region. An insulating film 212 is formed on the carrier supply layer 203 so as to cover the source electrode 205 and the drain electrode 206. In the insulating film 212, an opening 213 is formed between the source electrode 205 and the drain electrode 206, and a gate electrode 204 that is in Schottky contact with the carrier supply layer 203 is provided through the opening 213. Yes. An insulating film 214 that covers the gate electrode 204 is formed over the insulating film 212. The material of the insulating film 212 and the insulating film 214 is not particularly limited, and the insulating film 212 and the insulating film 214 are, for example, silicon nitride films.

In the second reference example , since the AlN layer 207 is thicker than the AlN layer 201b, the potential below the channel layer 202 is raised higher than when the thickness of the AlN layer 207 is equal to the thickness of the AlN layer 201b. It is done. Therefore, it is difficult for current to flow under the channel layer 202. Therefore, like the first reference example , the leakage current can be greatly reduced.

  The layer directly in contact with the channel layer 202 in the superlattice buffer layer 201 may be the AlN layer 201b.

Next, a method for manufacturing a compound semiconductor device according to the second reference example will be described. 4A to 4B are cross-sectional views illustrating a method of manufacturing a compound semiconductor device according to a second reference example in the order of steps.

First, as shown in FIG. 4A (a), an initial layer 209 and a buffer layer 210 are formed on a substrate 208. The initial layer 209 and the buffer layer 210 can be formed by a crystal growth method such as a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method, for example. As the source gas, for example, a mixed gas of trimethylaluminum (TMA) gas, trimethylgallium (TMG) gas, and ammonia (NH ₃ ) gas is used. In forming the initial layer 209 (AlN layer), for example, the V / III ratio is about 1000 to 2000, the growth temperature is about 1000 ° C., and the pressure is about 50 mbar. Further, it is preferable to select a condition in which the C impurity is less taken into the initial layer 209. In forming the buffer layer 210 (Al _0.4 Ga _0.6 N layer), the V / III ratio is about 100 to 300, the growth temperature is about 1000 ° C., and the pressure is about 50 mbar. The reason why the V / III ratio at the time of forming the buffer layer 210 is lower than that at the time of forming the initial layer 209 is to obtain high flatness.

Next, as shown in FIG. 4A (b), a superlattice buffer layer 201 is formed on the buffer layer 210. In the formation of the superlattice buffer layer 201, the formation of the AlN layer 201b and the formation of the AlGaN layer 201a are repeated about 80 times. The AlN layer 201b and the AlGaN layer 201a can also be formed by a crystal growth method such as an MOCVD method or an MBE method, and a mixed gas of TMA gas, TMG gas, and NH ₃ gas is used as a source gas, for example. In the formation of the AlN layer 201b and the formation of the AlGaN layer 201a, for example, the growth temperature is set to about 1020 ° C. and the pressure is set to about 50 mbar, and the source gas is switched. Thus, for example, the growth temperature and pressure are made common.

Thereafter, an AlN layer 207 is formed on the superlattice buffer layer 201 as shown in FIG. 4A (c). The AlN layer 207 can also be formed, for example, by a crystal growth method such as MOCVD method or MBE method. As the source gas, for example, a mixed gas of TMA gas and NH ₃ gas is used. In forming the AlN layer 207, for example, the growth temperature is about 1020 ° C. and the pressure is about 50 mbar. That is, the growth temperature and pressure are made common when the AlN layer 201b and the AlGaN layer 201a are formed.

Subsequently, as shown in FIG. 4B (d), the channel layer 202 and the carrier supply layer 203 are formed on the AlN layer 207. The channel layer 202 and the carrier supply layer 203 can also be formed by, for example, a crystal growth method such as MOCVD method or MBE method. As the source gas, for example, a mixed gas of TMA gas, TMG gas, and NH ₃ gas is used. In forming the channel layer 202 (i-GaN layer), for example, the V / III ratio is about 600, the growth temperature is about 1000 ° C., and the pressure is about 200 mbar. In the formation of the carrier supply layer 203 (n-AlGaN layer), the V / III ratio is 3000 or more, the growth temperature is about 1040 ° C., and the pressure is about 300 mbar. In order to suppress the current collapse phenomenon, it is preferable to select a condition for reducing the C concentration. When growing the n-type compound semiconductor layer (for example, the carrier supply layer 203), for example, SiH ₄ gas containing Si is added to the mixed gas at a predetermined flow rate, and the compound semiconductor layer is doped with Si.

Next, as shown in FIG. 4B (d), an element isolation region 211 that defines an element region is formed in the carrier supply layer 203 and the channel layer 202. In the formation of the element isolation region 211, for example, a photoresist pattern exposing a region where the element isolation region 211 is to be formed is formed on the carrier supply layer 203, and ion implantation of Ar or the like is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask. Thereafter, the source electrode 205 and the drain electrode 206 are formed on the carrier supply layer 203 in the element region. The source electrode 205 and the drain electrode 206 can be formed by, for example, a lift-off method. That is, a region in which the source electrode 205 is to be formed and a region in which the drain electrode 206 is to be formed are exposed, a photoresist pattern covering the other region is formed, and a metal film is formed by vapor deposition using this pattern as a growth mask. Then, the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, after forming a Ti film having a thickness of about 100 nm, an Al film having a thickness of about 300 nm is formed. Next, for example, heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400 ° C. to 1000 ° C. (for example, 600 ° C.) in an N ₂ gas atmosphere to obtain ohmic contact.

  After the formation of the source electrode 205 and the drain electrode 206, as shown in FIG. 4B (e), an insulating film 212 that covers the source electrode 205 and the drain electrode 206 is formed on the carrier supply layer 203. The insulating film 212 can be formed by, for example, an atomic layer deposition (ALD) method, a plasma chemical vapor deposition (CVD) method, or a sputtering method. After that, an opening 213 is formed in a region where a gate electrode of the insulating film 212 is to be formed. The opening 213 can be formed by, for example, dry etching, wet etching, or ion milling. Subsequently, a gate electrode 204 is formed in the opening 213. The gate electrode 204 can be formed by a lift-off method, for example. That is, a photoresist pattern exposing a region where the gate electrode 204 is to be formed is formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, after forming a Ni film having a thickness of about 50 nm, an Au film having a thickness of about 300 nm is formed. Next, an insulating film 214 that covers the gate electrode 204 is formed over the insulating film 212. As with the insulating film 212, the insulating film 214 can be formed by, for example, an ALD method, a plasma CVD method, or a sputtering method.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

The thicker the AlN layer 207, the higher the potential of the lower portion of the channel layer 202 is raised. However, when the thickness of the AlN layer 207 is larger than a certain threshold, two-dimensional electron gas is generated near the surface of the superlattice buffer layer 201. obtain. For this reason, it is preferable that the AlN layer 207 be within a range in which such a two-dimensional electron gas is not generated. In order to suppress the generation of such a two-dimensional electron gas, it is also preferable that an acceptor impurity is contained in the AlGaN layer 201a closest to the AlN layer 207. The acceptor impurity is, for example, Fe, Mg, or C. With such a configuration, the breakdown voltage in the direction parallel to the surface of the superlattice buffer layer 201 is further improved, and the leakage current can be further suppressed. The concentration of the acceptor impurity is preferably, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and more preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. preferable.

  The AlN layer 207 is preferably included in only one layer, but a plurality of stacked bodies of the AlN layer 207 and the AlGaN layer 201a may be included. Since the two-dimensional electron gas that can be generated in the vicinity of the surface of each AlGaN layer 201a included in this stacked body can contribute to an increase in leakage current, the number of stacked bodies depends on the total thickness of the superlattice buffer layer 201, It is preferable to determine. The AlGaN layer 201a included in this stacked body is located outside the superlattice buffer layer 201.

(First Embodiment)
Next, a first embodiment will be described. The first embodiment is an example of a GaN-based HEMT. FIG. 5 is a cross-sectional view showing the structure of the compound semiconductor device according to the first embodiment.

In the first embodiment, as shown in FIG. 5, a channel layer is formed above the superlattice buffer layer 301 of the first AlGaN layer 301a having the first Al composition and the second AlGaN layer 301b having the second Al composition. 302 is formed, and a carrier supply layer 303 is formed above the channel layer 302. A gate electrode 304, a source electrode 305, and a drain electrode 306 are formed above the carrier supply layer 303. The second AlGaN layer 301b is thinner than the first AlGaN layer 301a, and the second Al composition is higher than the first Al composition. A fourth AlGaN layer 307 having a fourth Al composition is formed between the superlattice buffer layer 301 and the channel layer 302. The fourth AlGaN layer 307 is thicker than the second AlGaN layer 301b. A fifth AlGaN layer 308 having a fifth Al composition is formed between the superlattice buffer layer 301 and the fourth AlGaN layer 307. The fifth AlGaN layer 308 is thinner than the fourth AlGaN layer. The first Al composition is 0 or more and less than 1, the second Al composition and the fifth Al composition are more than 0 and less than 1, the fourth Al composition is higher than the first Al composition, It is lower than the Al composition and the fifth Al composition. That is, the first AlGaN layer 301a may be a GaN layer, and the second AlGaN layer 301b and the fifth AlGaN layer 308 may be AlN layers. For example, the first Al composition and the second Al composition are within a range in which two-dimensional electron gas is not generated in the vicinity of the interface between the first AlGaN layer 301a and the second AlGaN layer 301b. For example, the fourth Al composition and the fifth Al composition are in a range where the two-dimensional electron gas is not generated near the interface between the fourth AlGaN layer 307 and the fifth AlGaN layer 308.

Channel layer 302 of the first embodiment, showing a fifth AlGaN layer 308, the fourth AlGaN layer 307, a second AlGaN layer 301b, and the outline of the band structure of the first AlGaN layer 301a in FIG. As shown in FIG. 6, since the fourth Al composition is higher than the first Al composition, the potential of the fifth AlGaN layer 308 is compared with the case where the fourth Al composition is equal to the first Al composition. And the lower potential of the channel layer 302 is raised higher. Therefore, it is difficult for current to flow under the channel layer 302. Therefore, like the first reference example , the leakage current can be greatly reduced. Further, since the two-dimensional electron gas is hardly generated near the interface between the fourth AlGaN layer 307 and the fifth AlGaN layer 308, the leakage current can be further suppressed as compared with the first reference example. .

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is an example of a GaN-based HEMT. FIG. 7 is a cross-sectional view showing the structure of the compound semiconductor device according to the second embodiment.

In the second embodiment, as shown in FIG. 7, the structure between the buffer layer 210 and the channel layer 202 is different from that of the second reference example . That is, in the second embodiment, the superlattice buffer layer 401 of the AlGaN layer 401 a and the AlN layer 401 b is formed on the buffer layer 210. An AlGaN layer 407 is formed on the superlattice buffer layer 401, an AlN layer 408 is formed on the AlGaN layer 407, and a channel layer 202 is formed on the AlN layer 408. The Al composition of the AlGaN layer 401a is 0 or more and less than 1, preferably 0 or more and 0.5 or less. The AlGaN layer 401a is, for example, an Al _0.2 Ga _0.8 N layer having a thickness of 20 nm. The thickness of the AlN layer 401b is, for example, 1.5 nm. The Al composition of the AlGaN layer 407 is higher than the Al composition of the AlGaN layer 401a, and lower than the Al composition of the AlN layer 401b and the Al composition of the AlN layer 408. The AlGaN layer 407 is, for example, an Al _0.3 Ga _0.7 N layer having a thickness of 20 nm. The thickness of the AlN layer 408 is, for example, 1.5 nm. The superlattice buffer layer 401 includes about 80 AlGaN layers 401a and AlN layers 401b. The AlN layer 401b is in direct contact with the buffer layer 210, and the other AlN layer 401b is in direct contact with the AlGaN layer 407. Other configurations are the same as those of the second reference example . The AlGaN layer 401a is an example of the first AlGaN layer, the AlN layer 401b is an example of the second AlGaN layer, the AlGaN layer 407 is an example of the fourth AlGaN layer, and the AlN layer 408 is the fifth AlGaN layer. It is an example of a layer. The thickness of the AlN layer 401b is preferably 2.0 nm or less in order to avoid a decrease in breakdown voltage due to generation of residual electrons in the superlattice buffer layer 401. In order to sufficiently relax the lattice strain, the thickness of the AlN layer 201b is preferably 0.8 nm or more.

  In the superlattice buffer layer 401, the composition and thickness of each AlGaN layer 401a are substantially equal to each other, and the composition and thickness of each AlN layer 401b are substantially equal to each other. The composition and thickness of the AlN layer 408 are substantially equal to the composition and thickness of the AlN layer 401b, and the thickness of the AlGaN layer 407 is substantially equal to the thickness of the AlGaN layer 401a.

In the second embodiment, since the Al composition of the AlGaN layer 407 is higher than the Al composition of the AlGaN layer 401a, the AlN layer 408 is compared with the case where the Al composition of the AlGaN layer 407 is equal to the Al composition of the AlGaN layer 401a. And the potential below the channel layer 202 are raised higher. Therefore, it is difficult for current to flow under the channel layer 202. Therefore, like the second reference example , the leakage current can be greatly reduced. Furthermore, since the two-dimensional electron gas is hardly generated near the interface between the AlGaN layer 407 and the AlN layer 408, the leakage current can be further suppressed as compared with the second reference example .

When manufacturing the compound semiconductor device according to the second embodiment, for example, instead of forming the superlattice buffer layer 201 and the AlN layer 207 in the second reference example , the superlattice buffer layer 401, the AlGaN layer 407, and the AlN The layer 408 may be formed.

  Although only one set of the AlGaN layer 407 and the AlN layer 408 is preferably included, a plurality of sets may be included. The total thickness of the AlGaN layer 407 and the AlN layer 408 is preferably 10% or less of the total thickness of the superlattice buffer layer 401. When the total thickness of the AlGaN layer 407 and the AlN layer 408 is more than 10% of the total thickness of the superlattice buffer layer 401, warping is likely to occur.

The first reference example and the first embodiment may be combined. That is, the fifth AlGaN layer 308 in the first embodiment may be thicker than the second AlGaN layer 301b. The fourth AlGaN layer 307 may contain an acceptor impurity. Similarly, the second reference example and the second embodiment may be combined. That is, the AlN layer 408 in the second embodiment may be thicker than the AlN layer 401b. The AlGaN layer 407 may contain acceptor impurities.

( Third embodiment)
The third embodiment relates to a GaN-based HEMT discrete package. FIG. 8 is a diagram illustrating a discrete package according to the third embodiment.

In the third embodiment, as shown in FIG. 8, the back surface of the GaN-based HEMT HEMT chip 1210 of any of the first to second embodiments is land (die pad) using a die attach agent 1234 such as solder. 1233 is fixed. In addition, a wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 106, 206, or 306 is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. Yes. A wire 1235 s such as an Al wire is connected to the source pad 1226 s connected to the source electrode 105, 205, or 305, and the other end of the wire 1235 s is connected to a source lead 1232 s independent of the land 1233. A wire 1235 g such as an Al wire is connected to the gate pad 1226 g connected to the gate electrode 104, 204, or 304, and the other end of the wire 1235 g is connected to a gate lead 1232 g independent from the land 1233. The land 1233, the HEMT chip 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

  Such a discrete package can be manufactured as follows, for example. First, the HEMT chip 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source of the lead frame. Connect to lead 1232s. Thereafter, sealing using a mold resin 1231 is performed by a transfer molding method. Subsequently, the lead frame is separated.

( Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a PFC (Power Factor Correction) circuit including a GaN-based HEMT. FIG. 9 is a connection diagram illustrating a PFC circuit according to the fourth embodiment.

The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251. An AC 1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In the present embodiment, the GaN-based HEMT according to any one of the first to second embodiments is used for the switch element 1251.

  In manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252, the choke coil 1253, and the like using, for example, solder.

( Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to a power supply device including a GaN-based HEMT. FIG. 10 is a connection diagram illustrating a power supply device according to the fifth embodiment.

  The power supply device is provided with a high-voltage primary circuit 1261 and a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

The primary circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the fourth embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

  The secondary side circuit 1262 is provided with a plurality (three in this case) of switch elements 1265a, 1265b, and 1265c.

In this embodiment, the switch element 1251 of the PFC circuit 1250 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260 that constitute the primary side circuit 1261 are either of the first to the second embodiments. A GaN-based HEMT is used. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

( Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment relates to an amplifier including a GaN-based HEMT. FIG. 11 is a connection diagram illustrating an amplifier according to the sixth embodiment.

  The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 1273 includes the GaN-based HEMT according to any one of the first to second embodiments, and amplifies the input signal mixed with the AC signal. In the present embodiment, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier.

  Note that the composition of the compound semiconductor layer used in the compound semiconductor stacked structure is not particularly limited, and for example, GaN, AlN, InN, or the like can be used. These mixed crystals can also be used.

  In any of the embodiments, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, or the like may be used as the substrate. The substrate may be conductive, semi-insulating, or insulating.

  Further, the structures of the gate electrode, the source electrode, and the drain electrode are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Moreover, these formation methods are not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and the drain electrode may be omitted. The gate electrode may contain Pd and / or Pt in addition to Ni and Au. An insulating film may be interposed between the gate electrode and the carrier supply layer.

  Although it depends on the material of the substrate, the thickness of the superlattice buffer layer is preferably 2000 nm or more. This is to sufficiently relax the lattice strain. The total thickness of the pair of first AlGaN layer and second AlGaN layer is preferably not less than 10 nm and not more than 100 nm. If the layers having different lattice constants are stacked too thick, the crystal strain is relaxed due to the difference in lattice constants, and cracks are likely to occur.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A first AlGaN layer of a first Al composition and a superlattice buffer layer of a second AlGaN layer of a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition;
A channel layer formed above the superlattice buffer layer;
A carrier supply layer formed above the channel layer;
A gate electrode, a source electrode and a drain electrode formed above the carrier supply layer;
Have
A third AlGaN layer having a third Al composition that is thicker than the second AlGaN layer and higher than the first Al composition, between the superlattice buffer layer and the channel layer;
The first Al composition is 0 or more and less than 1,
2. The compound semiconductor device according to claim 1, wherein the second Al composition and the third Al composition are more than 0 and 1 or less.

(Appendix 2)
The compound semiconductor device according to appendix 1, wherein an acceptor impurity is contained in the first AlGaN layer located closest to the third AlGaN layer.

(Appendix 3)
The compound semiconductor device according to appendix 1 or 2, wherein the third Al composition is equal to the second Al composition.

(Appendix 4)
A first AlGaN layer of a first Al composition and a superlattice buffer layer of a second AlGaN layer of a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition;
A channel layer formed above the superlattice buffer layer;
A carrier supply layer formed above the channel layer;
A gate electrode, a source electrode and a drain electrode formed above the carrier supply layer;
Have
A fourth AlGaN layer having a fourth Al composition that is thicker than the second AlGaN layer between the superlattice buffer layer and the channel layer;
Between the superlattice buffer layer and the fourth AlGaN layer, there is a fifth AlGaN layer having a fifth Al composition thinner than the fourth AlGaN layer,
The first Al composition is 0 or more and less than 1,
The second Al composition and the fifth Al composition are more than 0 and 1 or less,
4. The compound semiconductor device, wherein the fourth Al composition is higher than the first Al composition and lower than the second Al composition and the fifth Al composition.

(Appendix 5)
The compound semiconductor device according to appendix 4, wherein the fifth AlGaN layer is thicker than the second AlGaN layer.

(Appendix 6)
The compound semiconductor device according to appendix 4 or 5, wherein the fourth AlGaN layer contains an acceptor impurity.

(Appendix 7)
The compound semiconductor device according to any one of appendices 4 to 6, wherein the fifth Al composition is equal to the second Al composition.

(Appendix 8)
The compound semiconductor device according to appendix 2 or 6, wherein the acceptor impurity is Fe, Mg, or C.

(Appendix 9)
9. The compound semiconductor device according to appendix 8, wherein the acceptor impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less.

(Appendix 10)
The compound semiconductor device according to appendix 8, wherein the acceptor impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

(Appendix 11)
11. The compound semiconductor device according to any one of appendices 1 to 10, wherein the first Al composition is 0 or more and 0.5 or less.

(Appendix 12)
The compound semiconductor device according to any one of appendices 1 to 11, wherein the thickness of the second AlGaN layer is not less than 0.8 nm and not more than 2.0 nm.

(Appendix 13)
A power supply device comprising the compound semiconductor device according to any one of appendices 1 to 12.

(Appendix 14)
An amplifier comprising the compound semiconductor device according to any one of appendices 1 to 12.

(Appendix 15)
A first AlGaN layer having a first Al composition and a channel layer above the superlattice buffer layer of a second AlGaN layer having a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition. Forming a step;
Forming a carrier supply layer above the channel layer;
Forming a gate electrode, a source electrode and a drain electrode above the carrier supply layer;
Forming a third AlGaN layer having a third Al composition that is thicker than the second AlGaN layer and higher than the first Al composition between the superlattice buffer layer and the channel layer;
Have
The first Al composition is 0 or more and less than 1,
The method of manufacturing a compound semiconductor device, wherein the second Al composition and the third Al composition are more than 0 and 1 or less.

(Appendix 16)
A first AlGaN layer having a first Al composition and a channel layer above the superlattice buffer layer of a second AlGaN layer having a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition. Forming a step;
Forming a carrier supply layer above the channel layer;
Forming a gate electrode, a source electrode and a drain electrode above the carrier supply layer;
Forming a fourth AlGaN layer having a fourth Al composition thicker than the second AlGaN layer between the superlattice buffer layer and the channel layer;
Forming a fifth AlGaN layer having a fifth Al composition thinner than the fourth AlGaN layer between the superlattice buffer layer and the fourth AlGaN layer;
Have
The first Al composition is 0 or more and less than 1,
The second Al composition and the fifth Al composition are more than 0 and 1 or less,
4. The method of manufacturing a compound semiconductor device, wherein the fourth Al composition is higher than the first Al composition and lower than the second Al composition and the fifth Al composition.

101, 201, 301, 401: Superlattice buffer layer 101a, 301a: First AlGaN layer 101b, 301b: Second AlGaN layer 102, 202, 302: Channel layer 103, 203, 303: Carrier supply layer 107: First 3 AlGaN layer 201a: AlGaN layer 201b: AlN layer 207: AlN layer 307: Fourth AlGaN layer 308: Fifth AlGaN layer 407: AlGaN layer 408: AlN layer

Claims (5)

A first AlGaN layer of a first Al composition and a superlattice buffer layer of a second AlGaN layer of a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition;
A channel layer formed above the superlattice buffer layer;
A carrier supply layer formed above the channel layer;
A gate electrode, a source electrode and a drain electrode formed above the carrier supply layer;
Have
A fourth AlGaN layer having a fourth Al composition that is thicker than the second AlGaN layer between the superlattice buffer layer and the channel layer;
A fifth AlGaN layer having a fifth Al composition that is thicker than the second AlGaN layer and thinner than the fourth AlGaN layer , between the fourth AlGaN layer and the channel layer ;
The first Al composition is 0 or more and less than 1,
The second Al composition and the fifth Al composition are more than 0 and 1 or less,
4. The compound semiconductor device, wherein the fourth Al composition is higher than the first Al composition and lower than the second Al composition and the fifth Al composition. The compound semiconductor device according to claim 1 , wherein an acceptor impurity is contained in the fourth AlGaN layer. Power supply, characterized in that it comprises a compound semiconductor device according to claim 1 or 2. Amplifier, characterized in that it comprises a compound semiconductor device according to claim 1 or 2. A first AlGaN layer having a first Al composition and a channel layer above the superlattice buffer layer of a second AlGaN layer having a second Al composition which is thinner than the first AlGaN layer and higher than the first Al composition. Forming a step;
Forming a carrier supply layer above the channel layer;
Forming a gate electrode, a source electrode and a drain electrode above the carrier supply layer;
Forming a fourth AlGaN layer having a fourth Al composition thicker than the second AlGaN layer between the superlattice buffer layer and the channel layer;
Forming a fifth AlGaN layer having a fifth Al composition that is thicker than the second AlGaN layer and thinner than the fourth AlGaN layer between the fourth AlGaN layer and the channel layer ;
Have
The first Al composition is 0 or more and less than 1,
The second Al composition and the fifth Al composition are more than 0 and 1 or less,
4. The method of manufacturing a compound semiconductor device, wherein the fourth Al composition is higher than the first Al composition and lower than the second Al composition and the fifth Al composition.

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