JP6176585B2 - Light receiving element and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light receiving element that receives light in an infrared region and a method for manufacturing the same.

Infrared light, including near infrared light, corresponds to the absorption spectrum region related to living organisms and environments such as animals and plants, and therefore, an infrared light detector using a III-V compound semiconductor in the light receiving layer has been developed. It has been broken. In particular, longer wavelengths of light receiving sensitivity are being promoted from near infrared. In many cases, these light receiving elements are planar photodiodes that form pixels separated by regions that are not selectively diffused by forming a pn junction by selective diffusion focusing on a low dark current. However, the planar photodiode has a limited improvement in sensitivity because the area ratio of the opening occupied by the incident surface or the selective diffusion region, that is, the fill factor is small.
On the other hand, the mesa photodiode compared with the planar photodiode has the following two advantages. One is that the fill factor can be improved more than that of a planar photodiode. Another advantage is that the controllability of the pn junction position is excellent because the pn junction is formed by epitaxial growth. When the pn junction position is shifted, the sensitivity and the response speed change in bias voltage, which affects the stability of product characteristics. On the other hand, the mesa photodiode has a drawback that the leakage current tends to increase because the pn junction is exposed on the wall surface of the groove of the mesa structure.

In order to overcome the drawbacks of the mesa light receiving element described above, attempts have been proposed to suppress leakage current by covering the wall surface of the groove of the mesa structure with a protective film. As for the InP-based light receiving element, for example, a silicon nitride film or a silicon nitride film containing hydrogen has been proposed as a passivation film on the mesa etching surface (Patent Documents 1 and 2). In addition, a method has been proposed in which the wall surface of the groove of the mesa structure is covered with a first conductivity type, a second conductivity type, a semi-insulating type or a non-doped semiconductor layer (Patent Document 3). Furthermore, in the InAs / GaSb type 2 quantum well light-receiving layer using a GaSb substrate, a method is proposed in which the wall surface of the groove of the mesa structure is covered with AlGaInAsSb for protection (Patent Document 4).
Conceptually, it may be possible to suppress leakage current by covering the wall surface of the groove of the mesa structure with a protective film as described above.

JP 2006-269978 A WO2009 / 081585 JP 2011-35114 A Special table 2008-508700 gazette

  However, actually, the wall surface of the groove of the mesa structure cannot be completely covered with the above-described protective film, and it is difficult to prevent the leakage current. When coating the walls of the mesa groove with a semiconductor layer or insulating film, from the mesa etching process chamber to the semiconductor layer deposition chamber (OMVPE chamber, MBE chamber, etc.) or insulating film formation chamber (plasma CVD chamber, etc.) During the movement, the mesa wall surface is oxidized and / or contaminated with impurities, and a current leakage path is formed between the wall surface of the groove of the mesa structure and the protective film. Further, in many cases, the light receiving element has a laminated structure of a plurality of semiconductor layers, and when mesa etching is performed, the etching amount varies depending on the material of each semiconductor layer, so that the wall surface of the groove of the mesa structure can be uneven. . It is difficult to cover the uneven wall surface, and a minute gap is formed. This minute gap causes a leak current. Furthermore, the protective film itself may cause stress, and this stress also promotes current leakage. So far, it is difficult to reliably suppress the leakage current by the method of covering the wall surface of the groove of the mesa structure with the protective film.

  An object of the present invention is to provide a light receiving element that can suppress a leakage current in a wall surface of a groove of a mesa structure after adopting a mesa structure having a large fill factor, and a method for manufacturing the light receiving element.

The light-receiving element of the present invention is a light-receiving element in which pixels are formed on a semiconductor substrate, and has a multiple quantum well structure in which semiconductor layers having different compositions are stacked. The light-receiving layer for receiving light; A pn junction located within the layer; a first conductivity type region provided on the opposite side of the pn junction from the semiconductor substrate and having a first conductive side electrode; and disposed between the light receiving layer and the semiconductor substrate. A buffer layer of the second conductivity type and a mesa structure that separates the pixel and the periphery of the pixel by a groove, and unevenness is formed on the wall surface of the mesa structure by exposing the stacked semiconductor layer. In addition, an impurity wall surface layer into which an impurity of the first conductivity type is introduced is formed over the wall surface of the groove of the mesa structure so that the end of the pn junction is not exposed to the wall surface of the groove. The semiconductor The impurity concentration of the impurity wall surface layer in the range of the light receiving layer on the substrate side is smaller than the concentration of the impurity of the first conductivity type in the region where the first conductivity side electrode in the first conductivity type region is in ohmic contact. The impurity concentration of the second conductivity type of the buffer layer is set higher than the impurity concentration of the impurity wall surface layer.

  According to the above configuration, if there is no impurity wall surface layer, the end of the pn junction in the light receiving layer is exposed on the groove wall surface of the mesa structure, but the impurity wall surface layer is formed on the wall surface of the mesa structure groove. The end of the is not exposed to the wall. The end of the pn junction is located inward from the wall surface by the thickness of the impurity wall surface layer. That is, the path through which current leaks from the end of the pn junction through the wall surface of the groove is blocked by the impurity layer. For this reason, it is possible to suppress the leakage current while improving the fill factor by the mesa structure. To protect the pn junction by the impurity wall surface layer, it is not necessary to form an additional film on the wall surface simply by introducing impurities into the wall surface of the groove after mesa etching. For this reason, compared with the case where another semiconductor layer or a protective film is formed on the wall surface, there is no room for gaps and the like, and current leakage can be reliably suppressed with high reproducibility. The prevention of the exposure of the end of the pn junction by the impurity wall surface layer may be epoch-making in that there is no room for this gap.

Further, the mesa structure has an advantage over the planar photodiode in the following points. Although selective diffusion has to be performed to fabricate a planar photodiode, when a large-diameter semiconductor substrate is used to increase mass production efficiency, the diameter is also increased to accommodate the large-diameter semiconductor substrate (epitaxial wafer). A quartz tube is required. A semiconductor substrate (epitaxial wafer) provided with a mask pattern in a quartz tube and an impurity material such as a Zn material are sealed to selectively diffuse impurities, and then the quartz tube is broken to take out the epitaxial wafer. Large diameter quartz tubes are expensive and negate the benefits of mass production efficiency. Since introduction of impurities in the mesa structure is performed by doping during epitaxial growth, a quartz tube is unnecessary and the above problem does not occur.
In addition, the mesa structure is excellent in controllability of the pn junction position because the pn junction is formed by epitaxial growth as described above. If the pn junction position is shifted, the sensitivity and the response speed depend on the bias voltage, which affects the stability of the product characteristics. Therefore, the ability to accurately place the pn junction position directly leads to an improvement in the product level.

When the light receiving element is composed of a single pixel, the mesa-structured groove is provided to separate the pixel from the periphery of the light receiving element. That is, the periphery of the pixel is the periphery of the light receiving element. In the case of a light receiving element array in which a plurality of pixels are arranged, the groove is provided between adjacent pixels so as to separate the pixels from each other.
The above pn junction should be interpreted broadly as follows. In the light-receiving layer, the opposite conductivity type region that forms a pn junction in contact with the impurity region provided with the pixel electrode may be an impurity region (referred to as an i region) that is low enough to be regarded as an intrinsic semiconductor. Accordingly, when the region where the pixel electrode is provided is a p-type region, it may be a pn junction or pi junction, and when the region where the pixel electrode is provided is an n-type region, it may be an np junction or ni junction. That is, the pn junction may be a pi junction or a ni junction, and further includes a case where the p concentration or the n concentration in the pi junction or ni junction is very low at the position of the junction.

The pixel includes a first conductivity type region on a side opposite to the semiconductor substrate with respect to the pn junction, and a first conductivity side electrode is provided in the first conductivity type region, and is formed on a wall surface of the groove of the mesa structure. Then, an impurity wall surface layer into which the first conductivity type impurity is introduced is formed . The first conductive side electrode may be provided in ohmic contact with the first conductive type region.
Thus, the impurity layer can be easily formed without greatly affecting the region where the pixel electrode is in ohmic contact.

In the case where the impurity wall surface layer is formed by introducing the first conductivity type impurity, the concentration of the first conductivity type impurity of the first conductivity type wall surface layer in the range from the pn junction to the light receiving layer on the semiconductor substrate side is The concentration of the first conductivity type impurity in the region where the first conductivity side electrode in the first conductivity type region is in ohmic contact can be made smaller.
As a result, while preventing the end of the pn junction from being exposed, the deterioration of the crystallinity on the wall surface of the groove is prevented, and the conductivity of the ground electrode is provided when, for example, a ground electrode that is paired with the pixel electrode is provided in the buffer layer. Can be prevented.

The concentration of the first conductivity type impurity of the impurity wall surface layer in the range from the pn junction to the light receiving layer on the semiconductor substrate side is preferably 5e15 cm ⁻³ or more and 5e17 cm ⁻³ or less.
When the light-receiving layer has a multiple quantum well structure such as (InGaAs / GaAsSb) or (InAs / GaSb), at an impurity concentration higher than 5e17 cm ⁻³ , the multiple quantum well collapses and the crystallinity deteriorates. Leakage current increases.

A buffer layer of a second conductivity type is provided in contact with the semiconductor substrate, the buffer layer having a portion exposed in the groove of the mesa structure, and the same surface as the first conductivity type wall surface layer on the surface exposed in the groove The second conductivity type can be maintained while the impurities are introduced.
In some cases, an electrode (ground electrode) that forms a pair with the pixel electrode is formed in the buffer layer. Since it is a ground electrode, it is not necessary to provide it for each pixel, and one ground electrode is provided in common for all pixels. At least the position where the ground electrode is formed needs to maintain the second conductivity type. In this case, the semiconductor substrate may be either the second conductivity type or semi-insulating.
In some cases, a ground electrode is provided on the back surface of the semiconductor substrate of the second conductivity type. In this case, if the buffer layer does not maintain the second conductivity type, it is difficult to apply a reverse bias voltage to the pn junction. .

The pixel includes a first conductivity type region on a side opposite to the semiconductor substrate with respect to the pn junction, and a first conductivity side electrode is in ohmic contact with the first conductivity type region, and is formed on the wall surface of the groove of the mesa structure. The second conductivity type wall surface layer into which the second conductivity type impurity is introduced may be formed.
The above configuration protects the pn junction by introducing impurities of the same conductivity type as the pixel region into the wall surface of the trench. However, in order to protect the pn junction, an impurity having a conductivity type opposite to that of the pixel region may be introduced into the wall surface of the trench. As a result, options for forming the impurity layer can be increased.

Furthermore, a coating layer may be formed so as to cover the impurity layer on the wall surface of the groove of the mesa structure.
By providing a coating layer that covers the impurity layer, the degree of protection can be increased.

The light receiving element can be formed of a group III-V semiconductor stack including a light receiving layer on a group III-V semiconductor substrate.
As a result, it is possible to obtain a light receiving element with low current leakage and high sensitivity with an InP substrate or the like as a light receiving target in the near infrared to infrared region.

The first conductivity type impurity may be zinc (Zn).
As a result, it is possible to obtain a light receiving element with high accuracy, high efficiency, low current leakage, and high sensitivity, using Zn, which has been used abundantly and has a lot of related data accumulated.

The light receiving layer may have an InGaAs / GaAsSb type 2 multiple quantum well structure.
In the multi-quantum well structure, fine irregularities tend to be remarkably generated on the wall surface of the groove formed by mesa etching. Even if an attempt is made to cover the wall surface with a semiconductor film or a protective film, the fine irregularities are not completely covered. On the other hand, when the impurity wall surface layer is formed by introducing the impurity of the present invention into the wall surface, the impurity penetrates into the uneven surface, covers the uneven surface, and definitely prevents the end of the pn junction from being exposed. it can. For this reason, the light receiving element of the present invention is very suitable when a light receiving layer having a multiple quantum well structure is provided. The light-receiving layer having an InGaAs / GaAsSb type 2 multiple quantum well structure has good sensitivity in the near-infrared to infrared regions where important absorption spectra of water, living organisms, foods and the like are located. In short, it is possible to obtain a light receiving element having good sensitivity in the near infrared region to the infrared region and having a small current leak. Further, since the above wavelength range corresponds to a wavelength range such as cosmic light, it is also useful for a night vision support device.

The light receiving element manufacturing method of the present invention manufactures a light receiving element having pixels. The manufacturing method includes a step of forming a semiconductor stacked body including a light receiving layer for receiving light on a semiconductor substrate, and a step of forming a mesa structure by providing a groove so as to separate a region to be a pixel from the periphery. And a step of introducing an impurity into the wall surface of the groove of the mesa structure to form an impurity wall surface layer.
Thus, the impurity wall surface layer can be easily formed on the groove wall surface of the mesa structure. As described above, the process of introducing impurities into the wall surface of the mesa structure has no room for gaps, and the impurity introduction process itself is much more difficult than the process of forming a semiconductor layer or a protective film on the wall surface of the groove. Easy to. Thereby, it is possible to reliably prevent the pn junction from being exposed by a simple process and suppress current leakage.
As described above, the light receiving element may be a light receiving element including a single pixel or a light receiving element in which a plurality of pixels are arrayed. The arrangement of the grooves of the mesa structure is as described above.

In the mesa structure forming step, a mask pattern having an opening is provided in the groove portion, and the groove is provided by dry etching. Next, in the impurity wall surface layer forming step, the intermediate pattern in which the mask pattern is left as it is and the groove is provided. Can be placed in a furnace for introducing impurities, and the impurity wall surface layer can be formed using the mask pattern as a mask.
Thereby, the mesa structure and the impurity wall surface layer can be provided efficiently. The mask pattern is preferably formed of SiN or the like.

  According to the present invention, it is possible to obtain a light receiving element that can suppress a leakage current in a wall surface of a groove of a mesa structure with a simple structure while adopting a mesa structure having a large fill factor.

It is a figure which shows the light receiving element in Embodiment 1 of this invention. 2A and 2B are schematic views in which a wall surface of a groove of the light receiving element shown in FIG. 1 is enlarged, in which FIG. 1A is an epitaxial laminate, and FIG. 2B is an enlarged view of an MQW light receiving layer on the groove wall surface. It is a flowchart for demonstrating the manufacturing method of the light receiving element shown in FIG. It is a figure which shows the state which formed the impurity wall surface layer after mesa etching. It is a figure which shows the light receiving element in Embodiment 2 of this invention. It is a figure which shows the light receiving element in Embodiment 3 of this invention. It is a figure which shows the light receiving element in Embodiment 4 of this invention. 8A is a diagram illustrating a state in which an impurity wall surface layer is formed after mesa etching, and FIG. 8B is a diagram illustrating a pi-junction end portion of the light receiving layer for explaining the light receiving element illustrated in FIG. 7. It is a figure which shows the light receiving element in Embodiment 5 of this invention.

(Embodiment 1-Case of MQW light-receiving layer, wall surface layer of same conductivity type as p-type pixel)
FIG. 1 is a diagram showing a light receiving element in Embodiment 1 of the present invention, which is a light receiving element 10 in which a plurality of pixels are arrayed. However, the present invention includes not only a light receiving element in which a plurality of pixels are arrayed as shown in FIG. 1 but also a light receiving element composed of a single pixel (single light receiving element portion).
According to FIG. 1, the light receiving element 10 has the following group III-V semiconductor stacked structure.
(InP substrate 1 / InP buffer layer 2 / InGaAs and GaAsSb type 2 MQW light receiving layer 3 / InGaAs concentration distribution adjusting layer 4 / InP window layer 5)
When the above epitaxial laminated body is formed, the pn junction 15 is formed in the light receiving layer 3 by doping impurities according to the distribution shown in FIG. In the InP window layer 5, Zn having a high concentration (p ⁺ ) of about 1e18 cm ⁻³ is preferably introduced so that the pixel electrode or the p-side electrode 11 is in ohmic contact. In addition, since a high-concentration p-type impurity causes deterioration in crystallinity for the MQW light-receiving layer 3, it is desirable to keep it at 5e16 cm ⁻³ or less. In doping during epitaxial growth, impurities are thermally diffused into the MQW light-receiving layer 3 during epitaxial growth to lower the crystallinity. For this reason, it is not preferable to sharply increase the impurity concentration from the low concentration impurity MQW light-receiving layer 3 to the epitaxial layer thereabove. However, since the thermal diffusion can be suppressed when the epitaxial growth temperature is lower than 500 ° C., the concentration distribution adjusting layer 4 can be dispensed with in that case.
The buffer layer 2 is an n ⁺ type region in order to provide a ground electrode that is paired with the pixel electrode 11.

As described above, even in an area on the substrate 1 side of the light receiving layer 3 on the opposite side of the pixel electrode 11 with the pn junction 15 interposed therebetween, even an impurity region (called an i region) that is low enough to be regarded as an intrinsic semiconductor. Good. Although it is called a pn junction, it is essentially a pi junction, which is a so-called pin type photodiode. Therefore, the pn junction 15 in the MQW light receiving layer 3 is formed by the low concentration p ⁻ type region and the i type region. This is very convenient in preventing the pn junction 15 from being exposed by the p-type wall layer 8 as will be described later.

A p-side electrode 11 made of AuZn is provided on the InP window layer 5 in the p ⁺ -type region, and an n-side electrode (ground electrode) 12 made of AuGeNi is provided in ohmic contact with the n ⁺ -type region InP buffer layer. Yes. In this case, the InP substrate 1 may be doped with n-type impurities or may be semi-insulating. An SiON antireflection film 35 is also provided on the back surface of the InP substrate 1 to prevent light reflection.

<Points in this embodiment>
In order to obtain the independence of the pixel P, a mesa structure in which a groove 7 is provided between the pixels P is provided. Then, a p-type wall surface layer 8 in which Zn is introduced over the wall surface of the groove 7 is formed. Needless to say, the impurity in the p-type wall layer 8 is the same as the conductivity type of the InP window layer 5 in which the pixel electrode 11 is in ohmic contact. Moreover, as described above, the pn junction 15 is formed of the low concentration p ⁻ type region 3a and the i type region 3b. In this i-type region 3b, n-type carriers are generally distributed by about 2e15 cm ⁻³ even though no impurity is introduced. The p-type wall surface layer 8 must have a p-type impurity concentration necessary for offsetting the n-type carrier 2e15 cm ⁻³ of the i-type region 3b to form a p-type region. For this reason, the p-type wall surface layer 8 should have a p-type impurity concentration of, for example, 5e15 cm ⁻³ or more, and more certainly about 1e16 cm ⁻³ or more. On the other hand, if the p-type impurity concentration of the p-type wall layer 8 exceeds 5e17 cm ⁻³ , the crystallinity of the multiple quantum well structure is deteriorated, which may increase current leakage. For this reason, the p-type impurity concentration of the p-type wall surface layer 8 is preferably 5e15 cm ⁻³ or more or about 1e16 cm ⁻³ or more and 5e17 cm ⁻³ or less. Moreover, the p-type wall surface layer 8 can prevent the end of the pn junction 15 from being exposed to the wall surface of the groove by setting the thickness to about 0.1 μm to 1 μm.
Since the p-type impurity is simply introduced into the wall surface of the groove 7, there is no room for a gap as compared with a case where the p-type impurity is to be covered with another semiconductor film or a protective film. This makes it possible to reliably suppress current leakage with a simple structure while improving the fill factor with the mesa structure. For example, in the case of a pixel pitch of 30 μm, the fill factor is a circle having a radius of about 9 μm (area 254 μm ² ) in the conventional planar type and a fill factor of 28%, whereas the mesa structure has a square of 24 μm × 24 μm (area 576 μm). ² ), the fill factor can be dramatically improved to 64%.
As shown in FIG. 1, the InP buffer layer 2 is of n conductivity type, and the n-type carrier concentration is about 1e18 cm ⁻³ . For this reason, even if the p-type impurity concentration of the p-type wall layer 8 is 5e17 cm ⁻³ or more or about 1e16 cm ⁻³ or more and 5e17 cm ⁻³ or less is introduced, the conductivity type of the buffer layer 2 is reversed, There will be no major changes.
In the light receiving element 10 in the present embodiment, the region of the window layer 5 in which the pixel electrode 11 is disposed is p conductivity type, the impurity wall surface layer 8 is p conductivity type, and both are the same conductivity type.

2A and 2B are schematic views in which the wall surface of the groove 7 of the light receiving element 10 shown in FIG. 1 is enlarged. As shown in FIG. 2A, in the InGaAs / GaAsSb type 2 MQW light-receiving layer 3, unevenness occurs on the wall surface because InGaAs and GaAsSb have different etching rates in mesa etching (dry etching). Since the thickness of each layer of the MQW light-receiving layer 3 is about 5 nm, very fine irregularities can be formed. As in the prior art, it is impossible to completely cover such fine irregularities with another semiconductor film, oxide film or nitride film. It is inevitable that a gap due to the unevenness is generated between another semiconductor film and the wall surface, and current leakage cannot be reduced.
However, even if there are fine irregularities, when impurities are introduced, impurities diffuse from the concave corners and concave wall surfaces of the irregularities and enter the MQW light receiving layer 3 as shown in FIG. For this reason, even if there is a convex part and a concave part, the front line for intrusion of impurities is averaged and smoothed, and it always enters a predetermined depth from any surface. For this reason, even if there are irregularities, the impurity wall surface layer 8 can be formed to a predetermined depth without any problem, and there is no room for gaps.

2A, the pn junction or the pi junction 15 is formed in the light receiving layer 3 at the boundary between the p ⁻ type layer (upper part) 3a and the i type layer (lower part) 3b. The undoped i-type layer (lower part) 3b has an n-type carrier concentration of about 2e15 cm ⁻³ as described above, but the p-type impurity concentration of the p-type wall layer 8 is 5e15 cm ⁻³ or more or 1e16 cm ⁻³ or more. By setting it to 5e17 cm ⁻³ or less, the predetermined depth of the wall surface can be made p-type by offsetting with a margin. The p ^- type layer (upper part) 3a is originally p-type. The p-type wall surface layer 8 is formed on the wall surface with a thickness of 0.1 μm to 1 μm. For this reason, the end of the pn junction or the pi junction is pushed inside the entire wall surface by the thickness of the p-type wall surface layer 8. Therefore, the pn junction 15 is not exposed on the wall surface of the groove 7.

Next, based on FIG. 3 and FIG. 4, the manufacturing method of the light receiving element in this Embodiment is demonstrated. First, on the InP substrate 1, an epitaxial laminated body composed of InP buffer layer 2 / type 2 MQW light receiving layer 3 / InGaAs concentration distribution adjusting layer 4 / InP window layer 5 is formed. During the epitaxial growth, impurities are doped so that the impurity concentration distribution shown in FIG. 1 is obtained. Next, as shown in FIG. 4, a mesa etching mask pattern 36 having an opening in a region corresponding to the groove 7 is formed. Next, a mesa structure is formed so as to provide the groove 7 by dry etching. In forming the groove 7, dry etching is preferably performed using SiCl ₄ (silicon tetrachloride), and a damage layer caused by dry etching generated at this time is preferably removed by HBr (hydrobromic acid). Thereafter, the process of forming the p-type wall surface layer 8 is started. The intermediate product with the mesa structure is introduced into an OMVPE (Organic Metal Vapor Phase Epitaxy) furnace to introduce impurities, and together with arsine (AsH3) and phosphine (PH3), diethylzinc (DEZn) and dimethylzinc ( DMZn). As a result, p-type impurities are introduced into the wall surface of the groove 7 at a predetermined depth, whereby the p-type wall surface layer 8 is formed.

  In addition to the unevenness of the wall surface in the MQW light-receiving layer 3 described above, as described in the second embodiment, there is a difficulty in forming another semiconductor film or the like on the wall surface of a narrow mesa structure groove. The difficulty of forming another protective film described in the second embodiment and the ease of forming the impurity wall surface layer in the present invention also apply to this first embodiment.

  In addition, selective diffusion must be performed to fabricate a planar photodiode, but when a large-diameter semiconductor substrate is used to increase mass production efficiency, the diameter of the large-diameter semiconductor substrate (epitaxial wafer) is also reduced. A large quartz tube is required. A semiconductor substrate (epitaxial wafer) provided with a mask pattern in a quartz tube and an impurity material such as a Zn material are sealed to selectively diffuse impurities, and then the quartz tube is broken to take out the epitaxial wafer. That is, this quartz tube is a consumable item, and a new one is used for each selective diffusion. Large diameter quartz tubes are expensive and negate the benefits of improving mass production effectiveness. On the other hand, since the introduction of impurities in the mesa structure in the present invention is performed by doping during epitaxial growth, a quartz tube is unnecessary and the above problem does not occur.

As shown in FIGS. 2A and 4, the p-type impurity is also introduced into the portion where the InP buffer layer 2 is exposed to the groove 7 at this time. However, as described above, since the concentration of the p-type impurity introduced in the formation of the p-type wall surface layer 8 is 5e15 cm ⁻³ or more or 1e16 cm ⁻³ or more and 5e17 cm ⁻³ or less, the ground electrode 12 is in ohmic contact. It does not affect the conductivity type of the buffer layer containing an n-type impurity with a high concentration of about 1e18 cm ⁻³ , and the conductivity is not significantly changed.

(Embodiment 2-Case of single-layer light-receiving layer and wall surface layer of same conductivity type as p-type pixel)
FIG. 5 is a diagram showing a light receiving element according to Embodiment 2 of the present invention, which is a light receiving element 10 in which a plurality of pixels are arrayed. In the present embodiment, the light receiving layer 3 is formed of a single group III-V compound semiconductor. Even if the light receiving layer 3 is a single semiconductor layer, it is difficult to completely cover the wall surface of the mesa structure even if another semiconductor film or the like is covered. The reason is that since the groove 7 is a narrow part, it is unavoidable that a spot that becomes a blind spot occurs in the flow of the material to be the coating film, and the material flow itself causes interference and the like. This becomes a serious problem as the semiconductor film is formed and the thickness is increased. For this reason, gaps are inevitable. In this respect, there is no room for the introduction of impurities as described above, and the space of the groove 7 does not change even when the introduction of p-type impurities proceeds. For this reason, the p-type wall surface layer 8 can be formed easily, and exposure of the end of the pn junction or the pi junction 15 can be prevented. The p-type impurity concentration and thickness of the p-type wall surface layer 8 are the same as those in the first embodiment. However, since there is no unevenness due to MQW in the light receiving layer 3, the depth or thickness may be slightly reduced. Also, the necessity for the density distribution adjusting layer 4 is reduced because the light receiving layer 3 is not MQW. The manufacturing method is the same as that of the first embodiment except for the light receiving layer 3.

(Embodiment 3-MQW light receiving layer, in the case of wall surface layer of the same conductivity type as the n-type pixel)
FIG. 6 is a diagram showing a light receiving element according to the third embodiment of the present invention, which is a light receiving element 10 in which a plurality of pixels are arrayed. The laminated structure in the present embodiment is as follows.
(P ⁺ type GaSb substrate 1 / p ⁺ GaSb buffer layer 2 / InAs and GaSb type 2 MQW light receiving layer 3 / n ⁺ type InAs window layer 5)
The type 2 (InAs / GaSb) MQW light receiving layer 3 has a cutoff wavelength of 3 μm or more, and has light receiving sensitivity to light in the near infrared to mid infrared (for example, wavelength 3 μm to 12 μm). This MQW is preferably formed, for example, by a single (InAs / GaSb) as one pair and about 100 to 300 pairs. The thickness of InAs and GaSb is preferably in the range of 1 nm to 10 nm, for example, about 3 nm. In order to make tens of pairs 3a on the InAs window layer 5 side of the whole MQW3 into an n ⁻ type layer, it is preferable to dope InAs with an n type impurity such as Si. Further, it is preferable to dope p-type impurities such as Be into GaSb of several tens of pairs 3c on the GaSb substrate 1 side. Both intermediate layers 3b are not doped with impurities to be i (intrinsic) type. That is, the MQW light-receiving layer 3 is an n ⁻ type 3a / i type 3b / p ⁻ type 3c in order from the top. By forming such a conductivity type distribution in MQW, a nip photodiode can be obtained. The pn junction or ni junction is formed in the MQW 3 by the impurity doping or undoping described above. That is, the above pn junction or ni junction is formed by the interface of presence / absence of impurity doping during film formation or switching of impurity species.

The electrode (pixel electrode) 11 of the pixel P is preferably formed of an Au / Ge / Ni alloy or the like so as to make ohmic contact with the n ⁺ type window layer 5. The ground electrode 12 is preferably formed of a Ti / Pt / Au alloy, an AuZn alloy or the like so as to be in ohmic contact with the p ⁺ type GaSb substrate 1. In FIG. 5, the n-type impurity of the GaSb buffer layer 2 is set to a high concentration of about 1e18 cm ⁻³ so that the ground electrode 12 is in ohmic contact with the GaSb buffer layer 2. However, the n-type impurity concentration of the GaSb substrate 1 may be set to a high concentration of about 1e18 cm ⁻³ so that the ground electrode 12 is in ohmic contact with the GaSb substrate 1.
Further, an InAs layer is used for the window layer 5, and the n-type impurity concentration is preferably set to a high concentration of about 1e18 cm ⁻³ so that the pixel electrode 11 is in ohmic contact.
Light enters from the back surface of the GaSb substrate 1. Since the GaSb substrate 1 easily absorbs infrared light, the GaSb substrate 1 is thinned by polishing or the like so as to have a thickness of about several tens of μm in order to reduce absorption. Next, the back surface of the GaSb substrate 1 polished with an AR (Anti-reflection) film 35 is covered to prevent reflection of incident light.
As features of the present embodiment, the <point in the present embodiment> shown in the embodiment is applied as it is. What has been described with reference to FIGS. 2A and 2B also applies.

(Embodiment 4-MQW light-receiving layer, p-type pixel and reverse conductivity type wall surface layer-)
FIG. 7 is a diagram showing a light receiving element according to Embodiment 4 of the present invention, which is a light receiving element 10 in which a plurality of pixels are arrayed. This light receiving element 10 is different from the first embodiment in that it has the same epitaxial laminated structure including the conductivity type, and that the conductivity type of the wall surface layer is an n type opposite to the p conductivity type of the pixel region. . That is, the epitaxial multilayer structure is as follows.
(InP substrate 1 / InP buffer layer 2 / InGaAs and GaAsSb type 2 MQW light receiving layer 3 / InGaAs concentration distribution adjusting layer 4 / InP window layer 5)
The arrangement and materials of the electrodes and the like are the same as in the first embodiment.

<Points in this embodiment>
FIGS. 8A and 8B are diagrams for explaining the points of the present invention. (A) is a figure which shows the state which introduce | transduced the n-type impurity under arrangement | positioning of the mask pattern 36, (b) is an enlarged view of the edge part of the pn junction or the pi junction 15. FIG. In this embodiment, an n-type wall layer 8 is formed by introducing an n-type impurity such as silicon (Si) opposite to the p conductivity type of the pixel region or InP window layer 5 over the wall surface of the groove 7 having a mesa structure. To do.
As described above, the pn junction 15 is formed at the interface between the low concentration p ⁻ -type region 3a and the i-type region 3b. In this p ⁻ -type region 3a, the p-type impurity concentration is 5e16 cm ⁻³ or less, usually 1e16 cm ⁻³ or less. This is necessary to keep the crystallinity of InGaAs / GaAsSb type 2 MQW good. The n-type wall surface layer 8 must have an n-type impurity concentration necessary to offset the p-type impurity concentration of about 5e16 cm ⁻³ of the p ⁻ -type region 3a to make an n-type region. For this purpose, the n-type wall surface layer 8 should have an n-type impurity concentration of, for example, about 5e16 cm ⁻³ or more. Further, when the n-type impurity concentration of the n-type wall surface layer 8 exceeds 5e17 cm ⁻³ , the crystallinity deteriorates and current leakage may increase. Therefore, the n-type impurity concentration of the n-type wall surface layer 8 is preferably 5e16 cm ⁻³ or more and 5e17 cm ⁻³ or less. And the n-type wall surface layer 8 can prevent the end of the pn junction 15 from being exposed to the wall surface of the groove by setting the thickness to about 0.1 μm to 1 μm.

Since the n-type impurity is simply introduced into the wall surface of the groove 7, there is no room for a gap as compared with a case where the n-type impurity is covered with another semiconductor film or a protective film. This makes it possible to reliably suppress current leakage with a simple structure while improving the fill factor with the mesa structure.
As shown in FIGS. 7 and 8A, the InP buffer layer 2 is of the n conductivity type, and even if an n-type impurity is introduced into the portion exposed in the trench 7, there is no influence.
The first embodiment and the fourth embodiment are exactly the same except for the conductivity type of the impurity wall surface layer 8. According to the present embodiment, options of the conductivity type of the impurity wall surface layer 8 can be expanded.

(Embodiment 5: a single-layer light-receiving layer, a wall surface layer of the same conductivity type as a p-type pixel, and a protective film plus)
FIG. 9 is a diagram showing a light receiving element according to the fifth embodiment of the present invention, which is a light receiving element 10 in which a plurality of pixels are arrayed. The light receiving element 10 is different from the second embodiment only in that the protective film 9 is added. In addition to the protection by the impurity wall surface layer 8 described in the second embodiment, a thicker protection can be obtained by the added protective film 9. The protective film 9 may be a semiconductor film or an insulating film such as SiN or SiOx. The thickness is preferably about 0.1 μm to 0.5 μm.

  Although the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is the implementation of these inventions. It is not limited to the form. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  According to the light receiving element or the like of the present invention, while having a mesa structure capable of obtaining a high fill factor, it is possible to suppress the disadvantage of a high current leak peculiar to the mesa structure with an unprecedented simple and reliable mechanism. For this reason, it is possible to provide a light-receiving element with high sensitivity and high image quality, particularly a light-receiving element in the near infrared to mid-infrared region.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate (InP, GaSb substrate, etc.), 2 buffer layer, 3 light receiving layer, 3a p ⁻ type or n ⁻ type, 3b i type, 3c p ⁻ type, 4 concentration distribution adjustment layer, 5 window layer, 7 mesa structure Groove, 8 impurity wall surface layer (p type, n type), 9 protective film, 10 light receiving element, 11 pixel electrode (p side or n side electrode), 12 ground electrode (n side or p side electrode), 15 pn junction (Pi junction), 35 antireflection film, 36 mask pattern for mesa etching, P pixel.

Claims (6)

A light receiving element having pixels formed on a semiconductor substrate,
A multi-quantum well structure in which semiconductor layers of different compositions are stacked, and a light-receiving layer for receiving light;
A pn junction located in the light receiving layer;
A first conductivity type region provided on a side opposite to the semiconductor substrate with respect to the pn junction and having a first conductivity side electrode;
A buffer layer of a second conductivity type disposed between the light receiving layer and the semiconductor substrate;
A mesa structure separating the pixel and the periphery of the pixel by a groove;
Concavities and convexities are formed on the wall surface of the mesa structure by exposing the laminated semiconductor layer , and the end of the pn junction is not exposed to the wall surface of the groove over the wall surface of the groove of the mesa structure. An impurity wall surface layer into which an impurity of one conductivity type is introduced is formed,
The impurity concentration of the impurity wall surface layer in the range of the light receiving layer on the semiconductor substrate side from the pn junction is such that the first conductivity type in the region where the first conductivity side electrode in the first conductivity type region is in ohmic contact. Less than the impurity concentration of
The light receiving element, wherein an impurity concentration of the second conductivity type of the buffer layer is greater than an impurity concentration of the impurity wall surface layer. The concentration of the first conductivity type impurity of the impurity wall surface layer in the range of the light receiving layer on the semiconductor substrate side from the pn junction is 5e15 cm ^-3 or more and 5e17 cm ^-3 or less. Light receiving element.   The light receiving element according to claim 1, wherein a covering layer is formed so as to cover the impurity wall surface layer of the groove having the mesa structure.   The light receiving element according to claim 1, wherein the light receiving element is formed of a group III-V semiconductor stack including the light receiving layer on a group III-V semiconductor substrate.   The light receiving element according to claim 1, wherein the first conductivity type impurity is zinc (Zn).   6. The light receiving element according to claim 1, wherein the light receiving layer has an InGaAs / GaAsSb type 2 multiple quantum well structure. 7.

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