JP6015435B2 - Method and apparatus for evaluating strength of semiconductor wafer - Google Patents

Description

  The present invention relates to a semiconductor wafer strength evaluation method and evaluation apparatus.

  When a semiconductor wafer such as a silicon wafer is cracked in a semiconductor device manufacturing process, a large loss occurs. For this reason, there is a high demand for semiconductor wafers that are difficult to break during device manufacturing. In other words, there is a focus on wafer strength.

  Semiconductor and liquid crystal manufacturing processes, particularly heat treatment after ion implantation, have been rapidly heated and rapidly cooled, and the number of manufacturing processes performed in a vacuum or in a dry environment is also increasing. In addition, silicon wafers, glass substrates, and the like as substrates have been increased in diameter, and the wafer strength has become more important.

  In such a device manufacturing process, the influence of the thermal stress applied to the wafer is large, and the development of an analysis method for fracture strength under these conditions is strongly desired at present.

  As a method for evaluating the wafer strength, a “selective etching method” has been generally used. This is a technique in which a silicon wafer is put on “hydrofluoric acid + nitric acid + acetic acid + water” or “chromic acid + hydrofluoric acid + nitric acid + acetic acid + water” to check the etching state. However, this measurement method has a large variation in personal measurement such as acid temperature and operator's procedure. In addition, even a wafer that does not have a problem with this method may break in the device process, and there is a problem that the evaluation ability is inferior.

  Further, an X-ray topograph (XRT) using X-rays is used. However, this method requires expensive equipment, requires the use of dangerous X-rays, and is generally difficult to evaluate. In addition, even wafers that do not have problems with this method may break in the device process and are not universal.

  Furthermore, since semiconductor wafers are crystalline brittle materials, variations in measured values are large in general material evaluation techniques.

  In the first place, standard equipment for evaluating and inspecting the easiness of cracking of a semiconductor wafer at room temperature is not commercially available. For example, an apparatus and a method disclosed in Patent Documents 1-5 have been devised.

  Patent Document 1 discloses a method in which a glass ball is dropped using a glass inlet tube as a guide, and the breaking strength is expressed by the minimum drop height H necessary for the semiconductor wafer to start cracking. However, this method has a problem that a mechanism for heating the evaluation material is not incorporated and the evaluation temperature cannot be examined.

  Patent Document 2 discloses a method for evaluating the occurrence of cracks, landslide deformation, and the like by repeatedly applying a thermal shock (room temperature to 740 (˜1100) ° C.) to a wafer. However, with this method, the occurrence rate of cracking is less than 1% for wafers with good product level, and a large amount of samples and a long test time are required to compare differences in product types. There is a problem that it is expensive. As a simplified method, there is a method of evaluating the number of landslide deformation due to thermal shock or comparing the occurrence rate of cracks by applying thermal shock to a wafer that has been damaged in advance, but these are qualitative evaluation methods. Therefore, statistical evaluation is difficult.

  Patent Document 3 discloses a four-point bending tester. In this case, since it is necessary to incorporate a heater into the evaluation machine, it has a drawback that it is difficult to evaluate the strength of the environment of rapid heating and rapid cooling. ing.

  Patent Document 4 discloses a method of evaluating thermal shock resistance by holding a wafer in a chamber equipped with a heating mechanism and applying an impact to the wafer. Although this method can evaluate the impact, it is impossible to monitor and evaluate the wafer behavior during the heat treatment.

  Patent Document 5 discloses a technique for evaluating warpage from an image on which reflected light is projected using lattice-like light in order to evaluate warpage when a wafer is taken in and out of a furnace. In this method, there is a problem that it is difficult to obtain a sufficient amount of reflected light when preparing a lattice-shaped light or when the wafer itself is heated at a high temperature.

  Furthermore, a configuration in which the wafer orientation in the heat treatment furnace is shifted by 90 ° so that the deformation of the wafer can be directly observed from the furnace port is proposed in Non-Patent Document 1, but it is difficult to obtain the data. However, it was not available in terms of wafer strength evaluation.

  As described above, there is no method that can stably evaluate the behavior during heat treatment of a semiconductor wafer or the like, and can quantitatively evaluate the strength of the semiconductor wafer, and an apparatus that can perform the method. .

JP 2001-122700 A JP 2007-48923 A Japanese Patent Laid-Open No. 9-229838 JP 2012-4438 A JP-A-6-18242

Yoshimitsu Sugita, Semiconductor Research 16 Ultra LSI Technology Semiconductor Process p. 322 (1979)

  The present invention has been made in view of the above problems, and provides an evaluation method and an evaluation apparatus capable of evaluating the strength of a heated semiconductor wafer in a more stable and accurate manner than conventional methods in accordance with actual heat treatment conditions. The purpose is to do.

  In order to achieve the above object, the present invention is a method for evaluating the strength of a semiconductor wafer that has been put into a horizontal furnace and heated, the main surface of the semiconductor wafer being parallel to the vertical direction, and In parallel with the direction of loading into the horizontal furnace, the step of loading the semiconductor wafer into the horizontal furnace and the amount of deformation of the semiconductor wafer loaded into the horizontal furnace are quantitatively measured from the furnace port of the horizontal furnace. There is provided a method for evaluating the strength of a semiconductor wafer, comprising a step and a step of evaluating the strength of the semiconductor wafer from the deformation amount.

  With such a process, the semiconductor wafer is put into a horizontal furnace with the semiconductor wafer rotated by 90 ° as usual, and the strength of the semiconductor wafer is matched to the actual heat treatment conditions by evaluating the strength of the semiconductor wafer. Can be evaluated stably and accurately.

  In this case, the input speed of the semiconductor wafer when being charged into the horizontal furnace is set to a predetermined value, the temperature distribution in the surface of the semiconductor wafer when being charged into the horizontal furnace is measured, The strength of the semiconductor wafer can be evaluated from the relationship between the temperature distribution and the deformation amount of the semiconductor wafer.

  Thus, the thermal stress applied to the semiconductor wafer can be changed by changing the loading speed of the semiconductor wafer. By measuring the temperature distribution in the surface of the semiconductor wafer at this time and comparing it with the deformation amount of the semiconductor wafer, the influence of the temperature gradient in the surface of the semiconductor wafer can be evaluated.

  Further, the present invention is an apparatus for evaluating the strength of a semiconductor wafer that has been charged and heated in a horizontal furnace, wherein the horizontal furnace and the main surface of the semiconductor wafer are parallel to a vertical direction, and the horizontal mold A jig for holding the semiconductor wafer so as to be parallel to a direction to be fed into the furnace and throwing it into the horizontal furnace, and quantitatively determining a deformation amount of the semiconductor wafer put into the horizontal furnace. An apparatus for evaluating the strength of a semiconductor wafer is provided.

  An apparatus for evaluating the strength of a semiconductor wafer having such a configuration can enter a horizontal furnace with the semiconductor wafer rotated by 90 ° as usual, and the strength of the semiconductor wafer can be adjusted according to the actual heat treatment conditions. Thus, the device can be evaluated stably and accurately.

  In this case, the strength evaluation apparatus for a semiconductor wafer according to the present invention further includes means for changing a loading speed of the semiconductor wafer into a horizontal furnace and means for measuring a temperature distribution in the surface of the semiconductor wafer to be charged. Can be provided.

  With such an evaluation apparatus, it is possible to change the manner in which thermal stress is applied to the semiconductor wafer by means of changing the charging speed of the semiconductor wafer into the horizontal furnace, and the temperature within the surface of the semiconductor wafer at that time Distribution can be measured.

  With the semiconductor wafer strength evaluation method and evaluation apparatus according to the present invention, the strength of a heated semiconductor wafer can be quantitatively evaluated more stably and accurately than before in accordance with actual heat treatment conditions.

It is the schematic which looked at the evaluation apparatus of the intensity | strength of the semiconductor wafer which concerns on this invention from the substantially side surface. It is the schematic which looked at the evaluation apparatus of the intensity | strength of the semiconductor wafer which concerns on this invention from the upper surface substantially. It is a graph which shows the result (deformation amount) of Example 1. It is a graph which shows the result (slip length / deformation amount) of Example 1. 10 is a graph showing the results of Example 2.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, but the present invention is not limited thereto.

  1 and 2 are schematic views of a semiconductor wafer strength evaluation apparatus according to the present invention. FIG. 1 is a view of a semiconductor wafer strength evaluation apparatus according to the present invention viewed from substantially the side, and FIG. 2 is a view viewed from substantially the top.

  An evaluation apparatus 10 according to the present invention is an apparatus for evaluating the strength of a semiconductor wafer W heated in a heat treatment furnace. As a heat treatment furnace used for evaluation, the evaluation apparatus 10 includes a horizontal furnace 11. The evaluation apparatus 10 further includes a jig (that is, a boat) 13 for holding the semiconductor wafer W and putting it into the horizontal furnace. The jig 13 used in the evaluation apparatus 10 of the present invention holds the main surface of the semiconductor wafer W so that it is parallel to the vertical direction and parallel to the direction in which it is introduced into the horizontal furnace 11. At this time, the jig 13 is configured such that the semiconductor wafer W does not tilt, and has, for example, a groove corresponding to the thickness of the semiconductor wafer W.

  The evaluation apparatus 10 further includes means (deformation amount measuring means) 14 for quantitatively measuring the deformation amount of the semiconductor wafer W put into the horizontal furnace 11. The deformation amount measuring means 14 measures the deformation amount of the semiconductor wafer W from the furnace port portion 12 of the horizontal furnace 11. As the deformation amount measuring means 14, for example, a device capable of taking a photograph after deformation of the semiconductor wafer W and reflecting it as the value of the deformation amount from the number of pixels on the image can be adopted.

  The evaluation apparatus 10 may include a means (input speed changing means) 15 that changes the input speed of the semiconductor wafer W into the horizontal furnace 11. The input speed changing means 15 can change the input speed of the semiconductor wafer W by being connected to the jig 13. Further, the evaluation apparatus 10 may include a means (temperature distribution measuring means) 16 for measuring the temperature distribution in the surface of the semiconductor wafer W put into the horizontal furnace 11. As the temperature distribution measuring means 16, for example, a normal thermography can be used. The temperature distribution measuring means 16 measures the temperature distribution in the wafer surface from the side surface of the semiconductor wafer W as shown in FIG.

  The method for evaluating the strength of a semiconductor wafer according to the present invention is a method for evaluating the strength of a heated semiconductor wafer, and can be performed using the evaluation apparatus 10 as shown in FIGS. The semiconductor wafer to be evaluated can be, for example, a single crystal silicon wafer, but is not limited thereto.

  In the evaluation method of the present invention, first, the semiconductor wafer W is put into the horizontal furnace 11 using the jig 13. At this time, the semiconductor wafer W is loaded into the horizontal furnace 11 with the main surface of the semiconductor wafer W parallel to the vertical direction and parallel to the direction (furnace direction) of loading into the horizontal furnace 11. That is, the semiconductor wafer W is put into the horizontal furnace 11 while being rotated by 90 ° as usual. The horizontal furnace 11 is set to a predetermined temperature (temperature at which the wafer strength is to be evaluated), and the semiconductor wafer W is entered at a constant speed.

  After completely entering the semiconductor wafer W, the deformation amount of the semiconductor wafer W put into the horizontal furnace 11 is quantitatively measured. The deformation amount is measured by the deformation amount measuring means 14 from the furnace port portion 12 of the horizontal furnace 11. As the deformation amount measuring means 14, as described above, a device that obtains the deformation amount from the number of pixels on the photographed image can be adopted. Based on the deformation amount of the semiconductor wafer W thus measured, the strength of the semiconductor wafer W can be evaluated. It is also possible to examine the wafer strength from the amount of deformation at that time by changing the temperature of the furnace after entering the furnace.

  With such an evaluation method, the strength of the semiconductor wafer W can be evaluated stably and accurately in accordance with actual heat treatment conditions. For example, it is possible to measure a difference in wafer strength due to a difference in the type of the semiconductor wafer W (difference in dopant type, concentration, wafer thickness, etc.).

  Further, in the method for evaluating the strength of the semiconductor wafer according to the present invention, the influence of the temperature distribution in the surface of the semiconductor wafer W when it is put into the horizontal furnace 11 on the deformation amount of the semiconductor wafer W is taken into consideration as follows. Can also be done.

  First, the charging speed of the semiconductor wafer W when it is charged into the horizontal furnace 11 is set to a predetermined value by the charging speed changing means 15. As a result, the input speed can be changed for each measurement, and the manner in which thermal stress is applied to the semiconductor wafer can be changed. The semiconductor wafer W can be charged into the horizontal furnace 11 in the same manner as described above except for the charging speed. Furthermore, the in-plane temperature distribution (gradient) of the semiconductor wafer W is confirmed by measuring the in-plane temperature distribution of the semiconductor wafer W when it is put into the horizontal furnace 11 by the temperature distribution measuring means 16 such as thermography. The quantitative measurement of the deformation amount of the semiconductor wafer W can be performed in the same manner as described above. In this case as well, it is possible to change the temperature of the furnace after entering the furnace and to examine the wafer strength from the amount of deformation at that time.

  Thus, the relationship between the in-plane temperature distribution (gradient) of the semiconductor wafer W and the deformation amount can be evaluated, that is, the wafer strength against thermal stress can be evaluated. According to this method, the influence of the temperature distribution on the deformation amount of the semiconductor wafer can be reflected in the evaluation of the strength of the semiconductor wafer.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples, but these do not limit the present invention.

Example 1
Using the evaluation apparatus 10 shown in FIGS. 1 and 2, the strength of the semiconductor wafer was evaluated according to the evaluation method of the present invention.

  First, as a material semiconductor wafer W, a silicon wafer having a resistivity of 10 Ω · cm, boron-doped, a diameter of 150 mm, and a thickness of 625 μm was prepared. This silicon wafer was mounted on a boat (jig 13) having a boat groove width of 800 μm. The semiconductor wafer W mounted on this boat was charged into the horizontal furnace 11 at a speed of 10 cm per minute in an oxygen atmosphere at 1000 ° C. The furnace entry direction and the main surface of the semiconductor wafer W were parallel. Next, the deformation amount of the silicon wafer in the horizontal furnace 11 was measured. In the measurement of the deformation amount, a numerical value was obtained by converting the number of pixels of the captured image by the deformation amount measuring means 14 into a length.

Next, the same measurement as described above was performed by changing the type of the semiconductor wafer W. Specifically, a silicon wafer having a resistivity of 10 Ω · cm, boron dope, nitrogen 1 × 10 ¹⁴ atoms / cm ³ dope, a diameter of 150 mm, and a thickness of 625 μm was prepared as the semiconductor wafer W. In the same manner as described above, this silicon wafer was mounted on a boat (jig 13) having a width of a boat groove of 800 μm, and charged into the horizontal furnace 11 at a speed of 10 cm per minute in an oxygen atmosphere at 1000 ° C. Thereafter, the deformation amount of the silicon wafer in the horizontal furnace 11 was measured.

  The difference in deformation amount of each silicon wafer is shown in FIG. As can be seen from FIG. 3, the difference in deformation amount depending on whether or not the silicon wafer is doped with nitrogen was clearly obtained as numerical values.

  FIG. 4 shows the difference in slip length and deformation amount after heat treatment at 1200 ° C. for 1 hour in each silicon wafer of this example. The slip length at this time was calculated from the slip in the wafer from the X-ray topographic image, and the longest slip length was selected as a representative value. When the amount of wafer deformation is large, the slip length tends to increase. That is, a wafer having a large amount of deformation has a relationship that the wafer strength is small. From this result, it can be seen that the wafer strength of the heated semiconductor wafer can be evaluated by the method of the present invention.

(Example 2)
As another example, the strength of the semiconductor wafer was evaluated using the evaluation apparatus 10 shown in FIGS. 1 and 2 according to the evaluation method of the present invention.

  First, as a material semiconductor wafer W, a silicon wafer having a resistivity of 10 Ω · cm, boron-doped, a diameter of 150 mm, and a thickness of 625 μm was prepared. This silicon wafer was mounted on a boat (jig 13) having a boat groove width of 800 μm. The semiconductor wafer W mounted on this boat was charged into the horizontal furnace 11 at a speed of 10 cm per minute in an oxygen atmosphere at 1000 ° C. The furnace entry direction and the main surface of the semiconductor wafer W were parallel. The temperature distribution in the surface of the silicon wafer being put in was measured by thermography (temperature distribution measuring means 16), and the temperature difference in the wafer surface and the deformation amount of the silicon wafer at that time were measured by the deformation amount measuring means 14. In the measurement of the amount of deformation, a numerical value was obtained by converting the number of pixels of the captured image into a length.

  This experiment makes it possible to obtain data on the temperature difference in the silicon wafer surface and the deformation amount of the silicon wafer. In this case, the temperature difference was 53 ° C., and the deformation amount was 7.45 mm.

Next, the same measurement as described above was performed by changing the type of the semiconductor wafer W. Specifically, a silicon wafer having a resistivity of 10 Ω · cm, boron dope, nitrogen 1 × 10 ¹⁴ atoms / cm ³ dope, a diameter of 150 mm, and a thickness of 625 μm was prepared as the semiconductor wafer W. In the same manner as described above, this silicon wafer was mounted on a boat (jig 13) having a boat groove width of 800 μm to obtain data. In this case, the temperature difference was 49 ° C., and the deformation was 0.92 mm.

  FIG. 5 shows the slip length when heat treatment is performed at 1200 ° C. for 1 hour on the horizontal axis and the amount of deformation divided by the temperature difference on the vertical axis. The slip length at this time was calculated by calculating the slip in the wafer from an X-ray topographic image and selecting the longest slip length as a representative value. When the amount of wafer deformation per unit temperature is large, the slip length tends to increase. That is, there is a relationship that the wafer strength is small when the wafer deformation amount divided by the temperature difference is large. From this result, it can be seen that the wafer strength of the heated semiconductor wafer can be evaluated by the method of the present invention.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 10 ... Evaluation apparatus, 11 ... Horizontal furnace, 12 ... Furnace part, 13 ... Jig,
14 ... deformation amount measuring means, 15 ... charging speed changing means, 16 ... temperature distribution measuring means,
W: Semiconductor wafer.

Claims (4)

A method for evaluating the strength of a semiconductor wafer that has been put into a horizontal furnace and heated,
Placing the semiconductor wafer into the horizontal furnace, with the main surface of the semiconductor wafer parallel to the vertical direction and parallel to the direction into the horizontal furnace;
Quantitatively measuring the amount of deformation of the semiconductor wafer charged into the horizontal furnace from the furnace port of the horizontal furnace;
A step of evaluating the strength of the semiconductor wafer from the deformation amount , and
Set the input speed of the semiconductor wafer when charging into the horizontal furnace to a predetermined value,
Measure the temperature distribution in the plane of the semiconductor wafer when thrown into the horizontal furnace,
A method for evaluating the strength of a semiconductor wafer , comprising evaluating the strength of the semiconductor wafer from a relationship between an in-plane temperature distribution and a deformation amount of the semiconductor wafer. 2. The deformation amount value of the semiconductor wafer according to claim 1 , wherein when the deformation amount of the semiconductor wafer is quantitatively measured, a photograph after the deformation of the semiconductor wafer is taken, and a value of the deformation amount is obtained from the number of pixels on the image . A method for evaluating the strength of a semiconductor wafer. An apparatus for evaluating the strength of a semiconductor wafer that has been put into a horizontal furnace and heated,
The horizontal furnace;
A jig that holds the semiconductor wafer and puts it in the horizontal furnace so that the main surface of the semiconductor wafer is parallel to the vertical direction and parallel to the direction to put into the horizontal furnace,
Means for quantitatively measuring the amount of deformation of the semiconductor wafer charged into the horizontal furnace from the furnace port of the horizontal furnace;
Means for changing the charging speed of the semiconductor wafer into the horizontal furnace;
And a means for measuring an in-plane temperature distribution of the semiconductor wafer to be introduced . 4. The means for quantitatively measuring the deformation amount of the semiconductor wafer is for taking a photograph after deformation of the semiconductor wafer and obtaining a value of the deformation amount from the number of pixels on the image. The evaluation apparatus of the intensity | strength of the semiconductor wafer of description.

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