JP6007509B2 - Serial I / F bus control device and imaging device - Google Patents

Description

  The present invention relates to a serial I / F bus control device and an imaging device using the serial I / F bus control device.

  Recent image pickup devices have various registers (command registers) inside an image pickup device including a CMOS sensor and the like, and determine various operation contents of the image pickup device by setting commands and parameters in these registers. ing. Reading and writing to the internal register group of the image sensor is performed by the imaging control circuit using a dedicated path different from the path of the image data. In general, one clock line (SCL) is connected to the dedicated path. A serial I / F bus (I2C bus) composed of one data line (SDA) is used. That is, the image pickup control circuit and the image pickup device are connected via an I2C bus, and the image pickup control circuit is operated as a master device and the image pickup device is operated as a slave device to read / write data from / to an internal register group of the image pickup device.

  On the other hand, there is known an omnidirectional imaging apparatus that captures omnidirectional images using a plurality of image sensors of the same type and generates a panoramic image by synthesizing a plurality of obtained image data. In such an omnidirectional imaging apparatus, when the I2C bus is used for reading and writing to each internal register group of a plurality of imaging elements of the same type, there are the following problems.

  Multiple slave devices can be connected to the I2C bus, but each slave device must have a different address (slave address), and multiple slave devices having the same slave address are connected to the I2C bus. Can not do it. Since the same type of image pickup device generally has the same slave address, a plurality of the same type of image pickup devices cannot be connected to the I2C bus.

  Some image sensors can specify a slave address with an external terminal. In such an image sensor, it is possible to connect a plurality of image sensors of the same type to the I2C bus by setting the slave address of each image sensor to a different value. However, even when setting the same command or the like in the internal register group of each image sensor, it is necessary to carry out each image sensor individually for the convenience of the I2C bus standard, such as checking a response signal such as ACK. There is a problem that the setting process takes time and the process becomes complicated. In addition, an image sensor that does not have a function of designating a slave address with an external terminal cannot be used. If each image sensor has an I2C control circuit, commands to the internal register group of each image sensor can be set at the same time, but the circuit scale increases and the cost increases.

  If the general code address function in the I2C bus standard is used, it is possible to transmit data to all slave devices connected to the I2C bus at the same time. However, in order to ignore response signals such as ACK The lack of reliability has the problem that the image pickup device itself often cannot cope with this function.

  Although the omnidirectional imaging apparatus has been described here, the above-described problem occurs when a command or the like is generally set to a plurality of devices of the same type using the I2C bus.

  In Patent Document 1, a plurality of slave devices are connected to the I2C bus, and a master device is connected to the I2C bus via a communication control device. The communication control device is connected between the master device and the plurality of slave devices. Although it is described that a plurality of slave devices having the same address value can be connected to the I2C bus by adopting a configuration for controlling data communication, the circuit scale increases, resulting in an increase in cost. There is a problem that the processing becomes complicated.

  The present invention provides a serial I / O capable of setting commands and the like simultaneously to a plurality of devices of the same type using a serial I / F bus with a simple configuration and without requiring complicated processing. An F bus control device and an imaging device using the serial I / F bus control device are provided.

The present invention is a serial I / F bus control device that transmits and receives data to and from a plurality of devices of the same type using a serial I / F bus, and a plurality of serial I / Fs respectively connected to the plurality of devices. One control means for controlling data transmission / reception based on a predetermined communication protocol using the device as a slave device, and the serial I / F buses of a plurality of devices as the control means. A bus switching means having a first mode for connecting to the control means and a second mode for connecting the serial I / F bus of any one of the plurality of devices to the control means; and the bus switching means for the first mode. when the response to each of the plurality of the devices makes a reception of the data at the same timing from the master device sheet of Based on the response signal to be sent to Al I / F bus, one of the device or of the device, when outputting the response signal indicating that not receive the data or the device each said master, Error detection means for detecting, as an error, a case in which the response signal indicating that the data has been received is not output as a response to the reception of the data from the device, and the serial I / F bus has The serial clock line is composed of a serial clock line and a serial data line, and the serial clock line is commonly connected to the plurality of devices.

  A plurality of devices can be controlled by a single serial I / F bus control means.

It is a figure which shows the example of a whole circuit structure of the imaging device to which the serial I / F bus control apparatus of this invention is applied. It is a detailed block diagram of the image processing unit of FIG. It is a figure explaining the operation timing of the serial clock line (SCL) and serial data line (SDA) of an I2C bus. It is a figure which shows the standard data format of I2C bus communication. It is a figure explaining the repeat start condition function of I2C bus communication. It is a detailed block diagram concerning one Embodiment of the imaging control unit (serial I / F bus control device) of FIG. It is a figure which shows the structure (the 1) of the imaging control unit at the time of single operation mode. It is a figure which shows the structure (the 2) of the imaging control unit at the time of single operation mode.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, an embodiment in which the serial I / F bus control device of the present invention is applied to an omnidirectional imaging device will be described. The serial I / F bus control device of the present invention generally uses a serial I / F bus. The present invention can be widely applied to apparatuses that need to set commands or the like to a plurality of devices of the same type. The serial I / F bus is I2C (Inter Integrated Circuit), but it may be SCCB (Serial Camera Control Bus).

  FIG. 1 shows an overall circuit configuration example of an omnidirectional imaging apparatus as an application example of a serial I / F bus control apparatus (I2C bus control apparatus) of the present invention.

  In FIG. 1, an imaging unit 10 includes a wide-angle lens (so-called fisheye lens) having an angle of view of 180 ° or more for forming a hemispherical image, and two of the same type provided corresponding to each wide-angle lens. Imaging elements 11 and 12 are provided. The image sensors 11 and 12 generate timings for generating an image sensor such as a CMOS sensor that converts an optical image obtained by the previous fisheye lens into image data of an electric signal and outputs it, and a horizontal / vertical synchronization signal and a pixel clock of the image sensor. Various commands and parameters required for the operation of the image sensor and the processor that controls the operation of the circuit, image sensor, and timing generation circuit, and performs the necessary preprocessing of the image data output from the image sensor. And a group of registers for storing various status data. Since this type of imaging device is already known (for example, OV5653 from Omni Vision Technologies), the specific configuration of the imaging devices 11 and 12 is omitted. In FIG. 1, two image sensors are used, but generally two or more image sensors may be used.

  The imaging elements 11 and 12 of the imaging unit 10 are each connected to the image processing unit 20 by a parallel I / F bus. On the other hand, the imaging elements 11 and 12 of the imaging unit 10 are separately connected to the imaging control unit 30 via a serial I / F bus (I2C bus). The image processing unit 20 and the imaging control unit 30 are connected to the CPU 40 via the bus 80. Further, a memory 50, an operation unit 60, an external I / F 70, and the like are connected to the bus 80.

  The image processing unit 20 takes in the image data output from the image sensors 11 and 12 through the parallel I / F bus, performs predetermined processing on the respective image data, and then combines these image data. Omnidirectional image data is generated.

  The imaging control unit 30 sets a command or the like in the register group of the imaging elements 11 and 12 using the I2C bus using the imaging control unit 30 as a master device and the imaging elements 11 and 12 as slave devices. Necessary commands and the like are received from the CPU 40. The imaging control unit 30 also uses the I2C bus to capture the status data of the register groups of the imaging elements 11 and 12 and send them to the CPU 40.

  As the imaging control unit 30, the serial I / F bus control device (I2C control device) of the present invention is used. As a result, the imaging control unit 30 can simultaneously set commands or the like for the register groups of the same type of imaging elements 11 and 12 with a standard data format of I2C communication. The configuration and operation of the imaging control unit 30 will be described in detail later. Here, the same type means having the same slave address and the same internal address. Therefore, the same type of device means a device having the same slave address and internal address.

  The CPU 40 controls the overall operation of the imaging apparatus and executes necessary processing. Here, regarding the imaging control unit 30, the CPU 40 sets commands and the like to the imaging elements 11 and 12 with respect to the imaging control unit 30 when the imaging elements 11 and 12 are initialized after the power is turned on, for example. And send a command or the like. In addition, the CPU 40 instructs the imaging control unit 30 to read status data and the like from the imaging elements 11 and 12 and receives the status data and the like at the end of shooting.

  The memory 50 is a general term for ROM, RAM, and external memory (USB card, SD card, etc.). The ROM stores various programs for the CPU 40. The RAM is a work memory and stores programs executed by the CPU 40, data being processed, and the like. The RAM temporarily stores image data being processed by the image processing unit 20. The external memory stores the omnidirectional image data processed by the image processing unit 20 directly or via the RAM as required.

  The operation unit 60 is a general term for various operation buttons, a power switch, a shutter button, a touch panel that has both display and operation functions, and the like. The user inputs various shooting modes and shooting conditions by operating the operation buttons and the like.

  For example, a personal computer is connected to the external I / F 70. The omnidirectional image data processed by the image processing unit 20 is transferred to the personal computer through the external I / F 70 as necessary. In the present embodiment, the imaging device is not provided with a display unit, but it is needless to say that a display unit may be provided. Furthermore, examples of the external I / F 70 include a USB I / F, a serial I / F, and a network I / F.

  FIG. 2 is a detailed configuration diagram of the image processing unit 20. The image processing unit 20 includes an image processing circuit (1) 210, an image processing circuit (2) 220, an image composition circuit 230, a bus I / F circuit 240, and an internal bus 250 connecting them.

  The image sensors 11 and 12 each output image data in units of lines. At the same time, the image sensors 11 and 12 also output horizontal / vertical synchronization signals, pixel clocks, and the like. The image processing circuits 210 and 220 perform predetermined image processing on the image data output from the imaging elements 11 and 12, respectively. Types of image processing in the image processing circuits 210 and 220 include lens correction, black level correction, color correction, defective pixel correction, white balance, and the like. The image data that has undergone predetermined image processing by the image processing circuits 210 and 220 is temporarily stored in the RAM of the memory 50 via the bus I / F 240. That is, in the RAM 50 of the memory 50, for example, two hemispherical image data obtained by photographing with the imaging elements 11 and 12 are stored after being subjected to predetermined image processing. The two hemispherical image data have overlapping areas. Here, in this embodiment, since the case where two image sensors are used is shown, it is a hemispherical image with an angle of view of 180 degrees or more. However, it goes without saying that when the number of image sensors is changed, the angle of view is changed accordingly. Although the case where the angle of view becomes narrow is conceivable, the term “wide-angle lens” is used in the present embodiment, but the angle may not always be wide.

  The two hemispherical image data stored in the RAM of the memory 50 are then taken into the image composition circuit 230 via the bus I / F. The image synthesizing circuit 230 synthesizes two hemispherical image data based on the overlapping areas of each other to generate omnidirectional image data. The generated omnidirectional image data is stored again in the RAM of the memory 50 via the bus I / F 240. Thereafter, the omnidirectional image data is accumulated from the RAM into an external memory (USB card, SD card, etc.), displayed on the display unit, or transferred to a personal computer or the like through the external I / F circuit 70 as necessary. Is done.

  Next, the imaging control unit 30 will be described. As described above, the imaging control unit 30 uses the serial I / F bus control device (I2C control device) according to the present invention.

  First, the I2C bus interface will be described. The I2C bus is composed of only two buses (serial I / F bus), one serial data line (SDA) and one serial clock line (SCL). A plurality of devices can be connected to this I2C bus. One of them is a master device, and the other device is a slave device. The master device takes the initiative and is usually connected to one I2C bus. Send / receive data to / from slave devices. Each slave device has a unique address (slave address).

  When the master device transmits / receives data or the like to / from a certain slave device, the master device transmits the slave address on the I2C bus to notify the slave device to be communicated of the start of communication. Thus, once a slave device is identified, the master device can transmit and receive data and the like only with the slave device. When the data transmission / reception ends, the master device notifies the slave device of the end of communication.

The outline of the communication protocol of the I2C bus will be described below.
(1) Start of communication When the master device starts communication with a certain slave device, it issues a start condition signal (S) to indicate the start of the communication sequence. This is established by changing SDA from the “H” level to the “L” level when the SCL is at the “H” level, as shown in FIG. The start condition signal (S) is simultaneously notified to all slave devices. The SCL is driven by the master device, and alternately repeats “H” level and “L” level at a predetermined frequency. Before communication is started, both SCL and SDA are at the “H” level.

(2) Selection of slave device After issuing a start condition signal, the master device transmits a control byte (CB) to all slave devices. The control byte consists of a 7-bit slave address and an R / W flag indicating the direction of 1-bit transmission / reception (read / write), and is sent bit by bit on the SDA in synchronization with the clock on the SCL. FIG. 3C shows this.
All slave devices receive the control byte (8 bits) on the SDA in synchronization with the clock on the SCL after receiving the start condition signal (S). When each slave device receives the control byte, it checks whether the slave address matches its own address. If it does not match, it returns to the idle state, and the start condition signal (S) is issued again. Wait until
On the other hand, if the slave address of the received control byte matches its own address, the slave device returns ACK as a response signal to the master device, and data is sent according to the R / W flag of the control byte. Preparing for the transmission / reception process. The ACK responds by setting the SDA to the “L” level in synchronization with the clock on the SCL.

(3) Data transmission / reception When the R / W flag in the control byte is “W” (eg, logic 0), the master device confirms that an ACK has been returned from the selected slave device and Start sending. When the R / W flag of the control byte is “R” (for example, logic 1), the selected slave device returns ACK to the master device and then starts data transmission.
Data is transmitted and received in units of 1 byte (8 bits). That is, the transmission side loads 1-byte data on the SDA bit by bit in synchronization with the clock on the SCL. This is the same as the case of the control byte shown in FIG. The receiving side receives the data on the SDA one bit at a time in synchronization with the clock on the SCL. When receiving 1 byte (8 bits) of data, the receiving side returns an ACK to the transmitting side. Returns NOACK to The transmission side confirms that the ACK has been returned from the reception side, and if there is still data to be transmitted, similarly, the next 1-byte data is put on the SDA bit by bit. This is repeated until there is no data to be transmitted.
As described above, data is output on the SDA bit by bit in synchronization with the clock on the SCL, like the control byte. The master device sends and receives data while outputting its own clock. On the other hand, the slave device transmits and receives data according to the clock output from the master device. The receiving side outputs ACK / NOACK regardless of the difference between the master and the slave.
Usually, ACK means that the data has been normally received, and NOACK means that the data has not been normally received. However, the NOACK may have a specific meaning. For example, after the master device receives the final data, NOACK is returned to notify the slave device of the end of communication.

(4) End of communication When a series of communication sequences is completed, the master device issues a stop condition signal (P) to notify the slave device of the end of the communication sequence. This is established by changing SDA from “L” level to “H” level when SCL is at “H” level, as opposed to the start condition, as shown in FIG. Thereafter, the slave device returns to the standby state.
FIG. 4 is a diagram showing a standard data format of I2C bus communication. Here, the transmission data is simply 1 byte.
FIG. 4A shows an example in which the master device transmits (writes) data to the slave device. The master device transmits a control byte after issuing a start condition signal (S). Here, A6 to A0 are slave addresses, and W means data transmission. The slave device whose own address matches the slave address (A6 to A0) of the control byte returns an ACK to the master device to prepare for data reception. The master device confirms that the ACK has been returned, and transmits data (D7 to D0) to the slave device. When the slave device normally receives the data, it returns ACK to the master device. The master device issues a stop condition signal (P) to inform the slave device of the end of the communication sequence.
FIG. 4B shows an example in which the master device receives (reads) data from the slave device. The master device transmits a control byte after issuing a start condition signal (S). Here, A6 to A0 are slave addresses, and R means data reception. The slave device whose slave address matches the slave address of the control byte returns ACK to the master device, and subsequently transmits data (D7 to D0) to the master device. When receiving the data, the master device returns NOACK to notify the slave device of the end of communication, and subsequently issues a stop condition signal (P).

Next, other main functions of the I2C bus communication protocol will be briefly described.
<Clock Stretch>
After receiving data from the master device (or after transmitting data to the master device), the slave device can apply a WAIT to the master device for the reason that it takes time for internal processing. As a means for this, the slave device sets the SCL to the “L” level. As a result, the master device cannot generate a clock and temporarily stops communication. When the slave device is ready, the SCL “L” level output is released. In response to this, the master device resumes communication. In this way, the slave device forcing the SCL to the “L” level in order to make the master device wait is called clock stretching.

<Repeat start condition>
Normally, the communication direction (send / receive) within the section of the start condition signal (S) and the stop condition signal (P) is the value of the R / W flag in the control byte except for the control byte. It is fixed in the direction according to. However, there are cases where it is desired to switch the communication direction during this interval. For example, when the slave device is an EEPROM and ROM data is to be read from a specific ROM address, the setting of the ROM address to be accessed issues a W (write) request to the slave device. An R (read) request must be issued to. In such a case, after transmitting the ROM address to the slave device (W), in order to switch the communication direction to read (R), the start condition signal (S) is reissued to control the R request. Send a byte. The start condition signal (S) issued at this time is called a repeat start condition. FIG. 5 shows a specific example of the repeat start condition.

<General call address>
The slave address “0” is defined as a special address. This is called a general call address, and is a special address for transmitting data to all slave devices on the bus simultaneously. However, the slave device must support this address mode. Of course, since data collides, it is not possible to receive data from slave devices all at once by a general call.

Returning to FIG. 1, the imaging control unit 30 that is a feature of the present invention will be described.
FIG. 6 is a detailed configuration diagram of the imaging control unit 30 as a serial I / F bus control device (I2C control device) according to the present embodiment. In FIG. 6, the imaging control unit 30 includes a bus I / F circuit 310, an I2C control circuit 320 as control means, an output selector 330 and an input selector 340 as bus switching means, an error detection circuit 350, and a three-state buffer circuit 361. 362, 363, buffer circuits 371, 372, 373, and an internal bus 370 for connecting the buffer I / F circuit 310 to the I2C control circuit 320 and the error detection circuit 350.

The imaging control unit 30 and the imaging elements 11 and 12 are connected by individual I2C buses. However, in this embodiment, the number of I2C buses between the imaging control unit 30 and the imaging unit 10 is reduced by using the SCL in common with the imaging elements 11 and 12. SCL, SDA1, and SDA2 are each connected to a predetermined power source through a resistor R. During standby, SCL, SDA1, and SDA2 are pulled up (H level) to the power supply voltage V _DD .

  The bus I / F circuit 310 sends a command or the like from the CPU 40 (FIG. 1) to the I2C control circuit 320, and sends a status or the like from the I2C control circuit 320 to the CPU 40. Further, the bus I / F circuit 310 sends an error detection signal from the error detection circuit 350 to the CPU 40. These are performed using a general-purpose bus protocol.

  The I2C control circuit 320 is basically the same as the conventional one. That is, the I2C control circuit 320 uses the I2C bus (SCL, SDA1, SDA2) by using the I2C control circuit 320 itself as a master device and the imaging devices 11 and 12 as slave devices, and the I2C bus. Sends and receives commands and statuses according to the communication protocol. The difference from the prior art is that the I2C control circuit 320 switches and controls the output selector 330 and the input selector 340 before starting transmission / reception of commands, statuses and the like with the image sensors 11 and 12. Switching is instructed from the CPU 40.

  Based on the switching signal from the I2C control circuit 320, the output selector 330 switches the SDA output of the I2C control circuit 320 so that it is connected to both SDA1 and SDA2 (first mode) or one (second mode). . FIG. 6 shows a state where the SDA output of the I2C control circuit 320 is connected to both SDA1 and SDA2. Based on the switching signal from the I2C control circuit 320, the input selector 340 switches so that one of SDA1 and SDA2 is connected to the SDA input of the I2C control circuit 320. FIG. 6 shows a state in which SDA 2 is connected to the SDA input of the I2C control circuit 320.

  The 3-state buffer circuit 361 is turned on and off at a predetermined frequency by the I2C control circuit 320. As a result, the SCL repeats the “H” level and the “H” level, and the clock is sent to the image sensors 11 and 12. The buffer circuit 371 functions to transmit the SCL to the I2C control circuit 320 when the image sensor or 12 temporarily sets the SCL to the “L” level (clock stretch function). Here, since the SCL is common to the imaging elements 11 and 12, the clock stretch function works effectively in the data line configuration of the three-state buffer circuit 361.

  The three-state buffer circuits 362 and 363 are turned on and off via the output selector 330 at the SDA output of the I2C control circuit 326. As a result, SDA1 and / or SDA2 becomes "H" level or "L" level according to the SDA output. That is, a command or the like is transmitted from the I2C control circuit 320 to the image sensor 11 and / or the image sensor 12.

  The buffer circuits 372 and 373 function to input the status output from the image sensor 11 or 12 to the I2C control circuit via the input selector 340.

  The error detection circuit 350 buffers response signals (ACK, NOACK) output from the image sensors 11 and 12 to SDA1 and SDA2, respectively, when the image sensors 11 and 12 are simultaneously performing I2C protocol communication with the I2C control circuit 320. Input via circuits 372 and 373 and monitor. The operation and effect of the error detection circuit 350 will be described later.

  Next, the operation when a command or the like is set in the register group of the image sensors 11 and 12 will be described in detail. The image sensors 11 and 12 are devices of the same type, and their addresses (slave addresses) and internal register addresses are the same. Here, a case where the I2C control circuit 320 simultaneously sets commands or the like to the image sensors 11 and 12 is referred to as a simultaneous operation mode.

  The I2C control circuit 320 of the imaging control unit 30 first receives a simultaneous operation mode command for the imaging elements 11 and 12 from the CPU 40 (FIG. 1) through the bus I / F circuit 310. Based on the simultaneous operation mode command, the I2C control circuit 320 sends a switching signal to the output selector 330 to connect the SDA output of the I2C control circuit 320 to both SDA1 and SDA2, and to the input selector 340 to the image sensor 11. A switch signal is sent to connect the SDA1 to the SDA input of the I2C control circuit 320. As a result, the output selector 330 connects the SDA output of the I2C control circuit 320 to both SDA1 and SDA2 via the three-state buffer circuits 362 and 363 (first mode). The input selector 340 connects the SDA 1 of the image sensor 11 to the SDA input of the I2C control circuit 320 via the buffer circuit 372. FIG. 6 shows this state.

  Note that the I2C control circuit 320 may instruct the input selector 340 to connect the SDA2 of the image sensor 12 to the SDA input of the I2C control circuit 320. That is, when the image sensors 11 and 12 are simultaneously operated, the image sensors 11 and 12 output response signals, respectively, but the I2C control circuit 320 cannot receive both response signals due to restrictions on the communication protocol of the I2C bus. . Therefore, the response signal of either one of the image sensors 11 and 12 is received.

  Next, the I2C control circuit 320 receives a series of data groups such as a slave address, a flag (W), an internal register address, and a command common to the image sensors 11 and 12 from the CPU 40 through the bus I / F circuit 310. After storing the series of data groups in the internal register, the I2C control circuit 320 follows the normal I2C bus communication protocol as if sending data to one slave device as follows. Commands and the like are simultaneously set in the register groups 11 and 12 of the image sensor.

  First, the I2C control circuit 320 sends a clock to the SCL through the 3-state buffer circuit 361. The clock is transmitted until a series of communication sequences is completed.

  Next, the I2C control circuit 320 outputs a start condition signal (S) in synchronization with the clock. The start condition signal (S) is notified to the image sensors 11 and 12 through the paths of the output selector 330, the three-state buffer circuits 362 and 363, and SDA1 and SDA2. The image sensors 11 and 12 recognize the start of communication by receiving the start condition signal (S) in synchronization with the clock.

  Next, the I2C control circuit 320 outputs a control byte in synchronization with the clock. The control byte includes a slave address (7 bits) and a W flag (1 bit) of the image sensors 11 and 12. The control byte is transmitted to the image sensors 11 and 12 through the path of the output selector 330, the three-state buffer circuits 362 and 363, and SDA1 and SDA2. Each of the image sensors 11 and 12 receives the control byte in synchronization with the clock, the slave address in the received control byte matches the address of the image sensor, and the flag is “W”. Prepare for reception processing. The image sensors 11 and 12 output response signals ACK to the SDA1 and SDA2 in synchronization with the clock, respectively. Among these, the ACK of the image sensor 11 is received by the I2C control circuit 320 through the path of the SDA 1, the buffer circuit 372, and the input selector 340.

  The I2C control circuit 320 confirms reception of ACK, and outputs the register address (8 bits) in the image sensors 11 and 12 in synchronization with the clock. The register address is transmitted to the image sensors 11 and 12 through the path of the output selector 330, the three-state buffer circuits 362 and 363, and SDA1 and SDA2. The image sensors 11 and 12 receive and hold register addresses in synchronization with the clocks. The image sensors 11 and 12 output response signals ACK to the SDA1 and SDA2 in synchronization with the clock, respectively. Among these, the ACK of the image sensor 11 is received by the I2C control circuit 320 through the path of the SDA 1, the buffer circuit 372, and the input selector 340.

  Next, the I2C control circuit 320 confirms reception of ACK, and outputs write data (8 bits) in synchronization with the clock. The write data is transmitted to the image sensors 11 and 12 through the path of the output selector 330, the three-state buffer circuits 362 and 363, and SDA1 and SDA2. The image sensors 11 and 12 receive the write data in synchronization with the clock, respectively, hold the data first, and write the write data to the register corresponding to the register address. The image sensors 11 and 12 output response signals ACK to the SDA1 and SDA2 in synchronization with the clock, respectively. Among these, the ACK of the image sensor 11 is received by the I2C control circuit 320 through the path of the SDA 1, the buffer circuit 372, and the input selector 340.

  Thereafter, in the same manner, transmission / reception of a register address, ACK, write data, and ACK is repeated between the I2C control circuit and the image sensors 11 and 12 in synchronization with the clock. As a result, data is written into a register group in the image sensors 11 and 12 (commands are set).

  When the I2C control circuit 320 finishes transmission of all data and confirms reception of the response signal from the image sensor side, it outputs a stop condition signal (P). The stop condition signal (P) is notified to the image sensors 11 and 12 through the path of the output selector 330, the three-state buffer circuits 362 and 362, and SDA1 and SDA2. The image sensors 11 and 12 receive the stop condition signal (P), thereby confirming the end of a series of communication sequences and returning to the standby state. After sending the stop condition signal, the I2C control circuit 320 stops sending the clock (holds SCL at “H” level) and returns to the standby state.

  In order to simplify the explanation, the register address and the write data are each 8 bits (1 byte). However, in the case of 8 bits or more, each 8 bits are transmitted and received twice or more. Will be.

  According to the imaging control unit 30 having the configuration of FIG. 6, writing (setting) processing of commands and the like to two imaging elements 11 and 12 having the same type, that is, the same slave address, can be performed at the same timing. Since it is not necessary to carry out each image pickup device individually, the setting processing time can be shortened. In addition, the image sensors 11 and 12 may not have a function of specifying a slave address with an external terminal. Thus, the shortening of the setting processing time is very useful in an apparatus that needs to control or use a device such as an image sensor at a time.

  The I2C communication protocol of the I2C control circuit 320 does not need to be changed. The I2C control circuit 320 regards the image sensors 11 and 12 as one slave device, and performs a command according to a normal I2C bus communication protocol. All you need to do is send etc. That is, the I2C control circuit 320 can simultaneously set commands and the like to the same type of image pickup devices 11 and 12 without performing specially complicated processing.

  In addition, when the image sensors 11 and 12 have the same slave address, it is possible to set commands to the image sensors 11 and 12 simultaneously by providing the I2C control circuit 320 for each image sensor 11 and 12. This increases the circuit scale and increases the cost. On the other hand, according to the configuration of FIG. 6 which is an embodiment according to the present invention, only one I2C control circuit 320 is required for the two image sensors 11 and 12, the circuit scale can be reduced, and the cost can be reduced. .

  Next, the error detection circuit 350 in the configuration of FIG. 6 will be described. The imaging elements 11 and 12 output ACK to the SDA1 and SDA2 as response signals if they normally receive a command from the I2C control circuit 310, and if they are not received normally, NOACK to the SDA1 and SDA2 as response signals. Output. Due to restrictions on the I2C bus communication protocol of the I2C control circuit 320, only one of the response signals is sent to the I2C control circuit 320 (the response signal of the image sensor 11 in FIG. 6).

  On the other hand, the error detection circuit 350 inputs response signals output from the image sensors 11 and 12 to the SDA1 and SDA2 via the buffer circuits 372 and 373, and monitors the state of the response signals output from the image sensors 11 and 12. ing. The error detection circuit 350 notifies the CPU 40 (FIG. 1) of the occurrence of an error via the bus I / F when one or both response signals are NOACK or when no response signal is output at the ACK output timing. To do. In response to this, the CPU 40 instructs the I2C control circuit 320 to stop the process, and for example, the process is restarted from the beginning. Thereby, the reliability of the command setting process can be improved.

  Note that the error detection circuit 350 may notify the I2C control circuit 320 together with the CPU 40 when an error occurs. In this case, the I2C control circuit 320 immediately stops processing and waits for a subsequent instruction from the CPU 40.

  Next, in the imaging control unit (I2C control device) 30 according to the present embodiment in FIG. 6, the operation in the single mode in which the I2C control circuit 320 individually transmits and receives data and the like with the imaging device 11 or the imaging device 12 will be described. .

  The I2C control circuit 320 of the imaging control unit 30 may perform transmission / reception of commands and status individually with the imaging device 11 or the imaging device 12 according to an instruction from the CPU 40 (FIG. 1) or the like as necessary. This will be referred to as a single operation mode. In the case of the configuration of FIG. 6, the single operation mode can be implemented simply by switching the output selector 330 and the input selector 340.

  FIG. 7 is a diagram illustrating states of the output selector 330 and the input selector 340 when the I2C control circuit 320 performs transmission / reception of commands, statuses, and the like with the image sensor 11. Note that the error detection circuit 350 is not necessary in the single operation mode, and is omitted in FIG.

  The I2C control circuit 320 receives a single operation mode command of the image sensor 11 from the CPU 40, and sends a switching signal to the output selector 330 to connect the SDA output of the I2C control circuit 320 to the SDA1 of the image sensor 11. The selector 340 sends a switching signal to connect the SDA 1 of the image sensor 11 to the SDA input of the I2C control circuit 320. As a result, the output selector 330 connects the SDA output of the I2C control circuit 320 to the SDA1 of the image sensor 11 via the three-state buffer circuit 362 (second mode). The input selector 340 connects the SDA 1 of the image sensor 11 to the SDA input of the I2C control circuit 320 via the buffer circuit 372. Thereby, SDA2 of the image sensor 12 becomes inactive.

  Thereafter, the I2C control circuit 320 serves as a master device, the image sensor 11 serves as a slave device, and the SDA1 is used between the I2C control circuit 320 and the image sensor 11 to execute commands and status in accordance with a normal I2C bus communication protocol. Etc. will be implemented. That is, in the data write operation, the I2C control circuit 320 transmits a command or the like to the image sensor 11 through the path of the output selector 330, the three-state buffer circuit 362, and SDA1, and the image sensor 11 has SDA1, the buffer circuit 372, and the input selector 340. The response signal (ACK) is returned to the I2C control circuit 320 through the path (1). In the data read operation, the image sensor 11 transmits the status and the like to the I2C control circuit 320 through the path of the SDA1, the buffer circuit 372, and the input selector 340. The I2C control circuit 320 outputs the output selector 330, the three-state buffer circuit 362, A response signal (ACK) is returned to the image sensor 11 through the route of SDA1. Until the end of a series of communication sequences, the I2C control circuit 320 drives the 3-state buffer circuit 361 and sends a clock to the SCL, as in the previous simultaneous operation mode.

  FIG. 8 is a diagram illustrating the states of the output selector 330 and the input selector 340 when the I2C control circuit 320 performs transmission / reception of commands, statuses, and the like with the image sensor 12. Again, the error detection circuit 350 is omitted.

  As illustrated in FIG. 8, when performing transmission / reception of commands, statuses, and the like between the I2C control circuit 320 and the image sensor 12, the output selector 330 receives a switching signal from the I2C control circuit 320, thereby causing the I2C control circuit 320 to perform transmission / reception. Are connected to the SDA2 of the image sensor 12 via the three-state buffer circuit 363 (second mode). Similarly, the input selector 340 receives the switching signal from the I2C control circuit 320 to connect the SDA2 of the image sensor 12 to the SDA input of the I2C control circuit 320 via the buffer circuit 373. As a result, the I2C control circuit 320 becomes a master device and the image pickup device 12 becomes a slave device, and the SDA2 is used between the I2C control circuit 320 and the image pickup device 12 to execute commands and commands in accordance with a normal I2C bus communication protocol. Status and other information can be sent and received. At this time, SDA1 of the image sensor 11 is inactive.

  As described above, in the imaging control unit 30 according to the present embodiment, the I2C control circuit 320 individually transmits and receives commands and statuses with the imaging device 11 or the imaging device 12, and the imaging device 11 and the imaging device 12. It is possible to use the simultaneous operation mode in which the same command or the like is simultaneously transmitted and set for both, and the convenience is improved by installing the image processing apparatus in the imaging apparatus or the like.

  In the embodiment, two image sensors are used, but three or more image sensors may be used. That is, the SDA may be increased by the number of image sensors, and the input / output selector may be configured to select each SDA. Needless to say, the target is not limited to the image sensor.

DESCRIPTION OF SYMBOLS 10 Imaging unit 11, 12 Image sensor 20 Image processing unit 30 Imaging control unit 40 CPU
320 I2C control circuit 330 Output selector 340 Input selector SCL Serial clock line SDA1, SDA2 Serial data line

JP 2009-105731 A

Claims (6)

A serial I / F bus control device that transmits and receives data to and from a plurality of devices of the same type using a serial I / F bus,
A plurality of serial I / F buses respectively connected to the plurality of devices;
One control means which becomes a master device and controls the data transmission / reception based on a predetermined communication protocol with the device as a slave device;
A first mode in which all the serial I / F buses of the plurality of devices are connected to the control means, and a second mode in which any one serial I / F bus of the plurality of devices is connected to the control means A bus switching means having
When the bus switching means is in the first mode, each of the plurality of devices is based on a response signal sent to the serial I / F bus as a response to the reception of the data from the master device at the same timing. The device or a plurality of the devices output the response signal indicating that the data is not received, or the plurality of devices each receive the data from the master device at the same timing as the response. Error detection means for detecting as an error a case where the response signal indicating that data has been received is not output,
The serial I / F bus includes a serial clock line and a serial data line, and the serial clock line is commonly connected to a plurality of the devices.
A serial I / F bus control device.   The control means simultaneously transmits the same data to a plurality of devices based on a predetermined communication protocol using the plurality of serial I / F buses when the bus switching means is in the first mode. The serial I / F bus control device according to claim 1, wherein:   When the bus switching means is in the second mode, the control means uses one of the devices and one of the serial I / F buses connected to the device to perform data based on a predetermined communication protocol. The serial I / F bus control device according to claim 1 or 2, wherein   The error detection means detects the presence or absence of an error by inputting response signals sent from the plurality of devices to the serial I / F bus when the bus switching means is in the first mode. The serial I / F bus control device according to any one of claims 1 to 3.   5. The serial I / F bus control device according to claim 1, wherein the serial I / F bus is an I2C bus, and the control unit is an I2C control unit. 6. An imaging apparatus having a plurality of imaging elements,
The serial I / F bus control device according to any one of claims 1 to 5,
An image pickup apparatus, wherein the image pickup device functions as a slave device.

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