JP6053968B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device using a silicon carbide semiconductor as a semiconductor substrate.

  In power electronics equipment, insulated gate bipolar transistors (IGBTs) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as means for switching between running and stopping power supply to drive loads such as electric motors. Switching devices, schottky barrier diodes (SBDs), rectifiers such as pn diodes are used. Further, a bipolar junction transistor (BJT), a thyristor, a GTO (gate turn off thyristor), or the like is also used.

  The silicon carbide (SiC) semiconductor has a wider band gap than the silicon (Si) semiconductor, and the SiC semiconductor device using the SiC semiconductor has superior pressure resistance compared to the Si semiconductor device using the Si semiconductor, The allowable current density is high and the heat resistance is high, so high temperature operation is possible. Accordingly, SiC semiconductor devices are being developed as next-generation power semiconductor devices.

  At present, in the field of SiC semiconductor devices, development of low-resistance SiC semiconductor devices is energetically aimed at realizing further reduction in loss.

  In a device in which carriers move in the vertical direction through the SiC substrate during operation in the SiC semiconductor device, it is necessary to provide an electrode also on the back surface of the SiC semiconductor substrate. SiC (drain) on the back surface side of the substrate, The contact resistance between the two is required to be low.

  In order to realize a contact with low resistance, a configuration is adopted in which metal silicide, which is a compound of metal and silicon (Si), is formed between the SiC drain and the back-side electrode formed of metal.

  In order to further reduce the resistance of the SiC semiconductor device, a configuration has been adopted in which the element resistance is reduced by reducing the thickness of the SiC substrate. In the method of manufacturing an SiC semiconductor device in which the SiC substrate is thinned, it is desirable to reduce the number of manufacturing steps in the state of the thin SiC substrate. That is, in the manufacturing process in the state of a thin SiC substrate, the probability that the SiC substrate breaks increases. For this reason, it is desirable to thin the SiC substrate after forming the structure on the surface opposite to the back surface, and then form the structure on the back surface side.

  When forming the structure on the back surface side in this manufacturing process, it is necessary to form an ohmic electrode that realizes ohmic connection by keeping the structure on the front surface side at a low temperature and annealing only the back surface side at a high temperature of about 1000 ° C.

  For this purpose, for example, laser annealing which performs local heating using a short pulse laser can be considered.

  A method for forming an ohmic electrode using laser annealing on a SiC semiconductor substrate is disclosed, for example, in Patent Document 1. In this method, first, the back surface of the SiC substrate is thinned by polishing. At that time, polishing is performed so as to form irregularities on the back surface of the SiC substrate.

  Next, after a nickel (Ni) film is deposited on the back surface of the SiC substrate, the nickel film is heated by irradiating the nickel film with laser light. Thereby, a nickel silicide (NiSi) layer is formed at the interface between the nickel film and the SiC semiconductor substrate. The nickel silicide layer is more ohmic than the SiC semiconductor substrate, and the nickel silicide layer becomes an ohmic electrode.

  In Patent Document 2, a nickel film and a titanium (Ti) film are deposited on the back surface of the SiC substrate. A technique is disclosed in which a nickel silicide layer is formed at the interface between the nickel film and the SiC semiconductor substrate by performing rapid thermal annealing (RTA) at 1050 ° C. for 2 minutes. The Ti film reacts with carbon (C) in SiC at the time of nickel silicide formation to form a titanium carbide (TiC) layer. The nickel silicide layer at this time serves as an ohmic electrode, and the TiC layer serves to improve the adhesion between the metal layer deposited on the back surface after this step and the nickel silicide layer.

  In Patent Document 3, a metal (nickel or molybdenum: Mo) film containing an impurity (phosphorus: P) is deposited on the back surface of a SiC substrate, and this film is irradiated with laser light to form a metal silicide film. At the same time, phosphorus is diffused into the SiC substrate, and a technology for a low resistance backside electrode is disclosed.

  In Patent Document 4, although laser annealing is not used, a silicon-rich nickel silicide layer containing silicon at a high concentration is formed by depositing a silicon layer and a nickel layer on the back surface of the SiC substrate and performing heat treatment. A technique for forming a low-resistance, back-side electrode is disclosed.

Special table 2008-135611 gazette JP 2012-248729 A JP 2013-214657 A Special table 2008-506258

  In the method of manufacturing a semiconductor device disclosed in Patent Document 1, irregularities are formed on the back surface of the SiC substrate on which the metal silicide layer is formed, but the irregularities on the back surface are formed in the polishing process. In order to form irregularities with a constant period and depth, the polishing process becomes complicated, which may lead to an increase in cost such as a reduction in throughput.

  In the SiC semiconductor device and its manufacturing method disclosed in Patent Document 2, a nickel silicide layer and a TiC layer are formed by depositing Ni and Ti films. The silicon-rich nickel disclosed in Patent Document 4 The silicide layer is formed by depositing Si and Ni layers to form a NiSi layer. In these SiC semiconductor devices, a step of depositing a Ti film or a Si film in addition to nickel is required, which is considered to cause an increase in cost.

  Further, in the SiC device and the manufacturing method disclosed in Patent Document 3, it is necessary to separately prepare a manufacturing apparatus provided with a metal target containing impurities such as P in the sputtering apparatus, which is also a factor of an increase in cost. It becomes.

  The present invention has been made to solve the above problems, and in a silicon carbide semiconductor device using a SiC substrate, a silicon carbide semiconductor device having a low-resistance and low-cost ohmic electrode on the back surface of the SiC substrate. The purpose is to provide.

A silicon carbide semiconductor device according to the present invention is provided on a silicon carbide semiconductor substrate having a thickness of 150 μm or less, a semiconductor layer disposed on a first main surface of the silicon carbide semiconductor substrate, and the semiconductor layer. A first electrode and a second electrode provided on a second main surface opposite to the first main surface of the silicon carbide semiconductor substrate, the silicon carbide semiconductor substrate The second electrode has a stacked structure in which a carbon layer, a metal silicide layer, and a metal film are stacked in this order from the silicon carbide semiconductor substrate side. In addition, a plurality of carbon aggregates having a diameter of 100 to 200 nm in which carbon is aggregated are scattered in the metal silicide layer.

  According to the silicon carbide semiconductor device of the present invention, since the carbon agglomerates are scattered in the metal silicide layer, the resistance is low and the second ohmic connection with the silicon carbide semiconductor substrate is achieved. A silicon carbide semiconductor device provided with an electrode is obtained. In addition, since the second electrode is composed of a carbon layer, a metal silicide layer, and a metal film, it is inexpensive in cost, and a silicon carbide semiconductor device can be obtained at low cost.

1 is a top view of a silicon carbide semiconductor device according to the present invention. It is a top view which shows typically each impurity region formed in the main surface of the semiconductor substrate of the silicon carbide semiconductor device which concerns on this invention. It is sectional drawing of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a back surface side sectional view of the silicon carbide semiconductor device of Embodiment 1 concerning the present invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a block diagram which shows the structure of a laser annealing apparatus. It is the figure which showed the scanning method of the laser beam typically. It is sectional drawing of the back surface side of the SiC substrate which irradiation of the laser beam was completed. It is a figure explaining the conditions of laser annealing. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a wave form diagram of a laser pulse. It is a block diagram which shows the structure of the laser annealing apparatus used with the manufacturing method of Embodiment 2 which concerns on this invention. It is sectional drawing of a Schottky barrier diode.

(Introduction)
The term “MOS” has been used in the past for metal / oxide / semiconductor junctions, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of the common general knowledge, “MOS” is not only an abbreviation derived from the word source, but also has a meaning including widely a laminated structure of a conductor / insulator / semiconductor.

  Further, in the following description, regarding the conductivity type of impurities, the n-type is generally defined as “first conductivity type” and the p-type is defined as “second conductivity type”, but the opposite definition may be used.

(Embodiment 1)
(Device configuration)
(overall structure)
FIG. 1 schematically shows a top surface configuration of a silicon carbide semiconductor device according to the first embodiment of the present invention, more specifically, a field effect transistor (silicon carbide MOSFET) 100 having a MOS structure formed on a SiC substrate. FIG.

  As shown in FIG. 1, the silicon carbide MOSFET 100 has a cell array region 20 in which a plurality of MOS minimum unit structures called “unit cells” are arrayed at the center of the main surface of a chip 40 having a rectangular outer shape. A gate wiring 15 a is provided so as to surround the outside of the cell array region 20.

  The planar view shape of the cell array region 20 is a square with a central portion of one side recessed inward, and a gate pad 21 extending from the surrounding gate wiring 15a so as to enter a recessed portion inside the cell array region 20. Is provided. Note that the cell array region 20 is separated from the gate pad 21 and the gate wiring 15a.

  An external output gate electrode 15 to which a gate voltage is applied from an external control circuit (not shown) is formed on the gate pad 21, and the gate voltage applied thereto is supplied to the gate of the unit cell through the gate wiring 15a. It is supplied to an electrode (not shown).

  In the cell array region 20, an external output source electrode 10 for connecting the source electrodes (not shown) of the unit cells in parallel is formed.

  Although the uppermost part of the chip 40 is covered with a protective film (not shown), in the gate pad 21 and the cell array region 20, a rectangular opening OP is provided above the external output gate electrode 15 and the external output source electrode 10, respectively. And is connected to an external control circuit (not shown) and an external power line (not shown) through the opening OP.

  Note that in ordinary products, electrodes for temperature sensors and current sensors are often formed together, but the presence or absence of these electrodes is not related to the configuration and effects of the present invention. And illustration is abbreviate | omitted.

  Further, the position and number of the gate pads 21, the shape of the gate wiring 15a and the shape and number of the cell array region 20 vary depending on the MOSFET, but they are also not related to the configuration and effects of the present invention. Explanation and illustration are omitted.

  FIG. 2 is a plan view schematically showing a configuration in the vicinity of the surface of the region PR shown in FIG. The region PR defines a region extending over a part of the edge portion on the gate pad 21 side of the cell array region 20 and a part of the edge portion of the gate pad 21 facing the region PR.

  Here, in the cell arrangement region 20, a plurality of unit cells UC (here, vertical MOSFET unit cells) are arranged in a matrix, but no unit cell is arranged on the gate pad 21, and a plurality of gate cells are arranged. Contact holes 13 are arranged in a matrix.

  2 shows an example in which the unit cells UC are arranged in a 3 × 3 matrix in the left and right and up and down directions in the cell arrangement area 20, but this shows only a part of the cell arrangement area 20. More unit cells are arranged in the entire arrangement region 20.

  As shown in FIG. 2, the unit cell UC has a planar view shape in which the source region 3 surrounds the well contact region 5 whose outer shape is substantially rectangular, and the outer periphery thereof is surrounded by the well region 4. Note that a source contact hole 12 is provided so as to be in contact with the well contact region 5 and a part of the surrounding source region 3. It is electrically connected to the output source electrode 10 (hatched).

  The gate pad 21 is provided on the field oxide film 14, and the gate oxide film 6 extending from the edge of the field oxide film 14 and the field oxide film 14 is interposed between the gate pad 21 and the cell array region 20. Existing. A gate electrode (not shown) is electrically connected to the upper external output gate electrode 15 (hatched) via the gate contact hole 13.

Next, a cross-sectional configuration taken along line AA shown in FIG. 2 will be described using the cross-sectional view shown in FIG. As shown in FIG. 3, silicon carbide MOSFET 100 is formed on SiC substrate 1 containing an n-type (first conductivity type) impurity at a relatively high concentration (n ⁺ ). The SiC substrate 1 is thinned to a thickness of 150 μm or less.

On the main surface of SiC substrate 1, drift layer 2 which is a semiconductor layer containing an n-type impurity at a relatively low concentration (n ⁻ ) is formed. The drift layer 2 is formed by, for example, epitaxial growth.

A plurality of well regions 4 containing p-type (second conductivity type) impurities are selectively formed in the upper layer portion of the drift layer 2, and p-type impurities are relatively formed in the upper layer portion of each well region 4. Well contact regions 5 included at a high concentration (p ⁺ ) are selectively formed. An n ⁺ source region 3 (current output region) is formed so as to surround the well contact region 5.

  Note that the source region 3 and the well region 4 are formed so as to concentrically surround the contact region 5 in plan view as described with reference to FIG. 2, and the depth from the outermost surface of the drift layer 2 in the well region 4. The source region 3 and the well contact region 5 are formed deeper than the depth from the outermost surface of the drift layer 2, and the well contact region 5 is formed in contact with the well region 4.

  In the cell arrangement region 20, a gate oxide film 6 is selectively formed on the drift layer 2, and a gate electrode 7 is formed on the gate oxide film 6. In the gate pad 21, a field oxide film 14 thicker than the gate oxide film 6 is formed on the drift layer 2, and contains phosphorus (P) from the gate oxide film 6 to the field oxide film 14. The gate electrode 7 is formed of a polycrystalline silicon film. That is, the gate electrode 7 is provided above the well region 4 via the gate oxide film 6 in the cell array region 20, but from the gate oxide 21 to the cell array region 20, the gate electrode 7 is gated from above the field oxide film 14. It is formed over the oxide film 6. Note that the plan view shown in FIG. 2 shows a planar configuration in the direction of the arrow along line BB in FIG.

  On the back surface of SiC substrate 1 (the main surface opposite to the side on which drift layer 2 is provided), drain electrode 9 having a laminated structure of a carbon film and a silicide film is formed. In FIG. 3, a single layer structure is shown for convenience. On the drain electrode 9, a back surface connection electrode 11 made of a laminated film of, for example, a nickel (Ni) film and a gold (Au) film is formed. In FIG. 3, a single layer structure is shown for convenience.

  Here, even when a high voltage is applied between the external output source electrode 10 and the back surface connection electrode 11, if no voltage is applied to the gate electrode 7, a channel is formed in the well region 4 immediately below the gate electrode 7. Is not formed. That is, in the case of the voltage application state, the silicon carbide MOSFET 100 is in an off state in which electrons do not flow. On the other hand, when a high voltage is applied between the external output source electrode 10 and the back surface connection electrode 11 and a positive voltage is further applied to the gate electrode 7, a channel is formed in the well region 4 immediately below the gate electrode 7, Electrons flow from the source region 3 through a channel region (well region 4), JFET region 16, drift layer 2, SiC substrate 1, and drain electrode 9. That is, silicon carbide MOSFET 100 is turned on so that electrons flow from external output source electrode 10 toward drain electrode 9. Thus, the on / off of the current is controlled by the gate voltage applied to the gate electrode 7.

  The gate oxide film 6 is formed so as to cover almost the entire main surface of the drift layer 2, but a silicide layer 17 is formed from the well contact region 5 to a part of the source region 3 around the well contact region 5. The gate oxide film 6 is not provided. A field oxide film 14 is provided in the formation region of the gate pad 21 instead of the gate oxide film 6. The gate oxide film 6 and the field oxide film 14 may be collectively referred to as “insulating film”.

  A gate electrode 7 is formed on the gate oxide film 6 from the JFET region 16 to the edge of the well region 4, and the gate electrode 7 extends from the edge of the cell array region 20 to the gate pad 21. It is also formed over the field oxide film 14 in the formation region. All the gate electrodes 7 are connected to each other at a portion not shown.

  Then, an interlayer insulating film 8 is formed so as to cover all the gate electrodes 7, and in the cell array region 20, a source contact hole 12 is provided so as to penetrate the interlayer insulating film 8 and reach the silicide layer 17, In the region where the gate pad 21 is formed, a gate contact hole 13 is provided so as to penetrate the interlayer insulating film 8 and reach the field oxide film 14.

  In the cell array region 20, the external output source electrode 10 made of, for example, aluminum (Al) is formed on the interlayer insulating film 8 so as to fill the source contact hole 12, and the formation region of the gate pad 21 , An external output gate electrode 15 made of, for example, Al is formed on the interlayer insulating film 8 so as to bury the gate contact hole 13.

  Further, the protective film 18 is formed so as to cover the external output source electrode 10 and the external output gate electrode 15, but as described above, the protective film 18 includes the external output source electrode 10 and the external output gate electrode. Openings OP are provided in 15 predetermined regions.

  In FIG. 3, one unit cell UC is surrounded by a broken line. As shown in FIG. 3, the unit cell UC includes an SiC substrate 1, a drift layer 2 formed thereon, one well region 4 formed in the upper layer portion of the drift layer 2, and the well region 4. Source region 3 formed in the surface, well contact region 5 penetrating through source region 3 from the upper surface side of the central portion of source region 3 into well region 4, and drain electrode formed on the back surface of SiC substrate 1 9 and a back surface connection electrode 11 formed thereon.

  In addition, a JFET (Junction Field Effect Transistor) region 16 is formed between the upper side edge portions of the well regions 4 adjacent to each other. The JFET region 16 is also included in the unit cell UC, and includes the silicide layer 17 and the external output source electrode. 10 is also included in the unit cell UC.

  Hereinafter, for simplicity, a region including the source region 3 and the well contact region 5 may be referred to as a SiC region 35.

(Drain electrode configuration)
Next, the configuration of the drain electrode 9 will be described in detail. When a positive voltage is applied to gate electrode 7 to turn on silicon carbide MOSFET 100, it is desirable that the on-resistance is lower. This is because when the on-resistance is high, power loss as a power semiconductor device increases. In order to reduce the on-resistance, it is desirable that the thickness of the SiC substrate 1 is 150 μm or less, but in the first embodiment, the thickness is 100 μm.

  Note that by reducing the thickness of SiC substrate 1, the resistance of SiC substrate 1 is reduced, and the on-resistance of silicon carbide MOSFET 100 can be reduced.

  Further, in order to reduce the on-resistance, the drain electrode 9 that connects the SiC substrate 1 and the back surface connection electrode 11 must also realize ohmic connection with the SiC substrate 1 to reduce the resistance. Therefore, the drain electrode 9 is configured as shown in FIG.

  FIG. 4 is a cross-sectional view showing only the configuration of the back surface side of SiC substrate 1 shown in FIG. 3, and includes carbon layer 92 in contact with SiC substrate 1, nickel silicide layer 94, and carbon aggregate 95. The drain electrode 9 is composed of the aggregate-containing nickel silicide layer 93.

  The carbon layer 92 has a thickness of 10 to 20 nm, and the nickel silicide layer 94 has a thickness of 100 to 150 nm. The carbon aggregate 95 has a circular or elliptical cross section, and has a diameter of 100 to 200 nm. The carbon aggregate 95 is scattered in the nickel silicide layer 94 at intervals of 5 to 15 μm. The carbon aggregate 95 is enclosed in the nickel silicide layer 94 and is not in contact with the carbon layer 92.

  Here, the nickel silicide layer 94 and the carbon aggregate 95 are referred to as a carbon aggregate-containing nickel silicide layer 93. Further, the drain electrode 9 is composed of the carbon aggregate-containing nickel silicide layer 93 and the carbon layer 92.

  As described above, in the present invention, carbon in the nickel silicide layer 94 that causes high resistance is aggregated and dispersed as the carbon aggregate 95, so that the carbon concentration in the nickel silicide layer 94 is reduced and the resistance becomes low. A drain electrode 9 having an ohmic connection with the SiC substrate 1 was obtained.

  In addition, drain electrode 9 is composed of carbon layer 92 and carbon aggregate-containing nickel silicide layer 93, and back surface connection electrode 11 is composed of a metal film, so that it is inexpensive in cost, and silicon carbide MOSFET 100 is obtained at low cost. It is done.

(Production method)
Hereinafter, a method for manufacturing silicon carbide MOSFET 100 will be described with reference to FIGS.

  First, in the step shown in FIG. 5, the n-type drift layer 2 is epitaxially grown on one main surface in the thickness direction of the SiC substrate 1 by using a CVD (chemical vapor deposition) method. The SiC substrate 1 is a substrate whose main surface has an off angle of 4 ° in the (11-20) direction from the (0001) plane, and has a 4H polytype.

The thickness of the SiC substrate 1 is 350 μm at this stage, and the concentration of the n-type impurity in the drift layer 2 is set in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the drift layer 2 is set in the range of 5 to 50 μm.

  On such a drift layer 2, a resist mask (not shown) having an opening is formed by using a photolithography technique so that a region to become the well region 4 is exposed later. This resist mask is used as an impurity implantation blocking mask.

  After formation of the resist mask, p-type impurities are ion-implanted from above the resist mask to selectively form the well region 4 in the upper layer portion of the drift layer 2 in the cell array region 20.

Here, as the p-type impurity, for example, Al is used, and the impurity concentration is set in a range of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ , but the n-type impurity concentration of the drift layer 2 is set. Higher value. The well region 4 may be formed by a single ion implantation, or may be formed by a plurality of ion implantations by changing the acceleration voltage. The acceleration voltage of Al ions is in the range of 100 to 500 kV. Is set.

  Next, after removing the resist mask, a new resist mask (not shown) having an opening is formed using a photoengraving technique so that a region to be the source region 3 is exposed later. This resist mask is also used as an impurity implantation blocking mask.

  After the resist mask is formed, n-type impurities are ion-implanted from above the resist mask to form the source region 3 in the upper layer portion of the well region 4.

Here, as the n-type impurity, for example, nitrogen (N) is used, the impurity concentration is set in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the acceleration voltage of N ions is 50 to The range is set to 200 kV. Note that the depth of ion implantation of the n-type impurity is set to be shallower than the thickness of the well region 4.

  Next, after removing the resist mask, a new resist mask (not shown) having an opening is formed by using a photoengraving technique so that a region that becomes the well contact region 5 is exposed later. This resist mask is also used as an impurity implantation blocking mask.

  After forming the resist mask, p-type impurities are ion-implanted from above the resist mask to form the well contact region 5 in the center of the source region 3.

Here, for example, Al is used as the p-type impurity, and the impurity concentration is set in a range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the acceleration voltage of Al ions is 100 to 200 kV. Set to range. Note that the depth of ion implantation of the p-type impurity is set to be shallower than the thickness of the well region 3.

  Next, after removing the resist mask, high-temperature annealing at 1500 ° C. or higher is performed in order to activate the implanted n-type and p-type impurities.

Next, an oxide film (SiO ² ) having a thickness of about 1 μm is formed on the entire surface of the drift layer 2 by, eg, CVD. Thereafter, an etching mask having an opening is formed so as to expose the cell array region 20 by using a photoengraving technique, and then the oxide film on the cell array region 20 side is removed by etching using the etching mask. Thereby, field oxide film 14 is formed on drift layer 2 in the formation region of gate pad 21.

Then, in the step shown in FIG. 6, the surface of the cell array region 20 is thermally oxidized by exposing the SiC substrate 1 (including the upper structure) to an atmosphere of about 1000 ° C. containing oxygen and water vapor, and the thermal oxide film A (SiO ₂ ) gate oxide film 6 is formed. The thickness of the gate oxide film 6 is, for example, 50 nm.

  The process of forming the gate oxide film 6 and the field oxide film 14 is referred to as a process of forming an “insulating film” on the upper surfaces of the cell array region 20 and the gate pad 21 formation region.

  In the above description, the gate oxide film 6 is a thermal oxide film. However, the gate oxide film 6 may be an oxide film formed by a CVD method, or a thermal oxide film and an oxide film formed by a CVD method. The laminated film may be used.

Next, a polycrystalline silicon film containing phosphorus (P) in the range of 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ is formed on the insulating film by a CVD method to form the gate electrode 7. Although the thickness of the gate electrode 7 is set in the range of 300 to 600 nm, in the first embodiment, the thickness is 500 nm, and the concentration of phosphorus is 2 × 10 ²⁰ / cm ³ .

  Next, an etching mask having an opening is formed so as to expose the gate electrode 7 above the source region 3 and the well contact region 5 by using a photoengraving technique, and then the opening is opened using the etching mask. The gate electrode 7 exposed in the portion is removed by etching. Thus, the gate electrode 7 is formed on the gate oxide film 6 from the JFET region 16 to the edge of the well region 4 and from the edge of the cell array region 20 to the field oxide film 14 in the formation region of the gate pad 21. Remains. A cross-sectional view after removing the etching mask on the gate electrode 7 is shown in FIG.

  Next, an oxide film having a thickness of 1 μm is formed on the entire surface of the SiC substrate 1 (including the upper structure) by, for example, a CVD method to form an interlayer insulating film 8. Subsequently, after forming an etching mask having an opening so as to expose the interlayer insulating film 8 above the well contact region 5 of the cell array region 20 and above the source region 3 using the photolithography technique. Using the etching mask, the interlayer insulating film 8 exposed in the opening is removed by etching, and the gate oxide film 6 thereunder is also removed, thereby forming the source contact hole 12. For this etching, RIE (Reactive Ion Etching) is used.

  By this etching, a part of the source region 3 and the well contact region 5 are exposed on the bottom surface of the source contact hole 12.

  Next, after removing the etching mask, a nickel film (not shown) having a thickness of about 50 nm is formed on the entire surface of the SiC substrate 1 (including the upper structure) by, eg, sputtering, and then annealed.

  Thus, a silicide film (here, nickel silicide film) 17 is formed on the source region 3 and the well contact region 5 exposed at the bottom surface of the source contact hole 12.

  Here, the annealing treatment is performed at a temperature of 300 to 800 ° C. by, for example, RTA (Rapid Thermal Annealing). By heating at the temperature, nickel of the nickel film reacts with SiC constituting the well contact region 5 and the source region 3 in contact with the nickel film, and the silicide layer 17 is formed.

  After the silicide layer 17 is formed, the SiC substrate 1 is cleaned with an acid-based solution containing, for example, sulfuric acid or hydrochloric acid. By this cleaning, the nickel film that has not reacted in the silicidation reaction is removed. The structure shown in FIG. 7 is obtained by removing the unreacted nickel film.

  Next, in the process shown in FIG. 8, an etching mask having a plurality of openings is formed by photolithography so that the interlayer insulating film 8 above the gate electrode 7 in the formation region of the gate pad 21 is exposed. Thereafter, by using the etching mask, the interlayer insulating film 8 exposed in the plurality of openings is removed by etching to form the gate contact hole 13. For this etching, RIE is used.

  By the etching, the gate electrode 7 is exposed on the bottom surface of the gate contact hole 13.

  Next, after removing the etching mask, an Al film having a thickness of about 3 μm is formed on the entire surface of the SiC substrate 1 (including the upper structure) by, eg, sputtering, so that the interlayer insulating film 8 is made of an Al film. Cover the source contact hole 12 and the gate contact hole 13 with an Al film.

  Subsequently, after forming an etching mask having an electrode pattern of the external output source electrode 10 and the external output gate electrode 15 using photolithography, the Al film is patterned by etching using the etching mask. An external output source electrode 10 and an external output gate electrode 15 which are separated electrically and in shape are obtained. Thereby, the structure shown in FIG. 8 is obtained.

  The external output source electrode 10 is electrically connected to the SiC region 35 through the silicide layer 17, and the external output gate electrode 15 is electrically connected to the gate electrode 7 of the gate pad 21.

  Thereafter, protective film 18 is formed on the entire surface of SiC substrate 1 (including the upper structure). An organic film can be used as the protective film 18. In the first embodiment, a polyimide film having a thickness of 8 μm is formed as the protective film 18.

  Then, using a photoengraving technique, after forming an etching mask having an opening in a region corresponding to the opening OP of the external output source electrode 10 and the external output gate electrode 15, using the etching mask, By removing the exposed protective film 18 by etching, an opening OP for connection to an external control circuit and an external power line is formed, and the configuration shown in FIG. 9 is obtained. Through the above steps, the manufacturing process on one main surface side of SiC substrate 1 is completed.

  Next, the structure shown in FIG. 10 is obtained by grinding the back surface side of SiC substrate 1 (including the upper structure) using a grinding apparatus and thinning SiC substrate 1. Here, the thickness of the SiC substrate 1 is reduced in the range of 50 to 150 μm, but in the first embodiment, it is set to 100 μm.

  The thinning process is performed after the manufacturing process on the one main surface side of the SiC substrate 1 is completed, because the SiC substrate 1 after the thinning is easily cracked, and the occurrence rate of the substrate cracking of the SiC substrate 1 This is to reduce the number of steps after thinning as much as possible.

  Therefore, by performing the thinning process after the manufacturing process on the one main surface side of the SiC substrate 1 is completed, the possibility of breaking the SiC substrate 1 is reduced and the manufacturing yield is improved.

  Thereafter, drain electrode 9 is formed on the back surface of SiC substrate 1. A method for forming the drain electrode 9 will be described below.

  First, in the step shown in FIG. 11, a nickel film 91 having a thickness of 100 nm is formed on the back surface of SiC substrate 1 by sputtering. It is necessary to heat-treat the nickel film 91 for silicidation. However, the temperature cannot be raised to 300 ° C. or more because the protective film 18 having low heat resistance and the external output source electrode 10 and the external output gate electrode 15 formed of Al are present on the surface side of the SiC substrate 1. Therefore, a laser annealing method is used as a heat treatment method in which only the nickel film 91 formed on the back surface of the SiC substrate 1 is heated and the temperature on the front surface side of the SiC substrate 1 is not increased. FIG. 11 is a diagram showing a state in which the nickel film 91 is irradiated with the laser light 50. The laser annealing method will be described below.

First, a semiconductor laser-pumped solid-state laser using Nd: YVO ₄ as a laser medium is prepared, and a non-linear optical crystal (wavelength conversion crystal) inside the laser resonator is used to reduce the Nd: YVO ₄ laser oscillation wavelength of 1064 nm. An ultraviolet laser beam having a wavelength of 355 nm which is a double wave is generated.

  As the oscillation state of the laser beam, a laser beam pulse-oscillated by a Q switch is used. This is because when the back surface of the SiC substrate 1 is irradiated with continuous wave laser light, the temperature on the front surface side of the SiC substrate 1 rises to 300 ° C. or higher.

  For pulse oscillation, the pulse width is 35 nsec and the oscillation frequency is 10 kHz. The pulse width is defined by the time (half width) during which the power becomes half or more of the peak value. The power of the laser beam is set to 12W.

  FIG. 12 is a block diagram showing the configuration of the laser annealing apparatus. As shown in FIG. 12, the laser annealing apparatus includes an ultraviolet laser light oscillator 60, a laser optical system 61, a mirror 62, and a stage 63, and the SiC semiconductor wafer 30 is placed on the stage 63. SiC semiconductor wafer 30 refers to SiC substrate 1 in a wafer state.

  As shown in FIG. 12, the laser beam 50 emitted from the ultraviolet laser beam oscillator 60 is shaped into a 300 × 200 μm rectangular beam by the laser optical system 61. The laser beam 50 shaped by the laser optical system 61 is reflected by the mirror 62 and is irradiated perpendicularly to the SiC semiconductor wafer 30 placed on the stage 63.

  A plurality of silicon carbide MOSFETs 100 that have undergone the above steps are formed on SiC semiconductor wafer 30 and placed on stage 63 so that the back surface of SiC substrate 1 on which nickel film 91 is formed faces the mirror 62 side. The

  FIG. 13 is a diagram schematically showing a scanning method of the laser beam 50. As shown in FIG. 13, the stage 63 is movable in the X direction orthogonal to the orientation flat OF and in the Y direction parallel to the orientation flat OF. When the laser beam 50 is irradiated, the stage 63 is moved in the X direction. Scanning at 20 cm / sec, the nickel film 91 on the back surface of the SiC substrate 1 is heated.

  In FIG. 13, the locus of the irradiation region of the laser beam 50 is represented as lines 101, 102, 103, and 104, and the uppermost portion in the Y direction of the SiC semiconductor wafer 30 is a line from the right end toward the left end in the drawing. After being irradiated with the laser beam 50 as in 101, the stage 63 moves by one line in the Y direction, and is irradiated as in the line 102 from the left end to the right end of the SiC semiconductor wafer 30. By repeating this, irradiation is performed as in the lines 103 and 104. The line 104 is in the middle of irradiation, and the laser beam 50 is located at the head of the line 104. In the adjacent lines (for example, lines 101 and 102), the irradiation time is shortened by reversing the scanning direction in the X direction.

  Since the portion of the nickel film 91 irradiated with the laser beam 50 becomes the nickel silicide layer 93, the lines 101 to 104 indicate the portions that have become the nickel silicide layer 93.

  Note that the amount of movement of the stage 63 in the Y direction after irradiation for one line is 180 μm. Here, since the length of the laser beam 50 in the Y direction is 200 μm, when the stage 63 is moved by 180 μm in the Y direction, 10% of the length of the laser beam 50 in the Y direction becomes an overlapping region. The reason for providing such an overlapping region is to prevent generation of an unirradiated portion of the laser light 50 due to gas fluctuation between the laser light 50 and the nickel film 91, a shift during movement of the stage 63, or the like. It is.

  In this way, the stage 63 is moved in the X direction and the Y direction, and the laser beam 50 is irradiated on the entire back surface of the SiC semiconductor wafer 30.

  Since the stage 63 is arranged perpendicular to the laser beam 50, a mechanism for moving the stage 63 in the X direction and the Y direction becomes relatively simple, and an increase in cost can be suppressed.

  FIG. 14 shows a cross-sectional structure of the back surface side of SiC substrate 1 when irradiation with laser beam 50 is completed. As shown in FIG. 14, all of the nickel film 91 formed in the step of FIG. 11 includes a carbon layer 92 in the vicinity of the SiC substrate 1, a carbon aggregate 95, nickel silicide 94, and a carbon layer 96 on the back surface. To change.

  The mechanism in which carbon in the nickel silicide layer 94 is separated and concentrated into the carbon layer 92 in the vicinity of the SiC substrate 1, the carbon aggregate 95, and the carbon layer 96 on the outermost surface of the back surface as described above is as follows. It is.

  That is, the temperature of the nickel film 91 is increased by the irradiation of the laser beam 50 and reacts with Si in the SiC substrate 1 to form nickel silicide. At this time, carbon in the SiC substrate 1 does not form a compound with nickel. This is because the temperature at which nickel carbide is formed is higher than the temperature at which nickel silicide is formed.

  Of the carbon taken into nickel silicide 94, carbon in the vicinity of SiC substrate 1 forms carbon layer 92. Of the carbon taken into nickel silicide 94, the part far from SiC substrate 1, that is, the carbon on the outermost surface (the lowermost part in FIG. 14) on the back surface forms carbon layer 96 and is taken into nickel silicide 94. Among the carbons, the carbon present in the vicinity of the central portion of the nickel silicide 94 in the film thickness direction aggregates to form a carbon aggregate 95.

  Next, laser annealing conditions for forming these layers will be described with reference to FIG. FIG. 15 is a diagram schematically showing a state in which the nickel film 91 is irradiated with the laser beam 50, and is an enlarged view of the region “A” shown in FIG. 13, and shows a part of the lines 103 and 104. ing.

  Here, since the scanning speed of the laser beam 50 (the moving speed of the stage 63 in the X direction) is 20 cm / sec and the oscillation frequency of the pulse oscillation of the laser beam 50 is 10 kHz, the laser beam 50 is 20 μm per pulse (= 20 cm). / 10000) will move. This moving distance is indicated by a length C in FIG.

  That is, from the portion indicated by the broken line in the line 104 in FIG. 15 to the tip is newly silicidated with one pulse, but the laser beam 50 has a length of 300 μm in the X direction. The irradiated region is expanded while the portion that is the layer 93 is repeatedly irradiated. That is, since the length of the laser beam 50 in the X direction is 300 μm, one arbitrary point on the nickel film 91 is irradiated with the laser beam 50 15 times (= 300 μm / 20 μm).

  In this manner, the laser film 50 is irradiated to the nickel film 91 a plurality of times to maintain the high temperature state for a long time. Therefore, the carbon in the nickel silicide layer 94 that causes the high resistance is changed as shown in FIG. As shown in FIG. 2, the carbon aggregate 95 and the carbon layer 96 on the outermost surface of the back surface can be separated and concentrated. As a result, the carbon concentration in the nickel silicide layer 94 is reduced, the resistance is lowered, and the drain electrode 9 in ohmic contact with the SiC substrate 1 is obtained.

  Here, it returns to description of a manufacturing process. The carbon layer 96 on the outermost surface of the back surface formed by irradiation with the laser beam 50 shown in FIG. 14 is removed by a method such as sputter etching. The cross-sectional structure on the back surface side of SiC substrate 1 after removing carbon layer 96 corresponds to FIG.

  FIG. 16 shows a cross-sectional view of silicon carbide MOSFET 100 at the stage where carbon layer 96 has been removed. As shown in FIG. 16, the carbon aggregate-containing nickel silicide layer 93 and the carbon layer 92 constitute the drain electrode 9.

  If unreacted nickel remains on the outermost surface of the back surface of SiC substrate 1 (the lowermost portion in FIG. 14), it is removed by the sputter etching method or the like, similar to carbon layer 96.

  Thereafter, the back connection electrode 11 is formed on the drain electrode 9 by sputtering or the like. For example, a laminated film of a nickel film having a thickness of 600 nm and a gold film having a thickness of 200 nm can be used as the back surface connection electrode 11, and the silicon carbide MOSFET 100 having the cross-sectional configuration shown in FIG. 17 is completed.

  Thus, drain electrode 9 is formed of carbon layer 92 and carbon aggregate-containing nickel silicide layer 93, and back surface connection electrode 11 is formed of a metal film, so that the cost is low and the silicon carbide MOSFET 100 is low in cost. Is obtained.

  In the manufacturing method of silicon carbide MOSFET 100 described above, an important point for obtaining low-resistance drain electrode 9 is to form carbon aggregate 95. For this purpose, it is necessary to increase the power density of the laser beam 50 to a value that is higher than the temperature at which nickel silicide is formed, but it is not sufficient to increase the power density. It is necessary to agglomerate the carbon by increasing the time at which the nickel silicide is formed, that is, the temperature at which nickel atoms, silicon atoms and carbon atoms can freely diffuse.

  Here, the laser power (power density) and the scanning speed of the stage 63 are changed, various contact patterns between the nickel silicide layer and the SiC substrate are produced, and the results of evaluating the characteristics are shown in Table 1 below.

In Table 1, whether the ohmic connection was obtained by changing the scanning speed of the stage 63 from 20 cm / sec to 120 cm / sec by 20 cm / sec for each of the cases where the laser power was changed by 2 W from 8 W to 22 W. It shows the result of judging. The power density (J / cm ² ) is a value obtained by laser power × 1 second ÷ oscillation frequency ÷ laser light area (300 × 200 μm).

  In Table 1, ◯ indicates a condition under which an ohmic connection is obtained, and X indicates a condition under which no ohmic connection is obtained. Further, the lowermost stage of Table 1 shows the total irradiation time (nsec) of the laser beam irradiated to one point of the nickel film, and the longest is 450 nsec when the scanning speed of the stage 63 is 20 cm / sec. , It is shortened in proportion to the increase in scanning speed. The total irradiation time of the laser light is a value obtained by the number of times of laser irradiation to one point of the nickel film × the power duration time required for silicidation.

  From Table 1, it can be seen that the ohmic connection is obtained under the conditions that the laser power is 12 W or more and the scanning speed is 80 cm / second or less, and the ohmic connection is not obtained even when the power is increased at a scanning speed of 100 cm / second or more. .

  Here, simply increasing the power does not change the area of the laser beam, and the pulse width of the laser beam is defined by the half-value width as described above, so that the pulse width does not change even if the power is changed. However, when the power is increased, the time for the nickel film to become more than the power for silicidation increases.

  FIG. 18 shows a waveform diagram of a laser pulse. In FIG. 18, time is taken on the horizontal axis, and power density (arbitrary unit) is taken on the vertical axis. The pulse when the power is 12 W is G1, and the pulse when the power is 18 W is G2. A pulse waveform is shown.

  In FIG. 18, the power at which nickel is silicided is shown as F, and it can be seen that the times during which pulses F1 and G2 are equal to or higher than power F are H1 and H2, respectively.

  As shown in FIG. 18, since the rise and fall times of the laser pulse are steep, even if the power is increased, the time over the power F for silicidation increases only slightly from H1 to H2. That is, even if the power is increased by 50%, the time only increases by about 30% (H2 / H1 = 1.3). Therefore, it can be said that the laser irradiation time for one point of the nickel film is almost independent of the power and is determined only by the scanning speed.

  Moreover, it was confirmed by observation with a TEM (transmission electron microscope) of the cross section that carbon aggregates were generated under the conditions of the circles in Table 1.

  Further, when the scanning speed is 100 cm / second or more, ohmic connection is not obtained even when the power is increased. Therefore, in order to obtain ohmic connection, it is necessary to irradiate the laser beam for 112.5 nsec or more. In other words, in order to obtain ohmic connection, it is necessary to continuously irradiate laser light until a carbon aggregate is formed.

(Modification 1)
In Embodiment 1 described above, an example in which the laser beam 50 uses an Nd: YVO ₄ laser with a wavelength of 355 nm has been described, but the wavelength of the laser beam is not limited to the above.

  For example, the second harmonic of the Nd: YAG laser (wavelength 532 nm), the second harmonic of the Nd: YLF laser (wavelength 532 nm), the second harmonic of the Nd: glass laser (wavelength 535 nm), and the second harmonic of the Yb: YAG laser Second harmonic (wavelength 512 nm), Yb: second harmonic of glass laser (wavelength 535 nm), Ar ion laser (wavelength 488 nm), Ti: sapphire laser second harmonic (wavelength 400 nm) can be used. However, since the reflectance of nickel changes when the wavelength is different, the power is adjusted according to the wavelength.

(Modification 2)
In the first embodiment described above, a configuration is adopted in which the laser beam is substantially scanned by moving the stage 63. Instead of the mirror 62 shown in FIG. 12, two axes (X axis, Y axis) are used. A galvano scanner provided with a (axis) galvanometer mirror may be used.

  That is, the laser light 50 itself may be scanned by rotating the galvanometer mirror in the X direction and the Y direction.

  When a galvano mirror is used, the laser light drive system can be reduced, so that the footprint (device plane area) of the laser annealing device can be reduced. Since the device area in the factory (clean room) is reduced, the manufacturing cost of the silicon carbide semiconductor device can be reduced.

  When a galvano mirror is used, the optical path length changes depending on the irradiation angle. Therefore, a measure such as setting a long distance from the galvano mirror to the SiC semiconductor wafer 30 so that the change in the optical path length is within an allowable range. Take.

(Embodiment 2)
In the manufacturing method of the first embodiment described above, it is necessary to irradiate the back surface of the SiC substrate 1 on which the nickel film 91 is formed with the laser beam 50 a plurality of times. Processing time is long.

  Therefore, in order to improve the throughput of the laser annealing process, it is conceivable to increase the scanning speed of the stage 63 shown in FIG. However, simply increasing the scanning speed of the stage 63 reduces the number of times the laser beam 50 is irradiated onto the nickel film 91, and as described with reference to Table 1, the nickel silicide layer 93 having a low resistance ohmic connection. Cannot be obtained.

  Therefore, when the scanning speed of the stage 63 is increased, the laser beam is increased after increasing the pulse width (pulse oscillation time) of the pulse laser, increasing the oscillation frequency of the pulse laser, or increasing the power of the laser beam. It is necessary to increase the area.

  However, since the pulse width is determined by the characteristics of the laser, it is not easy to increase the pulse width. Further, in the ultraviolet laser light oscillator 60 of the type as shown in FIG. 12 that pulsates with a Q switch and outputs a laser beam of a second harmonic wave or a third harmonic wave with a wavelength conversion crystal, the oscillation frequency is increased. And there is a characteristic that power decreases. This is because when the oscillation frequency is increased, the number of atoms in the laser medium that is excited to a high energy state decreases. Therefore, a method of increasing the oscillation frequency of the pulse laser cannot be used. Further, in the method of increasing the laser power to increase the area of the laser light, it is relatively easy to increase the power, but it is not easy to increase (change) the area of the laser light.

  That is, the profile (intensity distribution) of the laser beam 50 is shaped by the laser optical system 61 (FIG. 12) so as to be uniform within the area (300 × 200 μm) of the laser beam. Since the laser optical system 61 is composed of a combination of cylindrical lenses, it is necessary to prepare a new optical system in order to change the area, and it is impossible for a mass production apparatus to change the area according to the laser power. It is.

  Therefore, in the second embodiment according to the present invention, a laser annealing method capable of obtaining a high-throughput, low-resistance ohmic connection will be described.

  FIG. 19 is a block diagram showing a configuration of a laser annealing apparatus used in the manufacturing method of the second embodiment. The laser annealing apparatus shown in FIG. 19 is configured such that the stage 63a can be installed at a predetermined angle with respect to the laser beam 50. In addition, about the same structure as the laser annealing apparatus demonstrated using FIG. 12, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted. The area of the laser beam 50 is 300 × 200 μm, which is the same as in the first embodiment, but the power of the laser beam 50 is 17W.

  The angle D formed by the stage 63a and the surface perpendicular to the laser beam 50 was 45 °. Thereby, the area of the laser beam 50 on the SiC semiconductor wafer 30 is 1.4 times. To be precise, 1 / cosD = 1.414 times.

  Here, since the power of the laser beam 50 is 17 W, the power density of the laser beam 50 on the SiC semiconductor wafer 30 is about 1.41 times that in the first embodiment, which is 12 W. It becomes the same (17W / 1.414 ≒ 12W).

  In the second embodiment, the X direction for the stage 63a is the direction of the arrow E shown in FIG. 19, and the scanning operation in this direction with the stage 63a tilted is the X direction scanning.

  After the scanning of one line is completed, the stage 63a is moved by 180 μm in the direction perpendicular to the arrow E. This is scanning in the Y direction.

  In the second embodiment, the stage 63a is scanned in the X direction at a speed of 28 cm / sec, which is 1.4 times the scanning speed of 20 cm / sec in the first embodiment (exactly 1 / cosD = 1.414 times). To do. Even if the scanning speed of the stage 63a is 1.4 times, the beam diameter is also 1.4 times. Therefore, the number of times one point of the nickel film 91 is irradiated is 15 times (= 300 μm × 1.4). / (20 μm × 1.4)).

  Since the irradiation scanning speed of the laser beam 50 is 1.4 times that of the first embodiment (more precisely, 1 / cosD = 1.414 times), the time for irradiating the entire SiC semiconductor wafer 30 with the laser beam 50 is 0. 0.7 times (more accurately, cosD = 0.0701 times), and the processing time can be reduced by about 30%.

  Here, the degree of change of each parameter with respect to the first embodiment when the tilt angle D of the stage 63a is changed is shown in Table 2 below.

  Here, as each parameter, the relationship between the total irradiation area, scanning time, required power, laser light area, scanning speed, power increment, shortening time, and efficiency (= shortening time / power increment) is shown. The total irradiation area, scanning time, required power, laser light area, scanning speed, power increment, shortening time, and efficiency are cosD, cosD, 1 / cosD, 1 / cosD, 1 / cosD, and 1 / cosD-1, respectively. , 1-cosD and (1-cosD) / (1 / cosD-1), and in Table 2, the magnification with respect to the case where the tilt angle D of the stage 63a is 0 ° (that is, each parameter of the first embodiment) it's shown.

  From Table 2, when the angle D is small, the power increment is small, that is, it is only necessary to slightly increase the power, but the processing time is hardly shortened. On the other hand, increasing the angle D shortens the scanning time, but it can be seen that the required laser power tends to increase rapidly. Practically, it is desirable to set the angle D in the range of 30 ° to 60 °, and the efficiency in the range of 0.8660 to 0.5.

  The reason why stage 63a is scanned in the direction indicated by arrow E in FIG. 19 is because the position at which laser beam 50 is irradiated onto SiC semiconductor wafer 30 is not changed. This is because the laser optical system 61 is focused at the irradiation position and adjusted so that the profile (intensity distribution) of the laser beam 50 is uniform at this focus.

  As described above, in the manufacturing method of the second embodiment, the power of the laser beam is increased and the stage 63a is tilted, so that the low resistance ohmic connection obtained by the manufacturing method of the first embodiment is obtained. This can be realized in a shorter time than the manufacturing method of the first embodiment.

(Other application examples)
In the first and second embodiments described above, the present invention has been described as being applied to a vertical silicon carbide MOSFET, but the scope of the present invention is not limited to a MOSFET.

  FIG. 20 is a diagram showing a cross-sectional configuration of a Schottky barrier diode (SBD) 200 as another application example.

As shown in FIG. 20, SBD 200 is formed on SiC substrate 1 containing an n-type impurity at a relatively high concentration (n ⁺ ). The SiC substrate 1 is thinned to a thickness of 150 μm or less.

On the main surface of SiC substrate 1, drift layer 2 which is a semiconductor layer containing an n-type impurity at a relatively low concentration (n ⁻ ) is formed. The drift layer 2 is formed by, for example, epitaxial growth.

  Two ion implantation regions 70 containing a p-type impurity are formed apart from each other in the upper layer portion of the drift layer 2, and over the drift layer 2 so as to extend between the two ion implantation regions 70 separated from each other. A formed Schottky electrode 71 is provided. A wiring electrode (anode electrode) 72 is formed on the Schottky electrode 71, and the protective film 18 is provided so as to cover the edge portions of the Schottky electrode 71 and the wiring electrode 72.

  On the back surface of SiC substrate 1 (main surface opposite to the side on which drift layer 2 is provided), a back surface electrode 80 having a laminated structure of a carbon film and a silicide film is formed. In FIG. 20, a single layer structure is shown for convenience. On the back electrode 80, a back connection electrode (cathode electrode) 81 made of, for example, a laminated film of a nickel (Ni) film and a gold (Au) film is formed. In FIG. 20, a single layer structure is shown for convenience.

The concentration of the n-type impurity in the drift layer 2 is set in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the drift layer 2 is set in the range of 5 to 50 μm.

The ion implantation region 70 is formed, for example, by ion implantation of Al as a p-type impurity, and the concentration thereof is set in a range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ .

  The Schottky electrode 71 is made of titanium (Ti) and has a thickness of 50 to 200 nm. The wiring electrode 72 is made of, for example, Al and has a thickness of 2 to 5 μm. The back surface electrode 80 and the back surface connection electrode 81 are the same material and the same structure as the drain electrode 9 and the back surface connection electrode 11 of Embodiment 1, respectively, and description thereof is omitted.

  In the SBD 200 having the structure described above, a current flows when a positive voltage is applied to the wiring electrode 72 and a negative voltage is applied to the back surface connection electrode 81, and no current flows when a negative voltage is applied to the wiring electrode 72 and a positive voltage is applied to the back surface connection electrode 81. .

  The ion implantation region 70 is provided in order to prevent a current from flowing to the periphery of the device when a positive high voltage is applied to the back surface connection electrode 81. In this way, the SBD 200 performs rectification by positive and negative of the voltage applied to the wiring electrode 72 and the back surface connection electrode 81.

  Here, by making the material and structure of the back electrode 80 of the SBD 200 exactly the same as that of the drain electrode 9 of the silicon carbide MOSFET 100 shown in FIG. 4, carbon in the nickel silicide layer that causes high resistance is aggregated. By dispersing the carbon aggregates in the nickel silicide layer, the carbon concentration in the nickel silicide layer was reduced, and the low-resistance back electrode 80 was obtained.

(Other variations)
In the above description, an example in which the back electrode is formed of nickel is shown. However, the back electrode is not limited to nickel, and may be a metal that forms a metal silicide with SiC and partially forms a carbon aggregate. Can be used as a material for the back electrode. For example, molybdenum (Mo), cobalt (Co), tungsten (W), etc. can be used. When nickel is used, the cost is low.

  In the above description, an example in which the silicide layer 17 formed by the RTA method is provided from the well contact region 5 provided in the upper layer portion of the drift layer 2 to a part of the source region 3 around the well contact region 5 is provided. However, the laser annealing method described above may be used instead of the RTA method. In that case, a laser beam may be irradiated after a nickel film is formed on the entire surface of the SiC substrate 1 (including the upper structure), for example, by sputtering.

  In the above description, application to vertical MOSFETs and SBDs has been exemplified. However, in a bipolar device in which both electrons and holes contribute to conduction, for example, in the cross-sectional structure shown in FIG. It goes without saying that the present invention can also be applied to an IGBT whose type is the second conductivity type (p-type).

  Accordingly, the scope of application of the present invention includes unipolar devices such as MOSFETs, and bipolar devices such as pn diodes and IGBTs.

  In the above description, the SiC substrate 1 has been described as being thinned to a thickness of 150 μm or less. However, even the SiC substrate 1 having a thickness exceeding 150 μm is manufactured according to the present invention. By applying this method, carbon in the silicide layer that causes high resistance is aggregated and dispersed as carbon aggregates in the silicide layer, and the carbon concentration in the silicide layer is reduced to obtain a low-resistance electrode. It goes without saying that it can be done.

  Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  Further, within the scope of the invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

Claims (7)

A silicon carbide semiconductor substrate having a thickness of 150 μm or less ;
A semiconductor layer disposed on a first main surface of the silicon carbide semiconductor substrate;
A first electrode provided on the semiconductor layer;
A second electrode provided on a second main surface opposite to the first main surface of the silicon carbide semiconductor substrate, and a main current in a direction perpendicular to the silicon carbide semiconductor substrate A silicon carbide semiconductor device through which
The second electrode is
In order from the silicon carbide semiconductor substrate side, it has a laminated structure in which a carbon layer, a metal silicide layer, and a metal film are laminated,
A silicon carbide semiconductor device characterized in that a plurality of carbon aggregates having a diameter of 100 to 200 nm in which carbon is aggregated are scattered in the metal silicide layer.   The silicon carbide semiconductor device according to claim 1, wherein the metal silicide layer is a nickel silicide layer. (A) preparing a silicon carbide semiconductor substrate;
(B) forming a semiconductor layer on the first main surface of the silicon carbide semiconductor substrate;
(C) forming a first electrode on the semiconductor layer;
(D) after the step (c), grinding the second main surface opposite to the first main surface of the silicon carbide semiconductor substrate to reduce the thickness of the silicon carbide semiconductor substrate; ,
(E) a step of forming a second electrode on the second main surface after the step (d), and a method of manufacturing a silicon carbide semiconductor device,
The step (e)
(E-1) forming a metal film on the second main surface;
(E-2) While irradiating the metal film with a laser beam having an area smaller than the entire surface of the silicon carbide semiconductor substrate in a pulsed manner, the silicon carbide semiconductor substrate is scanned to make the metal film a metal silicide layer. A process of reforming to
(E-3) removing the outermost carbon layer of the metal silicide layer;
Have
The step (e-2)
A silicon carbide semiconductor device comprising a step of irradiating the laser beam at a constant power density for a period of time until a carbon aggregate formed by agglomeration of carbon enclosed in the metal silicide layer is formed in the metal silicide layer Manufacturing method. The step (e-2)
The manufacturing method of the silicon carbide semiconductor device of Claim 3 including the process of irradiating the said laser beam for 112.5 nsec or more. The step (e-2)
The method for manufacturing a silicon carbide semiconductor device according to claim 3 , further comprising a step of arranging the silicon carbide semiconductor substrate so as to be perpendicular to the laser light and irradiating the laser light. The step (e-2)
5. The method for manufacturing a silicon carbide semiconductor device according to claim 3 , further comprising a step of irradiating the laser light while tilting the silicon carbide semiconductor substrate so as to have an angle smaller than perpendicular to the laser light. The step (e-1)
Forming a nickel film as the metal film,
The method for manufacturing a silicon carbide semiconductor device according to claim 3 , wherein the metal silicide layer is a nickel silicide layer.

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