JP5929840B2 - Power supply control device - Google Patents

Description

  The present invention relates to a technique for detecting a short circuit of a load.

  In the following Patent Document 1, in an apparatus that drives a load using an intelligent power device, when an overcurrent (load short-circuit) is detected, the current flowing through the switching element is cut off by shutting off the gate voltage of the switching element. The point which restricts is described.

JP 2005-312099 A

In order to suppress heat loss, it is preferable to use an intelligent power device having a low on-resistance. However, intelligent power devices with low on-resistance are expensive. Therefore, development of a low-cost power supply control device that can suppress heat loss has been demanded.
The present invention has been completed based on the above circumstances, and an object thereof is to provide a low-cost power supply control device that can suppress heat loss.

The present invention is a power supply control device for controlling power supply from a power source to a load, the first FET having an overcurrent detection circuit provided for the energization path to the load, and the first By outputting a drive signal to each of the second FET connected in parallel to the FET and not having an overcurrent detection circuit, and to the first FET and the second FET, the first FET A control circuit for individually turning on and off the FET and the second FET, and when the control circuit starts to supply power to the load, the first FET is turned on. Delay the timing to turn on the second FET, and when supplying power to the load, turn on both the first FET and the second FET and stop supplying power to the load Turn off the second FET Off the first FET delayed timing, further, with the on-off control of the switching of said first FET and said second FET, a decision value of the overcurrent by the overcurrent detection circuit, Switch to a value according to the diversion ratio of the two FETs.

  In this configuration, when supplying power, in addition to the first FET on the intelligent power switch side, the second FET side connected in parallel is also turned on, and the load is driven using two FETs. Therefore, it is possible to suppress the drain current flowing through the first FET, as compared with the case where the load is driven using only the first FET on the intelligent power switch side. Accordingly, since it is possible to suppress heat loss in the first FET, it is possible to use an intelligent power device that has a relatively large on-resistance and is inexpensive, and can reduce the cost of the power supply control device.

  In addition, since the control circuit of the power supply control device switches the determination value for detecting the overcurrent according to the shunt ratio of the two FETs, whether or not there is an overcurrent such as a load short-circuit regardless of the difference in the shunt ratio. It can be detected accurately.

  According to the present invention, it is possible to provide a low-cost power supply control device that can suppress heat loss.

Circuit diagram of power supply control device applied to one embodiment The figure which shows the relation between ON / OFF of each FET and judgment value A diagram summarizing the relationship between the diversion ratio and judgment value

<One Embodiment>
An embodiment of the present invention will be described with reference to FIGS.
The present embodiment exemplifies a power supply control device 1 that controls power supply to an electrical load such as a headlight mounted on an automobile.

1. Circuit Configuration of Power Supply Control Device 1 As shown in FIG. 1, the power supply control device 1 includes an intelligent power switch 10 and a second FET 21.

  The intelligent power switch 10 includes a first FET 11, an overcurrent detection circuit 15 that detects an overcurrent of the first FET 11, and a control circuit 17 in the same semiconductor envelope (package).

  The first FET 11 is an N-channel, E-mode (enhancement mode) power MOSFET (insulated gate field effect transistor), and has a drain D connected to a power line (power line drawn from the battery B) Lv, and a source S is connected to a load R. The intelligent power switch 10 is provided with external connection terminals C1 and C2, and the second FET 21 is connected in parallel to the first FET 11.

  Similar to the first FET 11, the second FET 21 is an N-channel, E-mode power MOSFET (insulated gate field effect transistor), and the drain D is connected to the power supply line Lv via the external terminal C1, and the source S is connected to the load R via the external terminal C2, and is connected in parallel to the first FET 11. The gate of the second FET 21 is connected to the control circuit 17 via the external control terminal C3.

  The control circuit 17 individually controls on / off of two FETs connected in parallel, that is, the first FET 11 and the second FET 21 in response to an input signal from the outside. While the drive signal S1 is output from the control circuit 17 to the gate G, the first FET 11 is turned on. When the output of the drive signal S1 is stopped, the first FET 11 is turned off.

  Similarly, the second FET 21 is turned on while the drive signal S2 is being output from the control circuit 17 to the gate G through the external control terminal C3. When the output of the drive signal S2 is stopped, the second FET 21 is turned off. It becomes a state. The overcurrent detection circuit 15 functions to detect an overcurrent of the first FET 11 by detecting a current (drain current) flowing through the first FET 11 and comparing it with a determination value. When an overcurrent is detected by the overcurrent detection circuit 15, the control circuit 17 stops the drive signals S 1 and S 2 for the gates G of the first FET 11 and the second FET 21 to cut off the overcurrent. The power supply control device 1 is protected from overcurrent.

  In the following description, the on-resistance of the two FETs 11 and 21 (resistance value when turned on) is 10Ω, and when the two FETs 11 and 21 are turned on simultaneously, the shunt ratio is 1: 1. .

2. Description of operation of the power supply control device 1 (1) At the start of power supply (turn-on)
When starting the supply of power to the load R (at the start of power supply), the control circuit 17 sets a time difference in the timing of turning on the two FETs 11 and 21, and after turning on the FET 11 on the intelligent power switch 10 side, Control to turn on the externally attached FET 21 is performed (turn-on control).

  That is, as shown in FIG. 2, the drive signal S1 is first output from the control circuit 17 to the first FET 11 (time t1). As a result, the first FET 11 shifts from OFF to ON in response to the input of the drive signal S1 (time t2). Then, the control circuit 17 outputs the drive signal S2 to the second FET 21 at time t3 after the first FET 11 is turned on. In response to the input of the drive signal S2, the second FET 21 shifts from off to on at time t4. Thereby, both the two FETs 11 and 21 are turned on (turn-on completion).

(2) During power supply When power is supplied to the load R, the output of the drive signals S1 and S2 is continued for the two FETs 11 and 21 that are turned on at time t4, and both the FETs 11 and 21 are in the on state. Become. Therefore, when power is supplied (in the period from time t4 to time t5 in FIG. 2), the load current Ir flows by half with respect to the two FETs 11 and 21, and the shunt ratio between the two FETs 11 and 21 is 1: 1. . In FIG. 1, “Id1” is the drain current of the FET 11, and “Id2” is the drain current of the FET 21.

(3) When power supply is stopped (turn off)
When the power supply to the load R is stopped (when the power supply is stopped), the control circuit 17 sets a time difference at the timing of turning off the two FETs 11 and 21 and turns off the externally attached FET 21 before the intelligent power Control to turn off the FET 11 on the switch 10 side is performed (turn-off control).

  That is, as shown in FIG. 2, the output of the drive signal S2 from the control circuit 17 to the second FET 21 is first stopped (time t5). Then, in response to the output stop of the drive signal S2, the second FET 21 shifts from on to off (time t6). Then, the control circuit 17 stops the output of the drive signal S1 to the first FET 11 at time t7 after the second FET 21 is turned off. The first FET 11 shifts from on to off at time t8 in response to the output stop of the drive signal S1. As a result, both the two FETs 11 and 21 are turned off (turn-off completion).

(4) Determination Value and Overcurrent Detection Operation The control circuit 17 performs a process of switching the overcurrent determination value by the overcurrent detection circuit 15 according to the shunt ratio of the two FETs 11 and 21. In this embodiment, since the shunt ratio of the FETs 11 and 21 has two patterns of “1 to 0” or “1 to 1”, the judgment value corresponds to the shunt ratio “1 to 0” as shown in FIG. Two patterns of a first determination value Ia to be performed and a second determination value Ib corresponding to the diversion ratio “1 to 1” are set.

  When the shunt ratio is “1: 1”, the drain current Id1 of the FET 11 is “1/2” compared to when the shunt ratio is “1: 0”. Therefore, as shown in the following equation (1), the second determination value Ib corresponding to the shunt ratio “1 to 1” is “1” of the first determination value Ia corresponding to the shunt ratio “1 to 0”. / 2 ".

Ib = Ia / 2 (1) formula

  Hereinafter, the overcurrent detection operation will be described in detail. Only the FET 11 is on during the turn-on period (time t1 to time t4) at the start of power supply and the turn-off period (time t5 to time t8) at the time of power supply stop. There is a period, and during that period, the shunt ratio between the FET 11 and the FET 21 is “1 to 0”. Therefore, the control circuit 17 sends a command to the overcurrent detection circuit 15 during the turn-on period (time t1 to time t4) and the turnoff period (time t5 to time t8), and sets the overcurrent determination value as “first determination. Value Ia ".

  Therefore, during the turn-on period (time t1 to time t4) and the turn-off period (time t5 to time t8), the overcurrent determination value is set to the “first determination value Ia”, and the overcurrent detection circuit 15 detects the drain current of the FET 11. Id1 is compared with “first determination value Ia”, and when the drain current Id1 exceeds “first determination value Ia”, an overcurrent detection signal is output to the control circuit 17.

  On the other hand, at the time of power supply (time t4 to time t5), both the two FETs 11 and 21 are turned on, and the shunt ratio between the FETs 11 and 21 is “one to one”. Therefore, the control circuit 17 sends a command to the overcurrent detection circuit 15 during power supply (time t4 to time t5), and changes the overcurrent determination value from “first determination value Ia” to “second determination value”. Switch to “Ib”.

  Therefore, at the time of power supply (time t4 to time t5), the overcurrent determination value is set to “second determination value Ib”, and the overcurrent detection circuit 15 sets the drain current Id1 of the FET 11 to “second determination value Ib”. In comparison, when the drain current Id1 exceeds the “second determination value Ib”, an overcurrent detection signal is output to the control circuit 17.

  When the overcurrent detection signal is input from the overcurrent detection circuit 15, the control circuit 17 stops the drive signals S 1 and S 2 for the gates G of the first FET 11 and the second FET 21 in response thereto. Cut off the overcurrent.

3. Explanation of Effect In the power supply control device 1, when power is supplied (time t4 to time t5), in addition to the FET 11 on the intelligent power switch 10 side, the FET 21 side connected in parallel is also turned on, and the load R is switched to the two FETs 11 and 21. Use to drive.

  Therefore, the drain current Id1 flowing through the FET 11 can be suppressed as compared with the case where the load R is driven using only the FET 11 on the intelligent power switch 10 side. Accordingly, since it is possible to suppress heat loss in the FET 11, it is possible to use the intelligent power switch 10 having a relatively large on-resistance and a low cost, and the power supply control device 1 can be reduced in cost.

  In addition, since the control circuit 17 of the power supply control device 1 sets (switches) the determination value for detecting the overcurrent according to the diversion ratio of the two FETs 11 and 21, the load does not depend on the difference in the diversion ratio. Existence of overcurrent such as short circuit can be detected accurately. Therefore, when an overcurrent is detected, the two FETs 11 and 21 can be protected from overcurrent by blocking the two FETs 11 and 21.

  Furthermore, the power supply control device 1 performs control to turn on the FET 21 that is externally attached with a delay in timing after the FET 11 on the intelligent power switch 10 side is turned on at the start of power supply (turn on). When power supply is stopped (turned off), the external FET 21 is turned off, and then the timing is delayed and the FET 11 on the intelligent power switch 10 side is turned off. That is, at the time of turn-on and turn-off, the supply of power is started or stopped after a period in which only the FET 11 is on.

If the supply of power is started or stopped after only the FET 21 having no overcurrent detection circuit is on, the overcurrent cannot be detected during the period when only the FET 21 is on, and the FET 21 may be damaged. There is. In this regard, as in this embodiment, if only the FET 11 is turned on and then the supply of power is started or stopped, overcurrent can be reliably detected even at turn-off and turn-on. It is possible to reliably protect the two FETs 11 and 21 from overcurrent.
<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  (1) In the above embodiment, the shunt ratio between the FET 11 and the FET 21 at the time of power supply is set to 1: 1, but it is sufficient that the two FETs 11 and 21 are simultaneously turned on at the time of power supply. It is not limited to the illustrated ratio.

  (2) In the above embodiment, an example in which the two FETs 11 and 21 are protected by blocking the output of the drive signals S1 and S2 to the two FETs 11 and 21 when an overcurrent is detected has been described. The FETs 11 and 21 may be protected by reducing the duty ratio to suppress the current value.

1 ... Power supply control device 10 ... Intelligent power switch 11 ... First FET
15 ... Overcurrent detection circuit (first FET overcurrent detection circuit)
17 ... Control circuit 21 ... Second FET

Claims (1)

A power supply control device for controlling power supply from a power source to a load,
A first FET provided for a current path to the load and having an overcurrent detection circuit;
A second FET connected in parallel to the first FET and having no overcurrent detection circuit;
A control circuit that individually controls on / off of the first FET and the second FET by outputting drive signals to the first FET and the second FET, respectively.
The control circuit includes:
When starting to supply power to the load, turn on the first FET, turn on the second FET with a delay in timing after turning on the first FET,
When supplying power to the load, turn on both the first FET and the second FET,
When stopping the power supply to the load, turn off the second FET and turn off the first FET by delaying the timing.
Further, along with the on / off control switching of the first FET and the second FET, the overcurrent determination value by the overcurrent detection circuit is switched to a value corresponding to the shunt ratio of the two FETs. A power supply control device characterized by that.

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