JP5922860B2 - Manufacturing method of high resistance silicon wafer - Google Patents

Description

  The present invention relates to a technique suitable for use in a high-resistance silicon wafer used for a substrate of a high-frequency integrated circuit device or the like.

The demand for high-frequency circuits is increasing due to the spread or miniaturization of high-frequency devices such as for mobile communication and short-range wireless LAN, and the increase in signal amount. High resistance is required for the substrate of the high frequency circuit. For such applications, CMOS (Complementary Metal Oxide semiconductor) with a substrate made from a silicon single crystal by the usual Czochralski method (CZ method) is applied instead of a very expensive compound semiconductor such as GaAs. There is also. In addition, the FZ method (band melting method) is difficult to produce a single crystal having a large diameter, has a problem in quality stability and cost, and cannot sufficiently respond to demand.
A CMOS using a CZ substrate has been regarded as inappropriate because it consumes a large amount of power and generates a large amount of substrate noise. However, improvements in miniaturization technology and design have been promoted, and these problems can be overcome by using a silicon wafer by the CZ method having a high resistance value.

In the CZ method, a raw material is melted using a quartz crucible, and a silicon single crystal is produced by directly pulling and growing from the melt, and the resistivity of high-purity silicon, which is 2.3 × 10 ⁵ Ωcm, is determined by boron (B : P-type) and phosphorus (P: n-type) are added in a small amount to adjust to a desired resistivity. The silicon single crystal by the CZ method usually contains about 20 ppma (16 × 10 ¹⁸ atoms / cm ³ [ASTMF121-1979]) of oxygen dissolved from the crucible.

The relatively high concentration of oxygen contained in silicon can cause defects in silicon wafers and cause device characteristics defects.On the other hand, in the device manufacturing process, it is possible to increase the strength of the wafer, such as preventing slip extension. There are effects such as suppressing deformation and forming minute defects in the wafer as gettering sites for trapping mixed heavy metal ions that cause device malfunction.
When a silicon single crystal by the CZ method is used, there is a case where the resistivity set to a high resistance is greatly changed by reducing the amount of dopant due to oxygen inevitably mixed. In silicon, oxygen atoms are usually electrically neutral and do not directly affect their electrical resistance.
When heat treatment is performed for a long time of about 1 hour or longer and under a low temperature range of 300 to 500 ° C., a composite that does not reach a stable SiO ₂ precipitate is formed. It is called an oxygen donor or a thermal donor because it emits and exhibits the properties of a donor.

  FIG. 1 is a diagram schematically showing the relationship between the amount of thermal donor generation and the resistivity of a wafer. In the case of a low-resistance wafer having a normal resistivity of about 10 Ωcm, the amount of dopant is sufficiently larger than the amount of thermal donors generated, so even if thermal donors are generated, the influence on the resistivity is negligible. However, in the case of a high-resistance wafer, since the amount of dopant is small, the resistivity is greatly influenced by the thermal donor. In particular, in the case of the p-type, the conductivity brought about by the holes by the acceptor disappears due to the supply of electrons by the donor, and the resistivity increases remarkably and increases to infinity. Then, when donors increase and the oxygen donor concentration exceeds the concentration of accessories, p / n-type inversion occurs, resulting in an n-type semiconductor and a decrease in resistivity. Heating in a temperature range where thermal donors are likely to occur is inevitably performed as a heat treatment such as wiring formation in the final stage of device manufacture.

The generation amount of thermal donors is small in a silicon wafer having a low oxygen concentration. Therefore, in order to reduce the oxygen content, a magnetic field application pulling method (MCZ method) in which a single crystal pulling is performed while controlling the flow by applying a magnetic field to the silicon melt in the crucible, and the inner surface is coated with SiC. A method for producing a low-oxygen single crystal such as a method using a crucible has been proposed.
However, these oxygen reduction methods have technical limitations in reducing oxygen, increase costs, and lower oxygen reduces the strength of the wafer, causing deformation in the device manufacturing process. There is also a problem that non-defective products are easily generated.

Patent Document 1 discloses an invention relating to a high-resistivity wafer using a silicon single crystal by the CZ method and excluding the influence of a thermal donor and a method for manufacturing the same. This invention has a resistivity of 100 Ωcm or more and an initial interstitial oxygen (solid oxygen) concentration of 10 to 25 ppma (7.9 × 10 ^{17 to} 19.8 × 10 ¹⁷ atoms / cm ³ [ASTMF121-1979]). Then, a single crystal by a CZ method containing a normal oxygen amount is processed into a wafer, and this is subjected to an oxygen precipitation treatment, so that the residual interstitial oxygen concentration is 8 ppma (6.4 × 10 ¹⁷ atoms / cm ³ [ASTMF121-1979]. ) The following. However, it is explained that the heat treatment method for reducing the residual interstitial oxygen concentration to 8 ppma is not particularly limited as long as oxygen precipitates are formed and the residual interstitial oxygen concentration should be 8 ppma or less. In a few examples, the heat treatment was performed in an oxygen atmosphere or a nitrogen atmosphere at 800 ° C. for 4 hours and in an oxygen atmosphere at 1000 ° C. for 16 hours, or in an oxygen atmosphere at 650 ° C. for 2 hours. Similarly, only three-stage heat treatment by heating at 800 ° C. for 4 hours and 1000 ° C. for 16 hours in an oxygen atmosphere is shown, and the heat treatment condition range and the like are not clarified.

In general, a DZ-IG (Intrinsic Gettering) process is performed as a method for controlling the presence of oxygen in the thickness direction of a wafer on which a device is formed. This is because the region near the wafer surface where the device is formed, that is, the activation region is a defect-free layer (DZ: Denuded Zone), and the inside is caused by oxygen precipitates that act to capture mixed heavy metal ions and the like. This is a heat treatment for forming defects.
Usually, (1) high temperature oxygen outward diffusion heat treatment for surface DZ formation, (2) low temperature heat treatment (precipitation nucleation heat treatment) for precipitation nucleation, and (3) internal gettering site A three-stage heat treatment, ie, a medium temperature or high temperature heat treatment (oxygen precipitate growth heat treatment) for forming defects due to oxygen precipitates is performed.

Patent Document 2 discloses a wafer for performing this DZ-IG treatment on a high-resistance wafer having a resistivity of 100 Ωcm or more and an invention of the conditions. As in the invention of Patent Document 1, the interstitial oxygen concentration is 8 ppm or less in any part of the wafer, and has a DZ near the surface and an oxygen precipitate layer in the bulk part. The width of the transition region with the oxygen precipitate layer is 5 μm or less.
The wafer manufacturing method of the above-mentioned Patent Document 2 uses a wafer processed from a single crystal having an initial interstitial oxygen concentration of 10 to 25 ppma obtained by the CZ method, and (a) 950 to 1050 ° C. for 2 to 5 hours. First heat treatment, (b) second heat treatment at 450-550 ° C. for 4-5 hours, (c) third heat treatment at 750-850 ° C. for 2-8 hours, and (d) fourth heat treatment at 950-1100 ° C., The interstitial oxygen concentration is set to 8 ppm or less as described above.
In this case, the first heat treatment (a) is an oxygen outward diffusion treatment for forming DZ on the surface, and the fourth heat treatment (d) is an oxygen precipitation treatment for forming a gettering site. And (c) seems to be trying to reduce the interstitial oxygen concentration to 8 ppm or less by carrying out the treatment for the formation of precipitation nuclei more sufficiently.

International Publication No. WO00 / 55397 Pamphlet Japanese Patent Laid-Open No. 2002-1000063 Japanese Patent No. 3985768

  However, it is not always easy to reduce the concentration of dissolved oxygen to 8 ppma or less over the entire wafer thickness direction by heat treatment, which requires a large number of heat treatment steps and increases the manufacturing cost. In addition, reducing the concentration of dissolved oxygen greatly reduces the strength of the wafer, so even if oxygen donors can be reduced, deformation and slip dislocations occur in the wafer during the high-temperature heat treatment performed in the device formation process. Easy to do.

  In Patent Document 3, the above-mentioned problem is solved by setting the depth of the p / n type inversion region by carbon doping to about 8 μm from the surface. However, in C-doping, if the carbon concentration is increased, polycrystallization occurs and the rate of single crystallization (Dislocation Free; hereinafter referred to as DF) decreases. As a result, the single crystal cannot be pulled up. There is a certain upper limit, and higher concentration carbon-doped wafers cannot be produced.

  Further, in the carbon-doped wafer, due to the upper limit of the carbon concentration range necessary for pulling up the single crystal, the depth position range where the n-type region can be formed by p / n-type inversion as in Patent Document 3 is about 10 μm from the surface at the maximum. P / n-type inversion from the increase of the applicable frequency range, which is called the high frequency, which is the latest device design condition, the demand for power consumption reduction and the requirement for miniaturization of the design rule, to a further depth, from 20 μm to 60 μm There has been a demand for expanding the range in which no occurrence occurs, and for accurately performing such deep position control.

  Further, in a voltage control oscillator used in a transmission / reception circuit of a cellular phone, as shown in FIG. 15, a magnetic field VCO-B generated when a current flows through a coil VCO-C in the digital domain VCO-D. The eddy current VCO-E flows, which becomes a loss current VCO-d to the analog region VCO-A, and there is a problem that the efficiency η is lowered. Remove voltage controller

The present invention has been made in view of the above circumstances, and in a p-type high-resistance wafer using a single crystal by the CZ method, the CMOS formed in the active region of the surface is defective in operation and insufficient n-well separation. Therefore, it is possible to provide a high-resistance wafer having excellent characteristics that can reduce the occurrence of current loss, and to achieve the following object.
1. A region where p / n-type inversion occurs can be formed in a deeper range than a carbon-doped wafer while maintaining a single crystal, and current loss can be reduced.
2. To be able to control the boundary depth at which p / n-type inversion occurs.
3. Specifically, the boundary depth is formed so that the depth can be controlled at least in the range of 10 μm to 70 μm from the wafer surface. To provide a wafer capable of maintaining p-type over its entire depth in a high-resistance wafer, that is, capable of preventing occurrence of p / n-type inversion, and a method for manufacturing the same.

  When a CMOS is manufactured as a device manufacturing process on a p-type high-resistance CZ wafer and the characteristics thereof are investigated, the target characteristics cannot be sufficiently obtained, or adjacent n-wells cannot be sufficiently separated. As a result of various investigations on high-resistance wafers that caused problems, the following things became clear.

  First, in the wafer before the device is formed on the surface, there is no problem with oxygen precipitates called DZ layer on the surface layer or BMD (Bulk Micro Defect) inside, but it is normally distributed. Examination of the wafer after the formation of the p-type semiconductor near the surface, but there is something that is inverted to the n-type semiconductor inside, especially this p / n-type inversion region is located near the surface In such a case, the characteristics of the CMOS did not reach the target value, or n-well separation was insufficient.

As shown in FIG. 1, it is presumed that the p / n-type inversion generated inside the wafer is caused by a thermal donor generated by heat treatment in the manufacturing process of device formation. However, reducing the dissolved oxygen throughout the depth direction of the wafer so that thermal donors do not occur requires heat treatment to be sufficiently long, which increases the manufacturing time and decreases the productivity. There is a problem that there is a risk of lowering.
Furthermore, this p / n-type inversion phenomenon is often observed in wafers with higher resistivity. Even if p / n-type inversion occurs, if this p / n-type inversion region is at a sufficiently deep position. Since the p / n type inversion region is formed at a deeper position and the position control is performed so as to maintain the p type at a shallower portion, the device characteristics are improved. It does not affect. That is, if the position where the thermal donor is generated is deep enough not to affect the operation of the CMOS formed on the surface, the wafer characteristics are sufficient.

  That is, when an n-well is formed on a p-type wafer, a depletion layer is formed between the well and the wafer substrate, but the p / n type inversion region is sufficiently separated from the depletion layer. It is only necessary to control the occurrence of n-type inversion. When the resistivity of the wafer is high, the region of the depletion layer becomes larger than when the resistivity is low, so in the case of a high resistance wafer applied to a device corresponding to a high frequency band, the generated p / n type The depth of the inversion region from the surface needs to be sufficiently large that a wafer manufactured by carbon doping cannot cope with it.

FIG. 2 is a diagram for explaining the relationship between the configuration of the CMOS formed on the p-type wafer and the p / n-type inversion region. The illustrated CMOS has a twin-well structure in which p and n-well complement each other. A p-well, an n-well, and a depletion layer 1 are formed in the substrate depth direction from the surface of the p-type wafer 3, and are inverted to the n-type wafer 4 by the generation of the p / n-type inversion region 2.
In FIG. 2A, since the p / n type inversion region 2 is in contact with the depletion layer region, n-well separation is not sufficient, and predetermined characteristics cannot be obtained. On the other hand, as shown in FIG. 5B, it can be seen that by generating the p / n type inversion region 2 at a sufficiently deep position, the CMOS characteristics and n-well isolation are hardly affected.

  Whether inversion to n-type occurs or not is greatly influenced by the amount of thermal donors generated and the amount of dopant in the wafer. The amount of thermal donor generated can be estimated from the amount of oxygen, the heat treatment conditions of the wafer, and the thermal history during device formation. The amount of dopant is almost determined by the resistivity of the wafer, and the lower the resistivity, the smaller the wafer.

  Therefore, whether or not reversal to n-type occurs can be predicted if the above-mentioned conditions are known. If the thermal history at the time of device formation can be known, n-type can be obtained by selecting the heat treatment conditions of the wafer. It seems possible to suppress the occurrence of reversal. However, even if inversion to the n-type occurs, the device formation region remains p-type, and if the portion inverted to the n-type has a sufficiently deep position, the device performance is not affected. Rather than controlling the occurrence of inversion, the generation position of the p / n-type inversion region, that is, the depth from the surface may be controlled.

  The wafer is subjected to high temperature heat treatment for the purpose of reducing defects in the active region on the surface. When the wafer is heated at a high temperature, in many cases, outward diffusion of oxygen occurs and the oxygen concentration in the surface layer decreases. Therefore, even when the inside of the wafer is inverted to n-type when it is subjected to a process for generating thermal donors in the device manufacturing process, the oxygen concentration is low near the surface, so that the thermal donor is small and the p-type can be maintained.

  In this way, it is presumed that the decrease in the oxygen concentration on the wafer surface determines the position of the p / n-type inversion region. Even if / n-type inversion occurs, the inversion region can be moved to a depth position that does not affect the operation of the surface device.

  Therefore, using a high-resistance wafer, the most probable condition for generating thermal donors, such as the sintering process during device manufacturing, is to perform a heat treatment at 450 ° C for 1 hour, then spread the resistance distribution in the depth direction and measure the resistance. In order to determine the depth position of the p / n type inversion region necessary for not affecting the device characteristics, the wafer is subjected to various heat treatments such as oxygen outward diffusion treatment, and the conditions The effect of was investigated.

  Here, the boundary depth position of the p / n type inversion region is defined as a depth position where the resistance value distribution in the depth direction exhibits a peak as an actual measurement value. This is because the p / n type inversion region does not affect the p type part where the electron supply from the thermal donor is the device region, that is, the wafer surface side boundary of the p / n type inversion region is the acceptor of the p type region. According to the recognition that the conductivity brought about by holes due to annihilation disappears due to the supply of electrons by the donor and the portion where the resistivity increases to infinity is theoretically an n-type semiconductor state. .

The boundary position of such a p / n-type inversion region may be at a depth that does not contact the region where the surface device is formed as described above, and further, the depletion layer formed in contact with the n-well. When this position is examined, it is preferably 10 μm or more from the surface, and is actually preferably 20 μm to 50 μm. However, in a wafer doped with carbon at a high concentration, polycrystallization (DF cut) occurs, so the carbon concentration cannot be made 5 × 10 ¹⁷ atoms / cm ³ or more. With such a carbon concentration, the boundary depth position of the p / n type inversion region cannot be deeper than about 10 μm, and even if the initial oxygen concentration Oi, heat treatment conditions, etc. are adjusted, it is formed exceeding 20 μm. I can't do it.

However, the present inventors have found that these problems can be solved by doping a wafer with nitrogen, which has conventionally been considered to cause n-type inversion because a donor called New Donor is generated.
In other words, the boundary depth of the p / n type inversion region can be set to a depth that could not be realized by carbon doping, and the p / n type inversion boundary can be formed only by controlling the concentration of nitrogen to be doped. It is possible to control the depth position (boundary depth). As a result, the p / n type inversion region can not be formed on the surface side of the boundary depth.
In addition, by performing the treatment under specific heat treatment conditions, the resistance value that could not be improved in the carbon-doped CZ wafer is prevented from decreasing at the depth position, that is, the resistance value is constant in the wafer depth direction. Thus, it is possible to provide a high resistance wafer that does not have a portion where the resistance value decreases in the depth direction relative to the surface resistance value.
The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. A silicon wafer manufacturing method capable of adjusting a depth range from a surface where a p / n type inversion region is generated with a high resistance value,
The p-type dopant concentration and nitrogen concentration at which the wafer surface resistance value becomes 591.6 to 1905 Ωcm; 3.98 × 10 ^{13 to} 8.92 × 10 ¹³ atoms / cm ³ (ASTM F123-1981 ), and the oxygen concentration Oi is 8. a pulling step of pulling a single crystal by the CZ method as ^{0 × 10 17 ~16.0 × 10 17} atoms / cm 3 (ASTM F123-1979), a processing step of processing the wafer was sliced from this single crystal, a non-oxidizing An oxygen outward diffusion heat treatment step with a sexual atmosphere,
The oxygen outward diffusion heat treatment is a heat treatment condition in which the treatment temperature is 1100 to 1250 ° C. and the treatment time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof,
By performing the oxygen outward diffusion heat treatment, when the heat treatment in the device manufacturing process is performed, the p / n type inversion region resulting from the generation of thermal donors is formed into the device active region and the depletion layer region formed in contact therewith. To a depth that does not touch the
Peak position of the resistance value at the boundary between the wafer front surface side of the p-type region and the thickness direction inside the p / n-type region is set to the range of the boundary depth 20~45μm from Thus the wafer surface to the nitrogen concentration And adjust
When nitrogen is doped, in the device region, after the oxygen outward diffusion heat treatment, the oxygen precipitate density generated when heat treatment is further performed at 780 ° C. 3 hr + 1000 ° C. 16 hr, the wafer surface resistance is 591.6-1905 Ωcm. The p-type dopant concentration and the oxygen concentration Oi are 8.0 × 10 ^{17 to} 16.0 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), which is the maximum limit concentration that does not cause polycrystallization (DF cut) Oxygen precipitation that occurs when a wafer obtained by CZ method by doping carbon of 32 × 10 ¹⁶ atoms / cm ³ (ASTM F123-1981) is further subjected to heat treatment at 780 ° C. 3 hr + 1000 ° C. 16 hr after the oxygen outward diffusion heat treatment. Compared to the object density, the density is increased by 2 to 4 × 10 ¹⁰ pieces / cm ³ .
The present invention has an oxygen precipitation nucleation heat treatment step after the oxygen outward diffusion heat treatment step,
The oxygen precipitation nucleation heat treatment may be a heat treatment condition of a treatment temperature of 400 to 800 ° C. and a treatment time of 0.5 to 1.5 hours or a heat treatment condition of 650 ° C. for 30 minutes + 400 ° C. for 1 hour.
The present invention can include an epitaxial process in which a p-type layer having a resistivity of 100 Ωcm or more is epitaxially grown on the surface to form a p / p + type wafer.
The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. With respect to a reference value in which a resistance distribution is set in a range of 591.6 to 1905 Ωcm with a high resistance value, no p / n type inversion region is generated, and the entire wafer thickness is 0 to 1905 Ωcm. A method for producing a silicon wafer having a p-type region set within 30%,
P-type dopant concentration and nitrogen concentration at which the wafer surface resistance value becomes 591.6 to 1905 Ωcm; 3.98 × 10 ^{13 to} 8.92 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) or carbon concentration; 5 × 10 ^A pulling step of pulling up the single crystal by the CZ method as ^{15 to} 5 × 10 ¹⁷ atoms / cm ³ and an oxygen concentration Oi of 8.0 × 10 ^{17 to} 16.0 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979); A processing step of slicing the single crystal into a wafer, an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere, an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step,
The oxygen outward diffusion heat treatment is a heat treatment condition in which the treatment temperature is 1100 to 1250 ° C. and the treatment time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof,
The oxygen precipitation nucleation heat treatment is a heat treatment condition of a treatment temperature of 400 to 800 ° C. and a treatment time of 0.5 to 1.5 hours or a heat treatment condition of 650 ° C. for 30 minutes + 400 ° C. for 1 hour. treatment temperature from 780 to 1,000 ° C., Ru can be a heat treatment condition of the heat treatment conditions are treatment time 3-19 hours or 780 ℃ 3hr + 1000 ℃ 16hr.
The present invention can include an epitaxial process in which a p-type layer having a resistivity of 100 Ωcm or more is epitaxially grown on the surface to form a p / p + type wafer.

The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. A silicon wafer manufacturing method capable of adjusting a depth range from a surface where a p / n type inversion region is generated with a high resistance value,
P-type dopant concentration and nitrogen concentration at which the wafer surface resistance value is 100 to 10 kΩcm; 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) or carbon concentration; 5 × 10 ^{15 to} 5 × 10 ¹⁷ atoms / cm ³ , oxygen concentration Oi is 5.0 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), a pulling process for pulling up the single crystal by the CZ method, and slicing from this single crystal A processing step for processing into a wafer and an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere,
The peak position of the resistance value that becomes the boundary between the p-type region on the wafer surface side and the p / n-type region on the inner side in the thickness direction is set to a boundary depth of 10 to 70 μm from the wafer surface depending on the nitrogen concentration or carbon concentration. The above-mentioned problems were solved by adjusting so as to be adjusted.
The present invention can include an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step after the oxygen outward diffusion heat treatment step.
The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. The resistance distribution is 0 to 30% with respect to a reference value set in a range of 100 to 10 kΩcm with a high resistance value and no p / n-type inversion region. A method of manufacturing a silicon wafer having a p-type region set within
P-type dopant concentration and nitrogen concentration at which the wafer surface resistance value is 0.1 to 10 kΩcm; 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) or carbon concentration; 5 × 10 ¹⁵ to A pulling step of pulling up the single crystal by CZ method at 5 × 10 ¹⁷ atoms / cm ³ and an oxygen concentration Oi of 5 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), and slicing from this single crystal The above-mentioned problems have been solved by having a processing step for processing into a wafer, an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere, an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step.
Further, the oxygen outward diffusion heat treatment may be a heat treatment condition in which the treatment temperature is 1100 to 1250 ° C. and the treatment time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof. .
In addition, by performing an oxygen outward diffusion heat treatment, when a heat treatment is performed in the device manufacturing process, a p / n type inversion region caused by thermal donor generation is formed in the device active region and a depletion layer formed in contact therewith. It can be generated at a depth that does not contact the region.
The oxygen precipitation nucleation heat treatment is performed under the heat treatment conditions of a processing temperature of 600 to 800 ° C. and a processing time of 1 to 20 hours, and the oxygen precipitate formation heat treatment is performed at a processing temperature of 1000 to 1100 ° C. and a processing time of 1. May be heat treatment conditions of ~ 20 hours.
In the present invention, after the oxygen outward diffusion heat treatment, it is desirable to further perform oxygen precipitation nucleus formation heat treatment and / or oxygen precipitate formation heat treatment.
The high-resistance silicon wafer of the present invention is used in a device process for forming a voltage controller in the surface of a wireless transmission / reception circuit having an output frequency of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz, and has a resistivity of 100 Ωcm Thus, a p-type silicon wafer having a defect-free layer formed on the surface of the silicon wafer,
A depth at which the p / n type inversion region resulting from thermal donor generation does not contact the active region of the device and the depletion region formed in contact with it when nitrogen or carbon is doped and heat treatment is performed in the device manufacturing process. The above problems have been solved.
In the present invention, it is more preferable that the p / n type inversion region is at a depth within a range of 10 μm to 70 μm from the wafer surface.
In the present invention, the p / n type inversion region may contain an oxygen precipitate.
In the present invention, the nitrogen concentration in the wafer is set to 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981), or the carbon concentration; 5 × 10 ^{15 to} 5 A means of × 10 ¹⁷ atoms / cm ³ can also be adopted.
In the present invention, a p-type wafer is doped with nitrogen or carbon, and is subjected to a heat treatment in a argon gas, hydrogen gas, or mixed gas atmosphere at a treatment temperature of 1100 to 1250 ° C. and a treatment time of 1 to 5 hours. A p-type surface region having a resistance distribution from the surface to the added direction of about 0.1 to 10 kΩcm, a peak region having a resistance value increasing and decreasing in the depth direction, and a p / n type by an oxygen donor. It is preferable that a peak position in the peak region is within a range of 10 to 70 μm from the wafer surface.
In the present invention, a p-type wafer is subjected to a heat treatment in which nitrogen or carbon is doped, and the processing temperature is 1100 to 1250 ° C. and the processing time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof. In addition, the resistance distribution from the surface to the direction of addition is set in the range of 0.1 to 10 kΩcm over the entire thickness by heat treatment at a processing temperature of 1000 to 1100 ° C. and a processing time of 1 to 20 hours. The variation with respect to the reference value can be set within 0 to 30%.
In the present invention, when nitrogen is doped, the density of oxygen precipitates generated when heat treatment is performed at 780 ° C. for 3 hours + 1000 ° C. for 16 hours is set to a maximum limit concentration that does not cause polycrystallization (DF breakage). Compared to the density of oxygen precipitates generated when a carbon-doped wafer of ¹⁶ atoms / cm ³ (ASTM F123-1981) is heat-treated under the same conditions, it can be increased by 2-4 × 10 ¹⁰ pieces / cm ³ .

The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. A silicon wafer manufacturing method capable of adjusting a depth range from a surface where a p / n type inversion region is generated with a high resistance value,
P-type dopant concentration and nitrogen concentration at which the wafer surface resistance value is 100 to 10 kΩcm; 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) or carbon concentration; 5 × 10 ^{15 to} 5 × 10 ¹⁷ atoms / cm ³ , oxygen concentration Oi is 5.0 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), a pulling process for pulling up the single crystal by the CZ method, and slicing from this single crystal A processing step for processing into a wafer and an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere,
The peak position of the resistance value that becomes the boundary between the p-type region on the wafer surface side and the p / n-type region on the inner side in the thickness direction is set to a boundary depth of 10 to 70 μm from the wafer surface depending on the nitrogen concentration or carbon concentration. By adjusting so that the depth position of the boundary of the p / n type inversion region expressed by the peak position in the above range is controlled, the depth position cannot be realized by the carbon-doped wafer, and this state is simultaneously set. It is formed on the entire surface in a substantially uniform state within the wafer surface, has a high gettering ability with the same heat treatment time, can realize higher wafer deformation prevention and slip / crack prevention, and the same surface resistance Even if this value is set, it is possible to handle higher frequency devices and provide a wafer that can reduce current loss as a device characteristic. Can.

  The present invention includes an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step after the oxygen outward diffusion heat treatment step, so that the p / n type inversion is deeper than the carbon-doped wafer. Region boundaries can be formed.

The method of manufacturing a high-resistance silicon wafer of the present invention can reduce current loss generated in a device region where a voltage controller is formed in a radio transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz. The resistance distribution is 0 to 30% with respect to a reference value set in a range of 100 to 10 kΩcm with a high resistance value and no p / n-type inversion region. A method of manufacturing a silicon wafer having a p-type region set within
P-type dopant concentration and nitrogen concentration at which the wafer surface resistance value is 0.1 to 10 kΩcm; 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) or carbon concentration; 5 × 10 ¹⁵ to A pulling step of pulling up the single crystal by CZ method at 5 × 10 ¹⁷ atoms / cm ³ and an oxygen concentration Oi of 5 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), and slicing from this single crystal A p / n-type inversion region by having a processing step for processing into a wafer, an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere, an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step It is possible to realize a high-resistance wafer that does not generate any defects.

  Further, the oxygen outward diffusion heat treatment may be a heat treatment condition in which the treatment temperature is 1100 to 1250 ° C. and the treatment time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof. .

  In addition, by performing an oxygen outward diffusion heat treatment, when a heat treatment is performed in the device manufacturing process, a p / n type inversion region caused by thermal donor generation is formed in the device active region and a depletion layer formed in contact therewith. It can be generated at a depth that does not contact the region.

  The oxygen precipitation nucleation heat treatment is performed under the heat treatment conditions of a processing temperature of 600 to 800 ° C. and a processing time of 1 to 20 hours, and the oxygen precipitate formation heat treatment is performed at a processing temperature of 1000 to 1100 ° C. and a processing time of 1. May be heat treatment conditions of ~ 20 hours.

  In the present invention, after the oxygen outward diffusion heat treatment is performed, the oxygen concentration is reduced by fixing the employed oxygen by further performing the oxygen precipitation nucleation heat treatment and / or the oxygen precipitate formation heat treatment. Thus, the influence of the donor can be reduced.

The high-resistance silicon wafer of the present invention is used in a device process for forming a voltage controller in the surface of a wireless transmission / reception circuit having an output frequency of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz, and has a resistivity of 100 Ωcm Thus, a p-type silicon wafer having a defect-free layer formed on the surface of the silicon wafer,
A depth at which the p / n type inversion region resulting from thermal donor generation does not contact the active region of the device and the depletion region formed in contact with it when nitrogen or carbon is doped and heat treatment is performed in the device manufacturing process. Accordingly, it becomes possible to provide a wafer that can manufacture a device such as a CMOS that eliminates the influence of a thermal donor and exhibits excellent characteristics.

  In the present invention, the influence of the thermal donor can be further reduced by having the p / n type inversion region at a depth in the range of 10 μm to 70 μm which is the boundary depth from the wafer surface. The boundary depth is preferably 15 to 60 μm, 20 to 50 μm, 30 to 45 μm, 35 to 55 μm, 25 to 40 μm, 40 to 65 μm, and 45 to 70 μm.

  In the present invention, since the p / n type inversion region contains oxygen precipitates, it has gettering ability and can prevent deformation and cracking.

In the present invention, the nitrogen concentration in the wafer is set to 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981), or the carbon concentration; 5 × 10 ^{15 to} 5 X10 ¹⁷ atoms / cm ^3, and within this range, by adjusting the nitrogen concentration, the p / n type inversion region boundary is set at a deep depth position in the case of high concentration, and in the case of low concentration Can set the p / n type inversion region boundary to a shallow depth position.

  In the present invention, a p-type wafer is doped with nitrogen or carbon, and is subjected to a heat treatment in a argon gas, hydrogen gas, or mixed gas atmosphere at a treatment temperature of 1100 to 1250 ° C. and a treatment time of 1 to 5 hours. A p-type surface region having a resistance distribution from the surface to the added direction of about 0.1 to 10 kΩcm, a peak region having a resistance value increasing and decreasing in the depth direction, and a p / n type by an oxygen donor. It is preferable that a peak position in the peak region is within a range of 10 to 70 μm from the wafer surface.

  In the present invention, a p-type wafer is subjected to a heat treatment in which nitrogen or carbon is doped, and the processing temperature is 1100 to 1250 ° C. and the processing time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof. In addition, the resistance distribution from the surface to the direction of addition is set in the range of 0.1 to 10 kΩcm over the entire thickness by heat treatment at a processing temperature of 1000 to 1100 ° C. and a processing time of 1 to 20 hours. The variation with respect to the reference value can be set within 0 to 30%.

In the present invention, when nitrogen is doped, the density of oxygen precipitates generated when heat treatment is performed at 780 ° C. for 3 hours + 1000 ° C. for 16 hours is set to a maximum limit concentration that does not cause crystallization (DF cut), 32 × 10 ¹⁶ atoms. The density of oxygen precipitates generated when a wafer doped with carbon of / cm ³ (ASTM F123-1981) is heat-treated under the same conditions can be increased by 2 to 4 × 10 ¹⁰ pieces / cm ³ .

  As the above heat treatment conditions, oxygen out-diffusion treatment is performed at a high temperature for 1 hour or more in a controlled atmosphere using argon, hydrogen, or a mixed gas thereof, or a mixed gas containing a small amount of oxygen in nitrogen. However, it has been found that the position of the p / n type inversion region can be deeper in a limited time. Although oxygen outdiffusion is possible even in an atmosphere containing oxygen or oxygen by heating at a high temperature, the oxygen partial pressure in the vicinity of the surface can be lowered and the oxygen desorption rate is larger in a non-oxidizing or weakly oxidizing atmosphere. It seems to be. This high-temperature heat treatment in a non-oxidizing atmosphere has the effect of eliminating defects near the surface such as COP (Crystal Originated Particle) defects as in the so-called DZ treatment.

  Further, the region used as the device formation region is limited to a depth region of about several μm from the wafer surface. For this reason, in recent years, lower layer regions of other wafers that are not used as device forming regions may be removed by polishing or the like. For this reason, even if the oxygen concentration is not lowered over the entire area of the wafer, the oxygen outer diffusion heat treatment is performed to sufficiently reduce the oxygen concentration in the surface layer of the wafer used as the device formation region. A device formation region having resistivity can be secured.

  After reducing the oxygen in the surface portion by outward diffusion, it is desirable to perform a heat treatment that heats at a low temperature and further heats at a high temperature, that is, an oxygen precipitation heat treatment. Oxygen precipitation is promoted by the oxygen precipitation heat treatment, the residual oxygen inside the wafer is reduced, and the resistance can be increased. Further, the p / n type inversion region can be generated at a deeper position.

  In the oxygen precipitation heat treatment, the oxygen precipitation nucleation heat treatment by low temperature heating to re-form or grow the nucleus for oxygen precipitation that disappeared or contracted by the high temperature heating for oxygen outward diffusion, and this nucleus was further grown. By heat treatment for growing oxygen precipitates by high-temperature heating to obtain oxygen precipitates.

  For example, as shown in FIG. 15, depending on the type of device, such as an oscillator for voltage control in a transmission / reception circuit in a wireless device such as a mobile phone, if the resistivity inside the wafer is too low, a position deeper than the device use area is formed. Since the amount of current passing through increases, energy loss and current noise are generated, device characteristics are significantly deteriorated. For this reason, high resistance is required at a position deeper than the device use region.

  In this case, it is difficult to reduce the oxygen inside the wafer, that is, the entire area of the wafer only by performing oxygen outward diffusion heat treatment on the wafer, and the residual oxygen concentration inside the wafer must be increased. In order to cope with this, it is desirable to perform oxygen precipitation heat treatment after oxygen on the wafer surface is diffused outward.

  In other words, problems such as energy loss and generation of current nozzles due to the low resistivity inside the wafer are only required to achieve high resistance at a position deeper than the device use region, and the polarity is n-type. Therefore, it is effective to increase the resistance inside the wafer inverted to n-type by performing oxygen precipitation heat treatment.

  As described above, in a wafer to be used for manufacturing a high-frequency device targeted by the present invention, conditions for obtaining a more desirable state for the surface DZ, the generation position of the p / n type inversion region, and the internal BMD formation, That is, a low oxygen concentration state is realized, a higher BMD density is realized, a p / n type inversion region formation position is deepened, or a p / n type inversion region is not formed, and the resistance value is deep. The condition that does not decrease in the direction is obtained.

The present invention is suitable for manufacturing devices such as oscillators in voltage control in transmission / reception circuits in radio equipment such as high-frequency diodes and mobile phones, and has a high density of defects caused by oxygen precipitation necessary for gettering. Provided is a high-resistance silicon wafer that is secured, can effectively suppress the generation of oxygen donors in a device heat treatment process, has sufficient mechanical strength, and can reduce power loss as device characteristics.
In addition, the present invention provides a method for producing a silicon wafer having a high resistivity that can produce the above-described silicon wafer at high quality and at low cost because the heat treatment time is short, and the heavy metal contamination of the silicon wafer in the heat treatment furnace hardly occurs.
Furthermore, it is suitable for use in an oscillator for voltage control in a transmitter / receiver circuit in a radio device such as a high-frequency diode or a mobile phone such as a low-cost, high-resistivity layer having a sufficiently high resistivity and low noise using the silicon wafer described above. New silicon wafers are provided.
In addition, after growing the high-resistance CZ crystal, the heat treatment process applied to the processed wafer is shortened, so that the economy is excellent, and the generation of oxygen donors in the device heat treatment process can be effectively suppressed. There is no need to form recombination centers because the defects caused by oxygen precipitation (oxygen precipitation nuclei or oxygen precipitates) are formed as recombination centers. In addition, gettering capability and wafer mechanical strength are high, and lifetime control is performed. Provided are a high-resistivity silicon wafer capable of manufacturing a high-frequency device capable of high yield and low cost, and a manufacturing method thereof.

  Furthermore, according to the high-resistance silicon wafer of the present invention, a high-resistance silicon wafer capable of reducing power loss as an optimum device characteristic for manufacturing devices such as an oscillator in voltage control in a transmission / reception circuit in a radio device such as a mobile phone Can be provided. In addition, when a device such as a CMOS is formed on the surface, there are few problems such as characteristic defects and inability to separate n-wells. One cause of the frequent occurrence of such problems in high-resistance silicon wafers is that they are easily affected by thermal donors. In order to suppress the generation of thermal donors, there is a method to keep the concentration of dissolved oxygen in the wafer as low as possible. However, since the decrease in dissolved oxygen reduces the strength of the wafer, troubles due to deformation occur in the device manufacturing process. There is a risk of causing. In addition, if it is attempted to keep the concentration of dissolved oxygen in the wafer low by heat treatment, a large number of man-hours are required. Therefore, in the high-resistance silicon wafer of the present invention, the solid solution oxygen inside the wafer is not reduced. Therefore, such a problem does not occur, and even when various heat treatments are performed in the device manufacturing process by efficient processing. Thus, it is possible to manufacture a device such as a CMOS that eliminates the influence of the thermal donor and exhibits excellent characteristics. Furthermore, in the present invention, it is possible to control the depth of the generation position of the p / n type inversion region and form it at a deeper position. .

It is a figure which shows the relationship between the thermal donor generation amount and resistivity in a silicon wafer. It is a figure explaining the relationship between the structure of CMOS formed on the p-type wafer, and the p / n type inversion area | region. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows resistance value distribution to the wafer depth direction after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows the residual oxygen concentration in the wafer surface after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a graph which shows the BMD (oxygen precipitate) density in the wafer surface after annealing in embodiment of the manufacturing method of the silicon wafer of this invention. It is a figure which shows the heat processing conditions which simulated the process in which CMOS was used for investigating the influence of thermal donor generation | occurrence | production on a wafer. It is a figure for demonstrating the heat processing rate in this invention. It is a figure which shows typically the relationship between the residual oxygen amount in a wafer and the thermal donor density produced | generated using the heat processing conditions in a device manufacturing process as a parameter. It is a schematic sectional drawing for demonstrating an example of the high frequency diode manufactured from the silicon wafer of this invention. It is a schematic sectional drawing for demonstrating an example of the voltage control oscillator manufactured from the silicon wafer of this invention. It is explanatory drawing which shows the relationship between resistance value (rho) of a wafer, and efficiency (eta). It is a figure for demonstrating the energy diagram of a PIN diode.

  Hereinafter, a first embodiment of a silicon wafer according to the present invention will be described with reference to the drawings.

The silicon wafer of the present invention is a silicon wafer that adjusts the depth range from the surface where the p / n-type inversion region is generated, and the p-type dopant concentration and nitrogen concentration at which the wafer surface resistance value is 0.1 to 10 kΩcm; CZ method with 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) and oxygen concentration Oi of 5.0 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979) As shown in FIG. 3, the single crystal is sliced from the single crystal pulled up by the above and subjected to an oxygen outward diffusion heat treatment step in a non-oxidizing atmosphere, and as shown in FIG. The peak position of the resistance value that becomes the boundary with the / n-type region is set to a boundary depth of 10 to 70 μm from the wafer surface by the nitrogen concentration, and a defect-free layer is formed in the vicinity of the surface. P / n-type inversion region resulting from thermal donor generation when the various heat treatments are performed in the device manufacturing process, the device active region and the depletion layer formed in contact therewith A region is one that is at a remote depth.

  In the silicon wafer of the present invention, a p / n type inversion region due to a thermal donor does not occur in a range within a boundary depth set to a depth of 10 to 70 μm from the surface. The p / n type inversion region can be generated at a depth away from the device active region and the depletion layer region formed in contact therewith.

  When the resistivity is 0.1 to 10 kΩcm, the frequency handled by the device becomes high, especially when it exceeds 2.5 GHz or the target is about 60 GHz or more, the conventional low resistance substrate of 10 Ωcm or less is used. This is because noise generation and signal attenuation become prominent, but these effects can be reduced by increasing the resistance. Further, in a low resistivity p-type wafer having a resistivity of less than 100 Ωcm, n-type inversion does not easily occur because of sufficient dopant.

  In addition, by using a silicon wafer having a resistivity of 600 to 1000 Ωcm, a high-quality high-frequency diode having a very high resistivity and a very low noise can be produced.

  When n-type inversion by a thermal donor occurs in the heat treatment in the device manufacturing process using a wafer, the p / n-type inversion region has a depth apart from the device active region and the depletion layer region formed in contact therewith. The reason is that when the p / n type inversion region is in contact with these regions, the device formed on the surface portion is affected, resulting in poor characteristics or insufficient n-well separation. Because it becomes.

  This p / n type inversion region needs to be generated at a depth apart from the device active region and the depletion layer region formed in contact therewith. For example, if the p / n type inversion region occurs at a position shallower than the set values 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, and 65 μm as the boundary depth is 10 to 70 μm. This is because the device formed on the surface portion is affected. The p / n-type inversion region is deeper than the above boundary depth from the surface. In other words, even if the n-type inversion occurs in the heat treatment in the device manufacturing process, the n-type inversion portion has a depth. It means that the inside exceeds the boundary depth.

  The heat treatment in the manufacturing process of this device can be represented by, for example, heating at 450 ° C. for 1 hour or 650 ° C. for 30 minutes under the condition that the thermal donor is most likely to be generated. Further, as shown in FIG. 3, the position of the p / n type inversion region is detected at a depth at which the resistivity is maximized by measuring the resistivity distribution in the depth direction of the wafer by the spreading resistance measurement method. be able to.

  The oxygen concentration of the wafer is not particularly limited as long as it is within a range included in a silicon single crystal produced by a normal CZ method. However, it is desirable that the oxygen in the wafer exists as oxygen precipitates that form BMD having a gettering action, and heat treatment for forming such oxygen precipitates is preferably performed.

In addition, nitrogen promotes the formation of electrically neutral and gettering oxygen precipitates, and maintains strength when interstitial oxygen (solid solution oxygen) decreases due to heat treatment and wafer strength decreases. Therefore, the nitrogen concentration is in the range of 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981). In this case, if the amount is less than the lower limit of the range, the effect does not sufficiently appear, and if the content is too large, polycrystallization tends to occur at the time of CZ method single crystal growth, or variation in resistivity and defect density becomes too large. The following is recommended.

Furthermore, in addition to nitrogen, carbon accelerates the formation of electrically neutral and gettering oxygen precipitates, or when heat treatment reduces interstitial oxygen (solid solution oxygen) and reduces wafer strength. Since it has an effect of maintaining the strength, it may be contained in an amount of 0.5 × 10 ^{16 to} 32 × 10 ¹⁶ atoms / cm ³ (ASTMF123-1981). In this case, if the amount is less than the lower limit of the range, the effect is not sufficiently exhibited, and if the content is too large, polycrystallization tends to occur at the time of growing a single crystal by the CZ method.

In order to manufacture the silicon wafer of the present invention, first, as a pulling process, the resistivity is 0.1 to 10 kΩcm or more and the initial interstitial oxygen concentration is 5.0 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / by CZ method. A p-type silicon single crystal having a cm ³ (ASTM F123-1979) and a nitrogen concentration of 1.0 × 10 ¹³ to 10 × 10 ¹³ atoms / cm ³ (ASTM F123-1981) is grown (single crystal growing step). At this time, the desired silicon single crystal described above is grown by appropriately adjusting the number of revolutions of the crucible, the type and flow rate of the introduced gas, the applied magnetic field conditions, the temperature distribution of the silicon melt and the convection. be able to.

  Next, as a processing step, the obtained silicon single crystal is sliced with a cutting device such as a wire saw or a slicer, and steps such as chamfering, lapping, etching, and polishing are performed as necessary to obtain a silicon wafer.

  Thereafter, the obtained silicon wafer is heated at a rate of temperature increase from 700 ° C. to 1 to 2 ° C./min in an atmosphere of argon, nitrogen, or a mixed gas thereof using a heat treatment furnace employing a lamp heating method. The silicon wafer of the present invention is obtained by performing the first heat treatment step of heating to 1000C and holding at 1000C for 0 to 6 hours and cooling.

  In the first heat treatment step described above, when this silicon wafer is subjected to the heat treatment in the device manufacturing process, a region within the boundary depth within a range of 10 to 70 μm from the surface is p / n type due to generation of thermal donors. The wafer is subjected to an oxygen outward diffusion heat treatment at 1100 to 1200 ° C. for 1 to 5 hours in a controlled atmosphere so that no inversion region occurs.

  As shown in FIG. 3, this heat treatment sufficiently diffuses oxygen outward to lower the oxygen concentration of the surface layer, generates thermal donors in the subsequent device manufacturing process, and the inside is an n-type semiconductor. This is because the p / n type inversion region is located at a sufficiently deep position from the surface.

  The treatment atmosphere is an adjusted atmosphere using argon, hydrogen, or a mixed gas thereof, or a mixed gas containing a small amount of oxygen in nitrogen. By using these gases, oxygen out-diffusion during high-temperature heating can be promoted, and the p / n type inversion region can be positioned sufficiently deep from the surface. First, in the case of using hydrogen, argon, or a mixed gas thereof, in addition to the desired oxygen outward diffusion effect, there is an effect of eliminating COP on the wafer surface layer, and a wafer with excellent surface quality can be obtained. .

  Nitrogen is cheaper and more cost-effective than argon and hydrogen, but if it is treated in a nitrogen atmosphere, oxygen can diffuse outward, but a nitride film is formed on the wafer surface, and the process of removing the nitride film Newly needed. For this reason, it is desirable to use a nitrogen atmosphere containing about 3% oxygen as the adjustment atmosphere. However, it should be noted that there is no effect of eliminating the COP on the wafer surface layer in an atmosphere using nitrogen.

  The heating temperature and time of the heat treatment are 1100 to 1250 ° C. and 1 to 5 hours. This is because oxygen out-diffusion itself hardly occurs at temperatures below 1100 ° C., and the effect is small. At temperatures above 1250 ° C., slip dislocation is likely to occur in the wafer, and at the same time, the burden on the heat treatment furnace is large. This is because the life of the parts is reduced. In addition, when the heat treatment is performed for less than 1 hour, the depth of the p / n type inversion region cannot be increased from the surface to the boundary depth or more. Even when heating for more than 5 hours is performed, This is because the effect of oxygen out-diffusion is saturated.

  In the wafer of the present invention, the depth of the p / n type inversion region is set to a depth away from the device active region and the depletion layer region formed in contact with the device active region, for example, a depth greater than the boundary depth from the surface, In order to sufficiently form BMD by oxygen precipitates having a gettering action inside the wafer and to reduce the residual oxygen inside the wafer and to increase the resistance, it is preferable to further perform oxygen precipitation heat treatment.

  As this oxygen precipitation treatment, after the heat treatment for oxygen out-diffusion described above, the silicon wafer after the first heat treatment step is 1200 using a heat treatment furnace or the like employing a lamp heating method similar to the first heat treatment step. The silicon wafer of the present invention is obtained by raising the temperature to 0 ° C., performing a second heat treatment step of holding at 1200 ° C. for 1 to 2 hours in an atmosphere of argon, hydrogen, or a mixed gas thereof, and cooling. In addition, as the second heat treatment, in order to form nuclei for oxygen precipitation, oxygen precipitation nucleation heat treatment is performed at 600 to 800 ° C. for 1 to 20 hours, and then at 1000 to 1100 ° C. for 1 to 20 hours. An oxygen precipitate growth heat treatment for the purpose of BMD formation can be performed.

  Since these heat treatments depend on the heating temperature and the heating time and do not depend on the atmospheric conditions to be used, argon, hydrogen, a mixed gas thereof, nitrogen, or the like can be used. As described above, since it is advantageous in terms of cost, it is desirable to make the atmosphere contain about 3% oxygen in nitrogen gas.

  The reason why the heating temperature is set to 600 to 800 ° C. in the heat treatment for forming oxygen precipitation nuclei is that the formation of oxygen precipitation nuclei hardly occurs when the temperature is out of this range, and the effect is limited. In addition, the heating time of 1 to 20 hours is not sufficient if the heating time is less than 1 hour, and heating exceeding 20 hours does not show a significant improvement even if the time is further increased, and is wasted. Because.

  In this heat treatment, the temperature of the silicon wafer is increased from 700 ° C. to 1000 ° C. at a temperature increase rate of 1 to 2 ° C./min in an atmosphere of argon, nitrogen, or a mixed gas thereof (non-oxidizing atmosphere). It can be set as the heat processing process hold | maintained at 0 degreeC for 0 to 6 hours, and, thereby, oxygen donors, such as a new donor, can be suppressed more effectively by short heat processing time.

  After heat treatment for nucleation, oxygen precipitate growth heat treatment is performed at 1000 to 1100 ° C. for 1 to 20 hours. In the heat treatment for growing oxygen precipitates, the heating temperature is set to 1000 to 1100 ° C. The growth of oxygen precipitates is not promoted at temperatures lower than 1000 ° C., and the growth of oxygen precipitates does not progress at temperatures exceeding 1100 ° C. This is because the formed precipitate may be reduced by re-dissolution. The reason for setting the heating time to 1 to 20 hours is that the growth of oxygen precipitates is not sufficient if the heating time is less than 1 hour, and the effect of saturation for heating exceeding 20 hours is saturated even if the time is further increased.

  As described above, in the manufacturing method of the present invention, even if the p / n type inversion region caused by the thermal donor occurs, the CMOS eliminates the operation failure and the n-well separation failure. The depth is not in contact with the active region and the depletion layer region.

  For this reason, after performing the oxygen outward diffusion heat treatment, an oxygen precipitate nucleation heat treatment and an oxygen precipitate growth heat treatment are performed as necessary. These treatment conditions include 1 to 1250 hours at 1100 to 1250 ° C. for oxygen outward diffusion heat treatment, 1 to 20 hours at 600 to 800 ° C. for oxygen precipitation nucleation heat treatment, and 1000 to 1100 ° C. for oxygen precipitate growth heat treatment. Illustrated as 1 to 20 hours.

  However, specific processing conditions are determined based on the wafer resistance value, the depth of the high resistance layer, the oxygen concentration, and the like required by the device manufacturing conditions. Therefore, in order to generate the p / n type inversion region at a depth position not in contact with the device active region or the depletion layer region, the initial oxygen concentration is determined by the following procedure, and specific heat treatment conditions are determined based on that. It is determined.

  FIG. 13 is a diagram schematically showing the relationship between the amount of residual oxygen in the wafer and the density of the generated thermal donor, using the heat treatment conditions in the device manufacturing process as parameters. First, as a master table, as shown in FIG. 11 or FIG. 12, the relationship between the amount of residual oxygen in the wafer and the amount of thermal donor generated for each heat treatment in the device manufacturing process is prepared. At this time, as heat treatment conditions in the device manufacturing process, for example, a heating temperature of 400 to 500 ° C. and a heating time of 1 to 12 hours may be used.

  Next, based on the heat treatment conditions (heat treatment sequence) in the device manufacturing process, the thermal donor density generated from each residual oxygen concentration is calculated from the master table. On the other hand, an allowable thermal donor generation amount is calculated from the wafer resistance value determined from the device manufacturing specifications and the depth of the high resistance layer.

  The residual oxygen concentration at the wafer depth position as the target (target) is determined from the amount of the allowable range of the thermal donor obtained. In order to secure the determined residual oxygen concentration, the initial oxygen concentration of the wafer obtained from the p-type single crystal is determined, and based on this assumption, an oxygen precipitation heat treatment simulator is used, an oxygen outward diffusion heat treatment, and if necessary Specific heat treatment conditions are determined.

  Furthermore, in the manufacturing method of the present invention, the p / n type inversion region is generated at a depth not in contact with the device active region and the depletion layer region, and after performing oxygen outward diffusion heat treatment, By performing the precipitation nucleation heat treatment and the oxygen precipitate growth heat treatment, the internal oxygen precipitates are further ensured and the generation of thermal donors is reduced.

  Usually, the device manufacturing heat treatment process in which generation of oxygen donor is concerned is a wiring sintering process, and the heat treatment conditions of a general sintering process are 400 ° C., 1 hour or 450 ° C., 5 hours. Even in the heat treatment in the device process, the generation of thermal donors is reduced.

  For this reason, in the high resistance silicon wafer of the present invention, when a p-type wafer is used, not only the n-type inversion in the p / n-type inversion region but also the p-type inversion is again caused by the promotion of internal oxygen precipitation. Can occur.

  According to the present invention, it is possible to effectively suppress the generation of oxygen donors in the device heat treatment process, and it is possible to control oxygen precipitation-induced defects in the silicon wafer to a desired state, so that sufficient mechanical strength can be obtained. In the high resistivity layer in which the oxygen precipitate itself is prevented from becoming a slip dislocation source, and oxygen precipitation-induced defects in the silicon wafer are disposed between the P-type region and the N-type region of the high-frequency diode. It can be used as a recombination center, and the number of processing steps is not required for forming a recombination center (recombination center by Au, Pt, etc., or recombination center by electron beam irradiation defect) for lifetime control. Has sufficient gettering capability, and the resistivity does not change from the desired range even with device manufacturing heat treatment, shortening processing time and reducing manufacturing cost It can provide a suitable silicon wafer for the production of small high-frequency diode resistivity sufficiently high noise inexpensive high-resistivity layer with high quality.

  Hereinafter, 2nd Embodiment of the silicon wafer which concerns on this invention is described based on drawing.

The silicon wafer of the present invention does not generate a p / n type inversion region, and the variation in resistance distribution is 0-30 with respect to a reference value set in the range of 0.1-10 kΩcm throughout the wafer thickness. a silicon wafer having a p-type region set within%, p-type dopant concentration wafer surface resistivity becomes 0.1～10Keiomegacm, nitrogen ^{concentration; 1.0 × 10 13 ~10 × 10} 13 atoms / cm ³ (ASTM F123-1981), oxygen concentration Oi is sliced from a single crystal pulled up by a CZ method as 5.0 × 10 ^{17 to} 20 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), As shown in FIG. 4, a wafer surface is obtained through an oxygen outward diffusion heat treatment step, an oxygen precipitation nucleation heat treatment step and / or an oxygen precipitate formation heat treatment step in a non-oxidizing atmosphere. A p-type region on the surface side, and a region where a portion deeper than the p-type region has a resistance value approximately equal to the resistance value of the p-type region, or a region having a higher resistance than the resistance value of the p-type region, It is what you have. That is, the wafer does not have a region having a lower resistance than the set resistance value of the surface p-type region in the wafer depth direction.

Thus, in this embodiment, in addition to the oxygen outward diffusion heat treatment step, the surface p-type generated in the carbon-doped wafer by applying a heat treatment having a thermal effect equal to or equivalent to 1000 ° C. for 1 hour, for example. It is possible to realize a wafer in which no p / n type inversion region having a resistance lower than the set resistance value of the region is present.
As a result, it is possible to provide a silicon wafer with high resistivity capable of manufacturing a high-frequency diode with high gettering capability, high mechanical strength of the wafer, lifetime controllable, high yield and low cost, and a manufacturing method thereof. .

Next, a high frequency diode to which the silicon wafer of the present invention is applied will be described.
FIG. 14 is a schematic cross-sectional view for explaining an example of a high-frequency diode manufactured from the silicon wafer of the present invention. The high-frequency diode shown in FIG. 14A is a PIN diode, and is disposed on the silicon wafer of the present invention between the P-type region 12, the N-type region 11, and the P-type region 12 and the N-type region 11. The high specific resistance layer (I layer) 13 is formed.

The high-frequency diode shown in FIG. 14A can be manufactured as follows.
First, a silicon wafer of the present invention is prepared, and boron (B) is diffused at a concentration of about 1 × 10 ¹⁸ atoms / cm ^{3 at} a position of about 2 μm from the surface. Here, boron can be diffused by a thermal diffusion method or an ion implantation method at a temperature of about 1000 ° C.
Next, phosphorus (P) is diffused at a concentration of about 1 × 10 ¹⁸ atoms / cm ^{3 at} a position of about 2 μm from the back surface of the silicon wafer on which boron is diffused. Here, phosphorus can be diffused by a thermal diffusion method or an ion implantation method at a temperature of about 850 ° C.
Subsequently, an Au electrode is formed on the surface of the silicon wafer by electron beam evaporation, and an Al electrode is formed on the back surface of the silicon wafer by electron beam evaporation. Thereafter, a diode is cut out from the silicon wafer, mesa etching is performed, and silicon resin is applied to the etched surface after the mesa etching (passivation processing of the end surface).

FIG. 14B is a schematic cross-sectional view for explaining another example of the high-frequency diode manufactured from the silicon wafer of the present invention.
The high-frequency diode shown in the figure is an imput diode, and the p + layer 22, the n + layer 21, the high resistivity layer (I layer) 23, the p + layer 22 and the high resistivity layer ( The n layer 24 disposed between the I layer 23 and the I layer 23 is formed. The impatt diode is a starting element using a negative resistance. In an impat diode, carriers generated by impact ionization in a semiconductor are moved at a saturation drift velocity. At this time, a phase difference of π / 2 appears between the phase of the current generated by the carriers and the applied voltage, and the effective resistance component is negative, that is, a negative resistance appears.
The high-frequency diode shown in FIG. 14B has a p + layer 22, an n + layer 21, a high specific resistance layer (I layer) 23, and an n layer 24 formed on a silicon wafer in the same manner as the above PIN diode. It can be formed and manufactured.

FIG.14 (c) is a schematic sectional drawing for demonstrating the other example of the high frequency diode manufactured from the silicon wafer of this invention.
The high-frequency diode shown in FIG. 14 (c) is an imput diode, and on the silicon wafer, the p + layer 31, the n + layer 32, the high resistivity layer (I layer) 33, the p + layer 32, and the high A p layer 34 disposed between the specific resistance layer (I layer) 33 and the specific resistance layer 33 is formed.
The high-frequency diode shown in FIG. 14 (c) has a p + layer 31, an n + layer 32, a high resistivity layer (I layer) 33, and a p layer 34 formed on a silicon wafer in the same manner as the above PIN diode. It can be formed and manufactured.

  Next, an energy diagram of the PIN diode shown in FIG. FIG. 17 is a diagram for explaining an energy diagram of a PIN diode. FIG. 17A shows an energy diagram of the PIN diode shown in FIG. 14A, and FIG. 17B shows a recombination center. 1 shows an energy diagram of a conventional PIN diode in which heavy metal is thermally diffused. In FIG. 17, the symbol Ec is the energy at the bottom of the conduction band, the symbol Ef is the Fermi level, and the symbol Ev is the energy at the top of the valence band.

  As shown in FIG. 17B, in the conventional PIN diode, the switching speed strongly depends on the activation energy of deep energy levels, the capture cross section, and the concentration of heavy metal of the thermally diffused heavy metal. For example, as shown in FIG. 17B, when Pt is thermally diffused as a heavy metal, a deep energy level is formed at Ev + 0.33 eV, and the lifetime is determined. For example, as shown in FIG. 17B, when Au and Pt are thermally diffused as heavy metals, a deep energy level is formed at Ev + 0.42 eV, and the lifetime is determined.

  On the other hand, as shown in FIG. 17A, in the PIN diode manufactured from the silicon wafer of this embodiment, the deep energy level introduced by the BMD in the silicon wafer is the energy at the top of the valence band. It is continuously formed from Ev to Fermi level Ef. Therefore, compared to the conventional PIN diode shown in FIG. 17B, the lifetime can be controlled in a wide range, and the degree of freedom in the control range of the switching speed is large.

  Hereinafter, a third embodiment of a silicon wafer according to the present invention will be described with reference to the drawings.

The silicon wafer according to the present embodiment is used for an oscillator in voltage control in a transmission / reception circuit in a wireless device such as a mobile phone shown in FIG. 15, and has a carbon concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ atoms / cm. ^3. A wafer sliced from a p + type ingot pulled up with an interstitial oxygen concentration of 6.5 × 10 ^{17 to} 13.5 × 10 ¹⁷ atoms / cm ³ and a resistivity of 100 Ωcm or more. First, the resistivity is 100 Ωcm or more, the initial interstitial oxygen concentration is 8.0 × 10 ^{17 to} 16.0 × 10 ¹⁷ atoms / cm ³ , and the carbon concentration is 5 × 10 ^{15 to} 5 × by the CZ method. A silicon single crystal of 10 ¹⁷ atoms / cm ³ is grown (single crystal growth step). At this time, the desired silicon single crystal described above can be grown by appropriately adjusting the pulling conditions such as the number of revolutions of the crucible, the type and flow rate of the introduced gas, the temperature distribution of the silicon melt, and convection.

  Next, as in the first embodiment described above, slicing, chamfering, lapping, etching, polishing, and the like are performed as necessary, and a p-type layer having a resistivity of 100 Ωcm or more is epitaxially grown on the surface, and p / p + A heat treatment process is performed on the obtained silicon wafer in the same manner as in the first or second embodiment described above using a heat treatment furnace employing a lamp heating method.

  As a result, a wafer whose resistivity is not lowered by the sintering heat treatment process of the device manufacturing heat treatment can be obtained, and as a result, this wafer can be used as an oscillator in voltage control in a transmission / reception circuit in a wireless device such as a mobile phone shown in FIG. When the device is subjected to the device manufacturing process, current loss can be reduced.

Furthermore, as shown in FIG. 16, the efficiency η can be improved compared to a wafer that has a low resistance value,
The effect that can be produced.

  In order to verify the present invention, portions having different nitrogen concentrations from silicon single crystals doped with boron and pulled up by the CZ method are cut out as ingots (Top) and (Tail), and sliced from the different ingots. A plurality of wafers were prepared. Table 1 shows the oxygen concentration, resistivity, and nitrogen concentration. For comparison, carbon doped with the concentrations shown in Table 1 was also prepared. Here, the oxygen concentration, the resistance value, and the nitrogen concentration indicate an upper limit value and a lower limit value in each ingot cut out of the wafer.

These wafers were heat-treated at 1200 ° C. for 1 hr as AN1, and then the resistivity distribution in the depth direction was spread and obtained by resistance measurement. The result is shown in FIG.
From this result, C-dope doped with carbon, N (Top) -dope with a low nitrogen concentration, N (Tail) -dope with a high nitrogen concentration, in order of resistance peak that becomes a p / n type inversion boundary, It can be seen that the depth directions are 30 μm, 38 μm, and 45 μm, and are deeper in order.

Further, these wafers were subjected to heat treatment at 1200 ° C. for 1 hour + 1000 ° C. for 6 hours as AN2, and then the resistivity distribution in the depth direction was spread and obtained by resistance measurement. The result is shown in FIG.
From this result, the carbon-doped C-dope has a resistance peak at 20 μm, but the nitrogen-doped one has a region where the resistance value is reduced compared to the p-type region of the surface layer. You can see that they are not.

Further, these wafers were heat-treated at 1200 ° C. for 1 hr as AN1, and then heat-treated at 650 ° C. for 30 minutes, and the resistivity distribution in the depth direction was spread and resistance measurement was performed. The result is shown in FIG.
From this result, the resistance of the carbon-doped C-dope, the low nitrogen concentration N (Top) -dope, and the high nitrogen concentration N (Tail) -dope are almost the same as the resistance value of the p-type region of the layer. It can be seen that there is no region where the value is formed in the added direction and the resistance value is reduced in the added direction.

Further, these wafers were heat treated at 1200 ° C. for 1 hr + 1000 ° C. for 6 hours as AN2, and then heat treated at 650 ° C. for 30 minutes, and the resistivity distribution in the depth direction was spread and resistance measurement was performed. The result is shown in FIG.
From this result, the resistance of the carbon-doped C-dope, the low nitrogen concentration N (Top) -dope, and the high nitrogen concentration N (Tail) -dope are almost the same as the resistance value of the p-type region of the layer. It can be seen that there is no region where the value is formed in the added direction and the resistance value is reduced in the added direction.

Further, these wafers were heat-treated at 1200 ° C. for 1 hr as AN1, and then heat-treated at 650 ° C. for 30 min + 400 ° C. for 1 hr, and the resistivity distribution in the depth direction was spread to determine the resistance. The result is shown in FIG.
From this result, C-dope doped with carbon, N (Top) -dope with a low nitrogen concentration, N (Tail) -dope with a high nitrogen concentration, in order of resistance peak that becomes a p / n type inversion boundary, It can be seen that the depth direction becomes 20 μm, 30 μm, and 31 μm, and the depth increases in order. Also, compared to carbon-doped C-dope, both N (Top) -dope with a low nitrogen concentration and N (Tail) -dope with a high nitrogen concentration reduce the decrease in resistance at deeper depths. I understand that.

Further, these wafers were heat-treated at 1200 ° C. for 1 hr + 1000 ° C. for 6 hr as AN2, and then heat-treated at 650 ° C. for 30 min + 400 ° C. for 1 hr. The result is shown in FIG.
From this result, the carbon-doped C-dope has a resistance peak at 20 μm, but the nitrogen-doped one has a region where the resistance value is reduced compared to the p-type region of the surface layer. You can see that they are not.

Next, in C-dope doped with carbon, N (Top) -dope with low nitrogen concentration, and N (Tail) -dope with high nitrogen concentration, as AN1, after heat treatment at 1200 ° C. for 1 hr, and as AN2 The residual oxygen concentration after heat treatment at 1200 ° C. for 1 hr + 1000 ° C. for 6 hr was measured. The result is shown in FIG. The oxygen concentration was measured by infrared absorption measurement (FT-IR).
From this result, it can be seen that the residual oxygen concentration is further reduced in AN2 in which the heat treatment time is longer in the case where nitrogen is doped as compared with C-dope doped with carbon.

Similarly, in C-dope doped with carbon, N (Top) -dope with low nitrogen concentration, and N (Tail) -dope with high nitrogen concentration, as AN1, after heat treatment at 1200 ° C. for 1 hr, and as AN2 After heat treatment at 1200 ° C. for 1 hr + 1000 ° C. for 6 hr and further heat treatment at 780 ° C. for 3 hr + 1000 ° C. for 16 hr, the generated BMD density was measured. The result is shown in FIG. This measurement was performed by observation with a cross-sectional optical microscope after light etching.
From this result, it can be seen that the BMD density is higher in AN2 in which the heat treatment time is longer in the case where nitrogen is doped as compared with C-dope doped with carbon.

<Example>
Further, as an example, a VCO (Voltage Control Oscillator was manufactured using the high resistance silicon wafer obtained by the present invention as described above, and a Q value (quality factor) as an evaluation index of power loss was measured. At the time, the effect on the power loss in the high resistance wafer (500 Ωcm) and the normal wafer (10 Ωcm) was evaluated.

  As a result, it was demonstrated that the Q value of a VCO fabricated using a high resistance wafer was improved by about three times in the frequency band of 60 GHz as compared with the normal resistance. This is considered to be because noise propagation (noise current propagation) in a deep region of the substrate is suppressed by using a high-resistance silicon substrate.

11: N type region, 12: P type region, 13, 23, 33: High specific resistance layer (I layer), 24:
n layer, 21, 32: n + layer, 22, 31: p + layer, 34: p

Claims (2)

A high resistance value capable of reducing current loss generated in a device region in which a voltage controller is formed in a wireless transmission / reception circuit with an output of about 10 mW to 100 mW, which is a high frequency of 10 GHz to 100 GHz, and a p / n type A silicon wafer manufacturing method capable of adjusting a depth range from a surface where an inversion region occurs,
The p-type dopant concentration and nitrogen concentration at which the wafer surface resistance value becomes 591.6 to 1905 Ωcm; 3.98 × 10 ^{13 to} 8.92 × 10 ¹³ atoms / cm ³ (ASTM F123-1981 ), and the oxygen concentration Oi is 8. a pulling step of pulling a single crystal by the CZ method as ^{0 × 10 17 ~16.0 × 10 17} atoms / cm 3 (ASTM F123-1979), a processing step of processing the wafer was sliced from this single crystal, a non-oxidizing An oxygen outward diffusion heat treatment step with a sexual atmosphere,
The oxygen outward diffusion heat treatment is a heat treatment condition in which the treatment temperature is 1100 to 1250 ° C. and the treatment time is 1 to 5 hours in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof,
By performing the oxygen outward diffusion heat treatment, when the heat treatment in the device manufacturing process is performed, the p / n type inversion region resulting from the generation of thermal donors is formed into the device active region and the depletion layer region formed in contact therewith. To a depth that does not touch the
Peak position of the resistance value at the boundary between the wafer front surface side of the p-type region and the thickness direction inside the p / n-type region is set to the range of the boundary depth 20~45μm from Thus the wafer surface to the nitrogen concentration And adjust
When nitrogen is doped, in the device region, after the oxygen outward diffusion heat treatment, the oxygen precipitate density generated when heat treatment is further performed at 780 ° C. 3 hr + 1000 ° C. 16 hr, the wafer surface resistance is 591.6-1905 Ωcm. The p-type dopant concentration and the oxygen concentration Oi are 8.0 × 10 ^{17 to} 16.0 × 10 ¹⁷ atoms / cm ³ (ASTM F123-1979), which is the maximum limit concentration that does not cause polycrystallization (DF cut) Oxygen precipitation that occurs when a wafer obtained by CZ method by doping carbon of 32 × 10 ¹⁶ atoms / cm ³ (ASTM F123-1981) is further subjected to heat treatment at 780 ° C. 3 hr + 1000 ° C. 16 hr after the oxygen outward diffusion heat treatment. A method for producing a high-resistance silicon wafer, characterized by increasing 2 to 4 × 10 ¹⁰ pieces / cm ³ as compared with an object density.   2. The method for producing a high resistance silicon wafer according to claim 1, further comprising an epitaxial step of epitaxially growing a p-type layer having a resistivity of 100 [Omega] cm or more on the surface to form a p / p + type wafer.

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