JP5965696B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In order to achieve high integration, high speed, and low power consumption of a semiconductor device, miniaturization of a transistor used in the semiconductor device is essential, and a technique for achieving miniaturization is required. In general, in a semiconductor device manufacturing process, a fine structure is formed using a photolithography process.

However, miniaturization of semiconductor devices in recent years has come to require a structure below the resolution limit of the exposure apparatus used in the photolithography process, and research has been conducted on a method for forming a structure below the resolution limit of the exposure apparatus. (For example, refer to Patent Document 1).

JP 2009-16814 A

In a semiconductor device having a structure below the resolution limit of an exposure apparatus, it is difficult to process the shape accurately, and problems such as short-circuiting between wirings and poor contact are likely to occur. For this reason, there is a concern that the yield may decrease with the miniaturization of the semiconductor device.

Thus, an object of one embodiment of the present invention is to provide a semiconductor device having a fine structure. An object is to manufacture a semiconductor device having a fine structure with high yield.

According to one embodiment of the present invention, a semiconductor layer, a gate insulating layer over the semiconductor layer, a gate electrode layer over the gate insulating layer, and a sidewall insulating layer that covers a side surface of the gate electrode layer are formed and covered. Forming a conductive film to be a source electrode layer and a drain electrode layer, forming a first protective film on the conductive film, and performing a first etching on a resist film provided on the first protective film, A resist mask from which a region overlapping with the gate electrode layer is removed is formed, and a second protective film is formed by performing second etching on the first protective film using the resist mask, and the second protective film is formed. This is a method for manufacturing a semiconductor device, in which a region overlapping with the gate electrode layer of the conductive film is removed by performing third etching on the conductive film using the protective film as a mask to form a source electrode layer and a drain electrode layer.

The resist film is formed by a coating method, and the lower surface of the resist film has irregularities corresponding to the structure overlapping with the resist film, but the upper surface of the resist film is substantially flat. Therefore, the region of the resist film that overlaps with the gate electrode layer is thinner than the other regions. When anisotropic etching (first etching) is performed on the resist film, the gate electrode is self-aligned. A resist mask from which a region overlapping with the layer is removed can be formed. In the formation of the resist mask, precise alignment is unnecessary, so that precise processing can be performed accurately, and variations in shape and characteristics can be reduced in the manufacturing process of the semiconductor device.

A second protective film is formed by performing second etching using the resist mask on the first protective film. Therefore, the second etching is performed under the condition that the etching rate of the first protective film is lower than the etching rate of the resist mask.

The source electrode layer and the drain electrode layer are formed by performing third etching on the conductive film using the second protective film as a mask. In the third etching, the etching rate of the second protective film is lower than the etching rate of the conductive film.

Therefore, according to one embodiment of the present invention, a semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a gate electrode layer is formed over the gate insulating layer, and a sidewall insulating layer covering a side surface of the gate electrode layer is formed And forming a conductive film covering the semiconductor layer, the gate insulating layer, the gate electrode layer, and the sidewall insulating layer, forming a first protective film over the conductive film, and forming a resist film over the first protective film. First etching is performed on the resist film to form a resist mask from which a region overlapping with the gate electrode layer of the resist film is removed, and second etching is performed on the first protective film using the resist mask. Forming a second protective film from which a region overlapping with the gate electrode layer of the first protective film is removed, and performing a third etching on the conductive film using the second protective layer as a mask, whereby the conductive film Except for the region overlapping with the gate electrode layer. And a method for manufacturing a semiconductor device for forming a source and drain electrode layers.

In the third etching, the etching selectivity of the conductive film with respect to the second protective film is 2 or more, more preferably 5 or more. Note that as a gas used for the third etching, a gas containing oxygen, a gas containing oxygen and chlorine, or the like can be given.

An oxide insulating layer is formed over the source electrode layer, the drain electrode layer, the second protective film, the gate electrode layer, and the sidewall insulating layer, and fourth etching is performed on the oxide insulating layer and the second protective film. Thus, openings reaching the source electrode layer and the drain electrode layer are formed, and the etching rate of the oxide insulating layer and the second protective film is higher than the etching rate of the source electrode layer and the drain electrode layer in the fourth etching. A method for manufacturing a semiconductor device.

One embodiment of the present invention includes a semiconductor layer, a gate insulating layer over the semiconductor layer, a gate electrode layer over the gate insulating layer, a sidewall insulating layer covering a side surface of the gate electrode layer, a semiconductor layer, and a gate insulating layer. Source electrode layer and drain electrode layer in contact with side surface and side surface of side wall insulating layer, protective film on source electrode layer and drain electrode layer, source electrode layer, drain electrode layer, protective film, gate electrode layer, and side wall insulating layer And the oxide insulating layer and the protective film include an opening reaching the source electrode layer or the drain electrode layer, and a side surface in contact with the sidewall insulating layer of the source electrode layer and the drain electrode layer is The semiconductor device includes a lower end portion in contact with the sidewall insulating layer and an upper end portion whose end portion coincides with the protective film, and the lower end portion and the upper end portion are different in height.

The protective film functions as a mask in etching of the source electrode layer and the drain electrode layer. The protective film includes tantalum nitride or silicon oxynitride.

The source electrode layer and the drain electrode layer may be formed using a conductive film containing tungsten or molybdenum.

Alternatively, an insulating layer stacked over the top surface of the gate electrode layer may be formed. By forming the insulating layer, insulation between the gate electrode layer and the source and drain electrode layers is guaranteed, so that the yield of the semiconductor device can be further improved.

In the case where an insulating layer is provided over the top surface of the gate electrode layer, the sidewall insulating layer preferably covers side surfaces of the gate electrode layer and the insulating layer.

Further, with the method for manufacturing a semiconductor device of one embodiment of the present invention, a fine semiconductor device can be formed with high yield. Therefore, in the semiconductor device of one embodiment of the present invention, the length of the gate electrode layer in the channel length direction can be 100 nm or less, preferably 30 nm or less, so that the semiconductor device can be highly integrated and have high performance. .

In addition, an oxide semiconductor layer is preferably used as the semiconductor layer.

Further, a wiring layer that is electrically connected to the source electrode layer and the drain electrode layer may be provided through an opening included in the oxide insulating layer.

According to one embodiment of the present invention, a semiconductor device having a fine structure can be provided. A semiconductor device having a fine structure can be manufactured with high yield.

4A and 4B are a top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. FIG. 10 is a cross-sectional view of a semiconductor device of one embodiment of the present invention. 4A and 4B are a cross-sectional view, a top view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating one embodiment of a semiconductor device. 10A and 10B each illustrate an electronic device that is one embodiment of a semiconductor device. 10A and 10B each illustrate an electronic device that is one embodiment of a semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below.

In the embodiments described below, the same reference numerals may be used in common in different drawings. Note that components shown in the drawings, that is, thicknesses, widths, relative positional relationships, and the like of layers and regions may be exaggerated for the sake of clarity in the description of the embodiments.

In the present specification and the like, the term “upper” does not limit that the positional relationship between the components is “directly above”. For example, the expression “a gate electrode layer over an insulating layer” does not exclude the case where another component is included between the insulating layer and the gate electrode layer. The same applies to “lower”.

Further, in this specification and the like, the terms “electrode layer” and “wiring layer” do not functionally limit these components. For example, an “electrode layer” may be used as part of a “wiring layer” and vice versa. Furthermore, the terms “electrode layer” and “wiring layer” include a case where a plurality of “electrode layers” and “wiring layers” are integrally formed.

In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.

For example, “thing having some electric action” includes electrodes and wirings.

Further, the “channel length direction” is a direction from the source region (or source electrode) to the drain region (drain electrode), or the opposite direction, and the path in which the distance between the source region and the drain region is minimized. The direction through.

Further, in this specification, the “selection ratio” of B etching with respect to A is defined as the B etching rate (also referred to as an etching rate) divided by the A etching rate under the same etching conditions. For example, “selective ratio of etching of conductive film with respect to protective film” means a value obtained by dividing the etching rate of the conductive layer by the etching rate of the protective film.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. FIG. 1 illustrates a semiconductor device of one embodiment of the present invention. 1A is a top view of the semiconductor device of one embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along one-dot chain line A-B in FIG.

A semiconductor device including the transistor 420 includes a base insulating layer 436 over a substrate 400, a semiconductor layer 403, a gate insulating layer 402 over the semiconductor layer 403, a gate electrode layer 401 over the gate insulating layer 402, and a gate electrode layer 401. The side wall insulating layer 412a and the side wall insulating layer 412b covering the side surfaces of the gate insulating layer 402, the source electrode layer 405a covering the side surfaces of the gate insulating layer 402 and the side wall insulating layer 412a on the semiconductor layer 403, and the gate insulating layer 402 on the semiconductor layer 403. And a drain electrode layer 405b covering the side surface of the sidewall insulating layer 412b, a protective film 407a over the source electrode layer 405a, a protective film 407b over the drain electrode layer 405b, a source electrode layer 405a, and a drain electrode layer 405b. .

In addition, the semiconductor device described in this embodiment includes the second protective film 407a, the second protective film 407b, the gate electrode layer 401, and the oxide insulating layer 408 over the sidewall insulating layers 412a and 412b, and an oxide insulating film. The wiring layer 409a and the wiring layer 409b are connected to the source electrode layer 405a and the drain electrode layer 405b through openings provided in the layer 408, the second protective film 407a, and the second protective film 407b, respectively.

The protective film 407a and the protective film 407b function as a mask in etching for forming the source electrode layer 405a and the drain electrode layer 405b. Therefore, side surfaces of the protective film 407a and the protective film 407b that overlap with the side wall insulating layers form substantially continuous surfaces with side surfaces of the source electrode layer 405a and the drain electrode layer 405b that are in contact with the side wall insulating layers.

Further, on the side surfaces of the source electrode layer 405a and the drain electrode layer 405b that are in contact with the sidewall insulating layers, the end portions that are in contact with the sidewall insulating layers 412a and 412b are the lower end portions, and the end portions that are in contact with the protective films 407a and 407b are The upper end portions of the source electrode layer 405a and the drain electrode layer 405b coincide with the end portions of the protective film 407a and the protective film 407b, and the upper end portion and the lower end portion of the source electrode layer 405a and the drain electrode layer 405b are high. Is different.

The protective film 407a and the protective film 407b may be an insulating material or a conductive material. In the case where the protective film 407a and the protective film 407b are formed using an insulating material, the protective film 407a and the protective film 407b function as part of the insulating layer formed over the transistor 420 as in the case of the oxide insulating layer 408. .

In the case where the protective film 407a and the protective film 407b are formed using a conductive material, the protective film 407a and the protective film 407b function as part of the source electrode layer 405a and the drain electrode layer 405b. Alternatively, the protective film 407a and the protective film 407b can have a stacked structure, and a region in contact with the source and drain electrode layers can be formed using a conductive material, and a region in contact with the oxide insulating layer 408 can be formed using an insulating material.

A method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

First, the base insulating layer 436 is formed over the substrate 400.

There is no particular limitation on the substrate that can be used, but it is necessary that the substrate has at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

As the substrate 400, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or the like may be used. Alternatively, an SOI substrate, a semiconductor substrate provided with a semiconductor element, or the like can be used.

The base insulating layer 436 can be formed by sputtering, MBE (Molecular Beam Epitaxy), CVD (Chemical Vapor Deposition), pulsed laser deposition (PLD), ALD (Atomic Layer Deposition), or the like. it can. Note that when the base insulating layer 436 is formed by a sputtering method, impurity elements such as hydrogen can be reduced.

As the base insulating layer 436, an oxide insulating layer such as silicon oxide, gallium oxide, aluminum oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, or tantalum oxide is preferably used. In addition, these compounds can be used in the form of a single layer structure or a laminated structure of two or more layers.

Note that silicon oxynitride refers to a silicon oxynitride having a higher oxygen content than nitrogen in the composition, for example, at least oxygen is 50 atomic% to 70 atomic% and nitrogen is 0.5 atomic% to 15 The atomic percent or less, and silicon is contained in the range of 25 atomic percent to 35 atomic percent. However, the above ranges are those measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). Further, the content ratio of the constituent elements takes a value that the total does not exceed 100 atomic%.

Note that as long as the insulating property between the substrate 400 and the semiconductor layer 403 provided later can be ensured, a structure in which a base insulating layer is not provided can be employed as in the transistor 430 illustrated in FIG.

Subsequently, a semiconductor layer 403 is formed over the base insulating layer 436. For the semiconductor layer 403, a silicon-based semiconductor (amorphous silicon, polycrystalline silicon, or the like), an oxide semiconductor (zinc oxide, indium oxide, or the like), or the like can be used. As a suitable semiconductor used for the semiconductor layer 403, an oxide semiconductor can be given. The details of the oxide semiconductor will be described in Embodiment 2.

The semiconductor layer 403 can be formed by forming a semiconductor film over the substrate 400 and then processing the semiconductor film into an island-shaped semiconductor layer 403. The semiconductor film can be formed by a sputtering method, an evaporation method, a pulsed laser deposition method (PCVD method), a PLD method, an ALD method, an MBE method, or the like.

Subsequently, a gate insulating film is formed over the semiconductor layer 403.

As a material for the gate insulating film, an oxide insulating layer such as silicon oxide, gallium oxide, aluminum oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, or tantalum oxide is preferably used. Also, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y , x> 0, y> 0), nitrogen-added hafnium silicate, hafnium aluminate (HfAl _x O _y , x> 0, y> 0) Gate leak current can be reduced by using a High-k material such as lanthanum oxide. Further, the gate insulating film may have a single-layer structure or a stacked structure.

The thickness of the gate insulating film is 1 nm to 20 nm, and a sputtering method, an MBE method, a CVD method, a PLD method, an ALD method, or the like can be used as appropriate. Further, the gate insulating film is formed by using a sputtering apparatus that performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target, that is, a so-called CP sputtering apparatus (Column Plasma Sputtering system). Also good.

In this embodiment, silicon oxynitride is formed to a thickness of 20 nm by a CVD method. Note that here, after the gate insulating film is formed, the island-shaped gate insulating layer 402 is not processed.

Note that planarization treatment may be performed on the top surface of the semiconductor layer 403 in order to improve the coverage with the gate insulating film. In particular, in the case where an insulating film with a small thickness is used as the gate insulating film, the surface of the semiconductor layer 403 is preferably flat.

Next, a gate electrode layer 401 is formed over the gate insulating film so as to overlap with the semiconductor layer 403.

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. Furthermore, indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

As one layer of the gate electrode layer 401 in contact with the gate insulating film, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, An In—Ga—O film containing nitrogen, an In—Zn—O film containing nitrogen, an Sn—O film containing nitrogen, an In—O film containing nitrogen, a metal nitride film (InN, SnN, etc.) Can be used. These films have a work function of 5 eV or 5.5 eV or more, and when used as a gate electrode, the threshold voltage of the electrical characteristics of the transistor can be made positive, so that a so-called normally-off switching element can be realized.

The thickness of the gate electrode layer 401 is preferably greater than or equal to 50 nm and less than or equal to 300 nm. In this embodiment, a stack of tantalum nitride with a thickness of 30 nm and tungsten with a thickness of 200 nm is formed by a sputtering method.

The length of the gate electrode layer 401 in the channel length direction is 100 nm or less, preferably 30 nm or less. In the semiconductor device of one embodiment of the present invention, the channel length can be determined by the length of the gate electrode layer 401 in the channel length direction; thus, a transistor with a small channel length can be obtained.

Note that here, the resistance of the semiconductor layer 403 may be reduced by introducing an impurity element into the semiconductor layer 403 using the gate electrode layer 401 as a mask. As a method for introducing the impurity element, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

As the impurity element to be introduced, phosphorus, boron, nitrogen, arsenic, argon, aluminum, molecular ions containing these, or the like can be used. The dose of these elements is preferably 1 × 10 ^{13 to} 5 × 10 ¹⁶ ions / cm ² . Further, when phosphorus is introduced as the impurity element, the acceleration voltage is preferably 0.5 to 80 kV.

Further, the treatment for introducing the impurity element into the semiconductor layer 403 may be performed a plurality of times. In the case where the treatment for introducing the impurity element into the semiconductor layer 403 is performed a plurality of times, the impurity element may be the same for all of the plurality of times, or may be changed for each treatment.

When the semiconductor layer has a region where resistance is reduced by introducing the impurity element, contact resistance between the semiconductor layer 403 and a source electrode layer and a drain electrode layer which are formed later is reduced. By reducing the contact resistance, an electric field in the vicinity of the source electrode layer and the drain electrode layer is relaxed, and a semiconductor device with excellent electrical characteristics that has high on characteristics, high speed operation, and high speed response can be obtained.

Next, an insulating film is formed over the gate insulating film and the gate electrode layer 401, and the sidewall insulating layer 412a and the sidewall insulating layer 412b are formed by etching the insulating film. For the etching, anisotropic etching is used. Further, the gate insulating film is etched using the gate electrode layer 401, the sidewall insulating layer 412a, and the sidewall insulating layer 412b as masks, so that the gate insulating layer 402 is formed (see FIG. 2A).

The insulating layer to be the sidewall insulating layer 412a and the sidewall insulating layer 412b is typically an inorganic insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, or aluminum nitride oxide. Materials can be used. Further, the sidewall insulating layer 412a and the sidewall insulating layer 412b can be formed by a plasma CVD method, a sputtering method, or the like.

In this embodiment, the sidewall insulating layer 412a and the sidewall insulating layer 412b are formed using a silicon oxynitride film.

Next, a source electrode layer and a drain electrode layer (including a wiring formed using the same layer) over the semiconductor layer 403, the gate insulating layer 402, the gate electrode layer 401, the sidewall insulating layer 412a, and the sidewall insulating layer 412b A conductive film 415 is formed (see FIG. 2B).

The conductive film 415 can be formed using a material and a method similar to those of the gate electrode layer 401. The conductive film 415 is formed by forming a conductive film, forming a resist mask over the conductive film by a photolithography process, processing the conductive film into an island shape by selective etching, and then removing the resist mask. it can. Note that in the etching step, the conductive film 415 in a region overlapping with the gate electrode layer 401 is not removed. The thickness of the conductive film 415 is 10 nm to 50 nm. In this embodiment mode, a 30 nm tungsten film is formed.

Subsequently, a first protective film 416 is formed over the conductive film 415 (see FIG. 2C), and a resist film 417 is formed over the first protective film (see FIG. 2D).

The first protective film 416 is a film that functions as a mask for etching (third etching) of the conductive film 415 in a subsequent formation step. Therefore, the first protective film 416 includes a material that can have an etching selectivity with respect to the conductive film 415. Specifically, in the third etching, the etching selectivity of the conductive film 415 with respect to the protective film 416 is 2 or more, preferably 5 or more. Since the protective film formed here and the protective film functioning as a mask are different in shape, the protective film before being processed into the mask shape functions as the first protective film and the mask for convenience of explanation. The processed protective film is called a second protective film for distinction.

For example, when tungsten or molybdenum is used for the conductive film 415, silicon oxynitride, tantalum oxide, or the like can be used for the first protective film 416. In this embodiment, a 30-nm-thick silicon oxynitride film is formed as the first protective film 416.

As the resist film 417, a photoresist material may be used. For example, a resist whose main component is a novolac resin, a resist whose main component is a polyethylene resin, and the like can be used. These resists are preferable because of their excellent resistance to dry etching.

The resist film 417 is formed by a coating method. Therefore, the lower surface of the resist film has irregularities corresponding to the structure formed under the resist film, but the upper surface of the resist film is substantially flat. Therefore, as shown in FIG. 2D, the region of the resist film 417 overlapping with the gate electrode layer 401 is thinner than the other regions.

Subsequently, anisotropic etching (first etching) is performed on the resist film 417, and the thickness of the resist film 417 is decreased until the resist film 417 overlapping with the gate electrode layer 401 is removed. A resist mask 418 is formed by exposing the protective film 416 and removing a region overlapping with the gate electrode layer 401 of the resist film 417 (see FIG. 3A).

Etching (first etching) of the resist film 417 is anisotropic etching. As described above, the thickness of the resist film 417 overlapping with the gate electrode layer 401 is smaller than that of other regions. Therefore, when anisotropic etching is performed on the resist film 417, even if the resist film 417 in the region overlapping with the thin gate electrode layer 401 is completely removed, the resist film in other regions remains and remains. The resist mask 418 can be formed in a self-aligned manner using the resist film. In the formation of the resist mask 418, precise alignment is unnecessary, so that precise processing can be performed accurately, and variation in shape and characteristics can be reduced in the manufacturing process of the semiconductor device.

As the etching, dry etching or wet etching may be used. However, dry etching is preferable as the highly anisotropic etching. For example, a gas containing carbon tetrafluoride (CF ₄ ), chlorine (Cl ₂ ), oxygen (O ₂ ), or the like is used as an etching gas. preferable. Furthermore, it is preferable to use a reactive ion etching method (RIE method) in which a high frequency voltage is applied to the substrate.

Next, the first protective film 416 is etched (second etching) using the resist mask 418, the region overlapping with the gate electrode layer 401 of the first protective film 416 is removed, and the second protective film 416 is divided. A protective film 407a and a second protective film 407b are formed (see FIG. 3B).

For the etching of the first protective film 416 (second etching), anisotropic etching is performed. For example, a gas containing fluorine such as trifluoromethane (CHF ₃ ), octafluorocyclobutane (C ₄ F ₈ ), tetrafluoromethane (CF ₄ ), or the like can be used as an etching gas, such as helium (He) or argon (Ar). A noble gas such as hydrogen or hydrogen (H ₂ ) may be added. Furthermore, it is preferable to use a reactive ion etching method (RIE method) in which a high frequency voltage is applied to the substrate.

In the second etching, precise processing that reflects the shape of the resist mask 418 is performed on the second protective film 407a and the second protective film 407b. Therefore, the etching selectivity between the resist mask 418 and the first protective film 416 (the second protective film 407a and the second protective film 407b) can be taken. Specifically, in the second etching, the resist mask 418 is compared with the resist mask 418. The etching selectivity of the first protective film 416 is 2 or more, preferably 5 or more.

The resist mask 418 is a mask that can be precisely processed because it is formed in a self-aligned manner and does not require precise alignment. Therefore, the second protective film 407a and the second protective film 407b reflecting the shape of the resist mask 418 also function as masks that can accurately perform precise processing.

Subsequently, the conductive film 415 is etched (third etching) using the second protective film 407a and the second protective film 407b as a mask, so that a region overlapping with the gate electrode layer 401 of the conductive film 415 is removed. The source electrode layer 405a and the drain electrode layer 405b are formed by separation (see FIG. 3C).

Note that the reason why the second protective film 407a and the second protective film 407b are used as masks in addition to the resist mask 418 in the etching of the conductive film 415 (third etching) is described below.

With the miniaturization of a semiconductor device, the channel length and the channel width of the gate electrode layer 401 are reduced, and the gate electrode layer 401 is being thinned. The resist mask 418 is formed in a self-aligned manner mainly using the thickness of the gate electrode layer 401. Therefore, when the gate electrode layer 401 is thinned, the resist mask 418 is also thinned.

When the resist mask 418 is thinned, depending on the material of the conductive film 415, the resist mask 418 may be removed by etching before the etching process of the conductive film 415 is completed, so that the resist mask 418 cannot function sufficiently.

Therefore, in order to accurately process the source electrode layer 405a and the drain electrode layer 405b, it is necessary to limit a material used for the source electrode layer 405a and the drain electrode layer 405b to a material having a selection ratio with respect to the resist mask. This causes a problem that the transistor characteristics are not sufficiently improved and the transistor characteristics cannot be sufficiently improved.

In the semiconductor device described in this embodiment, a second protective film 407 a and a second protective film 407 a which can have an etching selectivity with respect to each film are formed between the resist mask 418 and the conductive film 415 to be the source electrode layer 405 a and the drain electrode layer 405 b. Since the second protective film 407b is formed, the etching of the conductive film 415 is completed using the second protective film 407a and the second protective film 407b even when the resist mask 418 disappears in the etching of the conductive film 415. Can be made. Therefore, etching can be performed accurately even if the resist mask is thinned.

Therefore, the material used for the source electrode layer 405a and the drain electrode layer 405b can be appropriately selected from materials that can improve transistor characteristics without being limited by a manufacturing process. Therefore, even in a fine semiconductor device, the semiconductor characteristics can be improved.

The second protective film 407a and the second protective film 407b can have an etching selectivity with respect to the conductive film 415. Specifically, in the third etching, the second protective film 407a and the second protective film 407b are compared with the second protective film 407a and the second protective film 407b. A material whose etching selectivity of the conductive film 415 is 2 or more, preferably 5 or more is used. Therefore, before the etching process of the conductive film 415 is completed, the second protective film 407a and the second protective film 407b are removed by etching and are not lost, and the processing can be finished accurately. .

Further, as described above, since the shape of the resist mask 418 is reflected in the second protective film 407a and the second protective film 407b, a precise shape is accurately formed regardless of alignment accuracy. Has been. Therefore, the source electrode layer 405a and the drain electrode layer 405b formed by etching using the second protective film 407a and the second protective film 407b as a mask can also have a precise shape. Since a precise shape can be accurately manufactured, variation in transistor shape and characteristics can be reduced. Therefore, defects caused by variations in shape and characteristics are less likely to occur, and the yield of semiconductor devices can be improved.

Note that the second protective film 407a and the second protective film 407b may be removed as appropriate after the source electrode layer 405a and the drain electrode layer 405b are formed. Further, the film thickness may be decreased by etching (third etching) of the conductive film 415.

Further, the resist mask 418 can be removed by etching at the same time as the etching of the conductive film 415 (third etching). By taking such a method, a manufacturing process can be reduced.

As an etching gas used for etching the conductive film 415 (third etching), a gas containing carbon tetrafluoride (CF ₄ ), chlorine (Cl ₂ ), oxygen (O ₂ ), or the like, a gas containing chlorine and oxygen, A gas containing sulfur hexafluoride (SF ₆ ) or the like is used.

Note that in the etching of the conductive film 415 (third etching), the gate electrode layer 401 is preferably not etched. A film having an etching selectivity with respect to each film may be formed between the gate electrode layer 401 and the conductive film 415 so that the gate electrode layer 401 is not etched.

For example, as in a transistor 440 illustrated in FIG. 4B, a structure in which an insulating layer 413 is stacked over the gate electrode layer 401 may be employed. The insulating layer 413 can ensure insulation between the gate electrode layer 401 and the source and drain electrode layers 405a and 405b. Therefore, a short circuit between the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b can be suppressed. Accordingly, generation of defects due to short-circuiting between the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b can be suppressed, so that the yield of transistors can be further improved.

Note that the insulating layer 413 is preferably formed by forming the sidewall insulating layer 412a and the sidewall insulating layer 412b so as to cover the side surfaces of the insulating layer 413 because the insulating property can be further ensured. In the case where the insulating layer 413 is provided, the source electrode layer 405 a and the drain electrode layer 405 b may be higher than the top surface of the gate electrode layer 401.

Subsequently, an oxide insulating layer 408 is formed over the source electrode layer 405a, the drain electrode layer 405b, the second protective film 407a, the second protective film 407b, the sidewall insulating layer 412a, the sidewall insulating layer 412b, and the gate electrode layer 401. Then, an opening is formed by etching (fourth etching) in the oxide insulating layer 408, the second protective film 407a, and the second protective film 407b, and a conductive material is formed in the opening. 409a and a wiring layer 409b are formed (see FIG. 3D).

As the oxide insulating layer 408, typically, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum oxynitride layer, a gallium oxide layer, a hafnium oxide layer formed by a sputtering method or a CVD method is used. An yttrium oxide layer or the like can be used. In this embodiment mode, silicon oxynitride formed by a CVD method is used.

When the oxide insulating layer 408 is formed using a material that can be etched under conditions similar to those of the second protective film 407a and the second protective film 407b, an opening in which the wiring layer 409a and the wiring layer 409b are formed can be formed by one etching. preferable.

Note that the second protective film 407a and the second protective film 407b, the source electrode layer 405a, and the drain electrode layer 405b are formed using materials that can be etched, and the source electrode layer 405a and the drain electrode layer 405b are formed in the formation of the openings. May function as an etching stopper.

Note that in the case where the protective film 407a and the protective film 407b are formed using a conductive material, as in the transistor 450 illustrated in FIG. 4C, the second protective film 407a and the second protective film 407b are provided. The wiring layer 409a and the wiring layer 409b may be electrically connected to the source electrode layer 405a and the drain electrode layer 405b.

In the semiconductor device described in this embodiment, a resist film can be formed in a self-aligned manner by forming a resist film over the gate electrode layer by a coating method and performing anisotropic etching on the resist film. . Since the resist mask can be formed in a self-aligned manner, precise alignment of the resist mask becomes unnecessary. In the formation of the resist mask, precise alignment accuracy is not required. Therefore, a fine transistor can be manufactured without realizing high alignment accuracy required for a fine transistor. Therefore, a fine transistor can be manufactured with high yield.

In addition, a protective film that can provide an etching selectivity between the resist film and the conductive film is formed. Therefore, the conductive film can be etched using the protective film as a mask even when the resist mask is thinned as the semiconductor device is miniaturized. In the etching of the conductive film, etching is performed using a protective film having a selection ratio with respect to the conductive film as a mask, so that the mask is not removed before the etching step is completed, and the etching can be performed accurately. Accordingly, variation in shape and characteristics of the transistor can be reduced, and defects caused by variation in shape and characteristics are less likely to occur, so that the yield of the semiconductor device can be improved.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, an oxide semiconductor which is a preferable embodiment as a semiconductor that can be used for the semiconductor layer of the semiconductor device described in Embodiment 1 is described in detail.

An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. In addition to the stabilizer, gallium (Ga) is preferably used as a stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. In addition, it is preferable to have tin (Sn), hafnium (Hf), and aluminum (Al) as the stabilizer.

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), One or more of dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), gadolinium (Gd), cerium (Ce), zirconium (Zr) You may have seeds.

For example, as an oxide semiconductor, indium oxide, tin oxide, and zinc oxide, which are oxides of a single metal, In—Zn oxide, Sn—Zn oxide, Al—Zn, which are oxides of a binary metal, Oxide, Zn—Mg oxide, Sn—Mg oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide that is an oxide of a ternary metal, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn Oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Sm—Zn oxide, In -Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, n-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn -Based oxides, In-Sn-Ga-Zn-based oxides that are oxides of quaternary metals, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn- An Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metals other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1). / 5), In: Ga: Zn = 3: 2: 1 (= 1/2: 1/3: 1/6) atomic ratio In—Ga—Zn-based oxides and oxides in the vicinity of the composition thereof. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or an oxide in the vicinity of the composition. Use it.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C, (A + B + C = 1) is the vicinity of r of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ It refers to meet the r ^2. For example, r may be 0.05. The same applies to other oxides.

However, the present invention is not limited to these, and a material having an appropriate composition may be used according to required characteristics (for example, mobility, threshold value, variation, etc.). In order to obtain the required characteristics, it is preferable that the carrier concentration, the impurity element concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic bond distance, the density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

An oxide semiconductor film is in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like. Preferably, the oxide semiconductor film is a CAAC-OS film (C Axis Crystallized Oxide Semiconductor) film.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

In the crystal part included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. Further, when an impurity or the like is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

By using the CAAC-OS film, change in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced. Thus, a highly reliable transistor can be obtained.

Note that the semiconductor device of this embodiment may use an oxide semiconductor layer having different crystallinity depending on a region. For example, a region where a channel is formed has high crystallinity, and a film with low crystallinity may be used in other regions. Specifically, the channel formation region is a CAAC-OS film, and the other regions can have an amorphous structure.

Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

Note that as an example, in the case where the oxide semiconductor film is formed using an In—Zn-based metal oxide, the composition ratio of the target in terms of the number of atoms is In / Zn = 1 to 100, preferably In / Zn = 1 to 1. 20, More preferably, In / Zn = 1 to 10. By setting the atomic ratio of Zn within a preferable range, the field effect mobility can be improved. Here, in order to include oxygen excessively, it is preferable that the atomic ratio of the metal oxide, In: Zn: O = X: Y: Z, is Z> 1.5X + Y.

In the case where an In—Ga—Zn-based oxide is formed as the oxide semiconductor film by a sputtering method, the atomic ratio is preferably In: Ga: Zn = 1: 1: 1, 4: 2: 3, 3: 1. : 2, 1: 1: 2, 2: 1: 3, or 3: 1: 4 In—Ga—Zn—O target is used. When an oxide semiconductor film is formed using the In—Ga—Zn—O target having the above-described atomic ratio, a polycrystalline film or a CAAC-OS film can be easily formed.

In the case where an In—Sn—Zn-based oxide is formed as the oxide semiconductor film by a sputtering method, the atomic ratio is preferably In: Sn: Zn = 1: 1: 1, 2: 1: 3, 1 : In: Sn—Zn—O target represented by 2: 2 or 20:45:35 is used. When the oxide semiconductor layer is formed using the In—Sn—Zn—O target having the above atomic ratio, a polycrystalline film or a CAAC-OS film can be easily formed.

Here, the relative density of the target is 90% to 100%, preferably 95% to 99.9%. By increasing the filling rate of the target, the formed oxide semiconductor layer can be made dense.

Note that a metal oxide that can be used for the oxide semiconductor film has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. In this manner, when a metal oxide having a wide band gap is used, the off-state current of the transistor can be reduced.

The oxide semiconductor film may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor film is a stack of a first oxide semiconductor film and a second oxide semiconductor film, and the first oxide semiconductor film and the second oxide semiconductor film have different metal oxide compositions. May be used. For example, a ternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, the first oxide semiconductor film and the second oxide semiconductor film may both be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 2: 1: 3. It is good.

At this time, the In and Ga contents in the oxide semiconductor film on the side close to the gate electrode (channel side) of the first oxide semiconductor film and the second oxide semiconductor film are preferably In> Ga. The content ratio of In and Ga in the oxide semiconductor film far from the gate electrode (back channel side) is preferably In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor film and the second oxide semiconductor film. In other words, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS film may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress of the oxide semiconductor layer and external stress are relieved, so that the transistor Variation in characteristics of the transistor can be reduced, and the reliability of the transistor can be further improved.

On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, it is preferable to use a crystalline oxide semiconductor such as a CAAC-OS film as the channel-side oxide semiconductor film.

Alternatively, the oxide semiconductor film may have a stacked structure of three or more layers, and a structure in which an amorphous oxide semiconductor layer is sandwiched between a plurality of crystalline oxide semiconductor layers. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the oxide semiconductor layer has a stacked structure of a plurality of layers can be used in appropriate combination.

Note that the number of alkali metals and alkaline earth metals in the oxide semiconductor layer is preferably small, and the concentration thereof is preferably 1 × 10 ¹⁸ atoms / cm ³ or more, more preferably 2 × 10 ¹⁶ atoms / cm ³ or less. And This is because an alkali metal and an alkaline earth metal may generate carriers when combined with an oxide semiconductor, which causes an increase in off-state current of the transistor.

The thickness of the oxide semiconductor film is 1 nm to 100 nm, preferably 1 nm to 35 nm.

The oxide semiconductor film is preferably formed by a sputtering method with a substrate heating temperature of 100 ° C. to 600 ° C., preferably 150 ° C. to 550 ° C., more preferably 200 ° C. to 500 ° C. in an oxygen gas atmosphere. . The higher the substrate heating temperature during film formation, the lower the impurity element concentration of the obtained oxide semiconductor film. In addition, the atomic arrangement in the oxide semiconductor film is aligned and the density is increased, so that a polycrystalline film or a CAAC-OS film is easily formed.

Further, even when a film is formed in an oxygen gas atmosphere, a polycrystalline film or a CAAC-OS film can be easily formed because an excess atom such as a rare gas is not included. However, a mixed atmosphere of oxygen gas or a rare gas such as argon may be used. In that case, the proportion of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more. Note that argon and oxygen used for forming the oxide semiconductor film preferably do not contain water, hydrogen, or the like. For example, it is preferable that the purity of argon is 9N (dew point −121 ° C., water 0.1 ppb, hydrogen 0.5 ppb), and the purity of oxygen is 8N (dew point −112 ° C., water 1 ppb, hydrogen 1 ppb).

In this embodiment mode, an sputtering method is used in an atmosphere where the flow ratio of argon to oxygen is 2: 1, and the atomic ratio is in the vicinity of In: Ga: Zn = 3: 1: 2. A system oxide film is formed to a thickness of 20 nm.

Since an amorphous oxide semiconductor can obtain a flat surface relatively easily, a transistor using the oxide semiconductor can reduce interface scattering of carriers (electrons) during operation, and is relatively easy and relatively high. Mobility can be obtained.

In addition, in an oxide semiconductor having crystallinity, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Note that Ra is a three-dimensional extension of the centerline average roughness defined in JIS B601 so that it can be applied to a surface. “A value obtained by averaging the absolute values of deviations from a reference surface to a specified surface” "And is defined by the following equation.

In the above, S ₀ is surrounded by four points represented by the measurement plane (coordinates (x ₁ , y ₁ ) (x ₁ , y ₂ ) (x ₂ , y ₁ ) (x ₂ , y ₂ )). (Rectangular region) indicates the area, and Z ₀ indicates the average height of the measurement surface. Ra can be evaluated with an atomic force microscope (AFM). The measurement surface is a surface indicated by all measurement data, is composed of three parameters (x, y, z), and is represented by Z = f (x, y).

The reference plane is a plane parallel to the xy plane at the average height of the designated plane. In other words, the average value of the height of the specific surface when the Z _0, the height of the reference surface is also represented by Z _0.

In order to planarize the formation surface of the oxide semiconductor film, a base insulating layer may be provided over the substrate, and the planarization treatment may be performed on the base insulating layer before the oxide semiconductor layer is formed. For the base insulating layer, a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. Note that when the base insulating layer is formed by a sputtering method, impurity elements such as hydrogen can be reduced.

In this manner, in the region where the channel of the oxide semiconductor layer is formed, planarization treatment may be performed so that the average surface roughness of the base insulating layer is 0.3 nm or less. The planarization treatment may be performed before formation of the oxide semiconductor film.

For example, dry etching or the like may be performed as the planarization process. Here, as an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride may be used.

Further, it is preferable that hydrogen contained in the oxide semiconductor film be as small as possible. This hydrogen may be contained as a hydrogen molecule, water, a hydroxyl group, or other hydride in addition to a hydrogen atom. Therefore, heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) included in the oxide semiconductor layer is preferably performed. The temperature of the heat treatment is 300 ° C. or more and 700 ° C. or less, or less than the strain point of the substrate. The heat treatment can be performed in a reduced pressure atmosphere or an inert atmosphere. Further, the heat treatment may be performed after the oxide semiconductor film is formed and before being processed into an island shape, or may be performed after being processed into an island shape. Further, the heat treatment for dehydration and dehydrogenation may be performed a plurality of times, and may be combined with other heat treatments.

The heat treatment is preferably performed by performing a heat treatment in a reduced pressure atmosphere or an inert atmosphere and then switching to an oxidizing atmosphere while maintaining the temperature. When heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, the concentration of impurities (for example, hydrogen) in the oxide semiconductor layer can be reduced, but oxygen deficiency may occur at the same time. The generated oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere.

By performing heat treatment on the oxide semiconductor film, an impurity element such as hydrogen in the film can be extremely small. As a result, the field effect mobility of the transistor can be increased to near the ideal field effect mobility.

In the base insulating layer in contact with the oxide semiconductor layer, oxygen in an amount exceeding the stoichiometric composition ratio is preferably present in the layer (in the bulk). For example, when a silicon oxide layer is used as the base insulating film, SiO _{2 (2 + α)} (where α> 0) is set.

As the base insulating layer, an oxide insulating layer such as silicon oxide, gallium oxide, aluminum oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, or tantalum oxide is preferably used. In addition, these compounds can be used in the form of a single layer structure or a laminated structure of two or more layers. When a stacked structure is used, for example, a silicon oxide film formed by a CVD method may be used for a base insulating layer in contact with a substrate, and a silicon oxide film formed by a sputtering method may be used for a base insulating layer in contact with an oxide semiconductor layer. . The insulating layer in contact with the oxide semiconductor layer is an oxide insulating layer with a reduced hydrogen concentration, so that diffusion of hydrogen to the oxide semiconductor layer is suppressed, and in addition, a base insulating layer is added to oxygen defects in the oxide semiconductor layer. Since oxygen is supplied from the oxide insulating layer, the electric characteristics of the transistor can be improved.

In addition, since the gate insulating film is in contact with the oxide semiconductor layer similarly to the base insulating layer, it is preferable that an amount of oxygen exceeding the stoichiometric composition ratio exists in the layer (in the bulk).

A heat treatment may be performed after an aluminum oxide film is formed as the planarization insulating layer over the oxide semiconductor layer. The aluminum oxide film has a function of preventing water (including hydrogen) from entering the oxide semiconductor layer and a function of preventing release of oxygen from the oxide semiconductor layer. Therefore, when the oxide semiconductor layer or the insulating layer in contact with the oxide semiconductor layer has an oxygen-excess region, heat treatment is performed in a state where the aluminum oxide film is provided, so that the oxide semiconductor layer or the insulating layer is oxidized. At the interface of the physical semiconductor layer, at least one region where oxygen exceeding the stoichiometric composition ratio of the film exists (also referred to as an oxygen excess region) can be provided.

By applying the oxide semiconductor described in this embodiment to the semiconductor device described in Embodiment 1, a transistor with excellent on-state characteristics and low leakage current can be obtained.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, a transistor in which the oxide semiconductor described in Embodiment 2 is used for a semiconductor layer is used, a memory content can be held even in a state where power is not supplied, and the number of writing operations is not limited. An example of the apparatus will be described with reference to the drawings. Note that the semiconductor device in this embodiment is configured using the transistor described in Embodiment 1 as the transistor 162.

FIG. 5 illustrates an example of a structure of a semiconductor device. 5A is a cross-sectional view of the semiconductor device, FIG. 5B is a top view of the semiconductor device, and FIG. 5C is a circuit diagram of the semiconductor device. Here, FIG. 5A corresponds to a cross section taken along lines CD and EF in FIG. Note that in FIG. 5B, some components of the semiconductor device illustrated in FIG. 5A are omitted for clarity.

The semiconductor device illustrated in FIGS. 5A and 5B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. . As the transistor 162, the transistor in which the oxide semiconductor layer is used for the semiconductor layer described in Embodiment 3 can be used.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. Further, the technical essence of the disclosed invention is that an oxide semiconductor is used for the transistor 162 in order to retain information; therefore, specific materials of the semiconductor device such as a material used for the semiconductor device and a structure of the semiconductor device are included. The configuration need not be limited to that shown here.

A transistor 160 in FIG. 5A is provided over the channel formation region 116, the channel formation region 116 provided in the substrate 100, the semiconductor layer including the impurity element region 120 provided so as to sandwich the channel formation region 116. The gate insulating layer 108, the gate electrode layer 110 provided on the gate insulating layer 108, the insulating layer 130 on the impurity element region 120, and the opening provided in the insulating layer 130 are formed. A conductive layer 112a and a conductive layer 112b in contact with each other.

An insulating layer 135 is provided over the insulating layer 130. The insulating layer 135 includes the conductive layer 114c, the conductive layer 114a, the conductive layer 114b, and the same layers that are in contact with the gate electrode layer 110, the conductive layer 112a, and the conductive layer 112b, respectively. A wiring layer 114d provided in the layer is formed.

An insulating layer 140 is provided over the insulating layer 135, and a conductive layer 115 in contact with the conductive layer 114c is provided in the insulating layer 140. The conductive layer 115 is in contact with the electrode layer 142 a that serves as the source electrode layer or the drain electrode layer of the transistor 162.

Note that in order to achieve high integration, it is preferable that the transistor 160 have no sidewall insulating layer as illustrated in FIG. On the other hand, in the case where importance is attached to the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode layer 110 to form the impurity element region 120 including regions having different impurity element degrees.

Planarization treatment is preferably performed on the top surface of the insulating layer 140. In this embodiment, the oxide semiconductor layer 144 is formed over the insulating layer 140 which is sufficiently planarized by polishing treatment (eg, CMP treatment) (preferably, the average surface roughness of the upper surface of the insulating layer 140 is 0.15 nm or less). Form.

A transistor 162 illustrated in FIG. 5A is a transistor in which the oxide semiconductor described in Embodiment 2 is used for a channel formation region. Here, the oxide semiconductor layer 144 included in the transistor 162 is preferably highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

The transistor 162 has a structure in which a conductive film, a first protective film, and a resist film are sequentially stacked over the gate electrode layer 148 and the sidewall insulating layers 136a and 136b in the manufacturing process described in Embodiment 1; In this semiconductor device, a resist mask is formed in a self-aligning manner by performing anisotropic etching on the resist film, and the shape of the resist mask is transferred to the source electrode layer and the drain electrode layer.

Thus, in the transistor 162, the distance between the electrode layer 142a functioning as a source or drain electrode layer, a region where the electrode layer 142b and the oxide semiconductor layer 144 are in contact (contact region), and the gate electrode layer 148 is the sidewall insulating layer 136a. In addition, the distance is easily determined by the sidewall insulating layer 136b. Accordingly, the region where the electrode layers 142a and 142b and the oxide semiconductor layer 144 are in contact (contact region) and the resistance between the gate electrode layer 148 are reduced, so that the on-state characteristics of the transistor 162 can be improved.

In addition, a protective film that can have an etching selectivity with respect to each film is formed between the resist mask and the conductive film. Therefore, the conductive film can be etched using the protective film as a mask even when the resist mask is thinned as the semiconductor device is miniaturized. In the etching of the conductive film, etching is performed using a protective film having a selection ratio with respect to the conductive film as a mask, so that the mask is not removed before the etching step is completed, and the etching can be performed accurately. Accordingly, variation in shape and characteristics of the transistor can be reduced, and defects caused by variation in shape and characteristics are less likely to occur, so that the yield of the semiconductor device can be improved.

Note that in this embodiment, the protective film 146a and the protective film 146b are described as insulating layers.

An insulating layer 145 is provided as a single layer or a stacked layer over the transistor 162. An insulating layer 150 is provided over the insulating layer 145, and a conductive layer 153 is provided in a region overlapping with the electrode layer 142a of the transistor 162 of the insulating layer 150. The electrode layer 142a, the protective film 146a, The capacitor 164 includes the insulating layer 130 and the conductive layer 153. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 164 and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

An insulating layer 155 is provided over the transistor 162 and the capacitor 164. Over the insulating layer 155, the transistor 162 and a wiring 158 for connecting another transistor are provided. The wiring 158 is electrically connected to an electrode layer 142 b that serves as a drain electrode layer of the transistor 162.

Note that the electrical connection between the electrode layer 142b and the wiring 158 may be performed by directly connecting the electrode layer 142b and the wiring 158. Alternatively, an electrode may be provided in an insulating film between the electrode layer 142b and the wiring 158, and the electrode may be connected. You may go through. A plurality of electrodes may be interposed therebetween. In FIG. 5A, the wiring 158 is an electrode through the conductive layer 152, the conductive layer 154, and the conductive layer 156 formed in openings formed in the insulating layer 155, the insulating layer 150, the insulating layer 145, the protective film 146b, and the like. It is electrically connected to the layer 142b.

As in the oxide insulating layer 408 described in Embodiment 1, the insulating layer 145 is formed using a material that can be etched under the same conditions as the protective film 146b and the protective film 146b, so that an opening in which the conductive layer 152 is provided is formed. In this case, an opening can be formed in the insulating layer 145 and the protective film 146b by one etching, which is preferable.

5A and 5B, the transistor 160 and the transistor 162 are provided so that at least part of them overlaps with each other, and the source region or the drain region of the transistor 160 and the oxide semiconductor layer 144 are provided. It is preferable that a part is provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided so as to overlap at least partly with the gate electrode layer 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Next, an example of a circuit configuration corresponding to FIGS. 5A and 5B is illustrated in FIG.

In FIG. 5C, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode layer of the transistor 160 are electrically connected. Connected. In addition, the third wiring (3rd Line) and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode layer of the transistor 162 are connected. Are electrically connected. One of a gate electrode layer of the transistor 160 and a source electrode layer or a drain electrode layer of the transistor 162 is electrically connected to the other electrode of the capacitor 164, and a fifth wiring (5th Line) and a capacitor The other of the 164 electrodes is electrically connected.

In the semiconductor device illustrated in FIG. 5C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode layer of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, predetermined charge is supplied to the gate electrode layer of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off and the transistor 162 is turned off, whereby the charge given to the gate electrode layer of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge given to the gate electrode layer of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, according to the amount of charge held in the gate electrode layer of the transistor 160, The second wiring takes different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold value V _{th_H in the} case where a high-level charge is applied to the gate electrode layer of the transistor 160 is a low-level charge applied to the gate electrode layer of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L in the} case of Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode layer of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned off regardless of the state of the gate electrode layer, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively} , a potential that turns on the transistor 160 regardless of the state of the gate electrode layer, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a semiconductor device which uses the transistor described in Embodiment 1 and can hold stored data even in a state where power is not supplied and has no limit on the number of writing times is described in Embodiment 3. A structure different from the illustrated structure will be described with reference to FIGS. Note that the semiconductor device of this embodiment is formed using a transistor in which the oxide semiconductor layer described in Embodiment 3 is used for the semiconductor layer as the transistor 162. Any structure of the transistor described in Embodiment 1 can be used as the transistor 162.

6A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 6B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 6A will be described, and then the semiconductor device illustrated in FIG. 6B will be described below.

6A, the bit line BL and the source or drain electrode layer of the transistor 162 are electrically connected, and the word line WL and the gate electrode layer of the transistor 162 are electrically connected. The source or drain electrode layer of the transistor 162 and the first terminal of the capacitor 254 are electrically connected.

The transistor 162 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG. 6A is described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or charge accumulated in the capacitor) can be held for a long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. It can be seen that (= CB × VB0 + C × V1) / (CB + C) is higher than the potential of the bit line BL when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 6A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 6B is described.

A semiconductor device illustrated in FIG. 6B includes a memory cell array 251a and a memory cell array 251b each including a plurality of memory cells 250 illustrated in FIG. 6A as a memory circuit in an upper portion, and a memory cell array 251 (memory cell array) in a lower portion. 251a and the memory cell array 251b) have a peripheral circuit 253 necessary for operating. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 6B, the peripheral circuit 253 can be provided directly below the memory cell array 251 (the memory cell array 251a and the memory cell array 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuit, drive circuit, etc.) that require high-speed operation can be suitably realized by the transistor.

Note that although the semiconductor device illustrated in FIG. 6B illustrates a structure in which two memory cell arrays 251 (a memory cell array 251a and a memory cell array 251b) are stacked, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of a semiconductor device applicable to the memory cell 250 illustrated in FIG. 6 is described with reference to FIGS. 7B is a top view of the semiconductor device, and FIG. 7A is a cross-sectional view taken along dashed-dotted lines GH and IJ in FIG. 7B. Note that in FIG. 7B, some components of the semiconductor device illustrated in FIG. 7A are omitted for clarity.

The memory cell illustrated in FIG. 7 includes a transistor 162 in which a channel is formed in an oxide semiconductor, and a capacitor 254. Note that the structure of the transistor 162 is similar to that of the transistor 162 included in the semiconductor device illustrated in FIG. 5, and thus detailed description thereof is omitted.

Note that in this embodiment, the protective film 146a and the protective film 146b are described as conductive layers.

In FIG. 7, the capacitor 254 includes an electrode layer 142a, a protective film 146a, an insulating layer 145, and a conductive layer 153. That is, the electrode layer 142 a and the protective film 146 a function as one electrode of the capacitor 254, and the conductive layer 153 functions as the other electrode of the capacitor 254.

The conductive layer 152, the conductive layer 154, the conductive layer 156, the wiring 158, and the layers electrically connected to the electrode layer 142b and the protective film 146b illustrated in FIG. 7 are formed as the bit lines BL illustrated in FIG. Function. In addition, the layer electrically connected to the gate electrode layer 148 illustrated in FIG. 7 functions as the word line WL illustrated in FIG.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

As shown in FIG. 6, since the memory cell array 251 including the transistor 162 and the capacitor 254 are densely stacked so as to overlap with each other, the area occupied by the semiconductor device can be further reduced. Can be achieved.

As described above, the plurality of memory cells formed in multiple layers in the upper portion are formed using transistors including an oxide semiconductor. Since a transistor including a highly purified and intrinsic oxide semiconductor has a small off-state current, stored data can be retained for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

The above transistor has high on-characteristics, and can operate at high speed and respond at high speed. In addition, miniaturization can be achieved by using a mask formed in a self-aligned manner. Therefore, a high-performance and highly reliable semiconductor device can be provided by using the transistor.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, a structure of a CPU which is one of signal processing circuits according to one embodiment of the present invention will be described.

  FIG. 8 shows the configuration of the CPU of this embodiment. The CPUs shown in FIG. / F9920. The ALU is an Arithmetic logic unit, the Bus / I / F is a bus interface, and the ROM / I / F is a ROM interface. The ROM 9909 and the ROM • I / F9920 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 9 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

  Instructions input to the CPU via the Bus I / F 9908 are input to the Instruction Decoder 9903, decoded, and then input to the ALU Controller 9902, Interrupt Controller 9904, Register Controller 9907, and Timer Control 9905.

  The ALU / Controller 9902, the Interrupt / Controller 9904, the Register / Controller 9907, and the Timing / Controller 9905 perform various controls based on the decoded instructions. Specifically, the ALU / Controller 9902 generates a signal for controlling the operation of the ALU 9901. The Interrupt Controller 9904 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The Register Controller 9907 generates an address of the Register 9906, and reads and writes the Register 9906 according to the state of the CPU.

  The Timing Controller 9905 generates signals that control the operation timings of the ALU 9901, ALU Controller 9902, Instruction Decoder 9903, Interrupt Controller 9904, and Register Controller 9907. For example, the Timing Controller 9905 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and inputs the clock signal CLK2 to the various circuits.

  In the CPU of this embodiment, the register 9906 is provided with a semiconductor memory device having the structure described in Embodiments 3 and 4. In accordance with an instruction from the ALU 9901, the Register Controller 9907 can stop the supply of the power supply voltage without saving and restoring data in the semiconductor memory device included in the Register 9906.

  In this manner, even when the operation of the CPU is temporarily stopped and the supply of the power supply voltage is stopped, the data signal can be held and power consumption can be reduced. Specifically, for example, the CPU can be stopped while the user of the personal computer stops inputting information to an input device such as a keyboard, thereby reducing power consumption.

  In this embodiment, the CPU has been described as an example. However, the signal processing circuit of the present invention is not limited to the CPU, and can be applied to LSIs such as a microprocessor, an image processing circuit, a DSP, and an FPGA.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices. Electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, audio Examples include a playback device, a gaming machine (such as a pachinko machine or a slot machine), and a game housing.

FIG. 9 shows a specific example of an electronic device. 9A and 9B illustrate a tablet terminal that can be folded. In FIG. FIG. 9A illustrates an open state in which the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, and a fastener 9033. And an operation switch 9038.

The semiconductor device described in the above embodiment can be used for the display portion 9631a and the display portion 9631b, so that a highly reliable tablet terminal can be provided. Further, the memory device described in the above embodiment may be applied to the semiconductor device in this embodiment.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. Note that in the display portion 9631a, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown as an example; however, the structure is not limited thereto. The entire surface of the display portion 9631a can display keyboard buttons to serve as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 9A illustrates an example in which the display areas of the display portion 9631b and the display portion 9631a are the same, but there is no particular limitation, and one size may be different from the other size, and the display quality may be different. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 9B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar battery 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that FIG. 9B illustrates a structure including a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 9A and 9B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge / discharge control circuit 9634 illustrated in FIG. 9B will be described with reference to a block diagram in FIG. FIG. 9C illustrates the solar cell 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are illustrated. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described. The power generated by the solar battery is boosted or lowered by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off SW1 and turning on SW2.

Note that the solar cell 9633 is described as an example of the power generation unit, but is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). There may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

100 Substrate 108 Gate insulating layer 110 Gate electrode layer 112a Conductive layer 112b Conductive layer 114a Conductive layer 114b Conductive layer 114c Conductive layer 114d Wiring layer 115 Conductive layer 116 Channel formation region 120 Impurity element region 130 Insulating layer 135 Insulating layer 136a Side wall insulating layer 136b Sidewall insulating layer 140 Insulating layer 142a Electrode layer 142b Electrode layer 144 Oxide semiconductor layer 145 Insulating layer 146a Protective film 146b Protective film 148 Gate electrode layer 150 Insulating layer 152 Conductive layer 153 Conductive layer 154 Conductive layer 155 Insulating layer 156 Conductive layer 158 Wiring 160 transistor 162 transistor 164 capacitor element 250 memory cell 251 memory cell array 251a memory cell array 251b memory cell array 253 peripheral circuit 254 capacitor element 400 substrate 401 gate electrode layer 4 2 gate insulating layer 403 semiconductor layer 405a source electrode layer 405b drain electrode layer 407a protective film 407b protective film 408 oxide insulating layer 409a wiring layer 409b wiring layer 412a side wall insulating layer 412b side wall insulating layer 413 insulating layer 415 conductive film 416 protective film 417 Resist film 418 Resist mask 420 Transistor 430 Transistor 436 Base insulating layer 440 Transistor 450 Transistor 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9630 Housing 9631 Display portion 9631a Display portion 9631b Display portion 9632a Region 9632b Region 9633 Solar cell 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DCDC Converter 9537 Converter 9638 Operation Key 9539 Down 9900 board 9901 ALU
9902 ALU Controller
9903 Instruction Decoder
9904 Interrupt Controller
9905 Timing Controller
9906 Register
9907 Register Controller
9908 Bus I / F
9909 ROM
9920 ROM ・ I / F

Claims (5)

Forming a semiconductor layer,
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
Forming a sidewall insulating layer having a region covering a side surface of the gate electrode layer;
Forming a conductive film having a region covering the semiconductor layer, the gate insulating layer, the gate electrode layer, and the sidewall insulating layer;
Forming a first protective film on the conductive film;
Forming a resist film on the first protective film;
Performing a first etching on the resist film to form a resist mask in which a region overlapping the gate electrode layer of the resist film is removed;
Performing a second etching on the first protective film using the resist mask to form a second protective film in which a region overlapping the gate electrode layer of the first protective film is removed;
The semiconductor device has a source electrode layer and a drain electrode layer formed by performing third etching on the conductive film using the second protective layer as a mask to remove a region of the conductive film that overlaps with the gate electrode layer. Manufacturing method. In claim 1,
The semiconductor layer is a method for manufacturing a semiconductor device including an oxide semiconductor. In claim 1 or 2 ,
Forming an oxide insulating layer over the source electrode layer, the drain electrode layer, the second protective film, the gate electrode layer, and the sidewall insulating layer;
Wherein the oxide insulating layer and the second protective film, by performing the fourth etching to form a first opening reaching the source electrode layer, and a second opening reaching the drain electrode layer,
In the fourth etching, a method for manufacturing a semiconductor device in which an etching rate of the oxide insulating layer and the second protective film is higher than an etching rate of the source electrode layer and the drain electrode layer. A semiconductor layer on the substrate;
A gate insulating layer on the semiconductor layer;
A gate electrode layer on the gate insulating layer;
A sidewall insulating layer having a region covering a side surface of the gate electrode layer;
A source electrode layer having a region in contact with the semiconductor layer , a region in contact with a side surface of the gate insulating layer, and a region in contact with a side surface of the sidewall insulating layer ;
A drain electrode layer having a region in contact with the semiconductor layer, a region in contact with a side surface of the gate insulating layer, and a region in contact with a side surface of the sidewall insulating layer ;
A protective film of the source electrode layer and the drain electrode layer,
An oxide insulating layer on the source electrode layer, on the drain electrode layer, on the protective film, on the gate electrode layer, and on the sidewall insulating layer;
The oxide insulating layer and the protective film include an opening reaching the source electrode layer or the drain electrode layer,
Each of the source electrode layer and the drain electrode layer may include a lower portion in the side in contact with the sidewall insulating layer, and a top end in the side in contact with the protective film,
The upper end is in contact with the end of the protective film,
The lower end portion and the upper end portion are semiconductor devices having different heights from the substrate . In claim 4 ,
The semiconductor layer includes a semiconductor device including an oxide semiconductor.

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