JP5956731B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory element that performs storage by injecting electrons into a floating gate, and more particularly to reduction of power consumption during erasure.

The market for nonvolatile memories that can electrically rewrite data and store data even when the power is turned off is expanding. The nonvolatile memory has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is characterized in that a region capable of accumulating charges for a long period is provided on the channel formation region. This charge storage region is formed on an insulating layer and is also called a floating gate because it is isolated from the surroundings. Since the floating gate is surrounded by an insulator and is electrically insulated from the surroundings, the floating gate has a characteristic of continuing to hold the charge when the charge is injected into the floating gate. On the floating gate, a gate electrode called a control gate is further provided via an insulating layer. The control gate is distinguished from the floating gate because a predetermined voltage is applied when data is written or read.

A so-called floating gate type nonvolatile memory having such a structure has a mechanism for storing data by electrically controlling charge injection into the floating gate and discharge of the charge from the floating gate. Specifically, charge injection into the floating gate (hereinafter referred to as writing) and charge emission from the floating gate (hereinafter referred to as erasing) are high between the semiconductor layer in which the channel formation region is formed and the control gate. This is done by applying a voltage. At this time, it is said that a Fowler-Nordheim (FN) tunnel current flows through the insulating layer on the channel formation region. Thus, the insulating layer is also called a tunnel insulating layer.

When data is stored using this mechanism, the voltage required for erasing is determined from the difference in work function between the semiconductor layer and the floating gate. The work function varies depending on the material. That is, the work function is determined by the material of the semiconductor layer and the floating gate.

In general, a polycrystalline silicon material is used as a floating gate material. On the other hand, a method using a metal material is also taken from the viewpoint of impurity diffusion countermeasures (for example, Patent Document 1). By providing the floating gate with a metal material, there is an effect that it is easy to manufacture by a low temperature process (600 ° C. or less). For example, in order to reduce power consumption or circuit area and improve productivity in a low-temperature process, the floating gate is provided with a material different from that of a semiconductor film (silicon), for example, a metal such as tungsten, tantalum nitride, or titanium nitride. A technique is disclosed (Patent Document 2). In addition, a technique using titanium or titanium nitride as a floating gate is disclosed in order to provide a semiconductor device having an EEPROM or an EPROM memory cell having excellent characteristics (write characteristics, read characteristics, and erase characteristics) ( Patent Document 3).

Japanese Patent Laid-Open No. 10-233505 JP 2009-040663 A Japanese Patent Laid-Open No. 9-036265

In a memory transistor using n-type silicon as a semiconductor film, when the floating gate is provided with a material having a work function higher than that of the semiconductor film, such as a metal material, the barrier height of the tunnel insulating film on the floating gate side is the semiconductor film. Therefore, in the erasing method using the FN tunnel current, the erasing voltage becomes high.

Therefore, the erase voltage can be lowered by fabricating the floating gate with titanium having a small work function. However, because of the high reducibility of titanium, the tunnel insulating layer is eroded by titanium, and the thickness of the tunnel insulating film is reduced. Since it becomes thinner than the film thickness, it is difficult to accurately control the film thickness. Therefore, there is a problem that writing / erasing occurs even with a small voltage, and reliability such as resistance to erroneous rewriting cannot be secured.

Titanium nitride can be used for the floating gate in order to suppress the reduction of titanium. However, when titanium nitride having a stoichiometric composition is used, the erase voltage rises and the power consumption increases. is there.

An object of the present invention is to provide a non-volatile semiconductor memory element with low power consumption and high resistance to erroneous rewriting.

The gist of the present invention is to solve such a problem even when titanium nitride is used for the floating gate, by shifting the composition ratio of titanium and nitrogen from the stoichiometric composition ratio.

One embodiment of a semiconductor memory device of the present invention includes a semiconductor film having a channel formation region, and a floating gate provided over the channel formation region of the semiconductor film with an insulating film interposed therebetween. It is characterized by being titanium nitride containing more titanium atoms than nitrogen atoms.

One of the semiconductor memory devices of the present invention includes a semiconductor film having a channel formation region, and a floating gate provided over the channel formation region of the semiconductor film via an insulating film. The material of the floating gate is a titanium composition. The titanium nitride is characterized in that the ratio is 56 atomic% or more and 75 atomic% or less in atomic percentage.

The floating gate is made of titanium nitride, so that the number of titanium atoms per unit volume is larger than the number of nitrogen atoms. Preferably, the titanium composition ratio of titanium nitride is set to 56 atomic% or more and 75 atomic% or less to reduce consumption. It is possible to provide a nonvolatile semiconductor memory element that achieves power consumption and has high resistance to erroneous rewriting.

1 is a diagram showing an example of a semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a semiconductor memory device of the present invention. FIG. 6 is a graph showing the relationship between the titanium composition ratio and the write / erase voltage in the memory transistor of the semiconductor memory device of the present invention. FIG. 6 is a graph showing the relationship between the titanium composition ratio and the error rewrite resistance in the memory transistor of the semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be implemented in many different modes, and that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings in this specification, the same portions or portions having similar functions are denoted by the same reference numerals, and description thereof may be omitted.

In this embodiment, a semiconductor memory device including a transistor-type semiconductor memory element (also referred to as a “memory transistor”) and a manufacturing method thereof will be described with reference to drawings. In the following description, “write voltage” and “erase voltage” refer to absolute values of voltage unless otherwise specified.

In this specification, the atomic percentage indicates the ratio of the number of atoms of interest when the number of all atoms contained in a unit volume is 100, and is expressed as atomic% or at. It shall be expressed in%.

If the floating gate is made of titanium with a low work function, the erasing voltage can be lowered. However, because titanium is highly reducible, the tunnel insulating layer is eroded by titanium, ensuring reliability such as resistance to erroneous rewriting. It becomes impossible. Therefore, titanium nitride is used for the floating gate. However, when titanium nitride having a stoichiometric composition is used, the erasing voltage rises and the power consumption increases. Therefore, the gist of the present invention is to shift the composition ratio of titanium and nitrogen from the stoichiometric composition ratio in order to reduce the voltage consumption while ensuring reliability, and the number of titanium atoms per unit volume is greater than the number of nitrogen atoms. Titanium nitride, which is also contained in a large amount, is used for the floating gate.

(Embodiment 1)
In this embodiment, a structure of a semiconductor memory device will be described.

The semiconductor memory device described in this embodiment includes a semiconductor film 102 including a channel formation region 102a, a first insulating film 103 or a first insulating film 203 formed over the channel formation region 102a of the semiconductor film 102, The memory transistor includes the floating gate 104, the second insulating film 105 or the second insulating film 205, and the control gate 106 (see FIG. 1).

The floating gate 104 is formed of titanium nitride. It is important that the titanium nitride used here contains more titanium atoms per unit volume than nitrogen atoms. Preferably, the titanium composition ratio in titanium nitride is 56 atomic% or more and 75 atomic% or less.

FIG. 5 shows a comparison of floating gate materials of write voltage and erase voltage in memory transistors manufactured in Example 1 and Comparative Example described later. Here, the write voltage is a positive voltage applied to the control gate 106 in order to set the threshold voltage of the memory transistor to 4V. The erase voltage is a negative voltage applied to the control gate 106 in order to set the threshold voltage of the memory transistor to 0V. The time for applying the write voltage and the time for applying the erase voltage were both set to 500 μsec. FIG. 5 shows that the erase voltage is large when the titanium composition ratio is 46 atomic% or less, and the erase voltage is small when the titanium composition ratio is 56 atomic% or more. There was no clear difference in the write voltage depending on the floating gate material. That is, by using titanium nitride having a titanium composition ratio of 56 atomic% or more as a floating gate material, a memory transistor with a low erase voltage can be manufactured.

FIG. 6 shows a comparison of floating gate materials having resistance to erroneous rewriting in memory transistors manufactured in Example 1 and Comparative Example described later. The error rewrite resistance here is a general term for the error write resistance and the error erase resistance, both of which are one of the reliability of the memory transistor, and when the other memory cell is written / erased on the same word line, An index of the small threshold voltage fluctuation of the memory transistor is shown, and the higher the value, the stronger the resistance and the better the memory transistor. Specifically, the erroneous write resistance indicates the ratio of the erroneous write voltage to the above-described write voltage, and the erroneous erase voltage indicates the ratio of the erroneous erase voltage to the above-described erase voltage. Here, the erroneous write voltage is a positive voltage applied to the control gate when the threshold voltage of the memory transistor, which was initially 0 V, is increased to 0.5 V. The voltage application time was 80 sec. The erroneous erasure voltage is a negative voltage applied to the control gate when the threshold voltage of the memory transistor, which was initially 4 V, drops to 2.5 V. The voltage application time was 80 sec. From FIG. 6, it can be seen that when the titanium composition ratio is 88 atomic% or more, the improvement is made as compared with the titanium composition ratio 100 atomic%, but the deterioration of the miswrite resistance starts compared with 75 atomic% or less. On the other hand, it can be seen that when the titanium composition ratio is 75 atomic% or less, the resistance to erroneous rewriting can be secured without any problem. In other words, by using titanium nitride as a floating gate material, and more preferably by setting the titanium composition ratio to 75 atomic% or less, a memory transistor having good miswrite resistance can be manufactured.

In addition, the titanium composition ratio shown in FIGS. 5 and 6 is a value based on the analysis result by the Raman diffusion method (RBS).

Therefore, in the present embodiment, the floating gate 104 is made of titanium nitride, and preferably the titanium composition ratio is 56 atomic% or more and 75 atomic% or less so that the number of titanium atoms per unit volume is larger than the number of nitrogen atoms. By manufacturing with the range of titanium nitride, a memory transistor with low power consumption and high miswrite resistance can be manufactured.

(Embodiment 2)
In this embodiment, a method for manufacturing a memory transistor of a semiconductor memory device will be described with reference to drawings. In the following description, a case where an n-type memory transistor is formed will be described.

First, the semiconductor film 102 is formed over the substrate 100 with the insulating film 101 interposed therebetween (see FIG. 2A).

As the substrate 100, a glass substrate, a metal substrate, a stainless steel substrate, a semiconductor substrate, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like may be used. If such a substrate is used, there is no significant limitation on the area and shape thereof. For example, if a substrate having a side of 1 meter or more and a rectangular shape is used, productivity can be significantly improved.

The insulating film 101 is formed as a single layer or a stacked layer using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). There is no particular limitation on the formation method, and the formation can be performed using a CVD method, a sputtering method, or the like. By providing the insulating film over the substrate 100, the influence of the unevenness of the substrate 100 can be reduced and impurity diffusion from the substrate 100 to the upper element can be prevented.

The semiconductor film 102 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by sputtering, LPCVD, plasma CVD, or the like. As the semiconductor film 102, for example, an amorphous semiconductor film (for example, an amorphous silicon film) or a polycrystalline semiconductor film (for example, a polycrystalline silicon film) may be formed. The polycrystalline semiconductor film can be formed by irradiating an amorphous semiconductor film with laser light, a thermal crystallization method using an RTA or a furnace annealing furnace, or the like.

Alternatively, an SOI (Silicon on Insulator) substrate may be used. By using an SOI substrate, a single crystal semiconductor film (eg, a single crystal silicon film) can be used as the semiconductor film 102. For example, the single crystal semiconductor film can be attached to the substrate 100 by a bonding method such as a smart cut method or an ELTRAN (Epitaxial Layer Transfer) method.

Here, after forming an amorphous silicon film as the semiconductor film 102, the amorphous silicon film is irradiated with laser light to form a polycrystalline silicon film.

Next, an impurity element is introduced into the semiconductor film (see FIG. 2B). In addition, the form which does not introduce | transduce an impurity element here may be sufficient.

Next, a first insulating film 203 is formed over the semiconductor film 102 (see FIG. 2C). The first insulating film 203 can function as a tunnel insulating film in the memory transistor.

The first insulating film 203 includes a film containing silicon oxide or silicon nitride (for example, a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy) (x> y) film, a silicon nitride (SiNx) film, A silicon nitride oxide (SiNxOy) (x> y) film or the like) is formed as a single layer or a stacked layer. The first insulating film 203 can be formed by a CVD method, a sputtering method, or the like. Alternatively, an oxide film may be formed on the surface of the semiconductor layer by performing plasma treatment on the semiconductor layer in an oxygen atmosphere.

Next, a conductive film 204, a second insulating film 205, and a conductive film 206 are sequentially formed over the first insulating film 203 (see FIG. 2D).

As the conductive film 204, a titanium nitride film is formed by a sputtering method or the like. However, the titanium composition ratio is preferably 56 atomic% or more and 75 atomic% or less so that the number of titanium atoms per unit volume is larger than the number of nitrogen atoms by adjusting the nitrogen gas flow rate during formation. A titanium nitride film is formed.

The second insulating film 205 is a film containing a silicon oxide or a silicon nitride (eg, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, or the like) by a sputtering method, a plasma CVD method, or the like. ) In a single layer or a stacked layer. For example, a silicon oxynitride film, a silicon nitride film, and a silicon oxynitride film can be provided in this order.

The conductive film 206 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or a film made of a nitride of these elements (typically, a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) can be used as a single layer or a stacked layer.

Next, the first insulating film 203, the conductive film 204, the second insulating film 205, and the conductive film 206 are selectively etched to form the first insulating film 103, the floating gate 104, the second insulating film 105, and the control. A gate 106 is formed (see FIG. 2E). Note that the first insulating film 203 may be left without being etched (see FIG. 1B).

Next, an impurity element is introduced into the semiconductor film 102 using the remaining stacked structure of the floating gate 104, the second insulating film 105, and the control gate 106 as a mask to form an impurity region 102b (see FIG. 3A).

As the impurity element to be introduced, an n-type impurity element or a p-type impurity element is used. As the n-type impurity element, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an n-type impurity element (eg, phosphorus (P)) is introduced into the semiconductor film 102 in order to manufacture an n-type memory transistor.

Note that the impurity region 102b functions as a source region or a drain region of the memory transistor, and the concentration of the impurity element contained in the impurity region 102b is higher than the concentration of the impurity element contained in the channel formation region 102a.

After that, after an interlayer insulating film 107 is formed, an opening is formed so as to reach the impurity region 102b, and a conductive film 108 is formed (see FIG. 3B). The conductive film 108 functions as a source electrode or a drain electrode in the memory transistor.

Through the above steps, a memory transistor constituting the semiconductor memory device is obtained.

Note that the memory transistor included in the semiconductor memory device described in this embodiment is not limited to the above structure, and an LDD region 102c or 122 may be provided between the channel formation region 102a and the impurity region 102b (see FIG. 1 (C), (D)).

Although this embodiment mode describes the formation of an n-type memory transistor, the present invention is not limited to this, and a p-type memory transistor can be formed in the same manner.
(Embodiment 3)

In this embodiment, application examples of a semiconductor device including the nonvolatile semiconductor memory device described in the above embodiment are described below with reference to drawings.

In addition, the nonvolatile semiconductor memory device of the present invention can be used for electronic devices in various fields equipped with a memory. For example, as an electronic device to which the nonvolatile semiconductor memory device of the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), Plays back recording media such as computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines or electronic books), and image playback devices (specifically DVDs (digital versatile discs)) equipped with recording media And an apparatus provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

7A and 7B show a digital camera. FIG. 7B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter button 2115, and the like. In addition, a nonvolatile memory 2116 that can be taken out is provided, and data captured by the digital camera is stored in the memory 2116. A nonvolatile semiconductor memory device formed using the present invention can be applied to the memory 2116.

FIG. 7C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the memory 2125 and played back. A nonvolatile semiconductor memory device formed using the present invention can be applied to the memory 2125.

FIG. 7D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 7D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the memory portion 2132, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, a NAND nonvolatile memory having a recording capacity of 20 to 200 gigabytes (GB) can be used. In addition, by operating the operation unit 2133, video and audio (music) can be recorded and reproduced. Note that the nonvolatile semiconductor memory device provided in the memory portion 2132 may be removable.

FIG. 7E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a memory portion 2144. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the memory portion 2144, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, a NAND nonvolatile memory having a recording capacity of 20 to 200 gigabytes (GB) can be used. Further, by operating the operation key 2143, video and audio (music) can be recorded and reproduced. Note that the nonvolatile semiconductor memory device provided in the memory portion 2144 may be removable.

As described above, the applicable range of the nonvolatile semiconductor memory device of the present invention is so wide that it can be used for electronic devices in various fields as long as it has a memory.

In this embodiment, a method for manufacturing a memory transistor that actually acquires the write / erase voltage data and the erroneous write tolerance / erase tolerance data shown in FIGS. 5 and 6 will be described with reference to the drawing (FIG. 4). .

First, a glass substrate is used as the substrate 100, and a silicon nitride oxide (SiNxOy, x> y> 0) having a thickness of 50 nm and a silicon oxynitride (SiOxNy, having a thickness of 100 nm) are formed as the insulating film 101 formed over the glass substrate. An insulating film of x> y> 0) was formed by a CVD method.

A semiconductor film 102 was formed using a polycrystalline silicon film over the insulating film 101. The polycrystalline silicon film was formed as follows. First, an amorphous silicon film having a thickness of 66 nm was formed from hydrogen monosilane by a CVD method. Next, heat treatment was performed at 500 ° C. for 1 hour and 550 ° C. for 4 hours to release hydrogen from the amorphous silicon film. The amorphous silicon film was crystallized by irradiating the amorphous silicon film with the second harmonic (wavelength of 532 nm) beam of the YVO4 laser oscillator to form a polycrystalline silicon film. The YVO4 laser oscillator is a semiconductor laser (LD) pumped continuous wave laser oscillator. Then, the polycrystalline silicon film was processed into a desired shape by an etching process to form a semiconductor film 102 (see FIG. 4A).

Next, high-density plasma oxidation treatment was performed on the semiconductor film 102 to form a first insulating film 203 with a thickness of 10 nm over the semiconductor film 102. The first insulating film 203 can function as a tunnel insulating film in the memory transistor.

Next, a titanium nitride film having a thickness of 30 nm was formed on the first insulating film 203 by a sputtering apparatus. The titanium composition ratio of the titanium nitride film to be formed is in the range of 46 atomic% to 88 atomic%. A titanium film having a titanium composition ratio of 100 atomic% was also produced.

A titanium target was used under the conditions of a chamber internal pressure of 0.2 Pa, a DC power source of 12 kW, and a nitrogen gas atmosphere (nitrogen flow rate 50 sccm). The titanium composition ratio of the obtained titanium nitride film was 46 atomic%.

Next, a titanium target was used under the conditions of a chamber internal pressure of 0.2 Pa, a DC power source of 12 kW, and a mixed atmosphere of argon gas and nitrogen gas (argon flow rate 20 sccm, nitrogen flow rate 30 sccm). The titanium composition ratio of the obtained titanium nitride film was 56 atomic%.

Next, a titanium target was used under the conditions of a chamber internal pressure of 0.2 Pa, a DC power source of 12 kW, and a mixed atmosphere of argon gas and nitrogen gas (argon flow rate 25 sccm, nitrogen flow rate 25 sccm). The titanium composition ratio of the obtained titanium nitride film was 66 atomic%.

Next, a titanium target was used under the conditions of a chamber internal pressure of 0.2 Pa, a DC power source of 12 kW, and a mixed atmosphere of argon gas and nitrogen gas (argon flow rate 30 sccm, nitrogen flow rate 20 sccm). The titanium composition ratio of the obtained titanium nitride film was 75 atomic%.

Next, a titanium target was used under the conditions of a chamber internal pressure of 0.2 Pa, a DC power source of 12 kW, and a mixed atmosphere of argon gas and nitrogen gas (argon flow rate 40 sccm, nitrogen flow rate 10 sccm). The resulting titanium nitride film had a titanium composition ratio of 88 atomic%.

In order to form a titanium film having a titanium composition ratio of 100 atomic%, a titanium target was used under the conditions of a chamber internal pressure of 0.1 Pa, a DC power source of 1 kW, and an argon gas atmosphere (argon flow rate 20 sccm).

After the titanium nitride film or the titanium film was formed, the titanium nitride film or the titanium film was processed into a predetermined shape by an etching process, and a conductive film to be the floating gate 104 was formed (FIG. 4B).

Next, phosphorus (P) was added to the semiconductor film 102 by a plasma doping apparatus to form an impurity region 122 (FIG. 4C). PH3 diluted with hydrogen was used as the source gas.

Next, a second insulating film 205 was formed so as to cover the floating gate 104. Here, a silicon oxynitride film having a thickness of 50 nm was formed by a plasma CVD apparatus.

Next, a stacked film of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 170 nm was formed over the second insulating film 205 by a sputtering apparatus. This stacked film was etched to form a control gate 106 (FIG. 4D).

Next, phosphorus was added to the semiconductor film 102 by a plasma doping apparatus using the control gate 106 as a mask (FIG. 4E). PH3 diluted with hydrogen was used as the source gas. In this step, an impurity region 102 b is formed in the semiconductor film 102.

Next, after a silicon oxide film having a thickness of 50 nm is formed to cover the control gate 106 (not shown), heat treatment is performed at 480 ° C. in a nitrogen atmosphere to activate phosphorus added to the impurity regions 102 b and 122. did. Next, a stacked film of a 100-nm-thick silicon oxynitride film and a 600-nm-thick silicon oxide film was formed as the interlayer insulating film 107. Next, the laminated film of the insulating films 203, 205, and 107 is opened, and with a sputtering apparatus, a titanium film with a thickness of 60 nm, a titanium nitride film with a thickness of 40 nm, a pure aluminum film with a thickness of 500 nm, and a titanium film with a thickness of 100 nm A conductive film having a laminated structure was formed. The laminated film was processed into a desired shape by an etching process, so that the conductive film 108 was formed. Through the above process, the memory cell of the present application was manufactured (see FIG. 4F).

FIG. 5 shows the result of measuring the writing voltage and the erasing voltage of the memory transistor manufactured in this example, and FIG. 6 shows the result of measuring the erroneous writing resistance and erroneous erasing resistance. In addition, the titanium composition ratio shown in the present Example is a value based on the analysis result by the Raman diffusion method (RBS).

FIG. 5 shows that the erase voltage is large when the titanium composition ratio is 46 atomic% or less, and the erase voltage is small when the titanium composition ratio is 56 atomic% or more. That is, by using titanium nitride having a titanium composition ratio of 56 atomic% or more as a floating gate material, a memory transistor with a low erase voltage can be manufactured.

From FIG. 6, it can be seen that when the titanium composition ratio is 88 atomic% or more, the improvement is made as compared with the titanium composition ratio 100 atomic%, but the deterioration of the miswrite resistance starts compared with 75 atomic% or less. On the other hand, it can be seen that when the titanium composition ratio is 75 atomic% or less, the resistance to erroneous rewriting can be secured without any problem. In other words, by using titanium nitride as a floating gate material, and more preferably by setting the titanium composition ratio to 75 atomic% or less, a memory transistor having good miswrite resistance can be manufactured.

100 substrate 101 insulating film 102 semiconductor film 102a channel forming region 102b impurity region 102c LDD region 103 insulating film 104 floating gate 105 insulating film 106 control gate 107 interlayer insulating film 108 conductive film 122 impurity region 203 insulating film 204 conductive film 205 insulating film 206 Conductive film 2111 Case 2112 Display portion 2113 Lens 2114 Operation key 2115 Shutter button 2116 Memory 2121 Case 2122 Display portion 2123 Operation key 2125 Memory 2130 Main body 2131 Display portion 2132 Memory portion 2133 Operation portion 2134 Earphone 2141 Main body 2142 Display portion 2143 Operation key 2144 Memory unit

Claims (3)

A semiconductor film having a channel formation region;
A floating gate located on the channel formation region via an insulating film,
The floating gate have a titanium nitride is titanium composition ratio than 56Atomic% by atomic percent,
2. The semiconductor memory device according to claim 1, wherein the titanium / nitrogen composition ratio of the titanium nitride deviates from the stoichiometric composition ratio . A semiconductor film having a channel formation region;
A floating gate located on the channel formation region via an insulating film,
The floating gate have a titanium titanium nitride composition ratio is less than 56atomic% 75atomic% by atomic percent,
2. The semiconductor memory device according to claim 1, wherein the titanium / nitrogen composition ratio of the titanium nitride deviates from the stoichiometric composition ratio . A semiconductor film having a channel formation region;
A first insulating film on the semiconductor film;
A floating gate located on the semiconductor film through the first insulating film;
A second insulating film on the floating gate;
A control gate positioned on the floating gate via the second insulating film,
The floating gate includes titanium nitride having a titanium composition ratio of 56 atomic% or more and 75 atomic% or less in atomic percent.
The composition ratio of titanium and nitrogen in the titanium nitride deviates from the stoichiometric composition ratio,
A semiconductor memory device, wherein the thickness of the first insulating film is smaller than the thickness of the second insulating film.

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