JP5942226B2 - Communication system, transmitter and receiver used therefor, and communication method - Google Patents

Description

  The present invention relates to a communication system in which a signal transmitted by radio from a transmitter is received by a receiver, a transmitter and a receiver used therefor, and a communication method.

  General wireless communication is asynchronous communication because the transmitter and the receiver operate with different clocks. Therefore, the receiver performs oversampling to sample the received baseband signal at a plurality of timings per symbol so as to be able to cope with reception of the baseband signal from the transmitter at any timing. Extract the timing that can be detected. This extraction process is referred to as a symbol synchronization process. In order to recognize a frame which is a basic unit of communication, it is necessary to identify the beginning of a header or data in the frame. This identification process is referred to as a frame synchronization process.

  As a conventional technique for establishing symbol synchronization, a zero cross detection method is widely known. In this zero cross detection method, a preamble (a signal following 101010...) That repeats 1 and 0 alternately is arranged at the head of the baseband signal. At the receiver, the baseband signal is oversampled, and the sign inversion timing of the preamble, that is, the timing of zero crossing is read. Then, based on the read zero-cross timing, a sampling timing capable of accurately detecting the symbol is obtained, and the sampling timing is set as the symbol synchronization timing. For example, the sampling timing closest to the middle between the zero cross and the next zero cross is set as the symbol synchronization timing.

  Next, FIG. 37 shows a conventional technique for establishing frame synchronization for a baseband signal with symbol synchronization. It is assumed that a value obtained by oversampling a baseband signal, that is, a sample value of the baseband signal is originally quantized in the symbol synchronization establishment process. In the conventional method of establishing frame synchronization, the value quantized as described above is discriminated based on the binarization threshold value and replaced with the binary value for the sample value sequence at the sampling timing set at the symbol synchronization timing. (S101). Then, a correlation value between the sample value string and a known unique word that is also binary is calculated (S102). If the calculated correlation value is greater than or equal to a preset correlation threshold value (Yes in S103), it is determined that the sample value sequence matches the unique word, and the timing at which they match is the frame synchronization timing. Is set. In this way, frame synchronization is established (S104).

  By the way, in a radio communication system, intersymbol interference of received signals caused by multipath fading is cited as one of the problems. As shown in FIG. 38, this interference is caused by the fact that the transmitted signal arrives at the receiving antenna through different paths (multipaths) with different delay times and is added to the receiving antenna. The In a multipath environment, direct waves coming directly from the transmitting antenna and indirect waves reflected by obstacles are input to the receiving antenna, or only indirect waves that do not have direct waves and pass through multiple paths are transmitted to the receiving antenna. Or

  When such a phenomenon occurs, the received signal waveform may be distorted. The received signal waveform tends to be more easily distorted as the signal transmission speed is higher. The reason will be described with reference to FIG. As shown in the figure, when the signal transmission rate is high, the symbol length of the signal is shortened, so that the relative ratio of the delay time to the symbol length is high. Therefore, for example, when there are two signals that have passed through different paths, and the other signal is delayed due to multipath fading with respect to one signal and the symbol length of the signal is close to the delay time, the first signal of one signal The overlapping portion of the symbol and the 0th symbol of the other signal becomes longer. As a result, the distortion of the received signal waveform with respect to the symbol length becomes relatively large. In the figure, only two signals are taken up. However, in practice, a large number of multi-pulse signals having different delay amounts are added, so that the distortion can be further increased. When the distortion becomes large in this way, the above-described symbol synchronization establishment process cannot detect the original zero-cross timing, and therefore, there is a problem that stable symbol synchronization cannot be obtained. As a result, the above-described frame synchronization establishment process The synchronization accuracy may also be affected.

  Therefore, as a typical measure for eliminating the influence of multipath fading, there is a multicarrier transmission technique such as OFDM (Orthogonal Frequency Division Multiplexing) (see, for example, Patent Document 1). It is possible to reduce the influence of multipath fading while maintaining the communication speed by dividing the information to be transmitted and transmitting in parallel on multiple carriers (subcarriers) and reducing the transmission speed of each carrier. Technology. In this technique, the symbol length is increased by reducing the transmission rate of each carrier, and the delay per symbol due to multipath fading is relatively sufficiently shorter than the symbol length as shown in FIG. . Therefore, even if it is affected by multipath fading, the distortion of the received signal waveform with respect to the symbol length is relatively small, so that symbol synchronization is easily established, and as a result, frame synchronization is also established stably. Can do.

JP 2010-103900 A

  However, multicarrier transmission requires a complicated configuration in which the frequency axis and the time axis are converted and processed by inverse Fourier transform and Fourier transform. For this reason, the communication system using the multicarrier transmission technique has a drawback that the cost becomes high, and the circuit scale increases and it is difficult to downsize the circuit.

  Therefore, as a method for reducing the influence of waveform distortion caused by multipath fading by a single carrier without using the multicarrier technique, there is a technique for lowering the transmission speed, but this technique slows the communication speed. . Therefore, a technique is conceivable in which the transmission rate of only the preamble is made lower than the transmission rate of the data to be communicated. However, with this technique, it is difficult to obtain a sampling timing capable of accurately detecting a data symbol from the preamble. Therefore, accurate symbol synchronization is difficult, and frame synchronization accuracy is reduced.

  The present invention has been made to solve this problem. An object of the present invention is to provide a communication system that can establish synchronization with high accuracy by a low-cost and small-scale circuit even in a multipath fading environment, a transmitter and a receiver used therefor, and a communication method. To do.

In order to achieve the above object, the communication system of the present invention provides:
A low-speed bit string generation unit that generates a first synchronization bit string having a transmission speed lower than that of data to be transmitted;
A bit string generation unit that generates a second synchronization bit string having the same transmission speed as the data;
Generating a baseband signal by framing and modulating the first synchronization bit string, the second synchronization bit string, and the data, up-converting the baseband signal to convert it to an RF signal, A wireless transmission unit for wirelessly transmitting an RF signal ;
A transmitter having
A wireless receiving unit that extracts a baseband signal by down-converting received RF signals wirelessly transmitted by the wireless transmission unit,
And: (integer of 2 or more M) oversampling unit for quantizing a bit, the baseband signal extracted by the radio reception section, the one symbol of the data is sampled at sampling timing of the multiple, and M
A detector for detecting the baseband signal quantized by the oversampling unit ;
Detecting the first synchronization bit string in the baseband signal detected by the detection unit, based on the detection result, to predict the range in which the second synchronization bit string in the baseband signal is present A low-speed bit string detector ,
The sample value sequence of the baseband signal within the prediction range by the low-speed bit sequence detection unit is stored in advance as the sample value sequence by using the detected sample value as it is without replacing it with a binary value . A synchronization establishment unit that calculates a correlation value with the known second synchronization bit string at each sampling timing , and establishes symbol synchronization and frame synchronization based on the calculated correlation value ;
A receiver having
Characterized by comprising a.

The synchronization establishment unit includes a plurality of correlation value calculation units that respectively calculate the correlation values at the plurality of sampling timings, and the plurality of correlation value calculation units execute the correlation value calculation processing in parallel. It is preferable.

The wireless transmission unit continuously transmits the second synchronization bit string a number of times equal to or greater than the number of sampling timings, and the synchronization establishing unit calculates sampling values within the prediction range. It is preferable to have a timing setting unit that sequentially switches each of the second synchronization bit strings for each length.

  The synchronization establishment unit further includes a timing interval detection unit that detects a timing at which the correlation value becomes the maximum value and becomes a maximum value candidate within the prediction range for each sampling timing, and measures the timing interval, When the timing interval measured by the timing interval detection unit is not within the specified range, the maximum value of the sampling timing at which the correlation value is maximized at a timing different from the original is excluded from the maximum value candidates within the prediction range, It is preferable that the sampling timing of the largest maximum value candidate among the remaining maximum value candidates is set as the symbol synchronization timing, and the timing at which the maximum value is obtained is set as the frame synchronization timing.

  When the number of sampling timings is n and n = m × p (m, p: an integer equal to or greater than 2), the wireless transmission unit continuously transmits the second synchronization bit string a number of times equal to or greater than m. The synchronization establishing unit calculates p correlation values at p sampling timings within the prediction range, and executes the correlation value calculation processing in parallel; and It is preferable to include a timing setting unit that sequentially switches the sampling timing at which the correlation values are calculated by the p correlation value calculation units for each length of the second synchronization bit string within the prediction range.

  The synchronization establishing unit sets a sampling timing at which the correlation value is maximum within the prediction range as a symbol synchronization timing, and sets a timing at which the correlation value is maximum within the prediction range as a frame synchronization timing. It is preferable.

  If the correlation value is equal to or greater than the correlation threshold, the synchronization establishment unit sets the sampling timing of the correlation value as the symbol synchronization timing, and sets the timing when the correlation value is equal to or greater than the correlation threshold as the frame synchronization timing. Is preferred.

  The synchronization establishment unit sets a sampling timing at which the correlation value is equal to or greater than a correlation threshold and is maximized within the prediction range as a symbol synchronization timing, and the correlation value is equal to or greater than a correlation threshold and within the prediction range It is preferable to set the timing that becomes the maximum at the frame synchronization timing.

  The synchronization establishment unit multiplies the sample value sequence and the second synchronization bit sequence by a sample value and a bit value in the same order in time series in the correlation value calculation process, Preferably, the multiplication results are cumulatively added using one register.

The communication method of the present invention includes:
A low-speed bit string generation step for generating a first synchronization bit string having a transmission speed lower than that of data to be transmitted;
A bit string generation step of generating a second synchronization bit string having the same transmission speed as the data;
Generating a baseband signal by framing and modulating the first synchronization bit string, the second synchronization bit string, and the data, up-converting the baseband signal to convert it to an RF signal, A wireless transmission step of wirelessly transmitting an RF signal;
A transmission step comprising:
A radio reception step of extracting a baseband signal by receiving and down-converting the RF signal wirelessly transmitted in the radio transmission step;
An oversampling step of sampling one symbol of the data at a plurality of sampling timings and quantizing the baseband signal extracted in the wireless reception step with M (M: integer of 2 or more) bits;
A detection step of detecting the baseband signal quantized by the oversampling step;
The first synchronization bit string in the baseband signal detected by the detection step is detected, and a range in which the second synchronization bit string exists in the baseband signal is predicted based on the detection result. A low-speed bit string detection step;
The sample value sequence of the baseband signal within the prediction range obtained by the low-speed bit sequence detection step is stored in advance as the sample value sequence by using the detected sample value as it is without replacing it with a binary value. A synchronization establishing step of calculating a correlation value with the known second synchronization bit string for each sampling timing, and establishing symbol synchronization and frame synchronization based on the calculated correlation value;
A receiving step comprising:
It is characterized by including.

  According to the present invention, since the range in which the second synchronization bit string exists is predicted based on the first synchronization bit string that is not easily affected by inter-symbol interference due to multipath fading, the second synchronization bit string Increase detection accuracy. Therefore, the synchronization establishment accuracy can be improved by attempting to establish synchronization based on the signal within the prediction range. Further, the processing necessary for improving the synchronization establishment accuracy is simpler than multi-carrier technology such as OFDM, and as a result, the circuit scale can be reduced and the cost of the circuit can be reduced. it can. Moreover, for the sample value sequence of the signal within the prediction range, the sample value is used as it is, and the correlation value is calculated. Therefore, even if the received signal waveform is distorted due to the influence of multipath fading, the error of the correlation value due to rounding at the time of binarization is eliminated as compared with the conventional case where the correlation value is calculated after binarizing the sample value. . Therefore, it is possible to further improve the accuracy of establishing synchronization based on the correlation value.

1 is a block diagram of a communication system according to an embodiment of the present invention. The frame block diagram of the baseband signal of the said communication system. The figure which shows the sampling timing to the unique word and data by the receiver of the said communication system. The figure which shows the sampling timing to the low-speed unique word and unique word by the said receiver. The block diagram of the low-speed unique word detection circuit of the said receiver. The block diagram of the synchronization establishment circuit of the said receiver. The figure which shows the correlation value calculation method of the said low speed unique word detection circuit. The figure which shows the correlation value calculation method of the said synchronization establishment circuit. The flowchart of the transmission process of the baseband signal in the transmitter of the said communication system. The flowchart of the reception process of the baseband signal in the said receiver. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the said receiver. (A) thru | or (d) is a figure for demonstrating the correlation value calculation method of the said synchronization establishment circuit. (A) thru | or (d) is another figure for demonstrating the correlation value calculation method of the said synchronization establishment circuit. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the receiver of the communication system which concerns on the 1st modification of the said embodiment. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the receiver of the communication system which concerns on the comparative example of this modification. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 2nd modification of the said embodiment. The conceptual diagram of the correlation value calculation process of the some sampling timing in the said synchronization establishment circuit. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The frame block diagram of the baseband signal of the communication system which concerns on the 3rd modification of the said embodiment. The block diagram of the synchronization establishment circuit of the said communication system. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows a timing interval when the correlation value becomes the maximum at the right timing for every sampling timing, when the sampling timing of the correlation value calculation object in the said synchronization establishment circuit is switched sequentially. The figure which shows a timing interval when a correlation value becomes the maximum at the wrong timing when the sampling timing of the correlation value calculation object in the said synchronization establishment circuit is switched sequentially. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 4th modification of the said embodiment. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 5th modification of the said embodiment. The frame block diagram of the baseband signal of the said communication system. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 6th modification of the said embodiment. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows the correlation value fluctuation | variation in case synchronization is established by the said synchronization establishment circuit. The figure which shows the correlation value fluctuation | variation when a synchronization is not established by the said synchronization establishment circuit. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 7th modification of the said embodiment. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows the correlation value fluctuation | variation in case synchronization is established by the said synchronization establishment circuit. The figure for demonstrating the correlation value calculation method in the communication system of the 8th modification of the said embodiment. 10 is a flowchart of conventional frame synchronization processing. The figure for demonstrating the influence which multipath fading has on communication. The figure which shows the received signal by the receiver when a signal with a high transmission rate is delayed due to multipath. The figure which shows the received signal by the receiver when the signal with a slow transmission rate delays due to multipath.

  FIG. 1 shows a configuration of a communication system according to an embodiment of the present invention. The communication system 1 includes a transmitter 2 and a receiver 3 that communicate in a wireless manner. The transmitter 2 modulates data to be transmitted to generate a symbol sequence, up-converts a baseband signal composed of the symbol sequence to convert it to an RF signal, and wirelessly transmits the RF signal. The baseband signal is transmitted in units of frames having a predetermined data length. The data length of the frame may be a plurality of patterns. The receiver 3 receives the RF signal transmitted from the transmitter 2, acquires a baseband signal by down-converting the received RF signal, detects the acquired baseband signal, and reads data. .

  By the way, since the communication between the transmitter 2 and the receiver 3 is wireless, the receiver 3 does not know the timing at which a signal is transmitted from the transmitter 2 at first, and is in an asynchronous state. It is in. Therefore, in order for the receiver 3 to read data from the baseband signal, it is necessary not only to detect the baseband signal but also to establish symbol synchronization and frame synchronization between the transmitter 2 and the receiver 3.

  Therefore, in this embodiment, as shown in FIG. 2, a low-speed unique word U1 (first synchronization bit string) and a unique word U2 (second synchronization bit string) for establishing synchronization are added to the head of the frame F1. Has been. The low speed unique word U1 is set so that the transmission speed is lower than that of the data D1, and the unique word U2 is set so that the transmission speed is substantially the same as that of the data D1. The low speed unique word U1 has a lower transmission rate and a longer symbol length than the unique word U2. The transmitter 2 converts the low-speed unique word U1, the unique word U2 and the transmission target data D1 into a frame and modulates it into a baseband signal. The low-speed unique word U1 and the unique word U2 are not limited to signals that alternately repeat 0 and 1 as illustrated. The receiver 3 detects the baseband signal, detects the low-speed unique word U1 in the detected baseband signal, and predicts the range where the unique word U2 in the baseband signal exists based on the detection result. . Then, the receiver 3 establishes symbol synchronization and frame synchronization based on a correlation value between a baseband signal existing within the predicted range and a known unique word U2 stored in advance. Hereinafter, when simply referred to as synchronization, symbol synchronization and frame synchronization are collectively indicated. Hereinafter, the description will return to FIG. 1, but FIG. 2 will be referred to again as appropriate.

  The transmitter 2 includes a low-speed unique word generation circuit 21 (low-speed bit string generation unit) that generates a low-speed unique word U1, a unique word generation circuit 22 (bit string generation unit) that generates a unique word U2, and a transmission circuit 23 (wireless transmission). Part). The low-speed unique word generation circuit 21 sets the transmission speed of the low-speed unique word U1 to 1 / k (a number larger than k: 1) of the transmission speed of the data D1. With this setting, the symbol frequency of the low-speed unique word U1 is 1 / k times the symbol frequency of the data D1, and the symbol length of the low-speed unique word U1 is k times the symbol length of the data D1. The symbol frequency is the number of symbols transmitted per second. That is, the symbol frequency is lowered by setting the transmission rate low, while the symbol frequency is raised by setting the transmission rate high. Since the unique word generation circuit 22 sets the transmission rate of the unique word U2 to be substantially the same as the transmission rate of the data D1, the symbol frequency and the symbol length are the same between the unique word U2 and the data D1. The transmission circuit 23 frames the low-speed unique word U1, the unique word U2, and the data D1 and modulates them to generate a baseband signal. The transmission circuit 23 up-converts the baseband signal to convert it to an RF signal, and wirelessly transmits the RF signal from the antenna 24 to the receiver 3.

  The receiver 3 includes a reception circuit 31 (radio reception unit) that receives an RF signal wirelessly transmitted by the transmission circuit 23 via the reception antenna 30, down-converts, and acquires a baseband signal. In addition, the receiver 3 includes an AD converter 32 (sampling unit) that performs AD conversion on the baseband signal acquired by the receiving circuit 31. The receiver 3 further includes a synchronization circuit 33 that establishes synchronization with the baseband signal that has passed through the AD converter 32, and a signal processing circuit 34 that processes the baseband signal whose synchronization is established by the synchronization circuit 33.

  When AD converting the baseband signal, the AD converter 32 oversamples the baseband signal at a sampling frequency higher than the symbol frequency of the unique word U2 and the data D1. Then, the AD converter 32 quantizes the sample value of the baseband signal obtained by the oversampling with M (M: integer greater than or equal to 2) bits.

  Here, the sampling process of the AD converter 32 will be described with reference to FIG. FIG. 3 shows a case where the sampling target is the unique word U2 and a case where the sampling target is the data D1. The sampling process in these two cases is common. The AD converter 32 samples the entire baseband signal B1 at a plurality of sampling timings at which one symbol Sb of each unique word U2 and data D1 can be sampled at a plurality of timings. Specifically, the AD converter 32 samples the signal value of the baseband signal B1 at, for example, four sampling timings (0) to (3) per symbol Sb (four times sampling). The sampling timings (0) to (3) are shifted at equal intervals in time. In the case of quadruple sampling, the interval is 1/4 of the period of the symbol Sb, that is, the baseband signal B1 is a symbol. Sampling is performed at a frequency four times the frequency of Sb. The number of sampling timings for one symbol Sb is not limited to the above four, and may be plural. In the present embodiment, a sampling timing that can accurately capture the value of the symbol Sb is detected from the sampling timings (0) to (3), and the sampling timing is set as the symbol synchronization timing. Established.

  As shown in FIG. 4, the symbol length T1 of the low-speed unique word U1 is k times the symbol length T2 of the data D1 and the unique word U2. Therefore, the low-speed unique word U1 is sampled at 4 × k sampling timings per symbol by the above-described quadruple sampling processing. Note that the low-speed unique word U1 and the unique word U2 are not limited to the illustrated number of bits. Returning to the description of FIG.

  The synchronization circuit 33 detects a baseband signal received by the receiving circuit 31 and a low-speed unique word detection that detects a low-speed unique word U1 in the baseband signal detected by the detection circuit 35. Circuit 36 (low-speed bit string detector). The detection circuit 35 detects (decodes) the sample value sequence of the baseband signal quantized by the AD converter 32 by delay detection or the like. The low speed unique word detection circuit 36 predicts a range where the unique word U2 exists in the baseband signal based on the detection result of the low speed unique word U1. The synchronization circuit 33 calculates a correlation value between a baseband signal existing within the range predicted by the low-speed unique word detection circuit 36 and a known unique word U2 stored in advance (synchronization establishment circuit 37 (synchronization establishment). Part). The synchronization establishment circuit 37 establishes symbol synchronization and frame synchronization based on the calculated correlation value.

  FIG. 5 shows a configuration of the low-speed unique word detection circuit 36. The low-speed unique word detection circuit 36 includes a bit string extraction circuit (hereinafter referred to as an extraction circuit) 36a, a storage circuit 36b, a correlation value calculation circuit (hereinafter referred to as a calculation circuit) 36c, a threshold setting circuit 36d, a comparison circuit 36e, and a prediction circuit 36f. Have.

  The extraction circuit 36a extracts a sample value sequence of 4 × k sampling timings from the sample value sequence detected by the detection circuit 35 at each sampling timing. The number of sample values in the sample value sequence to be extracted is set to the same number as the number of bits of the low-speed unique word U1. The storage circuit 36b stores a bit string of a known low-speed unique word U1 in advance.

  The calculation circuit 36c calculates a correlation value between the sample value sequence extracted by the extraction circuit 36a and the bit sequence of the low-speed unique word U1 stored in advance in the storage circuit 36b for each sampling timing. The calculation circuit 36c multiplies the sample value string extracted by the extraction circuit 36a and the low-speed unique word U1 stored in the storage circuit 36b by the sample value and the bit value in the same order in time series, The sum of the multiplication results is calculated as a correlation value. At this time, in the actual calculation, signal processing corresponding to multiplication of the sample value sequence and the low-speed unique word U1 is executed. The correlation value calculated by the calculation circuit 36c increases as the sample value string extracted by the extraction circuit 36a approaches the bit string of the low-speed unique word U1. The value of each bit of the low-speed unique word U1 stored in advance in the storage circuit 36b is an ideal value composed of binary values of 0 or 1. The binary values 0 and 1 are converted so as to be treated in the same way as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 36c. The The value subjected to the conversion process is used as a bit value for the correlation value calculation process by the calculation circuit 36c.

  The threshold setting circuit 36d presets a correlation value threshold based on an input from an operation unit (not shown) or an interface unit. The set threshold value (hereinafter referred to as the first set threshold value) is a signal processing so that the absolute value of the maximum possible correlation value (ideal correlation value) is multiplied by a coefficient of 1 or less, for example, 0.7. It is controlled by. The reason why the first set threshold is set to such a value is that even if the received signal waveform is distorted and the correlation value becomes small, the first set threshold is distinguished between the correlation value of the low-speed unique word U1 and the correlation value of noise. This is because it is not necessary to completely match the ideal correlation value as long as it is possible. The comparison circuit 36e compares the correlation value calculated by the calculation circuit 36c with the first set threshold value at each sampling timing, and determines whether or not the calculated correlation value is greater than or equal to the first set threshold value. When the comparison circuit 36e determines that the correlation value is greater than or equal to the first set threshold, the prediction circuit 36f recognizes that the low-speed unique word U1 has been detected, and determines the range in which the unique word U2 in the baseband signal exists. Predict.

  FIG. 6 shows the configuration of the synchronization establishment circuit 37. The synchronization establishment circuit 37 includes a bit string extraction circuit (hereinafter referred to as extraction circuit) 37a, a storage circuit 37b, a correlation value calculation circuit (hereinafter referred to as calculation circuit) 37c, a maximum value extraction circuit (hereinafter referred to as extraction circuit) 37d, and synchronization detection. A circuit 37e and a synchronization setting circuit 37f are included.

  The extraction circuit 37a extracts a sample value sequence of each sampling timing (0) to (3) for each sampling timing from the sample value sequence of the baseband signal within the prediction range by the prediction circuit 36f. The number of sample values of the extracted sample value sequence is the same as the number of bits of the unique word U2. The storage circuit 37b stores a known unique word U2 in advance.

  By the way, the sample value sequence of each sampling timing (0) to (3) extracted by the extraction circuit 37a is a sample value sequence obtained by sampling the unique word U2 once per symbol for each sampling timing. The calculation circuit 37c calculates a correlation value between the sample value sequence and the bit sequence of the unique word U2 stored in advance in the storage circuit 37b at each sampling timing. In this calculation process, the calculation circuit 37c multiplies the sample value string and the unique word U2 by the sample value and the bit value in the same order in time series order, calculates the sum of the multiplication results, and calculates the correlation value. And At this time, in the actual calculation, signal processing corresponding to multiplication of the sample value string and the unique word U2 is executed. The correlation value calculated by the calculation circuit 37c becomes higher as the sample value string is closer to the unique word U2. The value of each bit of the unique word U2 stored in advance in the storage circuit 37b is an ideal value composed of binary values of 0 or 1. The binary values 0 and 1 are converted so as to be treated in the same manner as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 37c. The The value subjected to the conversion process is used as a bit value for the correlation value calculation process by the calculation circuit 37c.

  The extraction circuit 37d extracts the correlation value that is maximized within the prediction range of the prediction circuit 36f from the correlation values calculated by the calculation circuit 37c. The synchronization detection circuit 37e detects the sampling timing of the correlation value extracted by the extraction circuit 37d as the symbol synchronization timing. Further, the synchronization detection circuit 37e detects the timing at which the correlation value becomes the maximum within the prediction range as the frame synchronization timing.

  The synchronization setting circuit 37f sets the sampling timing detected as the symbol synchronization timing by the synchronization detection circuit 37e to the symbol synchronization timing of the baseband signal detected by the detection circuit 35. The synchronization setting circuit 37f sets the timing detected as the frame synchronization timing by the synchronization detection circuit 37e to the frame synchronization timing of the baseband signal detected by the detection circuit 35. In this way, the synchronization setting circuit 37f sets the symbol synchronization timing and the frame synchronization timing based on the correlation value calculated by the calculation circuit 37c, and establishes synchronization.

  After synchronization is established, the synchronization setting circuit 37f extracts and outputs each sample value after detection of the symbol synchronization timing as each symbol value of the baseband signal after detection. For example, when the sampling timing (1) is set to the symbol synchronization timing among the sampling timings (0) to (3), the synchronization setting circuit 37f uses each sample value sampled at the sampling timing (1) as a symbol. Output as a value. Therefore, the signal output from the synchronization setting circuit 37f is a sample value sequence obtained by sampling the baseband signal after detection at a frequency that is one time the symbol frequency (a sample value sequence obtained by sampling the baseband signal by one time). The synchronization setting circuit 37f does not output the sample value sequence of other sampling timings, that is, the sample value sequence of the sampling timings (0), (2), and (3) in the above example. Therefore, the subsequent processing for the output of the synchronization setting circuit 37f is only required for one sampling timing, and the processing load is reduced.

  FIG. 7 shows a correlation value calculation method by the calculation circuit 36c. The calculation circuit 36c replaces the sample value quantized with M bits with the binary value of -1 or 1 for the sample value sequence extracted by the extraction circuit 36a, and correlates the sample value sequence with the low-speed unique word U1. Is calculated. In this calculation process, the result of hard decision by binarization of the sample value after detection is used. In the present embodiment, the hard decision is performed in the above calculation process to reduce the circuit scale, but it may be a soft decision that uses the sample value after detection as it is without being binarized. . The low speed unique word U1 is not limited to the number of bits shown.

  FIG. 8 shows a correlation value calculation method by the calculation circuit 37c. The calculation circuit 37 c uses the sample value sequence extracted by the extraction circuit 37 a as it is without replacing the sample value quantized with M bits with the binary value of −1 or 1, and uses the sample value sequence as it is. And the correlation value between the unique word U2 and the bit string. In this calculation process, since the sample value after detection quantized by soft-decision of the sample value after detection is used as it is, the certainty as to whether the sample value is binary is used as it is. It is done. The unique word U2 is not limited to the number of bits shown.

  Next, communication processing in the communication system 1 will be described with reference to FIGS. 9 and 10 in addition to FIGS. 1 and 2. FIG. 9 shows a signal transmission step by cooperation of each circuit of the transmitter 2, and FIG. 10 shows a reception step by cooperation of each circuit of the receiver 3.

  As shown in FIG. 9, the low speed unique word generation circuit 21 generates a low speed unique word U1 (S11; low speed bit string generation step), and the unique word generation circuit 22 generates a unique word U2 (S12; bit string generation). Part). Thereafter, the transmission circuit 23 frames the low-speed unique word U1, the unique word U2 and the data D1 and modulates them to generate a baseband signal (S13; wireless transmission step). Then, the transmission circuit 23 up-converts the baseband signal to convert it into an RF signal, and wirelessly transmits the RF signal (S14; wireless transmission step). During the wireless transmission, the low-speed unique word U1, the unique word U2, and the data D1 are transmitted in this order.

  As shown in FIG. 10, the reception circuit 31 receives an RF signal, down-converts the received RF signal to obtain a baseband signal (S21; wireless reception step), and the AD converter 32 The acquired baseband signal is AD converted (S22). The detection circuit 35 detects the baseband signal after AD conversion (S23; detection step). The low-speed unique word detection circuit 36 detects the low-speed unique word U1 in the baseband signal detected in S23 (Yes in S24). At that time, the low-speed unique word detection circuit 36 predicts a range where the unique word U2 exists in the baseband signal based on the detection result (S25; low-speed bit string detection step). The synchronization establishment circuit 37 calculates a correlation value between the baseband signal existing within the prediction range in S25 and the bit string of the unique word U2, and establishes symbol synchronization and frame synchronization based on the calculated correlation value (S26). ; Synchronization establishment step).

  Next, synchronization establishment processing by cooperation of each circuit of the synchronization establishment circuit 37 will be described with reference to FIG. 11 in addition to FIG. 2, FIG. 3, FIG. 5 and FIG. FIG. 11 shows the procedure of the synchronization establishment process. Here, N is the number of bits of the unique word U2.

  The extraction circuit 37a sequentially extracts an N-bit sample value sequence for each sampling timing (0) to (3) from the sample value sequence of the baseband signal within the prediction range by the prediction circuit 36f (S31). The calculation circuit 37c calculates a correlation value between the sample value string extracted in S31 and the bit string of the unique word U2 stored in advance in the storage circuit 37b (S32). The correlation value is calculated at every sampling timing.

  The extraction circuit 37d extracts the correlation value that is maximized within the prediction range from the correlation values calculated in S32 (S33). The synchronization detection circuit 37e detects the sampling timing of the correlation value extracted in S33 as the symbol synchronization timing. Further, the synchronization detection circuit 37e detects the timing at which the correlation value becomes maximum within the prediction range as the frame synchronization timing (S34). The synchronization setting circuit 37f sets the symbol synchronization timing and the frame synchronization timing detected in S34 for the sample value sequence after detection by the detection circuit 35, and establishes synchronization (S35; synchronization establishment step).

In the present embodiment, the low-speed unique word U1 has a lower transmission speed and a longer symbol length than the unique word U2 and the data D1. Therefore, even if the reception signal waveform of the low speed unique word U1 is distorted due to multipath fading, the distortion of the reception signal waveform with respect to the symbol length can be made relatively smaller than that of the unique word U2. Therefore, the influence on the low-speed unique word U1 due to multipath fading can be reduced. As a result, the low-speed unique word U1 can be accurately detected, and based on the detection, the range in which the unique word U2 exists is predicted, thereby increasing the accuracy of detecting the unique word U2. Therefore, by trying to establish synchronization based on the correlation value between the baseband signal in the prediction range and the known unique word U2, the correlation value is outside the prediction range A1 as shown in FIG. Even if it becomes the same as the maximum value C _max of, it is possible to prevent erroneous synchronization at that timing. Therefore, the probability of erroneous synchronization can be reduced, and synchronization establishment accuracy can be improved. FIG. 12 shows an example in which erroneous synchronization during reception of the frame F1 is prevented. Similarly to the example, erroneous synchronization due to noise or the like when the frame F1 is not received can be prevented. Further, the processing necessary for improving the synchronization establishment accuracy is simpler than multi-carrier technology such as OFDM, and as a result, the circuit scale can be reduced and the cost of the circuit can be reduced. it can. The prediction range A1 is a range in which the entire unique word U2 can exist, but the maximum correlation value is actually the timing when all the unique words U2 have been received. Therefore, in FIG. 12, the prediction range A1 is shown near the last symbol of the unique word U2.

  If the correlation value of any sampling timing among the sampling timings (0) to (3) becomes maximum within the prediction range A1, the sampling timing is set as the symbol synchronization timing. The timing at which the correlation value is maximized is set as the frame synchronization timing. Therefore, both symbol synchronization and frame synchronization can be established at the same time, the time required for establishing these synchronizations can be shortened, and the processing speed can be increased. Further, in order to establish symbol synchronization, it is not necessary to detect a zero cross by arranging a signal that repeats 1 and 0 alternately at the head of the baseband signal. Therefore, a signal that repeats 1 and 0 alternately becomes unnecessary and a zero-cross detection circuit is not required. Even if the correlation value decreases due to the influence of noise, synchronization can be established.

  Further, in the sample value sequence of the baseband signal after detection, the sample value is quantized with M bits and is used as it is without being binarized by the calculation circuit 37c to calculate the correlation value. . Therefore, even if the received baseband signal waveform is distorted due to multipath fading, it is based on rounding at the time of binarization compared to the case of calculating the correlation value after converting the quantized sample value to binary. Correlation value error is eliminated. Therefore, it is possible to improve the accuracy of establishing synchronization based on the correlation value. Further, the processing necessary for improving the accuracy of establishing synchronization is simpler than multi-carrier techniques such as OFDM, and therefore the circuit scale can be reduced and the cost of the circuit can be reduced. .

  The effect of the calculation method of the calculation circuit 37c will be further described. As comparison targets of the calculation method, sample values are replaced with binary values of 1 or −1 with a threshold value of 0, and two examples of correlation values calculated after a so-called hard decision are shown in FIGS. ). In these examples, the bit string of the unique word U2 has a 3-bit configuration of 1, -1, 1, and so on. The value and the number of bits of each bit of the unique word U2 are not limited to this. Hereinafter, a method of calculating a correlation value by replacing a sample value with a binary value is referred to as a binarization calculation method.

  FIG. 13A shows a case where the extracted sample value sequence is a sample value sequence of the unique word U2 in the received signal and is, for example, 0.8, −0.3, and −0.1. In this example, the sample value −0.1 has an ideal value of 1 and the sign is inverted compared to the ideal value, but the difference from the threshold is only 0.1. However, the sample value -0.1 is rounded to -1 by binarization to -1 or 1 with 0 as the threshold, and the difference from the threshold is considered to be 1. As a result, the correlation value of the extracted sample value sequence is 1.0.

  On the other hand, FIG. 13B shows sample value sequences of other signals that are not the unique word U2 in the received signal, for example, 0.8, −0.3, −0. 7 is shown. The correlation value in this case is also 1.0.

  As shown in these results, in the binarization calculation method, the difference between the correlation value when the unique word U2 is received and the correlation value when another signal is received may be small. As the example shows, sometimes it is zero. Therefore, it may be difficult to distinguish the unique word U2 from other signals in the received signal, and there is a risk of erroneous synchronization.

  On the other hand, in the calculation method of the calculation circuit 37c, even if the conditions are the same as those in FIGS. 13A and 13B, the correlation value is 1 as shown in FIGS. 0.0 and 0.4, and the difference between the correlation values in each case is 0.6. As shown in this result, in the calculation method of the present embodiment, the difference between the correlation value when the unique word U2 is received and the correlation value when other signals are received increases. Therefore, it is easy to distinguish the unique word U2 from other signals in the received signal, and the synchronization accuracy is increased.

  By the way, in the binarization calculation method, as shown in FIGS. 14A and 14B, even if the sample value is, for example, 0.8, −0.3, 0.1, or 0.9, Even if −0.9 and 0.9, the correlation value is 3.0, which is the same. When the first set threshold value of the correlation value is set to 2.0, for example, the correlation value is equal to or higher than the first set threshold value at the sampling timings in FIGS. 14A and 14B. I can't judge. Since the sample value sequence at the latter sampling timing is closer to the unique word U2, it is more appropriate to set the timing at which the sample value sequence is extracted as the synchronization timing. However, it is difficult because the correlation values of both sample value sequences are equal.

  On the other hand, in the calculation method of this embodiment, as shown in FIGS. 14C and 14D, the correlation values in the above two examples are 1.2 and 2.7, respectively, and any sampling timing is obtained. Can be determined. As described above, in the calculation method of the present embodiment, the correlation value is calculated in detail according to the sample value string, and therefore, a more appropriate timing can be set as the synchronization timing based on the correlation value. Is even higher.

  14 (a) and 14 (c), the sample value of −0.1 in FIGS. 13 (a) and 13 (c) is 0.1 instead, which is closer to the ideal value 1. Shows the case. As shown in FIG. 14A, in the case of the binarization calculation method, the correlation value is 2.0 (= 3.0) even though the sample value is only 0.2 close to the ideal value. -1.0) also increases. On the other hand, as shown in FIG. 14C, in the case of the calculation method of the present embodiment, the correlation value is 1.2, and the increase in the correlation value is 0.2 (= 1.2-1. Stay 0).

  As can be seen by comparing these two examples, with the binarization calculation method, the correlation value may increase significantly even if the sample value changes slightly in the vicinity of the threshold value. Therefore, a timing that is not appropriate is set as the synchronization timing. The synchronization accuracy may be reduced. On the other hand, in the calculation method of the present embodiment, since the correlation value is appropriately calculated according to the sample value, a more appropriate timing can be set as the synchronization timing, and the synchronization accuracy is further improved.

  Next, modifications of the above embodiment will be described with reference to the drawings. The same reference numerals are given to the same components as those of the above-described embodiment, and when the configuration is described, FIGS. Only the configuration and processing different from the above embodiment will be described below.

(First modification)
FIG. 15 shows a received signal by the receiver 3 of the communication system according to the first modification, and a correlation value between the received signal and the bit string of the unique word U2. In this modification, the unique word U2 is configured by a pseudo-random signal, for example, a 15-bit M sequence. The number of bits of the M sequence is not limited to this. The transmission circuit 23 of the transmitter 2 continuously and repeatedly transmits the M sequence that is the unique word U2, for example, continuously three times. The M sequences that are continuously transmitted are the same signal. The receiving circuit 31 of the receiver 3 receives the M sequence three times in succession. The storage circuit 37b of the receiver 3 stores in advance the entire M sequence identical to the M sequence transmitted from the transmission circuit 23 or a part thereof as a unique word U2, and the calculation circuit 37c receives the M sequence, The correlation value with the sample value sequence of the received signal by the circuit 31 is calculated.

  The M sequence is composed of binary values of 1 and 0, and the number of 0s is one more than the number of 1s. The binary values 0 and 1 are converted so as to be treated in the same manner as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 37c. The When the sum of each bit of the M sequence after the conversion is obtained, the sum is -1. For the M sequence and the M sequence obtained by cyclically shifting the M sequence, when bits in the same order are multiplied, the bit string obtained by the multiplication is obtained by further cyclically shifting the original M sequence. There is a characteristic that it becomes the same. Therefore, the sum total of each bit of the bit string is also -1.

  The prediction circuit 36f predicts a range in which the second M sequence in the baseband signal exists when the low-speed unique word U1 is detected. Here, the prediction range is A2. During reception of the baseband signal within the prediction range A2, if the M sequence in the baseband signal remains an ideal value, the baseband signal and the unique word U2 are received during reception of the second M sequence. The correlation value is 15 due to the above characteristics of the M series. On the other hand, before and after the reception, the correlation value is the sum of each bit of the bit string obtained by multiplying the M sequence and the cyclically shifted version of the M sequence for each bit. -1. Note that the prediction range A2 is a range in which the entire second M-sequence can exist, but the fact that the correlation value is actually maximized is the timing when all the M-sequences have been received. 15, the prediction range A2 is indicated near the last symbol of the second M series.

  Here, the comparative example of this modification is shown in FIG. As shown in FIG. 16, when the transmitter transmits the M sequence only once and transmits other signals before and after that, the correlation value at the M sequence reception timing A3 by the receiver is 15. However, the correlation value is disturbed before and after the reception, and there is a possibility that the correlation value becomes large even when the M sequence is not received.

  Compared to such an example, in the present modification, the difference between the correlation value when the receiver 3 receives the unique word U2 (M sequence) and the correlation value (degree of coincidence) when other signals are received. Will definitely grow. In particular, when the receiver 3 continuously receives three unique words U2, a correlation value when the second unique word U2 is received, and a correlation value when other signals before and after the second unique word U2 are received, The difference is surely increased. Therefore, even if the difference is somewhat reduced due to multipath fading or noise, the range in which the existence of the unique word U2 is predicted is limited to a range in which the second unique word U2 can exist, for example. The unique word U2 and other signals can be reliably discriminated. As a result, the synchronization accuracy can be improved.

(Second modification)
FIG. 17 shows a configuration of the synchronization establishment circuit 37 of the communication system 1 according to the second modification. The synchronization establishment circuit 37 includes, for example, four timing-specific correlation value calculation circuits (hereinafter referred to as calculation circuits) 37g. The calculation circuit 37g calculates correlation values of a plurality of sampling timings, specifically sampling timings (0) to (3), within the prediction range by the prediction circuit 36f (see FIG. 5 above), and correlates them. The value calculation process is executed in parallel.

  The calculation circuit 37g is associated with the sampling timings (0) to (3), and includes the extraction circuit 37a, the storage circuit 37b, and the calculation circuit 37c. The extraction circuit 37a has a register 37h. The extraction circuit 37a extracts only the sample value string of the sampling timing associated with the calculation circuit 37g from the sampling timings (0) to (3) from the prediction range of the prediction circuit 36f, and stores it in the register 37h. Store. As illustrated, the storage circuit 37b may be provided in each calculation circuit 37g, or one storage circuit 37b may be shared by these calculation circuits 37g. Each of the calculation circuits 37c calculates a correlation value between the sample value sequence stored in the register 37h and the bit sequence of the unique word U2 stored in advance in the storage circuit 37b.

  The synchronization establishment process in this modification is demonstrated with reference to FIG.18 and FIG.19. FIG. 18 shows a correlation value calculation process that forms part of the synchronization establishment process. In the figure, the register 37h of the calculation circuit 37g associated with each of the sampling timings (0) to (3) is represented as registers (0) to (3), respectively. FIG. 19 shows the overall procedure of the synchronization establishment process. The synchronization establishment process is obtained by changing the processes of S31 and S32 to the processes of S41 and S42 in the synchronization establishment process shown in FIG.

  In the synchronization establishment process in the present modification, the four extraction circuits 37a parallelly extract N-bit sample value sequences of the sampling timings (0) to (3) for each sampling timing from the prediction range by the prediction circuit 36f. Extract sequentially. The extraction circuits 37a store the extracted sample value sequences of the sampling timings (0) to (3) in the registers (0) to (3), respectively ((a) in FIG. 18 and S41 in FIG. 19). The four calculation circuits 37c, in parallel, store the correlation values between the stored sample values at the sampling timings (0) to (3) and the bit string of the unique word U2 stored in the storage circuit 37b for each sampling timing. It calculates ((b) of FIG. 18, S42 of FIG. 19).

  In this modification, the correlation value calculation process is performed independently for each sampling timing, so that the processing algorithm can be simplified and development is facilitated. Further, since the correlation value calculation processing is performed in parallel at each sampling timing, only one unique word U2 is required, and the time required for calculating correlation values at all sampling timings can be shortened. Can be achieved.

(Third Modification)
FIG. 20 shows a frame configuration of a baseband signal in the communication system 1 according to the third modification. As will be described later, in this modification, the synchronization establishment circuit 37 of the receiver 3 switches the sampling timing for calculating the correlation value for each length of one unique word U2. Therefore, in order to enable the synchronization establishment circuit 37 to calculate the correlation values of all sampling timings (0) to (3), the transmission circuit 23 of the transmitter 2 performs sampling timings (0) to (3) in one frame F1. ) And more unique words U2 are inserted. Assuming that the number of sampling timings per symbol Sb is n (n: an integer of 2 or more, 4 in this modification), n or more unique words U2 are inserted into one frame F1. The transmitter 2 continuously transmits these unique words U2.

  Also in this modified example, the unique word U2 is composed of an M sequence as in the first modified example, and in order to improve the synchronization accuracy using the characteristics of the M sequence, 1 is placed before and after the n unique words U2. A unique word U2 is added one by one. As a result, the transmission circuit 23 continuously transmits a total of (n + 2) (six in this modification) unique word U2 in one frame F1.

  FIG. 21 shows the configuration of the synchronization establishment circuit 37 in this modification. The synchronization establishment circuit 37 is obtained by adding a timing setting circuit (hereinafter referred to as a setting circuit) 37i (timing setting unit) to the configuration shown in FIG. In the present modification, the prediction circuit 36f (see FIG. 5) detects the second to fifth unique words among the six unique words U2 in the baseband signal when the low speed unique word U1 is detected. Predict the range in which the word U2 exists. The setting circuit 37i has one unique sampling timing for extracting the sample value by the extraction circuit 37a among the sampling timings (0) to (3) in the prediction range A2 (see FIG. 20 above) by the prediction circuit 36f. It switches in order for every length of the word U2. This length is a period required for transmission of one unique word U2. The setting circuit 37i switches the sampling timing for calculating the correlation value by the calculation circuit 37c for each length.

  FIG. 22 shows the procedure of the synchronization establishment process in this modification. The synchronization establishment process is obtained by changing the processes of S31 and S32 to the processes of S51 to S56 in the synchronization establishment process shown in FIG.

  The setting circuit 37i sets the sampling timing as a variable i and sets i = 0 (S51). The extraction circuit 37a sequentially extracts and extracts an N-bit sample value sequence at the sampling timing (i) by one symbol Sb within the prediction range A2 by the prediction circuit 36f (S52). The calculation circuit 37c calculates a correlation value between the sample value sequence of the extracted sampling timing (i) and the bit sequence of the unique word U2 stored in advance in the storage circuit 37b (S53). If the shift amount in S52 corresponds to the length of one unique word U2 (Yes in S54) and the variable i is 2 or less, that is, (n-2) or less (Yes in S55), the setting circuit 37i The variable i is incremented (S56), and the process returns to S52. If the variable i is 3, that is, (n-1) (No in S55), the process proceeds to S33.

  In this modification, sample value sequences having different sampling timings (0) to (3) can be extracted from the unique words U2 received in the same number as the sampling timings (0) to (3). Therefore, it is not necessary to provide as many calculation circuits 37c as the number of sampling timings to calculate correlation values necessary for establishing synchronization from the extracted sample value sequence. Therefore, the circuit scale can be reduced and the manufacturing cost can be reduced.

(Fourth modification)
As shown in FIG. 23, in the third modified example, when the sampling timing of the correlation value calculation target is sequentially switched, the correlation value is maximized at substantially correct timing for all of the sampling timings (0) to (3). Suppose. In that case, sampling (0) to timing interval of the correlation value is maximized in (3), respectively _{T A,} T B, when the _{T C,} the _{T A ≒ T B ≒ T C} .

On the other hand, as shown in FIG. 24, for example when it becomes maximum at the timing when the correlation value is incorrect for sampling timing (1), the _{T A ≠ T B ≠ T C} . Here, it is assumed that the correlation value is maximum even within the prediction range by the prediction circuit 36f. In that case, synchronization is established at an incorrect timing based on the correlation value. The fourth modification is configured to prevent such erroneous synchronization.

  FIG. 25 shows a configuration of the synchronization establishment circuit 37 of the communication system 1 according to the fourth modification. The synchronization establishment circuit 37 has a configuration in which a timing interval detection circuit (hereinafter referred to as a detection circuit) 37j (timing interval detection unit) is added to the configuration of the third modification shown in FIG. For each sampling timing (0) to (3) (for each sampling timing), the detection circuit 37j detects the timing at which the correlation value becomes the maximum value and becomes the maximum value candidate within the prediction range by the prediction circuit 36f. Measure the timing interval.

Here, it is assumed that the timing interval measured by the detection circuit 37j is not within the specified range. In this case, the synchronization detection circuit 37e sets the maximum correlation value of the sampling timing at which the correlation value is maximized at a timing different from the original among the sampling timings (0) to (3) to the maximum value within the prediction range. Exclude from candidates. In the prescribed range, an upper limit value and a lower limit value of the timing interval are set. Here, a detection example of the maximum value to be excluded will be described. For example, in the case shown in FIG _24, T A, _{T B} is not fit in the specified range, _{T c} is fit into the specified _range, the _{(T A + T B) /} 2 ≒ T C. Therefore, the maximum value obtained at the start point and become timing T _A T _B is the end point of, i.e., it can be detected that the maximum correlation value of the sampling timing (1) corresponds to the excluded. The maximum value to be excluded is not limited to the above detection method, and can be detected based on the timing interval.

  The extraction circuit 37d extracts the largest maximum value candidate among the remaining maximum value candidates as the maximum value within the prediction range. The synchronization detection circuit 37e detects the sampling timing of the maximum value extracted by the extraction circuit 37d as the symbol synchronization timing, and detects the timing at which the maximum value is obtained as the frame synchronization timing.

  FIG. 26 shows the procedure of the synchronization establishment process in this modification. The synchronization establishment process is the same as the synchronization establishment process of the third modification shown in FIG. 22 described above, except that the process of S61 is added between the processes of S53 and S55, and the processes of S62 to S64 are performed between the processes of S55 and S33. It is a process added. After the processing of S53, the detection circuit 37j detects the timing when the correlation value becomes the maximum value at each sampling timing (0) to (3) and becomes the maximum value candidate within the prediction range by the prediction circuit 36f (S61). Is measured (S62). When the timing interval measured in S62 is not within the specified range (Yes in S63), the extraction circuit 37d determines the maximum value of the sampling timings (0) to (3) at which the correlation value becomes the maximum at a timing different from the original. Are excluded from the maximum value candidates within the prediction range. This maximum value is the maximum value in which the interval between the timing at which this maximum value is obtained and the timing at which other maximum value candidates are obtained is outside the specified range (S64). Thereafter, in the process of S33, the extraction circuit 37d extracts the largest maximum value candidate among the remaining maximum value candidates as the maximum value within the prediction range.

  In this modification, when the sampling timing for calculating the correlation value is sequentially switched, it is assumed that the correlation value becomes maximum at an erroneous timing different from the original for any of the sampling timings (0) to (3). Even in such a case, the possibility that the sampling timing is set as the symbol synchronization timing can be reduced, and the probability that the timing at which the correlation value is maximized is set as the frame synchronization timing is reduced. be able to. Therefore, the occurrence of erroneous synchronization can be suppressed.

(Fifth modification)
The communication system 1 according to the fifth modification has a configuration in which the second modification and the third modification are combined. Here, the number of sampling timings is assumed to be n = m × p (m, p: an integer of 2 or more).

  FIG. 27 shows a configuration of the synchronization establishment circuit 37 in this modification. The synchronization establishment circuit 37 includes p calculation circuits 37g configured in the same manner as the calculation circuit 37g of the second modification example (see FIG. 17), and the third modification example. And a setting circuit 37i configured in the same manner as the setting circuit 37i (see FIG. 21). Each of the p calculation circuits 37g calculates p correlation values at the sampling timing within the prediction range by the prediction circuit 36f (see FIG. 5 above), and executes the correlation value calculation processing in parallel. The setting circuit 37i sequentially switches the sampling timing at which the correlation values are calculated by the p correlation value calculation units for each length of the unique word U2 within the prediction range.

  FIG. 28 shows a frame configuration of a baseband signal in this modification. In the present modification, since the above switching is performed, the transmission circuit 23 of the transmitter 2 is set to 1 frame F1 so that the correlation values of all the sampling timings (0) to (3) can be calculated. At least m (2 in this modification) unique words U2 are inserted. The transmission circuit 23 continuously transmits the unique word U2 for the number of times of m or more per frame F1.

  In the present modification, the unique word U2 is composed of an M sequence as in the first modification, and the synchronization accuracy is improved by utilizing the characteristics of the M sequence. A unique word U2 is added one by one. As a result, the transmission circuit 23 continuously transmits a total of (m + 2; 4 in the present modification) unique word U2 in one frame F1. When the low-speed unique word U1 is detected, the prediction circuit 36f includes the second unique word U2 from the second unique word U2 in the baseband signal (m + 1; 3 in this modification). Predict the range to be performed.

  Of the two calculation circuits 37g, one calculation circuit 37g is associated with sampling timings (0) and (2), and the other calculation circuit 37g is associated with sampling timings (1) and (3). Yes. The extraction circuit 37a of the calculation circuit 37g extracts only the sample value string at one sampling timing out of the two sampling timings associated with the calculation circuit 37g, and stores it in the register 37h. Each of the calculation circuits 37c calculates a correlation value between the sample value sequence stored in the register 37h and the bit sequence of the unique word U2 stored in advance in the storage circuit 37b. The setting circuit 37i sets the sampling timing at which the extraction circuit 37a extracts the sample value within the prediction range A2 by the prediction circuit 36f to the length of one unique word U2 within the sampling timing associated with the calculation circuit 37g. Switch in turn every time. As such, the setting circuit 37i switches the sampling timing at which the correlation value is calculated by the calculation circuit 37c for each of the lengths.

  In this modification, it is possible to obtain both the effect of speeding up the processing according to the second modification and the effect of downsizing and cost reduction according to the third modification.

(Sixth Modification)
FIG. 29 shows a configuration of the synchronization establishment circuit 37 of the communication system according to the sixth modification. The configuration is the same as the configuration shown in FIG. 6 except that the extraction circuit 37d is changed to a threshold setting circuit 37k and a comparison circuit 37l.

  The threshold setting circuit 37k presets a correlation value threshold based on an input from an operation unit or an interface unit (not shown). Signal processing is performed so that the set threshold value (hereinafter referred to as the second set threshold value) is a value obtained by multiplying the absolute value of the maximum possible correlation value (ideal correlation value) by a coefficient of 1 or less, for example, 0.7. It is controlled by. The reason why the second set threshold is set to such a value is that even if the received signal waveform is distorted and the correlation value becomes small, the second set threshold can be distinguished from the correlation value of the unique word U2 and the correlation value of noise. This is because it is not necessary to completely match the ideal correlation value if possible.

  The comparison circuit 37l samples the second set threshold value and the correlation values of the sampling timings (0) to (3) calculated by the calculation circuit 37c within the prediction range by the prediction circuit 36f (see FIG. 5 above). Compare at each timing. The comparison circuit 37l determines whether or not the calculated correlation value is equal to or greater than a second set threshold value.

  Here, it is assumed that any one of the correlation values of the sampling timings (0) to (3) calculated by the calculation circuit 37c is determined by the comparison circuit 37l to be equal to or greater than the second set threshold value. At that time, the synchronization detection circuit 37e detects the sampling timing of the correlation value as the symbol synchronization timing, and detects the timing when the correlation value is determined to be equal to or higher than the second set threshold as the frame synchronization timing.

  FIG. 30 shows the procedure of the synchronization establishment process in this modification. The synchronization establishment process is obtained by changing the process of S33 to the processes of S71 and S72 in the synchronization establishment process shown in FIG. The comparison circuit 37l compares the correlation value calculated by the process of S32 with the second setting threshold within the prediction range by the prediction circuit 36f, and determines whether or not the calculated correlation value is equal to or greater than the second setting threshold. Is determined at every sampling timing (S71). When it is determined that the correlation value calculated by the process of S32 is greater than or equal to the second set threshold value (Yes in S72), in the process of S34, the synchronization detection circuit 37e sets the sampling timing of the correlation value as the symbol synchronization timing. Further, the synchronization detection circuit 37e detects the timing at which the correlation value is determined to be equal to or higher than the second setting threshold as the frame synchronization timing. When it is determined that the correlation value calculated by the process of S32 is less than the second set threshold (No in S72), the process returns to S31.

In the present modification, as shown in FIG. 31, synchronization is established when the calculated correlation value is equal to or greater than the second set threshold _Cth . On the other hand, as shown in FIG. 32, when the reception level is low, the calculated correlation value is lower than the second setting threshold _Cth , and there is a concern about mis-synchronization, synchronization is not established. Therefore, erroneous synchronization can be prevented.

(Seventh Modification)
FIG. 33 shows a configuration of the synchronization establishment circuit 37 of the communication system according to the seventh modification. The synchronization establishment circuit 37 is obtained by adding the extraction circuit 37d and the correlation value extraction circuit 37m to the configuration of the sixth modification shown in FIG. The correlation value extraction circuit 37m extracts a correlation value determined by the comparison circuit 37l to be equal to or greater than the second set threshold value from the correlation values at the sampling timings (0) to (3) calculated by the calculation circuit 37c. The extraction circuit 37d extracts the maximum correlation value within the prediction range by the prediction circuit 36f (see FIG. 5 above) from the correlation values extracted by the correlation value extraction circuit 37m.

  FIG. 34 shows the procedure of synchronization establishment processing in this modification. The synchronization establishment process is obtained by returning the process of S33 after the process of S72 and adding the process of S81 between them in the synchronization establishment process of the sixth modified example shown in FIG. In this synchronization establishment process, the correlation value extraction circuit 37m extracts the correlation value determined to be greater than or equal to the second set threshold value in the process of S72 from the correlation values at the sampling timings (0) to (3) and temporarily stores them in the memory. (S81). In the process of S33, the extraction circuit 37d extracts the maximum correlation value within the prediction range by the prediction circuit 36f from the correlation values extracted by the process of S81. Thereafter, in the process of S34, the synchronization detection circuit 37e detects the sampling timing of the extracted maximum correlation value as the symbol synchronization timing. In addition, the synchronization detection circuit 37e detects a timing at which the correlation value is determined to be equal to or greater than the second setting threshold and becomes the maximum within the prediction range as the frame synchronization timing.

In this modified example, as shown in FIG. 35, even if the correlation value exceeds the second set threshold C _th within the prediction range A1 and other than the normal timing due to noise or multipath fading (broken line) If the correlation value is not the maximum within the prediction range A1, synchronization is not established. On the other hand, when the correlation value becomes equal to or greater than the second set threshold value _Cth at the regular timing and becomes maximum within the prediction range A1 (solid circle), synchronization is established. Therefore, the accuracy of establishment of synchronization can be improved.

(Eighth modification)
FIG. 36 shows a correlation value calculation method of the calculation circuit 37c in the communication system according to the eighth modification. Similarly to the above embodiment, the calculation circuit 37c multiplies the sample value sequence detected by the detection circuit 35 and the unique word U2 by the sample value and the bit value in the same order in time series order, The sum of the multiplication results is calculated and used as a correlation value. However, the calculation circuit 37c cumulatively adds the multiplication results of the sample value and the bit value in the correlation value calculation process using one register. Specifically, the calculation circuit 37c stores the multiplication result of the first values in one register, and the multiplication result of the second values is used as the first multiplication stored in the register. The result is added and the addition result is stored in the register. In this way, the calculation circuit 37c sequentially adds the multiplication results and stores the addition results in the register. The unique word U2 is not limited to the number of bits shown.

  Normally, a register used for calculating a correlation value between the sample value sequence and the bit sequence of the unique word U2 is required to be equal to or greater than the number of bits of the unique word U2, but in this modification example, it is related to the number of bits of the unique word U2. There is only one register. Therefore, the circuit scale of the calculation circuit 37c can be reduced, and the cost can be reduced.

  In addition, this invention is not limited to the structure of the said embodiment and each modification, A various deformation | transformation is possible according to the intended purpose. For example, any characteristic configuration of the above-described modifications may be combined with any other configuration. In addition, a filter may be provided between the AD converter 32 and the synchronization circuit 33 to pass only the baseband signal component and remove the noise component.

DESCRIPTION OF SYMBOLS 1 Communication system 2 Transmitter 21 Low speed bit stream generation circuit (low speed bit stream generation part)
22 Bit string generation circuit (bit string generation unit)
23 Transmitter circuit (wireless transmitter)
3 Receiver 31 Receiver circuit (wireless receiver)
32 AD converter (oversampling unit)
35 Detection circuit (detection part)
36 Low-speed bit string detection circuit (low-speed bit string detection unit)
37 Synchronization establishment circuit (synchronization establishment unit)
37g Correlation value calculation circuit for each timing (correlation value calculation unit)
37i Timing setting circuit (timing setting unit)
37j Timing interval detection circuit (timing interval detector)
A1, A2 Prediction range B1 Baseband signal F1 Frame D1 Data U1 Low-speed unique word (first synchronization bit string)
U2 unique word (second synchronization bit string)

Claims (10)

A low-speed bit string generation unit that generates a first synchronization bit string having a transmission speed lower than that of data to be transmitted;
A bit string generation unit that generates a second synchronization bit string having the same transmission speed as the data;
The first synchronization bit sequence, the second synchronization bit sequence, and generates a baseband signal by modulating the data to frame the, into an RF signal by upconverting the baseband signal, the A wireless transmission unit for wirelessly transmitting an RF signal ;
A transmitter having
A wireless receiving unit that extracts a baseband signal by down-converting received RF signals wirelessly transmitted by the wireless transmission unit,
And: (integer of 2 or more M) oversampling unit for quantizing a bit, the baseband signal extracted by the radio reception section, the one symbol of the data is sampled at sampling timing of the multiple, and M
A detector for detecting the baseband signal quantized by the oversampling unit ;
Detecting the first synchronization bit string in the baseband signal detected by the detection unit, based on the detection result, to predict the range in which the second synchronization bit string in the baseband signal is present A low-speed bit string detector ,
The sample value sequence of the baseband signal within the prediction range by the low-speed bit sequence detection unit is stored in advance as the sample value sequence by using the detected sample value as it is without replacing it with a binary value . A synchronization establishment unit that calculates a correlation value with the known second synchronization bit string at each sampling timing , and establishes symbol synchronization and frame synchronization based on the calculated correlation value ;
A receiver having
Communication system, comprising the. The synchronization establishment unit includes a plurality of correlation value calculation units that respectively calculate the correlation values of the plurality of sampling timings,
The communication system according to claim 1, wherein the plurality of correlation value calculation units execute the correlation value calculation processing in parallel . The wireless transmission unit continuously transmits the second synchronization bit string a number of times greater than or equal to the number of sampling timings,
The synchronization establishing unit is within the expected range, the sampling timing to calculate the correlation value, to claim 1, characterized in that it comprises the timing setting unit that switches in sequence for each length of the second synchronization bit sequence The communication system described. The synchronization establishment unit further includes a timing interval detection unit that detects a timing at which the correlation value becomes the maximum value and becomes a maximum value candidate within the prediction range at each sampling timing, and measures the timing interval thereof,
When the timing interval measured by the timing interval detection unit is not within the specified range, the maximum value of the sampling timing at which the correlation value is maximized at a timing different from the original is excluded from the maximum value candidates within the prediction range. the sampling timing of the largest maximum value candidate among the remaining said maximum value candidate set to the symbol synchronization timing, in claim 3, characterized in that to set the timing at which the maximum value is obtained in the frame synchronization timing The communication system described. When the number of sampling timings is n and n = m × p (m, p: an integer of 2 or more),
The wireless transmission unit continuously transmits the second synchronization bit string a number of times of m or more,
The synchronization establishment unit calculates p correlation values at the p sampling timings within the prediction range and executes the correlation value calculation processing in parallel, and the p correlations 2. The timing setting unit according to claim 1 , further comprising a timing setting unit that sequentially switches the sampling timing at which the correlation value is calculated by the value calculation unit for each length of the second synchronization bit string within the prediction range. Communications system. The synchronization establishing unit sets a sampling timing at which the correlation value is maximum within the prediction range as a symbol synchronization timing, and sets a timing at which the correlation value is maximum within the prediction range as a frame synchronization timing. The communication system according to any one of claims 1 to 3 and claim 5 . If the correlation value is equal to or greater than the correlation threshold, the synchronization establishment unit sets the sampling timing of the correlation value as the symbol synchronization timing, and sets the timing when the correlation value is equal to or greater than the correlation threshold as the frame synchronization timing. communication system according to any one of claims 1 to 5, characterized in. The synchronization establishment unit sets a sampling timing at which the correlation value is equal to or greater than a correlation threshold and is maximized within the prediction range as a symbol synchronization timing, and the correlation value is equal to or greater than a correlation threshold and within the prediction range communication system according to any one of claims 1 to 5, characterized in that for setting the timing of the maximum to the frame synchronization timing in. The synchronization establishment unit multiplies the sample value sequence and the second synchronization bit sequence by a sample value and a bit value in the same order in time series in the correlation value calculation process, a multiplication result, a communication system according to any one of claims 1 to 8, characterized in that cumulative addition using one register. A low-speed bit string generation step for generating a first synchronization bit string having a transmission speed lower than that of data to be transmitted;
A bit string generation step of generating a second synchronization bit string having the same transmission speed as the data;
Generating a baseband signal by framing and modulating the first synchronization bit string, the second synchronization bit string, and the data, up-converting the baseband signal to convert it to an RF signal, A wireless transmission step of wirelessly transmitting an RF signal;
A transmission step comprising:
A radio reception step of extracting a baseband signal by receiving and down-converting the RF signal wirelessly transmitted in the radio transmission step;
An oversampling step of sampling one symbol of the data at a plurality of sampling timings and quantizing the baseband signal extracted in the wireless reception step with M (M: integer of 2 or more) bits;
A detection step of detecting the baseband signal quantized by the oversampling step;
The first synchronization bit string in the baseband signal detected by the detection step is detected, and a range in which the second synchronization bit string exists in the baseband signal is predicted based on the detection result. A low-speed bit string detection step;
The sample value sequence of the baseband signal within the prediction range obtained by the low-speed bit sequence detection step is stored in advance as the sample value sequence by using the detected sample value as it is without replacing it with a binary value. A synchronization establishing step of calculating a correlation value with the known second synchronization bit string for each sampling timing, and establishing symbol synchronization and frame synchronization based on the calculated correlation value;
A receiving step comprising:
A communication method comprising:

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